1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
|
// IBM_PROLOG_BEGIN_TAG
// This is an automatically generated prolog.
//
// $Source: src/usr/fsi/test/fsiddtest.H $
//
// IBM CONFIDENTIAL
//
// COPYRIGHT International Business Machines Corp. 2011
//
// p1
//
// Object Code Only (OCO) source materials
// Licensed Internal Code Source Materials
// IBM HostBoot Licensed Internal Code
//
// The source code for this program is not published or other-
// wise divested of its trade secrets, irrespective of what has
// been deposited with the U.S. Copyright Office.
//
// Origin: 30
//
// IBM_PROLOG_END
#ifndef __FSIDDTEST_H
#define __FSIDDTEST_H
/**
* @file fsiddtest.H
*
* @brief Test cases for FSI Device Driver
*/
#include <cxxtest/TestSuite.H>
#include <errl/errlmanager.H>
#include <errl/errlentry.H>
#include <errl/errltypes.H>
#include <limits.h>
#include <devicefw/driverif.H>
#include "../fsidd.H"
extern trace_desc_t* g_trac_fsi;
class FsiDDTest : public CxxTest::TestSuite
{
public:
/**
* @brief FSI DD test - Read/Write
* Perform basic read/write operations
*/
void test_readWrite(void)
{
TRACFCOMP( g_trac_fsi, "FsiDDTest::test_readWrite> Start" );
uint64_t fails = 0;
uint64_t total = 0;
errlHndl_t l_err = NULL;
// scratch data to use
struct {
uint64_t addr;
uint32_t data;
bool writeable;
} test_data[] = {
//** Master Control Space
// version number
{ FsiDD::CMFSI_CONTROL_REG | 0x000074, 0x91010800, false },
{ FsiDD::MFSI_CONTROL_REG | 0x000074, 0x91010800, false },
// clock rate delay for ports 32-63 (unused ports)
{ FsiDD::MFSI_CONTROL_REG | 0x00000C, 0x11111111, true },
{ FsiDD::CMFSI_CONTROL_REG | 0x00000C, 0x22222222, true },
// port static level
{ FsiDD::MFSI_CONTROL_REG | 0x000018, 0x80000000, false }, //port0
{ FsiDD::MFSI_CONTROL_REG | 0x00001C, 0x00000000, false },
{ FsiDD::CMFSI_CONTROL_REG | 0x000018, 0x00000000, false },
{ FsiDD::CMFSI_CONTROL_REG | 0x00001C, 0x00000000, false },
//** Master Control Regs in Port space
//{ FsiDD::MFSI_PORT_0 | 0x000000, 0x91010800, false }, //Slave Config Table
};
const uint64_t NUM_ADDRS = sizeof(test_data)/sizeof(test_data[0]);
// allocate some space to play with
uint32_t read_data[NUM_ADDRS];
size_t op_size = sizeof(uint32_t);
// target the master processor
TARGETING::TargetService& targetService = TARGETING::targetService();
TARGETING::Target* fsi_target = NULL;
targetService.masterProcChipTargetHandle( fsi_target );
// read address X,Y,Z
for( uint64_t x = 0; x < NUM_ADDRS; x++ )
{
total++;
TRACFCOMP( g_trac_fsi, "FsiDDTest::test_readWrite> Reading %llX", test_data[x].addr );
l_err = DeviceFW::deviceOp( DeviceFW::READ,
fsi_target,
&(read_data[x]),
op_size,
DEVICE_FSI_ADDRESS(test_data[x].addr) );
if( l_err )
{
TRACFCOMP(g_trac_fsi, "FsiDDTest::test_readWrite> Error from device : addr=0x%X, RC=%X", test_data[x].addr, l_err->reasonCode() );
TS_FAIL( "FsiDDTest::test_readWrite> ERROR : Unexpected error log from read1" );
fails++;
errlCommit(l_err);
delete l_err;
}
TRACFCOMP( g_trac_fsi, "READ Reg 0x%X = 0x%X", test_data[x].addr, read_data[x] );
//@todo - check op_size
}
// write X=A, Y=B, Z=C
for( uint64_t x = 0; x < NUM_ADDRS; x++ )
{
if( test_data[x].writeable )
{
total++;
l_err = DeviceFW::deviceOp( DeviceFW::WRITE,
fsi_target,
&(test_data[x].data),
op_size,
DEVICE_FSI_ADDRESS(test_data[x].addr) );
if( l_err )
{
TRACFCOMP(g_trac_fsi, "FsiDDTest::test_readWrite> Error from device : addr=0x%X, RC=%X", test_data[x].addr, l_err->reasonCode() );
TS_FAIL( "FsiDDTest::test_readWrite> ERROR : Unexpected error log from write1" );
fails++;
errlCommit(l_err);
delete l_err;
}
//@todo - check op_size
}
}
// read X,Y,Z
for( uint64_t x = 0; x < NUM_ADDRS; x++ )
{
total++;
l_err = DeviceFW::deviceOp( DeviceFW::READ,
fsi_target,
&(read_data[x]),
op_size,
DEVICE_FSI_ADDRESS(test_data[x].addr) );
if( l_err )
{
TRACFCOMP(g_trac_fsi, "FsiDDTest::test_readWrite> Error from device : addr=0x%X, RC=%X", test_data[x].addr, l_err->reasonCode() );
TS_FAIL( "FsiDDTest::test_readWrite> ERROR : Unexpected error log from read2" );
fails++;
errlCommit(l_err);
delete l_err;
}
//@todo - check op_size
}
// verify X==A, Y==B, Z==C
for( uint64_t x = 0; x < NUM_ADDRS; x++ )
{
total++;
if( read_data[x] != test_data[x].data )
{
TRACFCOMP(g_trac_fsi, "FsiDDTest::test_readWrite> Data mismatch : addr=0x%X, exp=0x%X, act=0x%X", test_data[x].addr, test_data[x].data, read_data[x] );
TS_FAIL( "FsiDDTest::test_readWrite> ERROR : Data mismatch" );
fails++;
}
}
//@todo - repeat for each address space
TRACFCOMP( g_trac_fsi, "FsiDDTest::test_readWrite> %d/%d fails", fails, total );
};
/**
* @brief FSI DD test - verifyAddressRange
* Test output of verifyAddressRange
*/
void test_verifyAddressRange(void)
{
TRACFCOMP( g_trac_fsi, "FsiDDTest::verifyAddressRange> Start" );
uint64_t fails = 0;
uint64_t total = 0;
//@todo
// values to try:
// -address 0
// -valid address at the beginning (if not 0)
// -valid address and size in the middle
// -valid address and size that hit the end of the range
// -valid address and size that exceeds range
// -address beyond range
// -address before beginning (if not 0)
TRACFCOMP( g_trac_fsi, "FsiDDTest::verifyAddressRange> %d/%d fails", fails, total );
};
};
#endif
|
