path: root/src/usr/diag/prdf/common/plat/centaur/centaur_membuf_actions.rule

# IBM_PROLOG_BEGIN_TAG
# This is an automatically generated prolog.
#
# $Source: src/usr/diag/prdf/common/plat/centaur/centaur_membuf_actions.rule $
#
# OpenPOWER HostBoot Project
#
# Contributors Listed Below - COPYRIGHT 2018
# [+] International Business Machines Corp.
#
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
#     http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
# implied. See the License for the specific language governing
# permissions and limitations under the License.
#
# IBM_PROLOG_END_TAG

/** Callout the connected MBA 0 */
actionclass calloutMba0 { callout(connected(TYPE_MBA, 0), MRU_MED); };

/** Callout the connected MBA 1 */
actionclass calloutMba1 { callout(connected(TYPE_MBA, 1), MRU_MED); };

/** Callout the connected MBA 0, threshold 1 */
actionclass mba0_th_1 { calloutMba0; threshold1; };

/** Callout the connected MBA 1, threshold 1 */
actionclass mba1_th_1 { calloutMba1; threshold1; };

/** Callout the connected MBA 0, threshold 1, SUE source */
actionclass mba0_th_1_UERE { mba0_th_1; SueSource; };

/** Callout the connected MBA 1, threshold 1, SUE source */
actionclass mba1_th_1_UERE { mba1_th_1; SueSource; };

/** Threshold and mask policy (MBA 0) */
actionclass threshold_and_mask_mba0 { calloutMba0; threshold_and_mask; };

/** Threshold and mask policy (MBA 1) */
actionclass threshold_and_mask_mba1 { calloutMba1; threshold_and_mask; };

/** Callout the connected L4 */
actionclass calloutL4 { callout(connected(TYPE_L4, 0), MRU_MED); };

/** Callout the connected L4, threshold 1 */
actionclass l4_th_1 { calloutL4; threshold1; };

/** Callout the connected L4, threshold 32/day */
actionclass l4_th_32perDay { calloutL4; threshold32pday; };

/** Callout the connected L4, threshold 1, SUE source */
actionclass l4_th_1_UERE { l4_th_1; SueSource; };

/** PLL error */
actionclass pll_unlock_UERE
{
    # These FIR bits should never trigger directly themselves in the rule code.
    # Instead, They should be handled by global PRD PLL isolation code. We will
    # add a threshold here to prevent flooding, just in case.
    threshold32pday;
};

/** Callout the DMI BUS interface */
actionclass calloutBusInterface_dmibus
{
    funccall("calloutBusInterfacePlugin");
};

/** Callout the DMI BUS interface, threshold 1 */
actionclass calloutBusInterface_dmibus_th1
{
    calloutBusInterface_dmibus;
    threshold1;
};

/** Callout the DMI BUS interface, threshold 1 */
actionclass calloutBusInterface_dmibus_th1_UERE
{
    calloutBusInterface_dmibus;
    threshold1;
    SueSource;
};

/** Lane Repair: spare deployed */
actionclass spareDeployed_dmibus
{
    calloutBusInterface_dmibus;
    funccall("spareDeployed");
};

/** Lane Repair: max spares exceeded */
actionclass maxSparesExceeded_dmibus
{
    calloutBusInterface_dmibus_th1;
    funccall("maxSparesExceeded");
};

/** Lane Repair: too many bus errors */
actionclass tooManyBusErrors_dmibus_UERE
{
    calloutBusInterface_dmibus_th1;
    funccall("tooManyBusErrors");
    SueSource; # channel failure
};

/** Calls out the DMI bus (TH 1) and clears any secondary attentions. */
actionclass replay_timeout_UERE
{
    calloutBusInterface_dmibus_th1_UERE;
    funccall("ClearMbsSecondaryBits");
};

/** Handles cases where both MBSFIR[3:4] are on, else calls out self. */
actionclass mbs_internal_timeout_precheck
{
    threshold32pday;
    funccall("mbsInternalTimeoutPrecheck");
};

/** Handles RCD parity errors, if present. Otherwise, calls out self (TH 1). */
actionclass mbs_internal_timeout
{
    try ( funccall("analyzeMbaRcdParityError0"),
          try ( funccall("analyzeMbaRcdParityError1"),
                mbs_internal_timeout_precheck ) );
};

/** Handles RCD parity errors, if present. Otherwise, calls out lvl 2 (TH 1). */
actionclass mbs_int_ext_timeout
{
    try ( funccall("analyzeMbaRcdParityError0"),
          try ( funccall("analyzeMbaRcdParityError1"), level2_th_1 ) );
};

/** L4 cache SRW CE */
actionclass l4_cache_srw_ce
{
    calloutL4;
    threshold( field(32 / day), mfg_file(ATTR_MNFG_TH_CEN_L4_CACHE_CES));
    funccall("CaptureL4CacheErr");
    funccall("ClearServiceCallFlag");
    funccall("ClearMbsSecondaryBits");
};

/** L4 cache SRW UE */
actionclass l4_cache_srw_ue_UERE
{
    calloutL4;
    threshold1;
    funccall("CaptureL4CacheErr");
    funccall("MaskMbsSecondaryBits");
    SueSource;
};

/** L4 cache CO UE */
actionclass l4_cache_co_ce
{
    calloutL4;
    threshold( field(32 / day), mfg_file(ATTR_MNFG_TH_CEN_L4_CACHE_CES));
    funccall("CaptureL4CacheErr");
    funccall("ClearServiceCallFlag");
    funccall("ClearMbaCalSecondaryBits");
};

/** L4 cache CO UE */
actionclass l4_cache_co_ue_UERE
{
    calloutL4;
    threshold1;
    funccall("CaptureL4CacheErr");
    funccall("MaskMbaCalSecondaryBits");
    SueSource;
};

/** Verify Chip Mark */
actionclass verify_chip_mark_rnk0_mba0 { funccall("AnalyzeFetchMpe0_0"); };
actionclass verify_chip_mark_rnk1_mba0 { funccall("AnalyzeFetchMpe0_1"); };
actionclass verify_chip_mark_rnk2_mba0 { funccall("AnalyzeFetchMpe0_2"); };
actionclass verify_chip_mark_rnk3_mba0 { funccall("AnalyzeFetchMpe0_3"); };
actionclass verify_chip_mark_rnk4_mba0 { funccall("AnalyzeFetchMpe0_4"); };
actionclass verify_chip_mark_rnk5_mba0 { funccall("AnalyzeFetchMpe0_5"); };
actionclass verify_chip_mark_rnk6_mba0 { funccall("AnalyzeFetchMpe0_6"); };
actionclass verify_chip_mark_rnk7_mba0 { funccall("AnalyzeFetchMpe0_7"); };
actionclass verify_chip_mark_rnk0_mba1 { funccall("AnalyzeFetchMpe1_0"); };
actionclass verify_chip_mark_rnk1_mba1 { funccall("AnalyzeFetchMpe1_1"); };
actionclass verify_chip_mark_rnk2_mba1 { funccall("AnalyzeFetchMpe1_2"); };
actionclass verify_chip_mark_rnk3_mba1 { funccall("AnalyzeFetchMpe1_3"); };
actionclass verify_chip_mark_rnk4_mba1 { funccall("AnalyzeFetchMpe1_4"); };
actionclass verify_chip_mark_rnk5_mba1 { funccall("AnalyzeFetchMpe1_5"); };
actionclass verify_chip_mark_rnk6_mba1 { funccall("AnalyzeFetchMpe1_6"); };
actionclass verify_chip_mark_rnk7_mba1 { funccall("AnalyzeFetchMpe1_7"); };

/** Fetch NCE */
actionclass mainline_nce_handling_mba0 { funccall("AnalyzeFetchNce0"); };
actionclass mainline_nce_handling_mba1 { funccall("AnalyzeFetchNce1"); };

/** Fetch UE */
actionclass mainline_ue_0
{
    funccall("AnalyzeFetchUe0");
    threshold( field(33 / 30 min) );
    SueSource;
};
actionclass mainline_ue_1
{
    funccall("AnalyzeFetchUe1");
    threshold( field(33 / 30 min) );
    SueSource;
};
actionclass mainline_ue_handling_mba0_UERE
{
    try ( funccall("analyzeMbaRcdParityError0"), mainline_ue_0 );
};
actionclass mainline_ue_handling_mba1_UERE
{
    try ( funccall("analyzeMbaRcdParityError1"), mainline_ue_1 );
};

/** Fetch RCE or Prefetch UE */
actionclass mainline_rce_pue_handling_mba0 { funccall("AnalyzeFetchRcePue0"); };
actionclass mainline_rce_pue_handling_mba1 { funccall("AnalyzeFetchRcePue1"); };

###############################################################################
# Analyze group
###############################################################################

/** There is a small window during the IPL where the MEM chiplet may be offline
 *  while the rest of the chip is working. Therefore, we cannot capture those
 *  registers unless we have an active attention from the MEM chiplet. */
actionclass analyzeMemChipletFir
{
    capture(MemChipletRegs);
    analyze(gMEM_CHIPLET_FIR);
};

actionclass analyzeMemChipletSpa
{
    capture(MemChipletRegs);
    analyze(gMEM_CHIPLET_SPA_FIR);
};

actionclass analyzeTP_LFIR      { analyze(gTP_LFIR);      };
actionclass analyzeNEST_LFIR    { analyze(gNEST_LFIR);    };
actionclass analyzeDMIFIR       { analyze(gDMIFIR);       };
actionclass analyzeMBIFIR       { analyze(gMBIFIR);       };
actionclass analyzeMBSFIR       { analyze(gMBSFIR);       };
actionclass analyzeMCBISTFIR_0  { analyze(gMCBISTFIR_0);  };
actionclass analyzeMCBISTFIR_1  { analyze(gMCBISTFIR_1);  };
actionclass analyzeMBSECCFIR_0  { analyze(gMBSECCFIR_0);  };
actionclass analyzeMBSECCFIR_1  { analyze(gMBSECCFIR_1);  };
actionclass analyzeSCACFIR      { analyze(gSCACFIR);      };
actionclass analyzeMBSSECUREFIR { analyze(gMBSSECUREFIR); };
actionclass analyzeMEM_LFIR     { analyze(gMEM_LFIR);     };

###############################################################################
# Analyze connected
###############################################################################

actionclass analyzeConnectedMBA0 { analyze(connected(TYPE_MBA, 0)); };
actionclass analyzeConnectedMBA1 { analyze(connected(TYPE_MBA, 1)); };