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* Disable memory throttle change_after_syncJacob Harvey2017-02-276-36/+112
* Cleaning up and implementing L3 eff_config_thermalJacob Harvey2017-02-279-287/+508
* PM: add ATTR_PGPE_HCODE_FUNCTION_ENABLE attribute to control PGPE opsGreg Still2017-02-272-0/+32
* Adding in default raw card informationJacob Harvey2017-02-276-23/+92
* Revert "Adding hardware to fspCI command for the release tool"Elizabeth K. Liner2017-02-241-1/+1
* p9_scominfo update cannot do a mask check with a mask value of 0's.Ben Gass2017-02-231-2/+2
* p9_sbe_chiplet_reset: Change NX_1 hang pulse period to 68sJoachim Fenkes2017-02-231-0/+1
* Procedures modified for DD1 changesSunil.Kumar2017-02-231-1/+2
* p9_sbe_chiplet_reset Level 2 update: set EC/core multicast reg3=group3Joe Dery2017-02-231-7/+7
* Fixed even/odd EX multicast setup checking ATTR_PG_EPxx clockdomainsJoe Dery2017-02-231-1/+0
* Level 2 HWP for p9_sbe_chiplet_resetAnusha Reddy Rangareddygari2017-02-231-1/+2
* IPL updates -- IPL_flow_v180Anusha Reddy Rangareddygari2017-02-231-1/+2
* Level 2 HWP for p9_sbe_chiplet_resetAnusha Reddy Rangareddygari2017-02-231-2/+0
* partial good/hang pulse updates to support all sim models/clock ratiosJoe McGill2017-02-231-0/+1
* IPL optimized codesAnusha Reddy Rangareddygari2017-02-231-5/+5
* Level 2 HWP for p9_sbe_chiplet_resetAnusha Reddy Rangareddygari2017-02-231-1/+6
* Level 2 HWPs for new IPL changesAnusha Reddy Rangareddygari2017-02-231-1/+6
* Level 2 HWP for p9_sbe_chiplet_resetAnusha Reddy Rangareddygari2017-02-231-1/+0
* Level 2 HWP for p9_sbe_chiplet_resetAnusha Reddy Rangareddygari2017-02-231-1/+5
* Level 2 HWP for p9_sbe_chiplet_resetAnusha Reddy Rangareddygari2017-02-231-2/+1
* Level 2 HWP for p9_sbe_chiplet_resetAnusha Reddy Rangareddygari2017-02-231-0/+1
* Level 2 HWP for p9_sbe_chiplet_resetAnusha Reddy Rangareddygari2017-02-231-1/+1
* Level 2 Procedure - p9_sbe_chiplet_resetSunil.Kumar2017-02-231-23/+55
* PERV SBE: Level 1 Procedure - p9_sbe_chiplet_resetAbhishek Agarwal2017-02-231-0/+78
* p9.fbc.ioo_tl.scom.initfile update for nvlinkdchowe2017-02-232-14/+47
* Adding hardware to fspCI command for the release toolElizabeth Liner2017-02-231-2/+2
* Level 2 p9_cpu_special_wakeupGreg Still2017-02-233-0/+81
* Dummy commit to delete files before mirror fixupDan Crowell2017-02-233-81/+0
* Updating NV scom address xlate for dd2.Ben Gass2017-02-235-22/+251
* New dummy pulse pok bits (for L2/L3)Alex Taft2017-02-231-0/+34
* NPU scan/scom init updatesRyan Black2017-02-232-1/+27
* Increase autocitest timeout to 25 minutesDan Crowell2017-02-231-2/+3
* Add MRW parsing code to populate ATTR_NEST_LEAKAGE_PERCENTAndres Lugo-Reyes2017-02-232-4/+1
* Add duplicate PHB check in Targets.pmMatt Ploetz2017-02-231-5/+73
* Removing ATTR_PROC_FABRIC_ADDR_BAR_MODEThi Tran2017-02-233-49/+0
* Fix up interrupt init process for MPIPLcrgeddes2017-02-222-24/+107
* p9_tor: fix tor_access_ring failureMartin Peschke2017-02-221-0/+2
* p9_tor: fix endianess conversionMartin Peschke2017-02-221-45/+42
* xip_customize: MVPD compatible file set.Claus Michael Olsen2017-02-229-41/+173
* PGPE WOF Enablement Fixed/UpdatesRahul Batra2017-02-221-13/+48
* Update p9_query_cache_access_state to use the correct scom registercrgeddes2017-02-221-2/+2
* Scan support for multiple chipsDan Crowell2017-02-224-210/+232
* Fix bad traceDan Crowell2017-02-221-1/+1
* Initial Support for VDM data from #W keyword of VPD in HostbootMarty Gloff2017-02-228-4/+169
* Fix for missing symbolKahn Evans2017-02-223-4/+5
* p9_hcode_image_build: Fix repair ring calls to use BASE variant, not risk levelGreg Still2017-02-221-2/+2
* pstate parameter block: precalculated slopesPrasad Bg Ranganath2017-02-223-143/+782
* Add three WATs, remove IMC2, replace stop2 workaroundNick Klazynski2017-02-221-1/+52
* Adding interface changes to provide I2C information to HDATElizabeth Liner2017-02-216-36/+445
* Only update SBEs on chips connected to powerbusDean Sanner2017-02-211-0/+18
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