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-rw-r--r--src/build/citest/etc/patches/p8.chip.patch32
-rw-r--r--src/build/citest/etc/patches/p8_inst.act585
-rw-r--r--src/build/citest/etc/patches/p8_master.por.patch17
-rw-r--r--src/build/citest/etc/patches/patchlist.txt14
-rwxr-xr-xsrc/build/citest/etc/workarounds.postsimsetup15
-rw-r--r--src/include/usr/hwas/common/hwas_reasoncodes.H45
-rw-r--r--src/include/usr/hwpf/plat/fapiPlatReasonCodes.H4
-rw-r--r--src/makefile2
-rw-r--r--src/usr/fsi/fsidd.C17
-rw-r--r--src/usr/fsi/fsidd.H50
-rw-r--r--src/usr/hwpf/hwp/makefile3
-rw-r--r--src/usr/hwpf/hwp/thread_activate/makefile55
-rw-r--r--src/usr/hwpf/hwp/thread_activate/thread_activate.C308
-rw-r--r--src/usr/initservice/extinitsvc/extinitsvctasks.H24
14 files changed, 1097 insertions, 74 deletions
diff --git a/src/build/citest/etc/patches/p8.chip.patch b/src/build/citest/etc/patches/p8.chip.patch
new file mode 100644
index 000000000..cd9227b20
--- /dev/null
+++ b/src/build/citest/etc/patches/p8.chip.patch
@@ -0,0 +1,32 @@
+
+
+##### from src/build/etc/patches/p8_master.por.patch
+
+ACTIONS=p8_inst.act
+
+#dc01
+########################## Logical Instruction State ###################
+REGSPACE THREADSTATE CHIPLET ex
+ ### Current State ###
+ # 0: thread is in POR state
+ # 1: thread is quiesced
+ # 2: thread is running
+ # 3: thread is in maint mode
+ # 4: thread is active (not in SLEEP or NAP or POR)
+ # 5: thread is in NAP state
+ # 6: thread is in SLEEP state
+ # 7: thread is in WINKLE state
+
+ # One register per thread
+ 0x0, 32
+ 0x1, 32
+ 0x2, 32
+ 0x3, 32
+ 0x4, 32
+ 0x5, 32
+ 0x6, 32
+ 0x7, 32
+
+END
+
+##### end patch
diff --git a/src/build/citest/etc/patches/p8_inst.act b/src/build/citest/etc/patches/p8_inst.act
new file mode 100644
index 000000000..523acd32b
--- /dev/null
+++ b/src/build/citest/etc/patches/p8_inst.act
@@ -0,0 +1,585 @@
+# Actions for P8 chips related to Instruction Processing
+
+# Flag PTR/DCR# Userid Date Description
+# ---- -------- -------- -------- -----------
+# D841334 dcrowell 06/11/11 File Created
+
+
+# Actions work like this:
+# Scoms to action bits will set state bits in THREADSTATE regspace
+# Changes to THREADSTATE regspace will update status bits in Scom regs
+#
+# See p8.chip for THREADSTATE bit definitions
+
+#NOTE: Hostboot patched version is hardcoded to Core5
+#NOTE: Hostboot patched version does not set NIA for SRESET
+
+
+###################
+## Scom Triggers ##
+
+##### SRESET #####
+
+CAUSE_EFFECT CHIPLETS ex {
+ LABEL=[Sreset Instructions - cXt0]
+ WATCH=[REG(MYCHIPLET,0x013000)] # RAS Control Reg
+ CAUSE: TARGET=[REG(MYCHIPLET,0x013000)] OP=[BIT,ON] BIT=[60] # SRESET
+ #EFFECT: TARGET=[PROCREG(nia, 5, 0)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000100)]
+ EFFECT: TARGET=[MODULE(startInstructions, 5, 0)] OP=[MODULECALL]
+ # Clear quiesce, por, maint mode, and all idle states
+ # Set running, active
+ EFFECT: TARGET=[THREADSTATE(MYCHIPLET,0x0)] OP=[EQUALTO,BUF] DATA=[LITERAL(32,28000000)]
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013000)] OP=[BIT,OFF] BIT=[60] # register is pulsed, clear the bit we just set
+}
+
+CAUSE_EFFECT CHIPLETS ex {
+ LABEL=[Sreset Instructions - cXt1]
+ WATCH=[REG(MYCHIPLET,0x013010)] # RAS Control Reg
+ CAUSE: TARGET=[REG(MYCHIPLET,0x013010)] OP=[BIT,ON] BIT=[60] # SRESET
+ #EFFECT: TARGET=[PROCREG(nia, 5, 1)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000100)]
+ EFFECT: TARGET=[MODULE(startInstructions, 5, 1)] OP=[MODULECALL] # Start Hostboot
+ # Clear quiesce, por, maint mode, and all idle states
+ # Set running, active
+ EFFECT: TARGET=[THREADSTATE(MYCHIPLET,0x1)] OP=[EQUALTO,BUF] DATA=[LITERAL(32,28000000)]
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013010)] OP=[BIT,OFF] BIT=[60] # register is pulsed, clear the bit we just set
+}
+
+CAUSE_EFFECT CHIPLETS ex {
+ LABEL=[Sreset Instructions - cXt2]
+ WATCH=[REG(MYCHIPLET,0x013020)] # RAS Control Reg
+ CAUSE: TARGET=[REG(MYCHIPLET,0x013020)] OP=[BIT,ON] BIT=[60] # SRESET
+ #EFFECT: TARGET=[PROCREG(nia, 5, 2)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000100)]
+ EFFECT: TARGET=[MODULE(startInstructions, 5, 2)] OP=[MODULECALL] # Start Hostboot
+ # Clear quiesce, por, maint mode, and all idle states
+ # Set running, active
+ EFFECT: TARGET=[THREADSTATE(MYCHIPLET,0x2)] OP=[EQUALTO,BUF] DATA=[LITERAL(32,28000000)]
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013020)] OP=[BIT,OFF] BIT=[60] # register is pulsed, clear the bit we just set
+}
+
+CAUSE_EFFECT CHIPLETS ex {
+ LABEL=[Sreset Instructions - cXt3]
+ WATCH=[REG(MYCHIPLET,0x013030)] # RAS Control Reg
+ CAUSE: TARGET=[REG(MYCHIPLET,0x013030)] OP=[BIT,ON] BIT=[60] # SRESET
+ #EFFECT: TARGET=[PROCREG(nia, 5, 3)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000100)]
+ EFFECT: TARGET=[MODULE(startInstructions, 5, 3)] OP=[MODULECALL] # Start Hostboot
+ # Clear quiesce, por, maint mode, and all idle states
+ # Set running, active
+ EFFECT: TARGET=[THREADSTATE(MYCHIPLET,0x3)] OP=[EQUALTO,BUF] DATA=[LITERAL(32,28000000)]
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013030)] OP=[BIT,OFF] BIT=[60] # register is pulsed, clear the bit we just set
+}
+
+CAUSE_EFFECT CHIPLETS ex {
+ LABEL=[Sreset Instructions - cXt4]
+ WATCH=[REG(MYCHIPLET,0x013040)] # RAS Control Reg
+ CAUSE: TARGET=[REG(MYCHIPLET,0x013040)] OP=[BIT,ON] BIT=[60] # SRESET
+ #EFFECT: TARGET=[PROCREG(nia, 5, 4)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000100)]
+ EFFECT: TARGET=[MODULE(startInstructions, 5, 4)] OP=[MODULECALL] # Start Hostboot
+ # Clear quiesce, por, maint mode, and all idle states
+ # Set running, active
+ EFFECT: TARGET=[THREADSTATE(MYCHIPLET,0x4)] OP=[EQUALTO,BUF] DATA=[LITERAL(32,28000000)]
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013040)] OP=[BIT,OFF] BIT=[60] # register is pulsed, clear the bit we just set
+}
+
+CAUSE_EFFECT CHIPLETS ex {
+ LABEL=[Sreset Instructions - cXt5]
+ WATCH=[REG(MYCHIPLET,0x013050)] # RAS Control Reg
+ CAUSE: TARGET=[REG(MYCHIPLET,0x013050)] OP=[BIT,ON] BIT=[60] # SRESET
+ #EFFECT: TARGET=[PROCREG(nia, 5, 5)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000100)]
+ EFFECT: TARGET=[MODULE(startInstructions, 5, 5)] OP=[MODULECALL] # Start Hostboot
+ # Clear quiesce, por, maint mode, and all idle states
+ # Set running, active
+ EFFECT: TARGET=[THREADSTATE(MYCHIPLET,0x5)] OP=[EQUALTO,BUF] DATA=[LITERAL(32,28000000)]
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013050)] OP=[BIT,OFF] BIT=[60] # register is pulsed, clear the bit we just set
+}
+
+CAUSE_EFFECT CHIPLETS ex {
+ LABEL=[Sreset Instructions - cXt6]
+ WATCH=[REG(MYCHIPLET,0x013060)] # RAS Control Reg
+ CAUSE: TARGET=[REG(MYCHIPLET,0x013060)] OP=[BIT,ON] BIT=[60] # SRESET
+ #EFFECT: TARGET=[PROCREG(nia, 5, 6)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000100)]
+ EFFECT: TARGET=[MODULE(startInstructions, 5, 6)] OP=[MODULECALL] # Start Hostboot
+ # Clear quiesce, por, maint mode, and all idle states
+ # Set running, active
+ EFFECT: TARGET=[THREADSTATE(MYCHIPLET,0x6)] OP=[EQUALTO,BUF] DATA=[LITERAL(32,28000000)]
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013060)] OP=[BIT,OFF] BIT=[60] # register is pulsed, clear the bit we just set
+}
+
+CAUSE_EFFECT CHIPLETS ex {
+ LABEL=[Sreset Instructions - cXt7]
+ WATCH=[REG(MYCHIPLET,0x013070)] # RAS Control Reg
+ CAUSE: TARGET=[REG(MYCHIPLET,0x013070)] OP=[BIT,ON] BIT=[60] # SRESET
+ #EFFECT: TARGET=[PROCREG(nia, 5, 7)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000100)]
+ EFFECT: TARGET=[MODULE(startInstructions, 5, 7)] OP=[MODULECALL] # Start Hostboot
+ # Clear quiesce, por, maint mode, and all idle states
+ # Set running, active
+ EFFECT: TARGET=[THREADSTATE(MYCHIPLET,0x7)] OP=[EQUALTO,BUF] DATA=[LITERAL(32,28000000)]
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013070)] OP=[BIT,OFF] BIT=[60] # register is pulsed, clear the bit we just set
+}
+
+
+##### Start #####
+
+CAUSE_EFFECT CHIPLETS ex {
+ LABEL=[Start Instructions - cXt0]
+ WATCH=[REG(MYCHIPLET,0x013000)] # RAS Control Reg
+ CAUSE: TARGET=[REG(MYCHIPLET,0x013000)] OP=[BIT,ON] BIT=[62] # Start
+ EFFECT: TARGET=[MODULE(startInstructions, 5, 0)] OP=[MODULECALL]
+ # Clear quiesce, por, maint mode
+ # Set running
+ # Leave other bits alone
+ EFFECT: TARGET=[THREADSTATE(MYCHIPLET,0x0)] OP=[EQUALTO,BUF,MASK] DATA=[LITERAL(32,20000000)] MASK=[LITERAL(32,70000000)]
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013000)] OP=[BIT,OFF] BIT=[62] # register is pulsed, clear the bit we just set
+}
+
+CAUSE_EFFECT CHIPLETS ex {
+ LABEL=[Start Instructions - cXt1]
+ WATCH=[REG(MYCHIPLET,0x013010)] # RAS Control Reg
+ CAUSE: TARGET=[REG(MYCHIPLET,0x013010)] OP=[BIT,ON] BIT=[62] # Start
+ EFFECT: TARGET=[MODULE(startInstructions, 5, 1)] OP=[MODULECALL] # Start Hostboot
+ # Clear quiesce, por, maint mode
+ # Set running
+ # Leave other bits alone
+ EFFECT: TARGET=[THREADSTATE(MYCHIPLET,0x1)] OP=[EQUALTO,BUF,MASK] DATA=[LITERAL(32,20000000)] MASK=[LITERAL(32,70000000)]
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013010)] OP=[BIT,OFF] BIT=[62] # register is pulsed, clear the bit we just set
+}
+
+CAUSE_EFFECT CHIPLETS ex {
+ LABEL=[Start Instructions - cXt2]
+ WATCH=[REG(MYCHIPLET,0x013020)] # RAS Control Reg
+ CAUSE: TARGET=[REG(MYCHIPLET,0x013020)] OP=[BIT,ON] BIT=[62] # Start
+ EFFECT: TARGET=[MODULE(startInstructions, 5, 2)] OP=[MODULECALL] # Start Hostboot
+ # Clear quiesce, por, maint mode
+ # Set running
+ # Leave other bits alone
+ EFFECT: TARGET=[THREADSTATE(MYCHIPLET,0x2)] OP=[EQUALTO,BUF,MASK] DATA=[LITERAL(32,20000000)] MASK=[LITERAL(32,70000000)]
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013020)] OP=[BIT,OFF] BIT=[62] # register is pulsed, clear the bit we just set
+}
+
+CAUSE_EFFECT CHIPLETS ex {
+ LABEL=[Start Instructions - cXt3]
+ WATCH=[REG(MYCHIPLET,0x013030)] # RAS Control Reg
+ CAUSE: TARGET=[REG(MYCHIPLET,0x013030)] OP=[BIT,ON] BIT=[62] # Start
+ EFFECT: TARGET=[MODULE(startInstructions, 5, 3)] OP=[MODULECALL] # Start Hostboot
+ # Clear quiesce, por, maint mode
+ # Set running
+ # Leave other bits alone
+ EFFECT: TARGET=[THREADSTATE(MYCHIPLET,0x3)] OP=[EQUALTO,BUF,MASK] DATA=[LITERAL(32,20000000)] MASK=[LITERAL(32,70000000)]
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013030)] OP=[BIT,OFF] BIT=[62] # register is pulsed, clear the bit we just set
+}
+
+CAUSE_EFFECT CHIPLETS ex {
+ LABEL=[Start Instructions - cXt4]
+ WATCH=[REG(MYCHIPLET,0x013040)] # RAS Control Reg
+ CAUSE: TARGET=[REG(MYCHIPLET,0x013040)] OP=[BIT,ON] BIT=[62] # Start
+ EFFECT: TARGET=[MODULE(startInstructions, 5, 4)] OP=[MODULECALL] # Start Hostboot
+ # Clear quiesce, por, maint mode
+ # Set running
+ # Leave other bits alone
+ EFFECT: TARGET=[THREADSTATE(MYCHIPLET,0x4)] OP=[EQUALTO,BUF,MASK] DATA=[LITERAL(32,20000000)] MASK=[LITERAL(32,70000000)]
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013040)] OP=[BIT,OFF] BIT=[62] # register is pulsed, clear the bit we just set
+}
+
+CAUSE_EFFECT CHIPLETS ex {
+ LABEL=[Start Instructions - cXt5]
+ WATCH=[REG(MYCHIPLET,0x013050)] # RAS Control Reg
+ CAUSE: TARGET=[REG(MYCHIPLET,0x013050)] OP=[BIT,ON] BIT=[62] # Start
+ EFFECT: TARGET=[MODULE(startInstructions, 5, 5)] OP=[MODULECALL] # Start Hostboot
+ # Clear quiesce, por, maint mode
+ # Set running
+ # Leave other bits alone
+ EFFECT: TARGET=[THREADSTATE(MYCHIPLET,0x5)] OP=[EQUALTO,BUF,MASK] DATA=[LITERAL(32,20000000)] MASK=[LITERAL(32,70000000)]
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013050)] OP=[BIT,OFF] BIT=[62] # register is pulsed, clear the bit we just set
+}
+
+CAUSE_EFFECT CHIPLETS ex {
+ LABEL=[Start Instructions - cXt6]
+ WATCH=[REG(MYCHIPLET,0x013062)] # RAS Control Reg
+ CAUSE: TARGET=[REG(MYCHIPLET,0x013062)] OP=[BIT,ON] BIT=[62] # Start
+ EFFECT: TARGET=[MODULE(startInstructions, 5, 6)] OP=[MODULECALL] # Start Hostboot
+ # Clear quiesce, por, maint mode
+ # Set running
+ # Leave other bits alone
+ EFFECT: TARGET=[THREADSTATE(MYCHIPLET,0x6)] OP=[EQUALTO,BUF,MASK] DATA=[LITERAL(32,20000000)] MASK=[LITERAL(32,70000000)]
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013062)] OP=[BIT,OFF] BIT=[62] # register is pulsed, clear the bit we just set
+}
+
+CAUSE_EFFECT CHIPLETS ex {
+ LABEL=[Start Instructions - cXt7]
+ WATCH=[REG(MYCHIPLET,0x013070)] # RAS Control Reg
+ CAUSE: TARGET=[REG(MYCHIPLET,0x013070)] OP=[BIT,ON] BIT=[62] # Start
+ EFFECT: TARGET=[MODULE(startInstructions, 5, 7)] OP=[MODULECALL] # Start Hostboot
+ # Clear quiesce, por, maint mode
+ # Set running
+ # Leave other bits alone
+ EFFECT: TARGET=[THREADSTATE(MYCHIPLET,0x7)] OP=[EQUALTO,BUF,MASK] DATA=[LITERAL(32,20000000)] MASK=[LITERAL(32,70000000)]
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013070)] OP=[BIT,OFF] BIT=[62] # register is pulsed, clear the bit we just set
+}
+
+
+
+####################
+## Status Updates ##
+
+##### Running #####
+
+CAUSE_EFFECT CHIPLETS ex {
+ LABEL=[Status - Running - cXt0]
+ WATCH=[THREADSTATE(MYCHIPLET,0x0)]
+ WATCH=[REG(MYCHIPLET,0x013002)]
+ # running=1, quiesced=0, idle states=0, por=0, maintmode=0
+ CAUSE: TARGET=[THREADSTATE(MYCHIPLET,0x0)] OP=[EQUALTO,BUF,MASK] DATA=[LITERAL(32,20000000)] MASK=[LITERAL(32,F7000000)]
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013002)] OP=[BUF,AND,OFF] DATA=[LITERAL(64,0x00000FFF FFFF87FF] #clear all state bits
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013002)] OP=[BIT,OFF] BIT=[49] #RUN=0b0010
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013002)] OP=[BIT,OFF] BIT=[50] #RUN=0b0010
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013002)] OP=[BIT,ON] BIT=[51] #RUN=0b0010
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013002)] OP=[BIT,OFF] BIT=[52] #RUN=0b0010
+}
+
+CAUSE_EFFECT CHIPLETS ex {
+ LABEL=[Status - Running - cXt1]
+ WATCH=[THREADSTATE(MYCHIPLET,0x1)]
+ WATCH=[REG(MYCHIPLET,0x013012)]
+ # running=1, quiesced=0, idle states=0, por=0, maintmode=0
+ CAUSE: TARGET=[THREADSTATE(MYCHIPLET,0x1)] OP=[EQUALTO,BUF,MASK] DATA=[LITERAL(32,20000000)] MASK=[LITERAL(32,F7000000)]
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013012)] OP=[BUF,AND,OFF] DATA=[LITERAL(64,0x00000FFF FFFF87FF] #clear all state bits
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013012)] OP=[BIT,OFF] BIT=[49] #RUN=0b0010
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013012)] OP=[BIT,OFF] BIT=[50] #RUN=0b0010
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013012)] OP=[BIT,ON] BIT=[51] #RUN=0b0010
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013012)] OP=[BIT,OFF] BIT=[52] #RUN=0b0010
+}
+
+CAUSE_EFFECT CHIPLETS ex {
+ LABEL=[Status - Running - cXt2]
+ WATCH=[THREADSTATE(MYCHIPLET,0x2)]
+ WATCH=[REG(MYCHIPLET,0x013022)]
+ # running=1, quiesced=0, idle states=0, por=0, maintmode=0
+ CAUSE: TARGET=[THREADSTATE(MYCHIPLET,0x2)] OP=[EQUALTO,BUF,MASK] DATA=[LITERAL(32,20000000)] MASK=[LITERAL(32,F7000000)]
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013022)] OP=[BUF,AND,OFF] DATA=[LITERAL(64,0x00000FFF FFFF87FF] #clear all state bits
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013022)] OP=[BIT,OFF] BIT=[49] #RUN=0b0010
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013022)] OP=[BIT,OFF] BIT=[50] #RUN=0b0010
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013022)] OP=[BIT,ON] BIT=[51] #RUN=0b0010
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013022)] OP=[BIT,OFF] BIT=[52] #RUN=0b0010
+}
+
+CAUSE_EFFECT CHIPLETS ex {
+ LABEL=[Status - Running - cXt3]
+ WATCH=[THREADSTATE(MYCHIPLET,0x3)]
+ WATCH=[REG(MYCHIPLET,0x013032)]
+ # running=1, quiesced=0, idle states=0, por=0, maintmode=0
+ CAUSE: TARGET=[THREADSTATE(MYCHIPLET,0x3)] OP=[EQUALTO,BUF,MASK] DATA=[LITERAL(32,20000000)] MASK=[LITERAL(32,F7000000)]
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013032)] OP=[BUF,AND,OFF] DATA=[LITERAL(64,0x00000FFF FFFF87FF] #clear all state bits
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013032)] OP=[BIT,OFF] BIT=[49] #RUN=0b0010
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013032)] OP=[BIT,OFF] BIT=[50] #RUN=0b0010
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013032)] OP=[BIT,ON] BIT=[51] #RUN=0b0010
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013032)] OP=[BIT,OFF] BIT=[52] #RUN=0b0010
+}
+
+CAUSE_EFFECT CHIPLETS ex {
+ LABEL=[Status - Running - cXt4]
+ WATCH=[THREADSTATE(MYCHIPLET,0x4)]
+ WATCH=[REG(MYCHIPLET,0x013042)]
+ # running=1, quiesced=0, idle states=0, por=0, maintmode=0
+ CAUSE: TARGET=[THREADSTATE(MYCHIPLET,0x4)] OP=[EQUALTO,BUF,MASK] DATA=[LITERAL(32,20000000)] MASK=[LITERAL(32,F7000000)]
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013042)] OP=[BUF,AND,OFF] DATA=[LITERAL(64,0x00000FFF FFFF87FF] #clear all state bits
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013042)] OP=[BIT,OFF] BIT=[49] #RUN=0b0010
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013042)] OP=[BIT,OFF] BIT=[50] #RUN=0b0010
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013042)] OP=[BIT,ON] BIT=[51] #RUN=0b0010
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013042)] OP=[BIT,OFF] BIT=[52] #RUN=0b0010
+}
+
+CAUSE_EFFECT CHIPLETS ex {
+ LABEL=[Status - Running - cXt5]
+ WATCH=[THREADSTATE(MYCHIPLET,0x5)]
+ WATCH=[REG(MYCHIPLET,0x013052)]
+ # running=1, quiesced=0, idle states=0, por=0, maintmode=0
+ CAUSE: TARGET=[THREADSTATE(MYCHIPLET,0x5)] OP=[EQUALTO,BUF,MASK] DATA=[LITERAL(32,20000000)] MASK=[LITERAL(32,F7000000)]
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013052)] OP=[BUF,AND,OFF] DATA=[LITERAL(64,0x00000FFF FFFF87FF] #clear all state bits
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013052)] OP=[BIT,OFF] BIT=[49] #RUN=0b0010
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013052)] OP=[BIT,OFF] BIT=[50] #RUN=0b0010
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013052)] OP=[BIT,ON] BIT=[51] #RUN=0b0010
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013052)] OP=[BIT,OFF] BIT=[52] #RUN=0b0010
+}
+
+CAUSE_EFFECT CHIPLETS ex {
+ LABEL=[Status - Running - cXt6]
+ WATCH=[THREADSTATE(MYCHIPLET,0x6)]
+ WATCH=[REG(MYCHIPLET,0x013062)]
+ # running=1, quiesced=0, idle states=0, por=0, maintmode=0
+ CAUSE: TARGET=[THREADSTATE(MYCHIPLET,0x6)] OP=[EQUALTO,BUF,MASK] DATA=[LITERAL(32,20000000)] MASK=[LITERAL(32,F7000000)]
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013062)] OP=[BUF,AND,OFF] DATA=[LITERAL(64,0x00000FFF FFFF87FF] #clear all state bits
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013062)] OP=[BIT,OFF] BIT=[49] #RUN=0b0010
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013062)] OP=[BIT,OFF] BIT=[50] #RUN=0b0010
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013062)] OP=[BIT,ON] BIT=[51] #RUN=0b0010
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013062)] OP=[BIT,OFF] BIT=[52] #RUN=0b0010
+}
+
+CAUSE_EFFECT CHIPLETS ex {
+ LABEL=[Status - Running - cXt7]
+ WATCH=[THREADSTATE(MYCHIPLET,0x7)]
+ WATCH=[REG(MYCHIPLET,0x013072)]
+ # running=1, quiesced=0, idle states=0, por=0, maintmode=0
+ CAUSE: TARGET=[THREADSTATE(MYCHIPLET,0x7)] OP=[EQUALTO,BUF,MASK] DATA=[LITERAL(32,20000000)] MASK=[LITERAL(32,F7000000)]
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013072)] OP=[BUF,AND,OFF] DATA=[LITERAL(64,0x00000FFF FFFF87FF] #clear all state bits
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013072)] OP=[BIT,OFF] BIT=[49] #RUN=0b0010
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013072)] OP=[BIT,OFF] BIT=[50] #RUN=0b0010
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013072)] OP=[BIT,ON] BIT=[51] #RUN=0b0010
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013072)] OP=[BIT,OFF] BIT=[52] #RUN=0b0010
+}
+
+##### Active #####
+
+CAUSE_EFFECT CHIPLETS ex {
+ LABEL=[Status - Active - cXt0]
+ WATCH=[THREADSTATE(MYCHIPLET,0x0)]
+ WATCH=[REG(MYCHIPLET,0x013002)]
+ # active=1, idle states=0
+ CAUSE: TARGET=[THREADSTATE(MYCHIPLET,0x0)] OP=[EQUALTO,BUF,MASK] DATA=[LITERAL(32,08000000)] MASK=[LITERAL(32,0F000000)]
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013002)] OP=[BIT,ON] BIT=[48] #THREAD_ENABLED
+ ELSE: TARGET=[REG(MYCHIPLET,0x013002)] OP=[BIT,OFF] BIT=[48] #THREAD_ENABLED
+}
+
+CAUSE_EFFECT CHIPLETS ex {
+ LABEL=[Status - Active - cXt1]
+ WATCH=[THREADSTATE(MYCHIPLET,0x1)]
+ WATCH=[REG(MYCHIPLET,0x013012)]
+ # active=1, idle states=0
+ CAUSE: TARGET=[THREADSTATE(MYCHIPLET,0x1)] OP=[EQUALTO,BUF,MASK] DATA=[LITERAL(32,08000000)] MASK=[LITERAL(32,0F000000)]
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013012)] OP=[BIT,ON] BIT=[48] #THREAD_ENABLED
+ ELSE: TARGET=[REG(MYCHIPLET,0x013012)] OP=[BIT,OFF] BIT=[48] #THREAD_ENABLED
+}
+
+CAUSE_EFFECT CHIPLETS ex {
+ LABEL=[Status - Active - cXt2]
+ WATCH=[THREADSTATE(MYCHIPLET,0x2)]
+ WATCH=[REG(MYCHIPLET,0x013022)]
+ # active=1, idle states=0
+ CAUSE: TARGET=[THREADSTATE(MYCHIPLET,0x2)] OP=[EQUALTO,BUF,MASK] DATA=[LITERAL(32,08000000)] MASK=[LITERAL(32,0F000000)]
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013022)] OP=[BIT,ON] BIT=[48] #THREAD_ENABLED
+ ELSE: TARGET=[REG(MYCHIPLET,0x013022)] OP=[BIT,OFF] BIT=[48] #THREAD_ENABLED
+}
+
+CAUSE_EFFECT CHIPLETS ex {
+ LABEL=[Status - Active - cXt3]
+ WATCH=[THREADSTATE(MYCHIPLET,0x3)]
+ WATCH=[REG(MYCHIPLET,0x013032)]
+ # active=1, idle states=0
+ CAUSE: TARGET=[THREADSTATE(MYCHIPLET,0x3)] OP=[EQUALTO,BUF,MASK] DATA=[LITERAL(32,08000000)] MASK=[LITERAL(32,0F000000)]
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013032)] OP=[BIT,ON] BIT=[48] #THREAD_ENABLED
+ ELSE: TARGET=[REG(MYCHIPLET,0x013032)] OP=[BIT,OFF] BIT=[48] #THREAD_ENABLED
+}
+
+CAUSE_EFFECT CHIPLETS ex {
+ LABEL=[Status - Active - cXt4]
+ WATCH=[THREADSTATE(MYCHIPLET,0x4)]
+ WATCH=[REG(MYCHIPLET,0x013042)]
+ # active=1, idle states=0
+ CAUSE: TARGET=[THREADSTATE(MYCHIPLET,0x4)] OP=[EQUALTO,BUF,MASK] DATA=[LITERAL(32,08000000)] MASK=[LITERAL(32,0F000000)]
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013042)] OP=[BIT,ON] BIT=[48] #THREAD_ENABLED
+ ELSE: TARGET=[REG(MYCHIPLET,0x013042)] OP=[BIT,OFF] BIT=[48] #THREAD_ENABLED
+}
+
+CAUSE_EFFECT CHIPLETS ex {
+ LABEL=[Status - Active - cXt5]
+ WATCH=[THREADSTATE(MYCHIPLET,0x5)]
+ WATCH=[REG(MYCHIPLET,0x013052)]
+ # active=1, idle states=0
+ CAUSE: TARGET=[THREADSTATE(MYCHIPLET,0x5)] OP=[EQUALTO,BUF,MASK] DATA=[LITERAL(32,08000000)] MASK=[LITERAL(32,0F000000)]
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013052)] OP=[BIT,ON] BIT=[48] #THREAD_ENABLED
+ ELSE: TARGET=[REG(MYCHIPLET,0x013052)] OP=[BIT,OFF] BIT=[48] #THREAD_ENABLED
+}
+
+CAUSE_EFFECT CHIPLETS ex {
+ LABEL=[Status - Active - cXt6]
+ WATCH=[THREADSTATE(MYCHIPLET,0x6)]
+ WATCH=[REG(MYCHIPLET,0x013062)]
+ # active=1, idle states=0
+ CAUSE: TARGET=[THREADSTATE(MYCHIPLET,0x6)] OP=[EQUALTO,BUF,MASK] DATA=[LITERAL(32,08000000)] MASK=[LITERAL(32,0F000000)]
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013062)] OP=[BIT,ON] BIT=[48] #THREAD_ENABLED
+ ELSE: TARGET=[REG(MYCHIPLET,0x013062)] OP=[BIT,OFF] BIT=[48] #THREAD_ENABLED
+}
+
+CAUSE_EFFECT CHIPLETS ex {
+ LABEL=[Status - Active - cXt7]
+ WATCH=[THREADSTATE(MYCHIPLET,0x7)]
+ WATCH=[REG(MYCHIPLET,0x013072)]
+ # active=1, idle states=0
+ CAUSE: TARGET=[THREADSTATE(MYCHIPLET,0x7)] OP=[EQUALTO,BUF,MASK] DATA=[LITERAL(32,08000000)] MASK=[LITERAL(32,0F000000)]
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013072)] OP=[BIT,ON] BIT=[48] #THREAD_ENABLED
+ ELSE: TARGET=[REG(MYCHIPLET,0x013072)] OP=[BIT,OFF] BIT=[48] #THREAD_ENABLED
+}
+
+##### Quiesced #####
+
+CAUSE_EFFECT CHIPLETS ex {
+ LABEL=[Status - Quiesced - cXt0]
+ WATCH=[THREADSTATE(MYCHIPLET,0x0)]
+ WATCH=[REG(MYCHIPLET,0x013002)]
+ # quiesced=1, running=0
+ CAUSE: TARGET=[THREADSTATE(MYCHIPLET,0x0)] OP=[EQUALTO,BUF,MASK] DATA=[LITERAL(32,40000000)] MASK=[LITERAL(32,60000000)]
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013002)] OP=[BUF,AND,OFF] DATA=[LITERAL(64,0x00000FFF FFFF87FF] #clear all state bits
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013002)] OP=[BIT,ON] BIT=[49] #QUIESCE=0b1000
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013002)] OP=[BIT,OFF] BIT=[50] #QUIESCE=0b1000
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013002)] OP=[BIT,OFF] BIT=[51] #QUIESCE=0b1000
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013002)] OP=[BIT,OFF] BIT=[52] #QUIESCE=0b1000
+}
+
+CAUSE_EFFECT CHIPLETS ex {
+ LABEL=[Status - Quiesced - cXt1]
+ WATCH=[THREADSTATE(MYCHIPLET,0x1)]
+ WATCH=[REG(MYCHIPLET,0x013012)]
+ # Quiesced=1, running=0
+ CAUSE: TARGET=[THREADSTATE(MYCHIPLET,0x1)] OP=[EQUALTO,BUF,MASK] DATA=[LITERAL(32,40000000)] MASK=[LITERAL(32,60000000)]
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013012)] OP=[BUF,AND,OFF] DATA=[LITERAL(64,0x00000FFF FFFF87FF] #clear all state bits
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013012)] OP=[BIT,ON] BIT=[49] #QUIESCE=0b1000
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013012)] OP=[BIT,OFF] BIT=[50] #QUIESCE=0b1000
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013012)] OP=[BIT,OFF] BIT=[51] #QUIESCE=0b1000
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013012)] OP=[BIT,OFF] BIT=[52] #QUIESCE=0b1000
+}
+
+CAUSE_EFFECT CHIPLETS ex {
+ LABEL=[Status - Quiesced - cXt2]
+ WATCH=[THREADSTATE(MYCHIPLET,0x2)]
+ WATCH=[REG(MYCHIPLET,0x013022)]
+ # Quiesced=1, running=0
+ CAUSE: TARGET=[THREADSTATE(MYCHIPLET,0x2)] OP=[EQUALTO,BUF,MASK] DATA=[LITERAL(32,40000000)] MASK=[LITERAL(32,60000000)]
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013022)] OP=[BUF,AND,OFF] DATA=[LITERAL(64,0x00000FFF FFFF87FF] #clear all state bits
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013022)] OP=[BIT,ON] BIT=[49] #QUIESCE=0b1000
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013022)] OP=[BIT,OFF] BIT=[50] #QUIESCE=0b1000
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013022)] OP=[BIT,OFF] BIT=[51] #QUIESCE=0b1000
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013022)] OP=[BIT,OFF] BIT=[52] #QUIESCE=0b1000
+}
+
+CAUSE_EFFECT CHIPLETS ex {
+ LABEL=[Status - Quiesced - cXt4]
+ WATCH=[THREADSTATE(MYCHIPLET,0x4)]
+ WATCH=[REG(MYCHIPLET,0x013042)]
+ # Quiesced=1, running=0
+ CAUSE: TARGET=[THREADSTATE(MYCHIPLET,0x4)] OP=[EQUALTO,BUF,MASK] DATA=[LITERAL(32,40000000)] MASK=[LITERAL(32,60000000)]
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013042)] OP=[BUF,AND,OFF] DATA=[LITERAL(64,0x00000FFF FFFF87FF] #clear all state bits
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013042)] OP=[BIT,ON] BIT=[49] #QUIESCE=0b1000
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013042)] OP=[BIT,OFF] BIT=[50] #QUIESCE=0b1000
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013042)] OP=[BIT,OFF] BIT=[51] #QUIESCE=0b1000
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013042)] OP=[BIT,OFF] BIT=[52] #QUIESCE=0b1000
+}
+
+CAUSE_EFFECT CHIPLETS ex {
+ LABEL=[Status - Quiesced - cXt5]
+ WATCH=[THREADSTATE(MYCHIPLET,0x5)]
+ WATCH=[REG(MYCHIPLET,0x013052)]
+ # Quiesced=1, running=0
+ CAUSE: TARGET=[THREADSTATE(MYCHIPLET,0x5)] OP=[EQUALTO,BUF,MASK] DATA=[LITERAL(32,40000000)] MASK=[LITERAL(32,60000000)]
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013052)] OP=[BUF,AND,OFF] DATA=[LITERAL(64,0x00000FFF FFFF87FF] #clear all state bits
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013052)] OP=[BIT,ON] BIT=[49] #QUIESCE=0b1000
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013052)] OP=[BIT,OFF] BIT=[50] #QUIESCE=0b1000
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013052)] OP=[BIT,OFF] BIT=[51] #QUIESCE=0b1000
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013052)] OP=[BIT,OFF] BIT=[52] #QUIESCE=0b1000
+}
+
+CAUSE_EFFECT CHIPLETS ex {
+ LABEL=[Status - Quiesced - cXt6]
+ WATCH=[THREADSTATE(MYCHIPLET,0x6)]
+ WATCH=[REG(MYCHIPLET,0x013062)]
+ # Quiesced=1, running=0
+ CAUSE: TARGET=[THREADSTATE(MYCHIPLET,0x6)] OP=[EQUALTO,BUF,MASK] DATA=[LITERAL(32,40000000)] MASK=[LITERAL(32,60000000)]
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013062)] OP=[BUF,AND,OFF] DATA=[LITERAL(64,0x00000FFF FFFF87FF] #clear all state bits
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013062)] OP=[BIT,ON] BIT=[49] #QUIESCE=0b1000
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013062)] OP=[BIT,OFF] BIT=[50] #QUIESCE=0b1000
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013062)] OP=[BIT,OFF] BIT=[51] #QUIESCE=0b1000
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013062)] OP=[BIT,OFF] BIT=[52] #QUIESCE=0b1000
+}
+
+CAUSE_EFFECT CHIPLETS ex {
+ LABEL=[Status - Quiesced - cXt7]
+ WATCH=[THREADSTATE(MYCHIPLET,0x7)]
+ WATCH=[REG(MYCHIPLET,0x013072)]
+ # Quiesced=1, running=0
+ CAUSE: TARGET=[THREADSTATE(MYCHIPLET,0x7)] OP=[EQUALTO,BUF,MASK] DATA=[LITERAL(32,40000000)] MASK=[LITERAL(32,60000000)]
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013072)] OP=[BUF,AND,OFF] DATA=[LITERAL(64,0x00000FFF FFFF87FF] #clear all state bits
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013072)] OP=[BIT,ON] BIT=[49] #QUIESCE=0b1000
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013072)] OP=[BIT,OFF] BIT=[50] #QUIESCE=0b1000
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013072)] OP=[BIT,OFF] BIT=[51] #QUIESCE=0b1000
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013072)] OP=[BIT,OFF] BIT=[52] #QUIESCE=0b1000
+}
+
+##### Maintmode #####
+
+CAUSE_EFFECT CHIPLETS ex {
+ LABEL=[Status - Maintmode - cXt0]
+ WATCH=[THREADSTATE(MYCHIPLET,0x0)]
+ WATCH=[REG(MYCHIPLET,0x013002)]
+ # maintmode=1, running=0
+ CAUSE: TARGET=[THREADSTATE(MYCHIPLET,0x0)] OP=[EQUALTO,BUF,MASK] DATA=[LITERAL(32,10000000)] MASK=[LITERAL(32,30000000)]
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013002)] OP=[BIT,ON] BIT=[21] #core_is_in_maintenance_mode
+ ELSE: TARGET=[REG(MYCHIPLET,0x013002)] OP=[BIT,OFF] BIT=[21] #core_is_in_maintenance_mode
+}
+
+CAUSE_EFFECT CHIPLETS ex {
+ LABEL=[Status - Maintmode - cXt1]
+ WATCH=[THREADSTATE(MYCHIPLET,0x1)]
+ WATCH=[REG(MYCHIPLET,0x013012)]
+ # maintmode=1, running=0
+ CAUSE: TARGET=[THREADSTATE(MYCHIPLET,0x1)] OP=[EQUALTO,BUF,MASK] DATA=[LITERAL(32,10000000)] MASK=[LITERAL(32,30000000)]
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013012)] OP=[BIT,ON] BIT=[21] #core_is_in_maintenance_mode
+ ELSE: TARGET=[REG(MYCHIPLET,0x013012)] OP=[BIT,OFF] BIT=[21] #core_is_in_maintenance_mode
+}
+
+CAUSE_EFFECT CHIPLETS ex {
+ LABEL=[Status - Maintmode - cXt2]
+ WATCH=[THREADSTATE(MYCHIPLET,0x2)]
+ WATCH=[REG(MYCHIPLET,0x013022)]
+ # maintmode=1, running=0
+ CAUSE: TARGET=[THREADSTATE(MYCHIPLET,0x2)] OP=[EQUALTO,BUF,MASK] DATA=[LITERAL(32,10000000)] MASK=[LITERAL(32,30000000)]
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013022)] OP=[BIT,ON] BIT=[21] #core_is_in_maintenance_mode
+ ELSE: TARGET=[REG(MYCHIPLET,0x013022)] OP=[BIT,OFF] BIT=[21] #core_is_in_maintenance_mode
+}
+
+CAUSE_EFFECT CHIPLETS ex {
+ LABEL=[Status - Maintmode - cXt3]
+ WATCH=[THREADSTATE(MYCHIPLET,0x3)]
+ WATCH=[REG(MYCHIPLET,0x013032)]
+ # maintmode=1, running=0
+ CAUSE: TARGET=[THREADSTATE(MYCHIPLET,0x3)] OP=[EQUALTO,BUF,MASK] DATA=[LITERAL(32,10000000)] MASK=[LITERAL(32,30000000)]
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013032)] OP=[BIT,ON] BIT=[21] #core_is_in_maintenance_mode
+ ELSE: TARGET=[REG(MYCHIPLET,0x013032)] OP=[BIT,OFF] BIT=[21] #core_is_in_maintenance_mode
+}
+
+CAUSE_EFFECT CHIPLETS ex {
+ LABEL=[Status - Maintmode - cXt4]
+ WATCH=[THREADSTATE(MYCHIPLET,0x4)]
+ WATCH=[REG(MYCHIPLET,0x013042)]
+ # maintmode=1, running=0
+ CAUSE: TARGET=[THREADSTATE(MYCHIPLET,0x4)] OP=[EQUALTO,BUF,MASK] DATA=[LITERAL(32,10000000)] MASK=[LITERAL(32,30000000)]
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013042)] OP=[BIT,ON] BIT=[21] #core_is_in_maintenance_mode
+ ELSE: TARGET=[REG(MYCHIPLET,0x013042)] OP=[BIT,OFF] BIT=[21] #core_is_in_maintenance_mode
+}
+
+CAUSE_EFFECT CHIPLETS ex {
+ LABEL=[Status - Maintmode - cXt5]
+ WATCH=[THREADSTATE(MYCHIPLET,0x5)]
+ WATCH=[REG(MYCHIPLET,0x013052)]
+ # maintmode=1, running=0
+ CAUSE: TARGET=[THREADSTATE(MYCHIPLET,0x5)] OP=[EQUALTO,BUF,MASK] DATA=[LITERAL(32,10000000)] MASK=[LITERAL(32,30000000)]
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013052)] OP=[BIT,ON] BIT=[21] #core_is_in_maintenance_mode
+ ELSE: TARGET=[REG(MYCHIPLET,0x013052)] OP=[BIT,OFF] BIT=[21] #core_is_in_maintenance_mode
+}
+
+CAUSE_EFFECT CHIPLETS ex {
+ LABEL=[Status - Maintmode - cXt6]
+ WATCH=[THREADSTATE(MYCHIPLET,0x6)]
+ WATCH=[REG(MYCHIPLET,0x013062)]
+ # maintmode=1, running=0
+ CAUSE: TARGET=[THREADSTATE(MYCHIPLET,0x6)] OP=[EQUALTO,BUF,MASK] DATA=[LITERAL(32,10000000)] MASK=[LITERAL(32,30000000)]
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013062)] OP=[BIT,ON] BIT=[21] #core_is_in_maintenance_mode
+ ELSE: TARGET=[REG(MYCHIPLET,0x013062)] OP=[BIT,OFF] BIT=[21] #core_is_in_maintenance_mode
+}
+
+CAUSE_EFFECT CHIPLETS ex {
+ LABEL=[Status - Maintmode - cXt7]
+ WATCH=[THREADSTATE(MYCHIPLET,0x7)]
+ WATCH=[REG(MYCHIPLET,0x013072)]
+ # maintmode=1, running=0
+ CAUSE: TARGET=[THREADSTATE(MYCHIPLET,0x7)] OP=[EQUALTO,BUF,MASK] DATA=[LITERAL(32,10000000)] MASK=[LITERAL(32,30000000)]
+ EFFECT: TARGET=[REG(MYCHIPLET,0x013072)] OP=[BIT,ON] BIT=[21] #core_is_in_maintenance_mode
+ ELSE: TARGET=[REG(MYCHIPLET,0x013072)] OP=[BIT,OFF] BIT=[21] #core_is_in_maintenance_mode
+}
+
diff --git a/src/build/citest/etc/patches/p8_master.por.patch b/src/build/citest/etc/patches/p8_master.por.patch
new file mode 100644
index 000000000..f74f75465
--- /dev/null
+++ b/src/build/citest/etc/patches/p8_master.por.patch
@@ -0,0 +1,17 @@
+
+##### from src/build/etc/patches/p8_master.por.patch
+
+#dc01
+#Flush state is : por=0,quiesced=1,running=0,maintmode=1,active=0,nap/sleep/winkle=0
+THREADSTATE(0x15000001)=0x10000000
+THREADSTATE(0x15000002)=0x10000000
+THREADSTATE(0x15000003)=0x10000000
+THREADSTATE(0x15000004)=0x10000000
+THREADSTATE(0x15000005)=0x10000000
+THREADSTATE(0x15000006)=0x10000000
+THREADSTATE(0x15000007)=0x10000000
+
+#Master thread is started by SBE : running=1,active=1
+THREADSTATE(0x15000000)=0x28000000
+
+##### end patch
diff --git a/src/build/citest/etc/patches/patchlist.txt b/src/build/citest/etc/patches/patchlist.txt
index e69de29bb..2274aa027 100644
--- a/src/build/citest/etc/patches/patchlist.txt
+++ b/src/build/citest/etc/patches/patchlist.txt
@@ -0,0 +1,14 @@
+# Example Format
+Brief description of the problem or reason for patch
+-RTC: Task/Story used to remove this patch
+-CMVC: Defect/Req for checking the changes into fips810
+-Files: list of files
+-Coreq: list of associated changes, e.g. workarounds.presimsetup
+
+
+New actions for instruction state processing
+-RTC: Task 43959 will remove the patches
+-CMVC: D841334 is integrating the changes
+-Files: p8_inst.act
+-Coreq: there are related changes in workarounds.postsimsetup
+
diff --git a/src/build/citest/etc/workarounds.postsimsetup b/src/build/citest/etc/workarounds.postsimsetup
index 04c47e541..51b45d176 100755
--- a/src/build/citest/etc/workarounds.postsimsetup
+++ b/src/build/citest/etc/workarounds.postsimsetup
@@ -26,3 +26,18 @@
## to setup the sandbox
##
+### Updates to handle instruction states (Remove with RTC:43959)
+echo "+++ Update cec-chip files for instruction state processing"
+mkdir -p $sb/simu/data/cec-chip/
+
+cp --update $bb/src/simu/data/cec-chip/p8.chip $sb/simu/data/cec-chip/
+cat $HOSTBOOTROOT/src/build/citest/etc/patches/p8.chip.patch >> $sb/simu/data/cec-chip/p8.chip
+grep -v DONE $sb/simu/data/cec-chip/p8.chip > $sb/simu/data/cec-chip/p8.chip.tmp
+echo "DONE" >> $sb/simu/data/cec-chip/p8.chip.tmp
+mv $sb/simu/data/cec-chip/p8.chip.tmp $sb/simu/data/cec-chip/p8.chip
+
+cp --update $bb/src/simu/data/cec-chip/p8_master.por $sb/simu/data/cec-chip/
+cat $HOSTBOOTROOT/src/build/citest/etc/patches/p8_master.por.patch >> $sb/simu/data/cec-chip/p8_master.por
+
+cp $HOSTBOOTROOT/src/build/citest/etc/patches/p8_inst.act $sb/simu/data/cec-chip/
+###
diff --git a/src/include/usr/hwas/common/hwas_reasoncodes.H b/src/include/usr/hwas/common/hwas_reasoncodes.H
index a7ad56aae..afd26b95a 100644
--- a/src/include/usr/hwas/common/hwas_reasoncodes.H
+++ b/src/include/usr/hwas/common/hwas_reasoncodes.H
@@ -1,25 +1,26 @@
-// IBM_PROLOG_BEGIN_TAG
-// This is an automatically generated prolog.
-//
-// $Source: src/include/usr/hwas/hwas_reasoncodes.H $
-//
-// IBM CONFIDENTIAL
-//
-// COPYRIGHT International Business Machines Corp. 2011
-//
-// p1
-//
-// Object Code Only (OCO) source materials
-// Licensed Internal Code Source Materials
-// IBM HostBoot Licensed Internal Code
-//
-// The source code for this program is not published or other-
-// wise divested of its trade secrets, irrespective of what has
-// been deposited with the U.S. Copyright Office.
-//
-// Origin: 30
-//
-// IBM_PROLOG_END
+/* IBM_PROLOG_BEGIN_TAG
+ * This is an automatically generated prolog.
+ *
+ * $Source: src/include/usr/hwas/common/hwas_reasoncodes.H $
+ *
+ * IBM CONFIDENTIAL
+ *
+ * COPYRIGHT International Business Machines Corp. 2011-2012
+ *
+ * p1
+ *
+ * Object Code Only (OCO) source materials
+ * Licensed Internal Code Source Materials
+ * IBM HostBoot Licensed Internal Code
+ *
+ * The source code for this program is not published or other-
+ * wise divested of its trade secrets, irrespective of what has
+ * been deposited with the U.S. Copyright Office.
+ *
+ * Origin: 30
+ *
+ * IBM_PROLOG_END_TAG
+ */
#ifndef HWAS_REASONCODES_H
#define HWAS_REASONCODES_H
diff --git a/src/include/usr/hwpf/plat/fapiPlatReasonCodes.H b/src/include/usr/hwpf/plat/fapiPlatReasonCodes.H
index fbcf758f5..a3011431c 100644
--- a/src/include/usr/hwpf/plat/fapiPlatReasonCodes.H
+++ b/src/include/usr/hwpf/plat/fapiPlatReasonCodes.H
@@ -51,6 +51,7 @@ namespace fapi
MOD_ATTR_GET_TARGET_NAME = 0x0B,
MOD_FAPI_GET_ASSOCIATE_DIMMS = 0x0C,
MOD_EDI_EI_IO_RUN_TRAINING = 0x0D,
+ MOD_THREAD_ACTIVATE = 0x0E, //@fixme RTC:42816
};
/**
@@ -77,6 +78,9 @@ namespace fapi
RC_MIXED_PBUS_CONNECTION = HWPF_COMP_ID | 0x19,
RC_SAME_CHIP_PBUS_CONNECTION = HWPF_COMP_ID | 0x1A,
RC_CONFLICT_PBUS_CONNECTION = HWPF_COMP_ID | 0x1B,
+ RC_NO_MASTER_CORE_TARGET = HWPF_COMP_ID | 0x1C,
+ RC_THREAD_IN_WRONG_STATE = HWPF_COMP_ID | 0x1D, //@fixme RTC:42816
+ RC_THREAD_DID_NOT_START = HWPF_COMP_ID | 0x1E, //@fixme RTC:42816
};
/**
diff --git a/src/makefile b/src/makefile
index 852a1103c..5de937420 100644
--- a/src/makefile
+++ b/src/makefile
@@ -60,7 +60,7 @@ EXTENDED_MODULES = targeting ecmddatabuffer fapi hwp plat \
activate_powerbus build_winkle_images \
core_activate dram_initialization edi_ei_initialization \
establish_system_smp load_payload \
- start_clocks_on_nest_chiplets start_payload
+ start_clocks_on_nest_chiplets start_payload thread_activate
DIRECT_BOOT_MODULES = example
RUNTIME_MODULES =
diff --git a/src/usr/fsi/fsidd.C b/src/usr/fsi/fsidd.C
index 73d6ebece..694d2ebd5 100644
--- a/src/usr/fsi/fsidd.C
+++ b/src/usr/fsi/fsidd.C
@@ -272,28 +272,11 @@ bool isSlavePresent( const TARGETING::Target* i_target )
}; //end FSI namespace
-/**
- * @brief set up _start() task entry procedure for FSI daemon
- */
-TASK_ENTRY_MACRO( FsiDD::init );
-
/********************
Public Methods
********************/
-/**
- * STATIC
- * @brief Static Initializer
- */
-void FsiDD::init( void* i_taskArgs )
-{
- TRACFCOMP(g_trac_fsi, "FsiDD::init> " );
- // nothing to do here...
-}
-
-
-
/**
* @brief Performs an FSI Read Operation to a relative address
diff --git a/src/usr/fsi/fsidd.H b/src/usr/fsi/fsidd.H
index 51dad9f54..b1f00e4d0 100644
--- a/src/usr/fsi/fsidd.H
+++ b/src/usr/fsi/fsidd.H
@@ -1,25 +1,26 @@
-// IBM_PROLOG_BEGIN_TAG
-// This is an automatically generated prolog.
-//
-// $Source: src/usr/fsi/fsidd.H $
-//
-// IBM CONFIDENTIAL
-//
-// COPYRIGHT International Business Machines Corp. 2011
-//
-// p1
-//
-// Object Code Only (OCO) source materials
-// Licensed Internal Code Source Materials
-// IBM HostBoot Licensed Internal Code
-//
-// The source code for this program is not published or other-
-// wise divested of its trade secrets, irrespective of what has
-// been deposited with the U.S. Copyright Office.
-//
-// Origin: 30
-//
-// IBM_PROLOG_END
+/* IBM_PROLOG_BEGIN_TAG
+ * This is an automatically generated prolog.
+ *
+ * $Source: src/usr/fsi/fsidd.H $
+ *
+ * IBM CONFIDENTIAL
+ *
+ * COPYRIGHT International Business Machines Corp. 2011-2012
+ *
+ * p1
+ *
+ * Object Code Only (OCO) source materials
+ * Licensed Internal Code Source Materials
+ * IBM HostBoot Licensed Internal Code
+ *
+ * The source code for this program is not published or other-
+ * wise divested of its trade secrets, irrespective of what has
+ * been deposited with the U.S. Copyright Office.
+ *
+ * Origin: 30
+ *
+ * IBM_PROLOG_END_TAG
+ */
#ifndef __FSI_FSIDD_H
#define __FSI_FSIDD_H
@@ -43,11 +44,6 @@
class FsiDD
{
public:
- /**
- * @brief Static Initializer
- * @param[in] Task Args pointer passed by init service
- */
- static void init( void* i_taskArgs );
/**
* @brief Initialize the FSI hardware
diff --git a/src/usr/hwpf/hwp/makefile b/src/usr/hwpf/hwp/makefile
index 2865f8f97..4437d463a 100644
--- a/src/usr/hwpf/hwp/makefile
+++ b/src/usr/hwpf/hwp/makefile
@@ -44,6 +44,7 @@ SUBDIRS = dmi_training.d sbe_centaur_init.d mc_init.d \
dram_training.d activate_powerbus.d build_winkle_images.d \
core_activate.d dram_initialization.d edi_ei_initialization.d \
establish_system_smp.d load_payload.d bus_training.d \
- nest_chiplets.d start_payload.d
+ nest_chiplets.d start_payload.d \
+ thread_activate.d
include ${ROOTPATH}/config.mk
diff --git a/src/usr/hwpf/hwp/thread_activate/makefile b/src/usr/hwpf/hwp/thread_activate/makefile
new file mode 100644
index 000000000..e76e6cb94
--- /dev/null
+++ b/src/usr/hwpf/hwp/thread_activate/makefile
@@ -0,0 +1,55 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: src/usr/hwpf/hwp/thread_activate/makefile $
+#
+# IBM CONFIDENTIAL
+#
+# COPYRIGHT International Business Machines Corp. 2012
+#
+# p1
+#
+# Object Code Only (OCO) source materials
+# Licensed Internal Code Source Materials
+# IBM HostBoot Licensed Internal Code
+#
+# The source code for this program is not published or other-
+# wise divested of its trade secrets, irrespective of what has
+# been deposited with the U.S. Copyright Office.
+#
+# Origin: 30
+#
+# IBM_PROLOG_END_TAG
+ROOTPATH = ../../../../..
+
+MODULE = thread_activate
+
+## support for Targeting and fapi
+EXTRAINCDIR += ${ROOTPATH}/src/include/usr/ecmddatabuffer
+EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/fapi
+EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/plat
+EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/hwp
+
+## pointer to common HWP files
+EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/include
+
+## NOTE: add the base istep dir here.
+EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/thread_activate
+
+## Include sub dirs
+## NOTE: add a new EXTRAINCDIR when you add a new HWP
+## EXAMPLE:
+## EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/thread_activate/<HWP_dir>
+
+
+## NOTE: add new object files when you add a new HWP
+OBJS = thread_activate.o
+
+
+## NOTE: add a new directory onto the vpaths when you add a new HWP
+## EXAMPLE:
+# VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/thread_activate/<HWP_dir>
+
+
+include ${ROOTPATH}/config.mk
+
diff --git a/src/usr/hwpf/hwp/thread_activate/thread_activate.C b/src/usr/hwpf/hwp/thread_activate/thread_activate.C
new file mode 100644
index 000000000..72a36bbbf
--- /dev/null
+++ b/src/usr/hwpf/hwp/thread_activate/thread_activate.C
@@ -0,0 +1,308 @@
+/* IBM_PROLOG_BEGIN_TAG
+ * This is an automatically generated prolog.
+ *
+ * $Source: src/usr/hwpf/hwp/thread_activate/thread_activate.C $
+ *
+ * IBM CONFIDENTIAL
+ *
+ * COPYRIGHT International Business Machines Corp. 2012
+ *
+ * p1
+ *
+ * Object Code Only (OCO) source materials
+ * Licensed Internal Code Source Materials
+ * IBM HostBoot Licensed Internal Code
+ *
+ * The source code for this program is not published or other-
+ * wise divested of its trade secrets, irrespective of what has
+ * been deposited with the U.S. Copyright Office.
+ *
+ * Origin: 30
+ *
+ * IBM_PROLOG_END_TAG
+ */
+/**
+ * @file thread_activate.C
+ *
+ * Support file to start non-primary threads
+ *
+ */
+
+/******************************************************************************/
+// Includes
+/******************************************************************************/
+#include <stdint.h>
+
+#include <initservice/taskargs.H>
+#include <errl/errlentry.H>
+
+#include <devicefw/userif.H>
+#include <sys/misc.h>
+
+// targeting support
+#include <targeting/common/commontargeting.H>
+#include <targeting/common/utilFilter.H>
+
+// fapi support
+#include <fapi.H>
+#include <fapiPlatHwpInvoker.H>
+#include <hwpf/plat/fapiPlatReasonCodes.H>
+#include <hwpf/plat/fapiPlatTrace.H>
+
+
+//@fixme - Patrick is adding this constant under 37009
+#define MAGIC_SIMICS_CORESTATESAVE 10
+
+namespace THREAD_ACTIVATE
+{
+
+
+void activate_threads( errlHndl_t& io_rtaskRetErrl )
+{
+ errlHndl_t l_errl = NULL;
+
+ TRACFCOMP( g_fapiTd,
+ "activate_threads entry" );
+
+ // get the master processor target
+ TARGETING::Target* l_masterProc = NULL;
+ TARGETING::targetService().masterProcChipTargetHandle( l_masterProc );
+ if( l_masterProc == NULL )
+ {
+ TRACFCOMP( g_fapiImpTd,
+ "Could not find master proc!!!" );
+ assert(false);
+ }
+
+ // get the list of core targets for this proc chip
+ TARGETING::TargetHandleList l_coreTargetList;
+ TARGETING::getChildChiplets( l_coreTargetList,
+ l_masterProc,
+ TARGETING::TYPE_EX,
+ false);
+
+ // find the core/thread we're running on
+ task_affinity_pin();
+ task_affinity_migrate_to_master(); //just in case...
+ uint64_t cpuid = task_getcpuid();
+ task_affinity_unpin();
+
+ //NNNCCCPPPPTTT
+ uint64_t l_masterCoreID = (cpuid & 0x0078)>>3;
+ uint64_t l_masterThreadID = (cpuid & 0x0007);
+
+ TARGETING::Target* l_masterCore = NULL;
+ for( TARGETING::TargetHandleList::iterator core_it
+ = l_coreTargetList.begin();
+ core_it != l_coreTargetList.end();
+ ++core_it )
+ {
+ uint8_t l_coreId = (*core_it)->getAttr<TARGETING::ATTR_CHIP_UNIT>();
+ if( l_coreId == l_masterCoreID )
+ {
+ l_masterCore = (*core_it);
+ break;
+ }
+ }
+ if( l_masterCore == NULL )
+ {
+ TRACFCOMP( g_fapiImpTd,
+ "Could not find a target for core %d",
+ l_masterCoreID );
+ /*@
+ * @errortype
+ * @moduleid fapi::MOD_THREAD_ACTIVATE
+ * @reasoncode fapi::RC_NO_MASTER_CORE_TARGET
+ * @userdata1 Master cpu id (NNNCCCPPPPTTT)
+ * @userdata2 Master processor chip huid
+ * @devdesc activate_threads> Could not find a target
+ * for the master core
+ */
+ l_errl = new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_UNRECOVERABLE,
+ fapi::MOD_THREAD_ACTIVATE,
+ fapi::RC_NO_MASTER_CORE_TARGET,
+ cpuid,
+ TARGETING::get_huid(l_masterProc));
+ l_errl->collectTrace("TARG",256);
+ l_errl->collectTrace(FAPI_TRACE_NAME,256);
+ l_errl->collectTrace(FAPI_IMP_TRACE_NAME,256);
+ io_rtaskRetErrl = l_errl;
+ return;
+ }
+
+ TRACFCOMP( g_fapiTd,
+ "Master CPU : c%d t%d (HUID=%.8X)",
+ l_masterCoreID, l_masterThreadID, TARGETING::get_huid(l_masterCore) );
+
+ // dump physical path to core target
+ TARGETING::EntityPath l_path;
+ l_path = l_masterCore->getAttr<TARGETING::ATTR_PHYS_PATH>();
+ l_path.dump();
+
+ // cast OUR type of target to a FAPI type of target.
+ const fapi::Target l_fapiCore(
+ fapi::TARGET_TYPE_EX_CHIPLET,
+ reinterpret_cast<void *>
+ (const_cast<TARGETING::Target*>(l_masterCore))
+ );
+
+ // loop around threads 0-6, SBE starts thread 7
+ uint64_t max_threads = cpu_thread_count();
+ for( uint64_t thread = 0; thread < max_threads; thread++ )
+ {
+ // Skip the thread that we're running on
+ if( thread == l_masterThreadID )
+ {
+ continue;
+ }
+
+ // send a magic instruction for PHYP Simics to work...
+ MAGIC_INSTRUCTION(MAGIC_SIMICS_CORESTATESAVE);
+
+ //@todo - call the real proc_thread_control HWP (RTC:42816)
+#if 0
+ // parameters: i_target => core target
+ // i_thread => thread (0..7)
+ // i_sreset => initiate sreset thread command
+ // i_start => initiate start thread command
+ // i_stop => initiate stop thread command
+ // i_step => initiate step thread command
+ // i_activate => initiate activate thread command
+ // i_query => query and return thread state
+ // return data in o_thread_state
+ // o_thread_state => output: thread state
+ uint8_t l_threadState = false;
+ FAPI_INVOKE_HWP( l_errl, proc_thread_control,
+ l_fapiCore, //i_target
+ thread, //i_thread
+ true, //i_sreset
+ false, //i_start
+ false, //i_stop
+ false, //i_step
+ false, //i_activate
+ false, //i_query
+ l_threadState ); //o_thread_state
+ if ( l_errl )
+ {
+ TRACFCOMP( g_fapiImpTd,
+ "ERROR: 0x%.8X : proc_thread_control HWP( cpu %d, thread %d )",
+ l_errl->reasonCode(),
+ l_masterCoreID,
+ thread );
+ // if 1 thread fails it is unlikely that other threads will work
+ // so we'll just jump out now
+ break;
+ }
+ else
+ {
+ TRACFCOMP( g_fapiTd,
+ "SUCCESS: 0x%.8X : proc_thread_control HWP( cpu %d, thread %d )",
+ l_errl->reasonCode(),
+ l_masterCoreID,
+ thread );
+ }
+#else
+ //@todo - Temp version, just do the scoms manually (RTC:42816)
+ size_t scom_size = sizeof(uint64_t);
+ uint32_t directControlAddr = 0x10013000 + (thread << 4);
+ uint32_t rasStatAddr = 0x10013002 + (thread << 4);
+
+ // Check the initial state
+ uint64_t statreg = 0;
+ l_errl = deviceRead( l_masterCore,
+ &statreg,
+ scom_size,
+ DEVICE_SCOM_ADDRESS(rasStatAddr) );
+ if( l_errl ) { break; }
+
+ // Make sure the thread is in maintenance mode
+ if( !(statreg & 0x0000040000000000) ) //21:PTC_RAS_STAT_MAINT
+ {
+ TRACFCOMP( g_fapiImpTd,
+ "ERROR: Thread c%d t%d is in the wrong state : Status=%.16X",
+ l_masterCoreID,
+ thread,
+ statreg );
+ /*@
+ * @errortype
+ * @moduleid fapi::MOD_THREAD_ACTIVATE
+ * @reasoncode fapi::RC_THREAD_IN_WRONG_STATE
+ * @userdata1 Thread RAS Status Scom Addr
+ * @userdata2 Thread RAS Status Data
+ * @devdesc activate_threads> Thread start attempted on
+ * thread that is not in maintenance mode
+ */
+ l_errl = new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_UNRECOVERABLE,
+ fapi::MOD_THREAD_ACTIVATE,
+ fapi::RC_THREAD_IN_WRONG_STATE,
+ rasStatAddr,
+ statreg);
+ l_errl->collectTrace(FAPI_TRACE_NAME,256);
+ l_errl->collectTrace(FAPI_IMP_TRACE_NAME,256);
+ break;
+
+ }
+
+ // Start the thread
+ uint64_t ctlreg = 0x0000000000000008; //60:PTC_DIR_CTL_SP_SRESET
+ l_errl = deviceWrite( l_masterCore,
+ &ctlreg,
+ scom_size,
+ DEVICE_SCOM_ADDRESS(directControlAddr) );
+ if( l_errl ) { break; }
+
+ // Make sure we really started
+ l_errl = deviceRead( l_masterCore,
+ &statreg,
+ scom_size,
+ DEVICE_SCOM_ADDRESS(rasStatAddr) );
+ if( l_errl ) { break; }
+
+ if( !(statreg & 0x0000000000001000) ) //51:PTC_RAS_STAT_RUN_BIT
+ {
+ TRACFCOMP( g_fapiImpTd,
+ "ERROR: Thread c%d t%d did not start : Status=%.16X",
+ l_masterCoreID,
+ thread,
+ statreg );
+ /*@
+ * @errortype
+ * @moduleid fapi::MOD_THREAD_ACTIVATE
+ * @reasoncode fapi::RC_THREAD_DID_NOT_START
+ * @userdata1 Thread RAS Status Scom Addr
+ * @userdata2 Thread RAS Status Data
+ * @devdesc activate_threads> Thread did not start
+ */
+ l_errl = new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_UNRECOVERABLE,
+ fapi::MOD_THREAD_ACTIVATE,
+ fapi::RC_THREAD_DID_NOT_START,
+ rasStatAddr,
+ statreg);
+ l_errl->collectTrace(FAPI_TRACE_NAME,256);
+ l_errl->collectTrace(FAPI_IMP_TRACE_NAME,256);
+ break;
+
+ }
+#endif
+
+ TRACFCOMP( g_fapiTd,
+ "SUCCESS: Thread c%d t%d started",
+ l_masterCoreID,
+ thread );
+
+ }
+
+ TRACFCOMP( g_fapiTd,
+ "activate_threads exit" );
+
+ io_rtaskRetErrl = l_errl;
+ return;
+}
+
+}; // end namespace
+
+/**
+ * @brief set up _start() task entry procedure for PNOR daemon
+ */
+TASK_ENTRY_MACRO( THREAD_ACTIVATE::activate_threads );
+
diff --git a/src/usr/initservice/extinitsvc/extinitsvctasks.H b/src/usr/initservice/extinitsvc/extinitsvctasks.H
index f9cbb9ff8..4a0ae8c17 100644
--- a/src/usr/initservice/extinitsvc/extinitsvctasks.H
+++ b/src/usr/initservice/extinitsvc/extinitsvctasks.H
@@ -107,12 +107,12 @@ const TaskInfo g_exttaskinfolist[] = {
* @brief FSI SCOM Device Driver
*/
{
- "libfsiscom.so" , // taskname
- NULL, // no pointer to fn
- {
- INIT_TASK, // task type
- EXT_IMAGE, // Extended Module
- }
+ "libfsiscom.so" , // taskname
+ NULL, // no pointer to fn
+ {
+ INIT_TASK, // task type
+ EXT_IMAGE, // Extended Module
+ }
},
/**
@@ -218,6 +218,18 @@ const TaskInfo g_exttaskinfolist[] = {
}
},
+ /**
+ * @brief Start slave threads
+ */
+ {
+ "libthread_activate.so" , // taskname
+ NULL, // no pointer to fn
+ {
+ START_TASK, // task type
+ EXT_IMAGE, // Extended Module
+ }
+ },
+
// TODO: Should these be automatically loaded / unloaded by istepdispatcher?
/**
* @brief VSBE FAPI interface code library.
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