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-rw-r--r--src/include/sys/mmio.h4
-rw-r--r--src/kernel/exception.C10
-rw-r--r--src/kernel/makefile4
-rw-r--r--src/kernel/softpatch_p8.S (renamed from src/kernel/softpatch_p7.S)50
-rw-r--r--src/makefile22
-rw-r--r--src/usr/intr/intrrp.C10
-rw-r--r--src/usr/intr/intrrp.H28
7 files changed, 51 insertions, 77 deletions
diff --git a/src/include/sys/mmio.h b/src/include/sys/mmio.h
index a00f124a1..610db0124 100644
--- a/src/include/sys/mmio.h
+++ b/src/include/sys/mmio.h
@@ -5,7 +5,7 @@
/* */
/* IBM CONFIDENTIAL */
/* */
-/* COPYRIGHT International Business Machines Corp. 2010,2012 */
+/* COPYRIGHT International Business Machines Corp. 2010,2013 */
/* */
/* p1 */
/* */
@@ -77,8 +77,6 @@ void mmio_hmer_write(uint64_t value);
* mmio_scratch_read / mmio_scratch_write.
*
* These values come from the Chip Pervasive Spec.
- *
- * TODO: Verify that P7/P8 offsets are the same.
*/
enum MMIO_Scratch_Register
{
diff --git a/src/kernel/exception.C b/src/kernel/exception.C
index d1b365535..80e04fc34 100644
--- a/src/kernel/exception.C
+++ b/src/kernel/exception.C
@@ -5,7 +5,7 @@
/* */
/* IBM CONFIDENTIAL */
/* */
-/* COPYRIGHT International Business Machines Corp. 2010,2012 */
+/* COPYRIGHT International Business Machines Corp. 2010,2013 */
/* */
/* p1 */
/* */
@@ -207,7 +207,7 @@ void kernel_execute_fp_unavail()
const uint64_t EXCEPTION_HSRR1_SOFTPATCH_MASK = 0x0000000000100000;
const uint64_t EXCEPTION_HSRR1_SOFTPATCH_DENORM = 0x0000000000100000;
-extern "C" void p7_softpatch_denorm_assist(context_fp_t*);
+extern "C" void p8_softpatch_denorm_assist(context_fp_t*);
extern "C"
void kernel_execute_softpatch()
@@ -225,10 +225,10 @@ void kernel_execute_softpatch()
switch (CpuID::getCpuType())
{
- case CORE_POWER8_MURANO: // @TODO: Verify same procedure.
- case CORE_POWER8_VENICE: // @TODO: Verify same procedure.
+ case CORE_POWER8_MURANO:
+ case CORE_POWER8_VENICE:
case CORE_UNKNOWN:
- p7_softpatch_denorm_assist(t->fp_context);
+ p8_softpatch_denorm_assist(t->fp_context);
break;
}
}
diff --git a/src/kernel/makefile b/src/kernel/makefile
index 67766b2b8..a3a750dcb 100644
--- a/src/kernel/makefile
+++ b/src/kernel/makefile
@@ -5,7 +5,7 @@
#
# IBM CONFIDENTIAL
#
-# COPYRIGHT International Business Machines Corp. 2010,2012
+# COPYRIGHT International Business Machines Corp. 2010,2013
#
# p1
#
@@ -26,7 +26,7 @@ OBJS = start.o kernel.o console.o pagemgr.o heapmgr.o taskmgr.o cpumgr.o
OBJS += syscall.o scheduler.o spinlock.o exception.o vmmmgr.o timemgr.o
OBJS += futexmgr.o ptmgr.o segmentmgr.o devicesegment.o basesegment.o
OBJS += block.o cpuid.o misc.o msghandler.o blockmsghdlr.o stacksegment.o
-OBJS += softpatch_p7.o barrier.o idebug.o intmsghandler.o deferred.o
+OBJS += softpatch_p8.o barrier.o idebug.o intmsghandler.o deferred.o
OBJS += shutdown.o forceattn_p8.o terminate.o
include ${ROOTPATH}/config.mk
diff --git a/src/kernel/softpatch_p7.S b/src/kernel/softpatch_p8.S
index 3e1da328a..e28eb2eb2 100644
--- a/src/kernel/softpatch_p7.S
+++ b/src/kernel/softpatch_p8.S
@@ -1,28 +1,28 @@
-# IBM_PROLOG_BEGIN_TAG
-# This is an automatically generated prolog.
-#
-# $Source: src/kernel/softpatch_p7.S $
-#
-# IBM CONFIDENTIAL
-#
-# COPYRIGHT International Business Machines Corp. 2011
-#
-# p1
-#
-# Object Code Only (OCO) source materials
-# Licensed Internal Code Source Materials
-# IBM HostBoot Licensed Internal Code
-#
-# The source code for this program is not published or other-
-# wise divested of its trade secrets, irrespective of what has
-# been deposited with the U.S. Copyright Office.
-#
-# Origin: 30
-#
-# IBM_PROLOG_END
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: src/kernel/softpatch_p8.S $
+#
+# IBM CONFIDENTIAL
+#
+# COPYRIGHT International Business Machines Corp. 2011,2013
+#
+# p1
+#
+# Object Code Only (OCO) source materials
+# Licensed Internal Code Source Materials
+# IBM HostBoot Licensed Internal Code
+#
+# The source code for this program is not published or otherwise
+# divested of its trade secrets, irrespective of what has been
+# deposited with the U.S. Copyright Office.
+#
+# Origin: 30
+#
+# IBM_PROLOG_END_TAG
.include "kernel/ppcconsts.S"
-/** @fn p7_softpatch_denorm_assist
+/** @fn p8_softpatch_denorm_assist
* @brief Performs denormalization assistance for floating point operations.
*
* Called by the softpatch exception when a denormalization assistance is
@@ -35,8 +35,8 @@
* Destroys the data in r4/r5. This is safe by the ABI since these are
* parameter registers which are otherwise unused by this function.
*/
-.global p7_softpatch_denorm_assist
-p7_softpatch_denorm_assist:
+.global p8_softpatch_denorm_assist
+p8_softpatch_denorm_assist:
mfmsr r4 # Load the MSR
oris r5,r4,0x2080 # Turn on FP,VSX available
mtmsrd r5 # Set the MSR
diff --git a/src/makefile b/src/makefile
index 0dd1fb12c..a5e788bc5 100644
--- a/src/makefile
+++ b/src/makefile
@@ -1,25 +1,25 @@
# IBM_PROLOG_BEGIN_TAG
# This is an automatically generated prolog.
-#
+#
# $Source: src/makefile $
-#
+#
# IBM CONFIDENTIAL
-#
-# COPYRIGHT International Business Machines Corp. 2010,2012
-#
+#
+# COPYRIGHT International Business Machines Corp. 2010,2013
+#
# p1
-#
+#
# Object Code Only (OCO) source materials
# Licensed Internal Code Source Materials
# IBM HostBoot Licensed Internal Code
-#
+#
# The source code for this program is not published or otherwise
# divested of its trade secrets, irrespective of what has been
# deposited with the U.S. Copyright Office.
-#
+#
# Origin: 30
-#
-# IBM_PROLOG_END_TAG
+#
+# IBM_PROLOG_END_TAG
ROOTPATH = ..
@@ -43,7 +43,7 @@ DIRECT_BOOT_OBJECTS = start.o kernel.o taskmgr.o cpumgr.o syscall.o \
syscall_mm.o init_main.o vfs_main.o sync.o futexmgr.o \
ptmgr.o segmentmgr.o basesegment.o devicesegment.o \
block.o cxxtest_data.o cpuid.o misc.o msghandler.o \
- blockmsghdlr.o stacksegment.o softpatch_p7.o \
+ blockmsghdlr.o stacksegment.o softpatch_p8.o \
shutdown.o forceattn_p8.o terminate.o
BASE_MODULES = trace errl devicefw scom xscom initservice \
diff --git a/src/usr/intr/intrrp.C b/src/usr/intr/intrrp.C
index f667220f3..d00dc5f8e 100644
--- a/src/usr/intr/intrrp.C
+++ b/src/usr/intr/intrrp.C
@@ -5,7 +5,7 @@
/* */
/* IBM CONFIDENTIAL */
/* */
-/* COPYRIGHT International Business Machines Corp. 2011,2012 */
+/* COPYRIGHT International Business Machines Corp. 2011,2013 */
/* */
/* p1 */
/* */
@@ -71,11 +71,7 @@ void IntrRp::init( errlHndl_t &io_errlHndl_t )
// ICPBAR = INTP.ICP_BAR[0:25] in P8 = 0x3FFFF800 + (8*node) + procPos
-// P7 Scom address 0x02011C09 P8 = 0x020109c9
-// BaseAddress P7:
-// BA[18:43] = ICPBAR (P8 says [14:43] (30 bits))
-// BA[47:49] = COREid (0-7)
-// BA[50:51] = cpu thread (0-3)
+// P8 Scom address = 0x020109c9
//
// BaseAddress P8:
// BA[14:43] = ICPBAR (30 bits)
@@ -427,7 +423,7 @@ void IntrRp::msgHandler()
case MSG_INTR_ENABLE_PSI_INTR:
{
- TARGETING::Target * target =
+ TARGETING::Target * target =
reinterpret_cast<TARGETING::Target *>(msg->data[0]);
errlHndl_t err = initIRSCReg(target);
msg->data[1] = reinterpret_cast<uint64_t>(err);
diff --git a/src/usr/intr/intrrp.H b/src/usr/intr/intrrp.H
index ad13c1679..2a32edca4 100644
--- a/src/usr/intr/intrrp.H
+++ b/src/usr/intr/intrrp.H
@@ -5,7 +5,7 @@
/* */
/* IBM CONFIDENTIAL */
/* */
-/* COPYRIGHT International Business Machines Corp. 2011,2012 */
+/* COPYRIGHT International Business Machines Corp. 2011,2013 */
/* */
/* p1 */
/* */
@@ -27,6 +27,7 @@
#include <builtins.h>
#include <limits.h>
#include <errl/errlentry.H>
+#include <kernel/intmsghandler.H>
#include <sys/msg.h>
#include <sys/misc.h>
#include <intr/interrupt.H>
@@ -143,7 +144,7 @@ namespace INTR
LINKC_OFFSET = 24, //!< offset to LINKC register
XISR_MASK = 0x00FFFFFF, //!< XISR MASK in XIRR register
- ICPBAR_EN = 30, //!< BAR enable bit pos
+ ICPBAR_EN = 30, //!< BAR enable bit pos
ICPBAR_SCOM_ADDR = 0x020109ca, //!< ICP BAR scom address
// MASK base ICP address
@@ -153,14 +154,6 @@ namespace INTR
// If the interrupt can't be handled by the current chip there are
// three link registers used provide targets to forward the
// interrupt to.
- // P7:
- // [0] last
- // [1] LoopTrip
- // [2:18] Reserved
- // [19:24] PChip
- // [25:27] PCore
- // [28:29] TSpec
- // [30:31] LSpec
//
// P8:
// [0] last
@@ -422,20 +415,7 @@ namespace INTR
ALWAYS_INLINE
uint64_t cpuOffsetAddr(const PIR_t i_pir) const
{
- // TODO when P7 support is removed then change this
- // to use InterruptMsgHdlr::mmio_offset()
- uint64_t offset = (i_pir.nodeId * 8) + i_pir.chipId;
- offset <<= 20;
- switch (cpu_core_type())
- {
- case CORE_POWER8_MURANO:
- case CORE_POWER8_VENICE:
- default:
- offset |= static_cast<uint64_t>(i_pir.coreId) << 15;
- break;
- }
- offset |= static_cast<uint64_t>(i_pir.threadId) << 12;
- return offset;
+ return InterruptMsgHdlr::mmio_offset(i_pir.word);
}
/**
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