diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_memory_attributes.xml | 424 | ||||
| -rw-r--r-- | src/usr/hwpf/makefile | 3 | ||||
| -rw-r--r-- | src/usr/targeting/common/xmltohb/attribute_types.xml | 441 | ||||
| -rwxr-xr-x | src/usr/targeting/common/xmltohb/common.mk | 1 | ||||
| -rwxr-xr-x | src/usr/targeting/common/xmltohb/target_types.xml | 21 |
5 files changed, 454 insertions, 436 deletions
diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_memory_attributes.xml b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_memory_attributes.xml deleted file mode 100644 index 163f8c3f5..000000000 --- a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_memory_attributes.xml +++ /dev/null @@ -1,424 +0,0 @@ -<!-- IBM_PROLOG_BEGIN_TAG --> -<!-- This is an automatically generated prolog. --> -<!-- --> -<!-- $Source: src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_memory_attributes.xml $ --> -<!-- --> -<!-- OpenPOWER HostBoot Project --> -<!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2012,2015 --> -<!-- [+] International Business Machines Corp. --> -<!-- --> -<!-- --> -<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> -<!-- you may not use this file except in compliance with the License. --> -<!-- You may obtain a copy of the License at --> -<!-- --> -<!-- http://www.apache.org/licenses/LICENSE-2.0 --> -<!-- --> -<!-- Unless required by applicable law or agreed to in writing, software --> -<!-- distributed under the License is distributed on an "AS IS" BASIS, --> -<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> -<!-- implied. See the License for the specific language governing --> -<!-- permissions and limitations under the License. --> -<!-- --> -<!-- IBM_PROLOG_END_TAG --> -<!-- $Id: proc_setup_bars_memory_attributes.xml,v 1.15 2015/01/22 17:16:36 jmcgill Exp $ --> -<!-- proc_setup_bars_memory_attributes.xml --> -<attributes> - <!-- ********************************************************************* --> - <attribute> - <id>ATTR_MEM_MIRROR_PLACEMENT_POLICY</id> - <targetType>TARGET_TYPE_SYSTEM</targetType> - <description>Define placement policy/scheme for non-mirrored/mirrored memory - layout - creator: platform - consumer: opt_memmap - firmware notes: - NORMAL = non-mirrored start: 0, mirrored start: 512TB - FLIPPED = mirrored start: 0, non-mirrored start: 512TB - SELECTIVE = non-mirrored/mirrored start (interleaved): 0 - DRAWER = non-mirrored start: 32TB*drawer, mirrored start: 512TB+(32TB*drawer) - FLIPPED_DRAWER = mirrored start: 32TB * drawer, non-mirrored start: 512TB+(32TB*drawer) - </description> - <valueType>uint8</valueType> - <enum> - NORMAL = 0x0, - FLIPPED = 0x1, - SELECTIVE = 0x2, - DRAWER = 0x3, - FLIPPED_DRAWER = 0x4 - </enum> - <platInit/> - <persistRuntime/> - </attribute> - <!-- ********************************************************************* --> - <attribute> - <id>ATTR_OPT_MEMMAP_GROUP_POLICY</id> - <targetType>TARGET_TYPE_SYSTEM</targetType> - <description> - Controls scope of group consideration in memory map calculations - creator: platform - consumer: opt_memmap - </description> - <valueType>uint8</valueType> - <enum> - CHIP_AS_GROUP = 0x0, - GROUP_AS_GROUP = 0x1 - </enum> - <platInit/> - <persistRuntime/> - </attribute> - <!-- ********************************************************************* --> - <attribute> - <id>ATTR_MIRROR_BASE_ADDRESS</id> - <targetType>TARGET_TYPE_SYSTEM</targetType> - <description> - System-level base address for the start of mirrored memory. - Defined by platform as part of the global memory map. - </description> - <valueType>uint64</valueType> - <platInit/> - <persistRuntime/> - </attribute> - <!-- ********************************************************************* --> - <attribute> - <id>ATTR_PROC_MEM_BASE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Base address for non-mirrored memory regions - creator: platform (proc_config_base_addr) - consumer: mss_setup_bars - firmware notes: - 64-bit RA - </description> - <valueType>uint64</valueType> - <writeable/> - <persistRuntime/> - </attribute> - <!-- ********************************************************************* --> - <attribute> - <id>ATTR_PROC_MEM_BASES</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Non-mirrored memory base addresses - creator: mss_setup_bars - consumer: proc_setup_bars, platform - firmware notes: - 64-bit RA - eight independent non-mirrored segments are supported - (max number based on Venice design) - </description> - <valueType>uint64</valueType> - <array>8</array> - <writeable/> - <persistRuntime/> - </attribute> - <!-- ********************************************************************* --> - <attribute> - <id>ATTR_PROC_MEM_BASES_ACK</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Non-mirrored memory base addresses - creator: mss_setup_bars - consumer: opt_mem_map - Mem opt map uses this for the bases of the non-mirror ranges. - (max number based on Venice design) - </description> - <valueType>uint64</valueType> - <array>8</array> - <writeable/> - <persistRuntime/> - </attribute> - <!-- ********************************************************************* --> - <attribute> - <id>ATTR_PROC_MEM_SIZES</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Size of non-mirrored memory regions - creator: mss_setup_bars - consumer: proc_setup_bars, platform - firmware notes: - for given index value, address space assumed to be contiguous - from ATTR_PROC_MEM_BASES value at matching index - eight independent non-mirrored segments are supported - (max number based on Venice design) - </description> - <valueType>uint64</valueType> - <array>8</array> - <writeable/> - <persistRuntime/> - </attribute> - <!-- ********************************************************************* --> - <attribute> - <id>ATTR_PROC_MEM_SIZES_ACK</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Size of non-mirrored memory regions up to a power of 2 - creator: mss_setup_bars - consumer: opt_mem_map - Mem opt map uses this to stack mirror ranges. The real amount of memory behind the mirror group maybe less than the number reported here if there are memory holes - </description> - <valueType>uint64</valueType> - <array>8</array> - <writeable/> - <persistRuntime/> - </attribute> - <!-- ********************************************************************* --> - <attribute> - <id>ATTR_PROC_MIRROR_BASE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Base address for mirrored memory regions - creator: platform (proc_config_base_addr) - consumer: mss_setup_bars - firmware notes: - 64-bit RA - </description> - <valueType>uint64</valueType> - <writeable/> - <persistRuntime/> - </attribute> - <!-- ********************************************************************* --> - <attribute> - <id>ATTR_PROC_MIRROR_BASES</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Mirrored memory base addresses - creator: mss_setup_bars - consumer: proc_setup_bars, platform - firmware notes: - 64-bit RA - four independent mirrored segments are supported - (max number based on Venice design) - </description> - <valueType>uint64</valueType> - <array>4</array> - <writeable/> - <persistRuntime/> - </attribute> - <!-- ********************************************************************* --> - <attribute> - <id>ATTR_PROC_MIRROR_BASES_ACK</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Mirrored memory base addresses - creator: mss_setup_bars - consumer: consumer: opt_mem_map - Mem opt map uses this for the bases of the mirror ranges. - (max number based on Venice design) - </description> - <valueType>uint64</valueType> - <array>4</array> - <writeable/> - <persistRuntime/> - </attribute> - <!-- ********************************************************************* --> - <attribute> - <id>ATTR_PROC_MIRROR_SIZES</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Size of mirrored memory region - creator: mss_setup_bars - consumer: proc_setup_bars, platform - firmware notes: - for given index value, address space assumed to be contiguous - from ATTR_PROC_MIRROR_BASES value at matching index - four independent mirrored segments are supported - (max number based on Venice design) - </description> - <valueType>uint64</valueType> - <array>4</array> - <writeable/> - <persistRuntime/> - </attribute> - <!-- ********************************************************************* --> - <attribute> - <id>ATTR_PROC_MIRROR_SIZES_ACK</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Size of mirrored memory region up to a power of 2 - creator: mss_setup_bars - consumer: opt_mem_map - Mem opt map uses this to stack mirror ranges. The real amount of memory behind the mirror group maybe less than the number reported here if there are memory holes - </description> - <valueType>uint64</valueType> - <array>4</array> - <writeable/> - <persistRuntime/> - </attribute> - <!-- ********************************************************************* --> - <attribute> - <id>ATTR_PROC_FOREIGN_NEAR_BASE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Foreign (near) address region base address - creator: platform - consumer: proc_setup_bars - firmware notes: - 64-bit RA - two independent regions are supported - (one per foreign link) - </description> - <valueType>uint64</valueType> - <array>2</array> - <platInit/> - <persistRuntime/> - </attribute> - <!-- ********************************************************************* --> - <attribute> - <id>ATTR_PROC_FOREIGN_NEAR_SIZE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Size of foreign (near) region - creator: platform - consumer: proc_setup_bars - firmware notes: - address space assumed to be contiguous from associated - ATTR_PROC_FOREIGN_NEAR_BASE for given index value - two independent regions are supported - (one per foreign link) - </description> - <valueType>uint64</valueType> - <array>2</array> - <platInit/> - <persistRuntime/> - </attribute> - <!-- ********************************************************************* --> - <attribute> - <id>ATTR_PROC_FOREIGN_FAR_BASE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Foreign (far) address region base address - creator: platform - consumer: proc_setup_bars - firmware notes: - 64-bit RA - two independent regions are supported - (one per foreign link) - </description> - <valueType>uint64</valueType> - <array>2</array> - <platInit/> - <persistRuntime/> - </attribute> - <!-- ********************************************************************* --> - <attribute> - <id>ATTR_PROC_FOREIGN_FAR_SIZE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Size of foreign (far) region - creator: platform - consumer: proc_setup_bars - firmware notes: - address space assumed to be contiguous from associated - ATTR_PROC_FOREIGN_FAR_BASE for given index value - two independent regions are supported - (one per foreign link) - </description> - <valueType>uint64</valueType> - <array>2</array> - <platInit/> - <persistRuntime/> - </attribute> - <!-- ********************************************************************* --> - <attribute> - <id>ATTR_PROC_HA_BASE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>HA logging base address - firmware notes: - 64-bit RA - eight independent segments are supported - (max number based on Venice design) - </description> - <valueType>uint64</valueType> - <array>8</array> - <platInit/> - <persistRuntime/> - </attribute> - <!-- ********************************************************************* --> - <attribute> - <id>ATTR_PROC_HA_SIZE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Size of HA memory region - firmware notes: - address space assumed to be contiguous from associated - ATTR_PROC_HA_BASE for given index value - eight independent segments are supported - (max number based on Venice design) - </description> - <valueType>uint64</valueType> - <array>8</array> - <platInit/> - <persistRuntime/> - </attribute> - <!-- ********************************************************************* --> - <attribute> - <id>ATTR_PROC_HTM_BAR_SIZE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Desired HTM trace memory size value - creator: platform - firmware notes: - set by platform to request size of per-chip area reserved - for HTM trace memory - </description> - <valueType>uint64</valueType> - <enum> - 256_GB = 0x0000004000000000, - 128_GB = 0x0000002000000000, - 64_GB = 0x0000001000000000, - 32_GB = 0x0000000800000000, - 16_GB = 0x0000000400000000, - 8_GB = 0x0000000200000000, - 4_GB = 0x0000000100000000, - 2_GB = 0x0000000080000000, - 1_GB = 0x0000000040000000, - 512_MB = 0x0000000020000000, - 256_MB = 0x0000000010000000, - 128_MB = 0x0000000008000000, - 64_MB = 0x0000000004000000, - 32_MB = 0x0000000002000000, - 16_MB = 0x0000000001000000, - ZERO = 0x0000000000000000 - </enum> - <platInit/> - <persistRuntime/> - </attribute> - <!-- ********************************************************************* --> - <attribute> - <id>ATTR_PROC_HTM_BAR_BASE_ADDR</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>HTM trace memory base address allocated - </description> - <valueType>uint64</valueType> - <writeable/> - <persistRuntime/> - </attribute> - <!-- ********************************************************************* --> - <attribute> - <id>ATTR_PROC_OCC_SANDBOX_SIZE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Desired size of OCC sandbox memory region - creator: platform - firmware notes: - set by platform to request size of per-chip area reserved - for OCC sandbox function - </description> - <valueType>uint64</valueType> - <enum> - 256_GB = 0x0000004000000000, - 128_GB = 0x0000002000000000, - 64_GB = 0x0000001000000000, - 32_GB = 0x0000000800000000, - 16_GB = 0x0000000400000000, - 8_GB = 0x0000000200000000, - 4_GB = 0x0000000100000000, - 2_GB = 0x0000000080000000, - 1_GB = 0x0000000040000000, - 512_MB = 0x0000000020000000, - 256_MB = 0x0000000010000000, - 128_MB = 0x0000000008000000, - 64_MB = 0x0000000004000000, - 32_MB = 0x0000000002000000, - 16_MB = 0x0000000001000000, - ZERO = 0x0000000000000000 - </enum> - <platInit/> - <persistRuntime/> - </attribute> - <!-- ********************************************************************* --> - <attribute> - <id>ATTR_PROC_OCC_SANDBOX_BASE_ADDR</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>OCC sandbox base address allocated - </description> - <valueType>uint64</valueType> - <writeable/> - <persistRuntime/> - </attribute> -</attributes> diff --git a/src/usr/hwpf/makefile b/src/usr/hwpf/makefile index 0b891bb7a..cf3e35a15 100644 --- a/src/usr/hwpf/makefile +++ b/src/usr/hwpf/makefile @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2011,2015 +# Contributors Listed Below - COPYRIGHT 2011,2016 # [+] International Business Machines Corp. # # @@ -183,7 +183,6 @@ HWP_ATTR_XML_FILES += hwp/chip_ec_attributes.xml HWP_ATTR_XML_FILES += hwp/centaur_ec_attributes.xml HWP_ATTR_XML_FILES += hwp/common_attributes.xml HWP_ATTR_XML_FILES += hwp/sync_attributes.xml -HWP_ATTR_XML_FILES += hwp/dram_initialization/proc_setup_bars/proc_setup_bars_memory_attributes.xml HWP_ATTR_XML_FILES += hwp/dram_initialization/proc_setup_bars/proc_setup_bars_l3_attributes.xml HWP_ATTR_XML_FILES += hwp/dram_initialization/proc_setup_bars/proc_setup_bars_mmio_attributes.xml HWP_ATTR_XML_FILES += hwp/activate_powerbus/proc_build_smp/proc_fab_smp_fabric_attributes.xml diff --git a/src/usr/targeting/common/xmltohb/attribute_types.xml b/src/usr/targeting/common/xmltohb/attribute_types.xml index bc514ebc5..cc87b86b4 100644 --- a/src/usr/targeting/common/xmltohb/attribute_types.xml +++ b/src/usr/targeting/common/xmltohb/attribute_types.xml @@ -2352,13 +2352,15 @@ Provided by the Machine Readable Workbook. Can vary across drawers. </description> - <simpleType><uint8_t> - <default>0</default> - </uint8_t></simpleType> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> <persistency>non-volatile</persistency> <readable/> <hwpfToHbAttrMap> - <id>ATTR_FABRIC_GROUP_ID</id> + <id>ATTR_PROC_FABRIC_GROUP_ID</id> <macro>DIRECT</macro> </hwpfToHbAttrMap> </attribute> @@ -2371,13 +2373,15 @@ Provided by the Machine Readable Workbook. Can vary across drawers. </description> - <simpleType><uint8_t> - <default>0</default> - </uint8_t></simpleType> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> <persistency>non-volatile</persistency> <readable/> <hwpfToHbAttrMap> - <id>ATTR_FABRIC_CHIP_ID</id> + <id>ATTR_PROC_FABRIC_CHIP_ID</id> <macro>DIRECT</macro> </hwpfToHbAttrMap> </attribute> @@ -12305,6 +12309,7 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript </simpleType> <persistency>non-volatile</persistency> <readable/> + <writeable/> <hwpfToHbAttrMap> <id>ATTR_PROC_OCC_SANDBOX_SIZE</id> <macro>DIRECT</macro> @@ -19993,4 +19998,424 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript <virtual/> </attribute> +<!-- ********************************************************************** --> +<attribute> + <id>FREQ_CORE_CEILING_MHZ</id> + <!-- <targetType>TARGET_TYPE_SYSTEM</targetType> --> + <description> + The maximum core frequency in MHz. + This is the same for all cores in the system. + Provided by the MRW. + </description> + <simpleType> + <uint32_t></uint32_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <hwpfToHbAttrMap> + <id>ATTR_FREQ_CORE_CEILING</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PROC_FABRIC_A_BUS_WIDTH</id> + <!-- <targetType>TARGET_TYPE_SYSTEM</targetType> --> + <description> + Processor SMP A bus width. + Provided by the MRW. + 2_BYTE = 0x01, 4_BYTE = 0x02 + </description> + <simpleType><uint8_t></uint8_t></simpleType> + <persistency>non-volatile</persistency> + <readable/> + <hwpfToHbAttrMap> + <id>ATTR_PROC_FABRIC_A_BUS_WIDTH</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PROC_FABRIC_X_BUS_WIDTH</id> + <!-- <targetType>TARGET_TYPE_SYSTEM</targetType> --> + <description> + Processor SMP X bus width. + Provided by the MRW. + 2_BYTE = 0x01, 4_BYTE = 0x02 + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <hwpfToHbAttrMap> + <id>ATTR_PROC_FABRIC_X_BUS_WIDTH</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PROC_FABRIC_CCSM_MODE</id> + <!-- <targetType>TARGET_TYPE_SYSTEM</targetType> --> + <description> + Processor SMP topology configuration. + 0 = default = 1 or 2 hop topology (PHYP image spans system) + 1 = 3 hop topology (PHYP image spans group). + Provided by the MRW. + OFF = 0x0 (default), ON = 0x1 + </description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <hwpfToHbAttrMap> + <id>ATTR_PROC_FABRIC_CCSM_MODE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>OPTICS_CONFIG_MODE</id> + <!-- <targetType>TARGET_TYPE_OBUS</targetType> --> + <description> + Per-link optics configuration + 0 = SMP (default) + 1 = CAPI 2.0 + 2 = NV 2.0 + Provided by the MRW. + </description> + <simpleType> + <uint8_t> + <default>0,0,0,0</default> + </uint8_t> + <array>4</array> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <hwpfToHbAttrMap> + <id>ATTR_OPTICS_CONFIG_MODE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PROC_FABRIC_SMP_OPTICS_MODE</id> + <!-- <targetType>TARGET_TYPE_SYSTEM</targetType> --> + <description> + Processor SMP optics mode. + 0 = Optics_is_X_bus (default) + 1 = Optics_is_A_bus + Provided by the MRW. + OPTICS_IS_X_BUS = 0x0, OPTICS_IS_A_BUS = 0x1 + </description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <hwpfToHbAttrMap> + <id>ATTR_PROC_FABRIC_SMP_OPTICS_MODE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PROC_FABRIC_CAPI_MODE</id> + <!-- <targetType>TARGET_TYPE_SYSTEM</targetType> --> + <description> + Processor CAPI attachment protocol mode. + 0 = no: SMPA CAPI attachment (default) + 1 = yes: SMPA CAPI attachment + Provided by the MRW. + </description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <hwpfToHbAttrMap> + <id>ATTR_PROC_FABRIC_CAPI_MODE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PROC_FABRIC_ADDR_BAR_MODE</id> + <!-- <targetType>TARGET_TYPE_SYSTEM</targetType> --> + <description> + Processor memory map configuration. + 0 = large system address map (default) + 1 = small system address map + Provided by the MRW. + </description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <hwpfToHbAttrMap> + <id>ATTR_PROC_FABRIC_ADDR_BAR_MODE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + + +<attribute> + <id>PROC_FABRIC_SYSTEM_MASTER_CHIP</id> + <!-- <targetType>TARGET_TYPE_PROC_CHIP</targetType> --> + <description> + Indicates if the given chip should serve as the fabric system master. + FALSE = 0x0, TRUE = 0x1 + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>non-volatile</persistency> + <writeable/> + <readable/> + <hwpfToHbAttrMap> + <id>ATTR_PROC_FABRIC_SYSTEM_MASTER_CHIP</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PROC_FABRIC_GROUP_MASTER_CHIP</id> + <!-- <targetType>TARGET_TYPE_PROC_CHIP</targetType> --> + <description> + Indicates if the given chip should serve as the fabric group master. + FALSE = 0x0, TRUE = 0x1 + </description> + <simpleType><uint8_t></uint8_t></simpleType> + <persistency>non-volatile</persistency> + <writeable/> + <readable/> + <hwpfToHbAttrMap> + <id>ATTR_PROC_FABRIC_GROUP_MASTER_CHIP</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PROC_FABRIC_X_ATTACHED_CHIP_CNFG</id> + <!-- <targetType>TARGET_TYPE_PROC_CHIP</targetType> --> + <description> + For each fabric X link on this chip, specifies whether or not the chip at + the receiving end of the link is present and configured + FALSE = 0x0, TRUE = 0x1 + </description> + <simpleType> + <uint8_t></uint8_t> + <array>7</array> + </simpleType> + <writeable/> + <readable/> + <persistency>volatile-zeroed</persistency> + <hwpfToHbAttrMap> + <id>ATTR_PROC_FABRIC_X_ATTACHED_CHIP_CNFG</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PROC_FABRIC_A_ATTACHED_CHIP_CNFG</id> + <!-- <targetType>TARGET_TYPE_PROC_CHIP</targetType> --> + <description> + For each fabric A link on this chip, specifies whether or not the chip at + the receiving end of the link is present and configured + FALSE = 0x0, TRUE = 0x1 + </description> + <simpleType> + <uint8_t></uint8_t> + <array>4</array> + </simpleType> + <writeable/> + <readable/> + <persistency>volatile-zeroed</persistency> + <hwpfToHbAttrMap> + <id>ATTR_PROC_FABRIC_A_ATTACHED_CHIP_CNFG</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PROC_FABRIC_X_ATTACHED_CHIP_ID</id> + <!-- <targetType>TARGET_TYPE_PROC_CHIP</targetType> --> + <description> + For each fabric X link on this chip, specifies the fabric ID of the chip + at the receiving end of the link. Should be considered valid only if + corresponding ATTR_PROC_FABRIC_X_ATTACHED_CHIP_CNFG index is true. + </description> + <simpleType> + <uint8_t></uint8_t> + <array>7</array> + </simpleType> + <writeable/> + <readable/> + <persistency>volatile-zeroed</persistency> + <hwpfToHbAttrMap> + <id>ATTR_PROC_FABRIC_X_ATTACHED_CHIP_ID</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PROC_FABRIC_A_ATTACHED_CHIP_ID</id> + <!-- <targetType>TARGET_TYPE_PROC_CHIP</targetType> --> + <description> + For each fabric A link on this chip, specifies the fabric ID of the chip + at the receiving end of the link. Should be considered valid only if + corresponding ATTR_PROC_FABRIC_A_ATTACHED_CHIP_CNFG index is true. + </description> + <simpleType> + <uint8_t></uint8_t> + <array>4</array> + </simpleType> + <writeable/> + <readable/> + <persistency>volatile-zeroed</persistency> + <hwpfToHbAttrMap> + <id>ATTR_PROC_FABRIC_A_ATTACHED_CHIP_ID</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PROC_FABRIC_X_ADDR_DIS</id> + <!-- <targetType>TARGET_TYPE_PROC_CHIP</targetType> --> + <description> + Indicates if link should be used to carry data only + (in aggregate configurations). + Should be considered valid only if corresponding + ATTR_PROC_FABRIC_X_ATTACHED_CHIP_CNFG index is true. + OFF = 0x0, ON = 0x1 + </description> + <simpleType> + <uint8_t></uint8_t> + <array>7</array> + </simpleType> + <writeable/> + <readable/> + <persistency>volatile-zeroed</persistency> + <hwpfToHbAttrMap> + <id>ATTR_PROC_FABRIC_X_ADDR_DIS</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PROC_FABRIC_A_ADDR_DIS</id> + <!-- <targetType>TARGET_TYPE_PROC_CHIP</targetType> --> + <description> + Indicates if link should be used to carry data only + (in aggregate configurations). + Should be considered valid only if corresponding + ATTR_PROC_FABRIC_A_ATTACHED_CHIP_CNFG index is true. + OFF = 0x0, ON = 0x1 + </description> + <simpleType> + <uint8_t></uint8_t> + <array>4</array> + </simpleType> + <writeable/> + <readable/> + <persistency>volatile-zeroed</persistency> + <hwpfToHbAttrMap> + <id>ATTR_PROC_FABRIC_A_ADDR_DIS</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PROC_EPS_READ_CYCLES</id> + <!-- <targetType>TARGET_TYPE_SYSTEM</targetType> --> + <description> + Calculated read epsilon protection count. + Counter tier is index. + </description> + <simpleType> + <uint32_t></uint32_t> + <array>3</array> + </simpleType> + <writeable/> + <readable/> + <persistency>volatile-zeroed</persistency> + <hwpfToHbAttrMap> + <id>ATTR_PROC_EPS_READ_CYCLES</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PROC_EPS_WRITE_CYCLES</id> + <!-- <targetType>TARGET_TYPE_SYSTEM</targetType> --> + <description> + Calculated write epsilon protection count. + Counter tier is index. + </description> + <simpleType> + <uint32_t></uint32_t> + <array>3</array> + </simpleType> + <writeable/> + <readable/> + <persistency>volatile-zeroed</persistency> + <hwpfToHbAttrMap> + <id>ATTR_PROC_EPS_WRITE_CYCLES</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PROC_HTM_BAR_SIZES</id> + <!-- <targetType>TARGET_TYPE_PROC_CHIP</targetType> --> + <description> The amount of memory a user can reserve to store HTM traces. + There are two different HTM trace areas, thus two different + sizes (For example, one to store NHTM0 and one for NHTM1). + Platform is to initialize this attribute to 0 (default). + Set by user via attribute override. + Used by p9_mss_eff_grouping. + 256_GB = 0x0000004000000000, + 128_GB = 0x0000002000000000, + 64_GB = 0x0000001000000000, + 32_GB = 0x0000000800000000, + 16_GB = 0x0000000400000000, + 8_GB = 0x0000000200000000, + 4_GB = 0x0000000100000000, + 2_GB = 0x0000000080000000, + 1_GB = 0x0000000040000000, + 512_MB = 0x0000000020000000, + 256_MB = 0x0000000010000000, + 128_MB = 0x0000000008000000, + 64_MB = 0x0000000004000000, + 32_MB = 0x0000000002000000, + 16_MB = 0x0000000001000000, + ZERO = 0x0000000000000000 + </description> + <simpleType> + <uint64_t> + <default>0,0</default> + </uint64_t> + <array>2</array> + </simpleType> + <writeable/> + <persistency>non-volatile</persistency> + <readable/> + <hwpfToHbAttrMap> + <id>ATTR_PROC_HTM_BAR_SIZES</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<!-- ********************************************************************** --> + </attributes> diff --git a/src/usr/targeting/common/xmltohb/common.mk b/src/usr/targeting/common/xmltohb/common.mk index 48fe16a15..5b56664f2 100755 --- a/src/usr/targeting/common/xmltohb/common.mk +++ b/src/usr/targeting/common/xmltohb/common.mk @@ -63,7 +63,6 @@ FAPI_ATTR_SOURCES += $(if $(CONFIG_VPD_GETMACRO_USE_EFF_ATTR), lab_dimm_spd_attr FAPI_ATTR_SOURCES += $(if $(CONFIG_VPD_GETMACRO_USE_EFF_ATTR), lab_dimm_attributes.xml, dimm_attributes.xml) FAPI_ATTR_SOURCES += unit_attributes.xml FAPI_ATTR_SOURCES += ei_bus_attributes.xml -FAPI_ATTR_SOURCES += dram_initialization/proc_setup_bars/proc_setup_bars_memory_attributes.xml FAPI_ATTR_SOURCES += dram_initialization/proc_setup_bars/proc_setup_bars_l3_attributes.xml FAPI_ATTR_SOURCES += dram_initialization/proc_setup_bars/proc_setup_bars_mmio_attributes.xml FAPI_ATTR_SOURCES += activate_powerbus/proc_build_smp/proc_fab_smp_fabric_attributes.xml diff --git a/src/usr/targeting/common/xmltohb/target_types.xml b/src/usr/targeting/common/xmltohb/target_types.xml index 9ce83d7be..a8a305930 100755 --- a/src/usr/targeting/common/xmltohb/target_types.xml +++ b/src/usr/targeting/common/xmltohb/target_types.xml @@ -566,6 +566,16 @@ <attribute><id>TIME_BASE</id></attribute> <attribute><id>CPU_ATTR</id></attribute> <attribute><id>ADU_XSCOM_BAR_BASE_ADDR</id></attribute> + <attribute><id>PROC_OCC_SANDBOX_SIZE</id></attribute> + <attribute><id>PROC_FABRIC_SYSTEM_MASTER_CHIP</id></attribute> + <attribute><id>PROC_FABRIC_GROUP_MASTER_CHIP</id></attribute> + <attribute><id>PROC_FABRIC_A_ATTACHED_CHIP_CNFG</id></attribute> + <attribute><id>PROC_FABRIC_X_ATTACHED_CHIP_CNFG</id></attribute> + <attribute><id>PROC_FABRIC_A_ATTACHED_CHIP_ID</id></attribute> + <attribute><id>PROC_FABRIC_X_ATTACHED_CHIP_ID</id></attribute> + <attribute><id>PROC_FABRIC_A_ADDR_DIS</id></attribute> + <attribute><id>PROC_FABRIC_X_ADDR_DIS</id></attribute> + <attribute><id>PROC_HTM_BAR_SIZES</id></attribute> </targetType> <targetType> @@ -654,7 +664,6 @@ <attribute><id>ECID</id></attribute> <attribute><id>PROC_HTM_BAR_SIZE</id></attribute> - <attribute><id>PROC_OCC_SANDBOX_SIZE</id></attribute> <attribute><id>PROC_HTM_BAR_BASE_ADDR</id></attribute> <attribute><id>PROC_OCC_SANDBOX_BASE_ADDR</id></attribute> <attribute><id>PROC_AS_MMIO_BAR_BASE_ADDR</id></attribute> @@ -2028,6 +2037,15 @@ <attribute><id>PFET_VDD_VOFF_SEL</id></attribute> <attribute><id>PFET_VCS_VOFF_SEL</id></attribute> <attribute><id>SYSTEM_IPL_PHASE</id></attribute> + <attribute><id>FREQ_CORE_CEILING_MHZ</id></attribute> + <attribute><id>PROC_FABRIC_A_BUS_WIDTH</id></attribute> + <attribute><id>PROC_FABRIC_X_BUS_WIDTH</id></attribute> + <attribute><id>PROC_FABRIC_CCSM_MODE</id></attribute> + <attribute><id>PROC_FABRIC_SMP_OPTICS_MODE</id></attribute> + <attribute><id>PROC_FABRIC_CAPI_MODE</id></attribute> + <attribute><id>PROC_FABRIC_ADDR_BAR_MODE</id></attribute> + <attribute><id>PROC_EPS_READ_CYCLES</id></attribute> + <attribute><id>PROC_EPS_WRITE_CYCLES</id></attribute> </targetType> <!-- enc-node-power9 --> @@ -2432,6 +2450,7 @@ <attribute><id>DECONFIG_GARDABLE</id><default>1</default></attribute> <attribute><id>SCRATCH_UINT8_1</id><default>5</default></attribute> <attribute><id>PARENT_PERVASIVE</id></attribute> + <attribute><id>OPTICS_CONFIG_MODE</id></attribute> </targetType> <targetType> |
