diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/usr/hwpf/hwp/centaur_ec_attributes.xml | 23 | ||||
| -rw-r--r-- | src/usr/hwpf/hwp/initfiles/mbs_def.initfile | 37 |
2 files changed, 56 insertions, 4 deletions
diff --git a/src/usr/hwpf/hwp/centaur_ec_attributes.xml b/src/usr/hwpf/hwp/centaur_ec_attributes.xml index 3047ccd26..53f1bba96 100644 --- a/src/usr/hwpf/hwp/centaur_ec_attributes.xml +++ b/src/usr/hwpf/hwp/centaur_ec_attributes.xml @@ -5,7 +5,9 @@ <!-- --> <!-- OpenPOWER HostBoot Project --> <!-- --> -<!-- COPYRIGHT International Business Machines Corp. 2012,2014 --> +<!-- Contributors Listed Below - COPYRIGHT 2012,2014 --> +<!-- [+] International Business Machines Corp. --> +<!-- --> <!-- --> <!-- Licensed under the Apache License, Version 2.0 (the "License"); --> <!-- you may not use this file except in compliance with the License. --> @@ -22,7 +24,24 @@ <!-- IBM_PROLOG_END_TAG --> <attributes> <!-- ********************************************************************* --> - <!-- $Id: centaur_ec_attributes.xml,v 1.24 2014/04/18 18:43:12 jdsloat Exp $ --> + <!-- $Id: centaur_ec_attributes.xml,v 1.27 2014/06/11 17:42:04 yctschan Exp $ --> + <attribute> + <id>ATTR_CENTAUR_EC_ENABLE_TRACE_ARRAY_CLKSTOP_ON_XSTOP_FW624741</id> + <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> + <description> + Set by the platform depending on DD2.x or newer (TRUE), otherwise FALSE. If true, it sets stop on error for xtsop in the Centaur arrays using ATTR_CENTAUR_EC_ENABLE_TRACE_ARRAY_CLKSTOP_ON_XSTOP_FW624741. + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_CENTAUR</name> + <ec> + <value>0x20</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <attribute> <id>ATTR_CENTAUR_EC_ENABLE_SAFE_MODE_THROTTLE</id> <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> diff --git a/src/usr/hwpf/hwp/initfiles/mbs_def.initfile b/src/usr/hwpf/hwp/initfiles/mbs_def.initfile index d58633cb5..f8653137a 100644 --- a/src/usr/hwpf/hwp/initfiles/mbs_def.initfile +++ b/src/usr/hwpf/hwp/initfiles/mbs_def.initfile @@ -1,8 +1,9 @@ -#-- $Id: mbs_def.initfile,v 1.48 2014/05/20 20:37:38 baysah Exp $ +#-- $Id: mbs_def.initfile,v 1.49 2014/06/11 20:01:29 yctschan Exp $ #-- CHANGE HISTORY: #-------------------------------------------------------------------------------- #-- Version:|Author: | Date: | Comment: #-- --------|--------|--------|-------------------------------------------------- +#-- 1.49 |tschang | 6/10/14| Enabled clock stop on xstop for the trace arrays FW624741 #-- 1.48 |baysah |04/21/14| Added L4 Cleaner settings per rank group to improve memory performance #-- 1.47 |tschang | 3/19/14| SW252733 - L4 Cache UE Handling #-- 1.46 |tschang | 3/19/14| SW252733 - L4 Cache UE Handling typo @@ -421,11 +422,43 @@ define def_num_mbs_ranks = (MBA0.ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] + MBA0.ATTR_E #--****************************************************************************** # scom 0x02011403 { # bits , scom_data ; -# 8 , 0b1 ; # int_parity_error - HW244827 and HW251643 +# 8 , 0b1 ; # int_parity_error - HW244827 and HW251643 # # } #--****************************************************************************** +#-- TRACE clock stop on checkstop MBA +#--****************************************************************************** +# TCM.EPS.DBG.DBG_MODE_REG + scom 0x03012300 { + bits , scom_data , ATTR_FUNCTIONAL, expr; + 7 , 0b1 , 1 , (ATTR_CENTAUR_EC_ENABLE_TRACE_ARRAY_CLKSTOP_ON_XSTOP_FW624741 == 1); # EC2.0 or greater enable + } + +# TCM.EPS.DBG.DBG_TRACE_MODE_REG_2 + scom 0x0301230B { + bits , scom_data , ATTR_FUNCTIONAL, expr; + 17 , 0b1 , 1 , (ATTR_CENTAUR_EC_ENABLE_TRACE_ARRAY_CLKSTOP_ON_XSTOP_FW624741 == 1); # EC2.0 or greater enable + } + + + +#--****************************************************************************** +#-- TRACE clock stop on checkstop MBS +#--****************************************************************************** +# TCN.EPS.DBG.DBG_MODE_REG + scom 0x02012300 { + bits , scom_data , ATTR_FUNCTIONAL, expr; + 7 , 0b1 , 1 , (ATTR_CENTAUR_EC_ENABLE_TRACE_ARRAY_CLKSTOP_ON_XSTOP_FW624741 == 1); # EC2.0 or greater enable + } + +# TCN.EPS.DBG.DBG_TRACE_MODE_REG_2 + scom 0x0201230B { + bits , scom_data , ATTR_FUNCTIONAL, expr; + 17 , 0b1 , 1 , (ATTR_CENTAUR_EC_ENABLE_TRACE_ARRAY_CLKSTOP_ON_XSTOP_FW624741 == 1); # EC2.0 or greater enable + } + +#--****************************************************************************** # HW246685 : Need RCE FIR bit if NCE/SCE/MPE/MCE on 2nd try # - Want to be able to see RCE reported even if we also have chip marks or symbol marks in place. # - To enable maint fix: set MBSTR(60)=1 to see the RCE in conjunction with the other errors |
