diff options
Diffstat (limited to 'src')
15 files changed, 1910 insertions, 651 deletions
diff --git a/src/usr/hwpf/hwp/dram_initialization/mss_memdiag/mss_maint_cmds.C b/src/usr/hwpf/hwp/dram_initialization/mss_memdiag/mss_maint_cmds.C index 650e35eda..8a6ccdc37 100644 --- a/src/usr/hwpf/hwp/dram_initialization/mss_memdiag/mss_maint_cmds.C +++ b/src/usr/hwpf/hwp/dram_initialization/mss_memdiag/mss_maint_cmds.C @@ -1,27 +1,26 @@ -/* IBM_PROLOG_BEGIN_TAG - * This is an automatically generated prolog. - * - * $Source: src/usr/hwpf/hwp/dram_initialization/mss_maint_cmds/mss_maint_cmds.C $ - * - * IBM CONFIDENTIAL - * - * COPYRIGHT International Business Machines Corp. 2012 - * - * p1 - * - * Object Code Only (OCO) source materials - * Licensed Internal Code Source Materials - * IBM HostBoot Licensed Internal Code - * - * The source code for this program is not published or other- - * wise divested of its trade secrets, irrespective of what has - * been deposited with the U.S. Copyright Office. - * - * Origin: 30 - * - * IBM_PROLOG_END_TAG - */ -// $Id: mss_maint_cmds.C,v 1.9 2012/07/18 21:37:50 gollub Exp $ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/dram_initialization/mss_memdiag/mss_maint_cmds.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2012 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +// $Id: mss_maint_cmds.C,v 1.11 2012/09/07 22:35:07 gollub Exp $ //------------------------------------------------------------------------------ // Don't forget to create CVS comments when you check in your changes! //------------------------------------------------------------------------------ @@ -41,6 +40,14 @@ // 1.8 | 07/16/12 | bellows | added in Id tag // 1.9 | 07/18/12 | gollub | Updates from review. // | | | Updates for timebase scrub. +// 1.10 | 07/24/12 | gollub | Fix UE/SUE status bit swap in MBMACA +// | | | Added stop condition enums +// | | | STOP_IMMEDIATE +// | | | ENABLE_CMD_COMPLETE_ATTENTION_ON_CLEAN_AND_ERROR +// | | | Now require cleanupCmd() for super fast read +// | | | to disable rrq fifo mode when done. +// 1.11 | 09/07/12 | gollub | Updates from review. +// | | | Support for more patterns. //------------------------------------------------------------------------------ // Includes @@ -88,6 +95,11 @@ const uint8_t MSS_X4_STEER_OPTIONS_PER_PORT1 = 18; */ const uint8_t MSS_X4_ECC_STEER_OPTIONS = 36; +/** + * @brief Max 8 patterns + */ +const uint8_t MSS_MAX_PATTERNS = 8; + namespace mss_MemConfig { @@ -307,19 +319,221 @@ static const uint8_t mss_eccSpareIndex_to_symbol[MSS_X4_ECC_STEER_OPTIONS]={ // NOTE: DRAM 0 (x4) (symbols 0,1) used for the ECC spare. // NOTE: Can't use ECC spare to fix bad spare DRAMs on Port0 or Port1 +// TODO: Update with actual patterns from Luis Lastras when they are ready +static const uint32_t mss_maintBufferData[MSS_MAX_PATTERNS][16][2]={ + +// PATTERN_0 + {{0x00000000, 0x00000000}, + {0x00000000, 0x00000000}, + {0x00000000, 0x00000000}, + {0x00000000, 0x00000000}, + {0x00000000, 0x00000000}, + {0x00000000, 0x00000000}, + {0x00000000, 0x00000000}, + {0x00000000, 0x00000000}, + {0x00000000, 0x00000000}, + {0x00000000, 0x00000000}, + {0x00000000, 0x00000000}, + {0x00000000, 0x00000000}, + {0x00000000, 0x00000000}, + {0x00000000, 0x00000000}, + {0x00000000, 0x00000000}, + {0x00000000, 0x00000000}}, + +// PATTERN_1 + {{0xffffffff, 0xffffffff}, + {0xffffffff, 0xffffffff}, + {0xffffffff, 0xffffffff}, + {0xffffffff, 0xffffffff}, + {0xffffffff, 0xffffffff}, + {0xffffffff, 0xffffffff}, + {0xffffffff, 0xffffffff}, + {0xffffffff, 0xffffffff}, + {0xffffffff, 0xffffffff}, + {0xffffffff, 0xffffffff}, + {0xffffffff, 0xffffffff}, + {0xffffffff, 0xffffffff}, + {0xffffffff, 0xffffffff}, + {0xffffffff, 0xffffffff}, + {0xffffffff, 0xffffffff}, + {0xffffffff, 0xffffffff}}, + +// PATTERN_2 + {{0xf0f0f0f0, 0xf0f0f0f0}, + {0xf0f0f0f0, 0xf0f0f0f0}, + {0xf0f0f0f0, 0xf0f0f0f0}, + {0xf0f0f0f0, 0xf0f0f0f0}, + {0xf0f0f0f0, 0xf0f0f0f0}, + {0xf0f0f0f0, 0xf0f0f0f0}, + {0xf0f0f0f0, 0xf0f0f0f0}, + {0xf0f0f0f0, 0xf0f0f0f0}, + {0xf0f0f0f0, 0xf0f0f0f0}, + {0xf0f0f0f0, 0xf0f0f0f0}, + {0xf0f0f0f0, 0xf0f0f0f0}, + {0xf0f0f0f0, 0xf0f0f0f0}, + {0xf0f0f0f0, 0xf0f0f0f0}, + {0xf0f0f0f0, 0xf0f0f0f0}, + {0xf0f0f0f0, 0xf0f0f0f0}, + {0xf0f0f0f0, 0xf0f0f0f0}}, + +// PATTERN_3 + {{0x0f0f0f0f, 0x0f0f0f0f}, + {0x0f0f0f0f, 0x0f0f0f0f}, + {0x0f0f0f0f, 0x0f0f0f0f}, + {0x0f0f0f0f, 0x0f0f0f0f}, + {0x0f0f0f0f, 0x0f0f0f0f}, + {0x0f0f0f0f, 0x0f0f0f0f}, + {0x0f0f0f0f, 0x0f0f0f0f}, + {0x0f0f0f0f, 0x0f0f0f0f}, + {0x0f0f0f0f, 0x0f0f0f0f}, + {0x0f0f0f0f, 0x0f0f0f0f}, + {0x0f0f0f0f, 0x0f0f0f0f}, + {0x0f0f0f0f, 0x0f0f0f0f}, + {0x0f0f0f0f, 0x0f0f0f0f}, + {0x0f0f0f0f, 0x0f0f0f0f}, + {0x0f0f0f0f, 0x0f0f0f0f}, + {0x0f0f0f0f, 0x0f0f0f0f}}, + +// PATTERN_4 + {{0xaaaaaaaa, 0xaaaaaaaa}, + {0xaaaaaaaa, 0xaaaaaaaa}, + {0xaaaaaaaa, 0xaaaaaaaa}, + {0xaaaaaaaa, 0xaaaaaaaa}, + {0xaaaaaaaa, 0xaaaaaaaa}, + {0xaaaaaaaa, 0xaaaaaaaa}, + {0xaaaaaaaa, 0xaaaaaaaa}, + {0xaaaaaaaa, 0xaaaaaaaa}, + {0xaaaaaaaa, 0xaaaaaaaa}, + {0xaaaaaaaa, 0xaaaaaaaa}, + {0xaaaaaaaa, 0xaaaaaaaa}, + {0xaaaaaaaa, 0xaaaaaaaa}, + {0xaaaaaaaa, 0xaaaaaaaa}, + {0xaaaaaaaa, 0xaaaaaaaa}, + {0xaaaaaaaa, 0xaaaaaaaa}, + {0xaaaaaaaa, 0xaaaaaaaa}}, + +// PATTERN_5 + {{0x55555555, 0x55555555}, + {0x55555555, 0x55555555}, + {0x55555555, 0x55555555}, + {0x55555555, 0x55555555}, + {0x55555555, 0x55555555}, + {0x55555555, 0x55555555}, + {0x55555555, 0x55555555}, + {0x55555555, 0x55555555}, + {0x55555555, 0x55555555}, + {0x55555555, 0x55555555}, + {0x55555555, 0x55555555}, + {0x55555555, 0x55555555}, + {0x55555555, 0x55555555}, + {0x55555555, 0x55555555}, + {0x55555555, 0x55555555}, + {0x55555555, 0x55555555}}, + +// PATTERN_6 + {{0xcccccccc, 0xcccccccc}, + {0xcccccccc, 0xcccccccc}, + {0xcccccccc, 0xcccccccc}, + {0xcccccccc, 0xcccccccc}, + {0xcccccccc, 0xcccccccc}, + {0xcccccccc, 0xcccccccc}, + {0xcccccccc, 0xcccccccc}, + {0xcccccccc, 0xcccccccc}, + {0xcccccccc, 0xcccccccc}, + {0xcccccccc, 0xcccccccc}, + {0xcccccccc, 0xcccccccc}, + {0xcccccccc, 0xcccccccc}, + {0xcccccccc, 0xcccccccc}, + {0xcccccccc, 0xcccccccc}, + {0xcccccccc, 0xcccccccc}, + {0xcccccccc, 0xcccccccc}}, + +// PATTERN_7 + {{0x33333333, 0x33333333}, + {0x33333333, 0x33333333}, + {0x33333333, 0x33333333}, + {0x33333333, 0x33333333}, + {0x33333333, 0x33333333}, + {0x33333333, 0x33333333}, + {0x33333333, 0x33333333}, + {0x33333333, 0x33333333}, + {0x33333333, 0x33333333}, + {0x33333333, 0x33333333}, + {0x33333333, 0x33333333}, + {0x33333333, 0x33333333}, + {0x33333333, 0x33333333}, + {0x33333333, 0x33333333}, + {0x33333333, 0x33333333}, + {0x33333333, 0x33333333}}}; + + +// TODO: Update with actual patterns from Luis Lastras when they are ready +static const uint8_t mss_65thByte[MSS_MAX_PATTERNS][4]={ + +// bit1=tag0_2, bit2=tag1_3, bit3=MDI + +// PATTERN_0 + {0x00, // 1st 64B of cachline: tag0=0, tag1=0, MDI=0 + 0x00, // 1st 64B of cachline: tag2=0, tag3=0, MDI=0 + 0x00, // 2nd 64B of cachline: tag0=0, tag1=0, MDI=0 + 0x00}, // 2nd 64B of cachline: tag2=0, tag3=0, MDI=0 + +// PATTERN_1 + {0x70, // 1st 64B of cachline: tag0=1, tag1=1, MDI=1 + 0x70, // 1st 64B of cachline: tag2=1, tag3=1, MDI=1 + 0x70, // 2nd 64B of cachline: tag0=1, tag1=1, MDI=1 + 0x70}, // 2nd 64B of cachline: tag2=1, tag3=1, MDI=1 + +// PATTERN_2 + {0x70, // 1st 64B of cachline: tag0=1, tag1=1, MDI=1 + 0x00, // 1st 64B of cachline: tag2=0, tag3=0, MDI=0 + 0x70, // 2nd 64B of cachline: tag0=1, tag1=1, MDI=1 + 0x00}, // 2nd 64B of cachline: tag2=0, tag3=0, MDI=0 + +// PATTERN_3 + {0x00, // 1st 64B of cachline: tag0=0, tag1=0, MDI=0 + 0x70, // 1st 64B of cachline: tag2=1, tag3=1, MDI=1 + 0x00, // 2nd 64B of cachline: tag0=0, tag1=0, MDI=0 + 0x70}, // 2nd 64B of cachline: tag2=1, tag3=1, MDI=1 + +// PATTERN_4 + {0x30, // 1st 64B of cachline: tag0=0, tag1=1, MDI=1 + 0x50, // 1st 64B of cachline: tag2=1, tag3=0, MDI=1 + 0x20, // 2nd 64B of cachline: tag0=0, tag1=1, MDI=0 + 0x40}, // 2nd 64B of cachline: tag2=1, tag3=0, MDI=0 + +// PATTERN_5 + {0x60, // 1st 64B of cachline: tag0=1, tag1=0, MDI=0 + 0x20, // 1st 64B of cachline: tag2=0, tag3=1, MDI=0 + 0x50, // 2nd 64B of cachline: tag0=1, tag1=0, MDI=1 + 0x30}, // 2nd 64B of cachline: tag2=0, tag3=1, MDI=1 + +// PATTERN_6 + {0x70, // 1st 64B of cachline: tag0=1, tag1=1, MDI=1 + 0x40, // 1st 64B of cachline: tag2=1, tag3=0, MDI=0 + 0x60, // 2nd 64B of cachline: tag0=1, tag1=1, MDI=0 + 0x50}, // 2nd 64B of cachline: tag2=1, tag3=0, MDI=1 + +// PATTERN_7 + {0x20, // 1st 64B of cachline: tag0=0, tag1=1, MDI=0 + 0x70, // 1st 64B of cachline: tag2=1, tag3=1, MDI=1 + 0x30, // 2nd 64B of cachline: tag0=0, tag1=1, MDI=1 + 0x60}}; // 2nd 64B of cachline: tag2=1, tag3=1, MDI=0 //------------------------------------------------------------------------------ // Parent class //------------------------------------------------------------------------------ + + //--------------------------------------------------------- // mss_MaintCmd Constructor //--------------------------------------------------------- mss_MaintCmd::mss_MaintCmd(const fapi::Target & i_target, const ecmdDataBufferBase & i_startAddr, const ecmdDataBufferBase & i_endAddr, - StopCondition i_stopCondition, + uint32_t i_stopCondition, bool i_poll, CmdType i_cmdType ) : iv_target( i_target ), @@ -576,59 +790,65 @@ fapi::ReturnCode mss_MaintCmd::loadStopCondMask() l_rc = fapiGetScom(iv_target, MBA01_MBASCTLQ_0x0301060F, l_mbasctlq); if(l_rc) return l_rc; - // Start by clearing all bits 0:12 + // Start by clearing all bits 0:12 and bit 16 l_ecmd_rc |= l_mbasctlq.clearBit(0,13); + l_ecmd_rc |= l_mbasctlq.clearBit(16); + + // Enable stop immediate + if ( 0 != (iv_stopCondition & STOP_IMMEDIATE) ) + l_ecmd_rc |= l_mbasctlq.setBit(0); - // Stop location // Enable stop end of rank if ( 0 != (iv_stopCondition & STOP_END_OF_RANK) ) - l_ecmd_rc |= l_mbasctlq.setBit(1); - // Enable stop immediate - else l_ecmd_rc |= l_mbasctlq.setBit(0); + l_ecmd_rc |= l_mbasctlq.setBit(1); // Stop on hard NCE ETE if ( 0 != (iv_stopCondition & STOP_ON_HARD_NCE_ETE) ) - l_ecmd_rc |= l_mbasctlq.setBit(2); + l_ecmd_rc |= l_mbasctlq.setBit(2); // Stop on intermittent NCE ETE if ( 0 != (iv_stopCondition & STOP_ON_INT_NCE_ETE) ) - l_ecmd_rc |= l_mbasctlq.setBit(3); + l_ecmd_rc |= l_mbasctlq.setBit(3); // Stop on soft NCE ETE if ( 0 != (iv_stopCondition & STOP_ON_SOFT_NCE_ETE) ) - l_ecmd_rc |= l_mbasctlq.setBit(4); + l_ecmd_rc |= l_mbasctlq.setBit(4); // Stop on SCE if ( 0 != (iv_stopCondition & STOP_ON_SCE) ) - l_ecmd_rc |= l_mbasctlq.setBit(5); + l_ecmd_rc |= l_mbasctlq.setBit(5); // Stop on MCE if ( 0 != (iv_stopCondition & STOP_ON_MCE) ) - l_ecmd_rc |= l_mbasctlq.setBit(6); + l_ecmd_rc |= l_mbasctlq.setBit(6); // Stop on retry CE ETE if ( 0 != (iv_stopCondition & STOP_ON_RETRY_CE) ) - l_ecmd_rc |= l_mbasctlq.setBit(7); + l_ecmd_rc |= l_mbasctlq.setBit(7); // Stop on MPE if ( 0 != (iv_stopCondition & STOP_ON_MPE) ) - l_ecmd_rc |= l_mbasctlq.setBit(8); + l_ecmd_rc |= l_mbasctlq.setBit(8); // Stop on UE if ( 0 != (iv_stopCondition & STOP_ON_UE) ) - l_ecmd_rc |= l_mbasctlq.setBit(9); + l_ecmd_rc |= l_mbasctlq.setBit(9); // Stop on end address if ( 0 != (iv_stopCondition & STOP_ON_END_ADDRESS) ) - l_ecmd_rc |= l_mbasctlq.setBit(10); + l_ecmd_rc |= l_mbasctlq.setBit(10); // Enable command complete attention if ( 0 != (iv_stopCondition & ENABLE_CMD_COMPLETE_ATTENTION) ) - l_ecmd_rc |= l_mbasctlq.setBit(11); + l_ecmd_rc |= l_mbasctlq.setBit(11); // Stop on SUE if ( 0 != (iv_stopCondition & STOP_ON_SUE) ) - l_ecmd_rc |= l_mbasctlq.setBit(12); + l_ecmd_rc |= l_mbasctlq.setBit(12); + + // Enable command complete attention on clean and error + if ( 0 != (iv_stopCondition & ENABLE_CMD_COMPLETE_ATTENTION_ON_CLEAN_AND_ERROR) ) + l_ecmd_rc |= l_mbasctlq.setBit(16); if(l_ecmd_rc) { @@ -655,8 +875,12 @@ fapi::ReturnCode mss_MaintCmd::startMaintCmd() uint32_t l_ecmd_rc = 0; ecmdDataBufferBase l_data(64); - FAPI_INF("ENTER mss_MaintCmd::startMaintCmd()"); + FAPI_INF("ENTER mss_MaintCmd::startMaintCmd()"); + // DEBUG - should be no special attentions before we start cmd + l_rc = fapiGetScom(iv_target, MBA01_MBSPAQ_0x03010611, l_data); + if(l_rc) return l_rc; + l_rc = fapiGetScom(iv_target, MBA01_MBMCCQ_0x0301060B, l_data); if(l_rc) return l_rc; @@ -752,6 +976,11 @@ fapi::ReturnCode mss_MaintCmd::pollForMaintCmdComplete() { fapiDelay(HW_MODE_DELAY, SIM_MODE_DELAY); + // DEBUG - want to see attention only when cmd done + FAPI_INF("MBSPAQ"); + l_rc = fapiGetScom(iv_target, MBA01_MBSPAQ_0x03010611, l_data); + if(l_rc) return l_rc; + FAPI_INF("Read MBMACAQ just to see if it's incrementing"); l_rc = fapiGetScom(iv_target, MBA01_MBMACAQ_0x0301060D, l_data); if(l_rc) return l_rc; @@ -805,8 +1034,8 @@ fapi::ReturnCode mss_MaintCmd::collectFFDC() if (l_data.isBitSet(42)) FAPI_ERR("42:MCE"); if (l_data.isBitSet(43)) FAPI_ERR("43:RCE"); if (l_data.isBitSet(44)) FAPI_ERR("44:MPE"); - if (l_data.isBitSet(45)) FAPI_ERR("45:SUE"); - if (l_data.isBitSet(46)) FAPI_ERR("46:UE"); + if (l_data.isBitSet(45)) FAPI_ERR("45:UE"); + if (l_data.isBitSet(46)) FAPI_ERR("46:SUE"); FAPI_INF("MBMEAQ"); l_rc = fapiGetScom(iv_target, MBA01_MBMEAQ_0x0301060E, l_data); @@ -906,48 +1135,7 @@ fapi::ReturnCode mss_MaintCmd::loadPattern(PatternIndex i_initPattern) {MAINT1_MBS_MAINT_BUFF3_DATA2_0x0201173C, MAINT1_MBS_MAINT_BUFF3_DATA_ECC2_0x02011744}, {MAINT1_MBS_MAINT_BUFF3_DATA3_0x0201173D, MAINT1_MBS_MAINT_BUFF3_DATA_ECC3_0x02011745}}}; - // DEBUG - /* - static const uint32_t maintBufferData[16][2]={ - {0x00000000, 0x10000000}, - {0x00000001, 0x10000001}, - {0x00000002, 0x10000002}, - {0x00000003, 0x10000003}, - {0x00000004, 0x10000004}, - {0x00000005, 0x10000005}, - {0x00000006, 0x10000006}, - {0x00000007, 0x10000007}, - {0x00000008, 0x10000008}, - {0x00000009, 0x10000009}, - {0x0000000A, 0x1000000A}, - {0x0000000B, 0x1000000B}, - {0x0000000C, 0x1000000C}, - {0x0000000D, 0x1000000D}, - {0x0000000E, 0x1000000E}, - {0x0000000F, 0x1000000F}}; - */ - - - static const uint32_t maintBufferData[16][2]={ - {0x00000000, 0x00000000}, - {0x00000000, 0x00000000}, - {0x00000000, 0x00000000}, - {0x00000000, 0x00000000}, - {0x00000000, 0x00000000}, - {0x00000000, 0x00000000}, - {0x00000000, 0x00000000}, - {0x00000000, 0x00000000}, - {0x00000000, 0x00000000}, - {0x00000000, 0x00000000}, - {0x00000000, 0x00000000}, - {0x00000000, 0x00000000}, - {0x00000000, 0x00000000}, - {0x00000000, 0x00000000}, - {0x00000000, 0x00000000}, - {0x00000000, 0x00000000}}; - - - + static const uint32_t maintBuffer65thRegs[4][2]={ {MAINT0_MBS_MAINT_BUFF_65TH_BYTE_64B_ECC0_0x0201164A, MAINT1_MBS_MAINT_BUFF_65TH_BYTE_64B_ECC0_0x0201174A}, {MAINT0_MBS_MAINT_BUFF_65TH_BYTE_64B_ECC1_0x0201164B, MAINT1_MBS_MAINT_BUFF_65TH_BYTE_64B_ECC1_0x0201174B}, @@ -977,8 +1165,8 @@ fapi::ReturnCode mss_MaintCmd::loadPattern(PatternIndex i_initPattern) { // A write to MAINT_BUFFx_DATAy will not update until the corresponding // MAINT_BUFFx_DATA_ECCy is written to. - l_ecmd_rc |= l_data.insert(maintBufferData[loop][0], 0, 32, 0); - l_ecmd_rc |= l_data.insert(maintBufferData[loop][1], 32, 32, 0); + l_ecmd_rc |= l_data.insert(mss_maintBufferData[i_initPattern][loop][0], 0, 32, 0); + l_ecmd_rc |= l_data.insert(mss_maintBufferData[i_initPattern][loop][1], 32, 32, 0); if(l_ecmd_rc) { l_rc.setEcmdError(l_ecmd_rc); @@ -996,7 +1184,6 @@ fapi::ReturnCode mss_MaintCmd::loadPattern(PatternIndex i_initPattern) //---------------------------------------------------- FAPI_INF("Load the 65th byte: 4 loops to fill in the two 65th bytes in the cacheline"); - // For now, just use all 0's l_ecmd_rc |= l_65th.flushTo0(); // Set bit 56 so that hw will generate the fabric ECC. @@ -1007,20 +1194,19 @@ fapi::ReturnCode mss_MaintCmd::loadPattern(PatternIndex i_initPattern) l_rc.setEcmdError(l_ecmd_rc); return l_rc; } - for(loop=0; loop<4; loop++ ) { - l_rc = fapiPutScom(iv_targetCentaur, maintBuffer65thRegs[loop][iv_mbaPosition], l_65th); - if(l_rc) return l_rc; - } + l_ecmd_rc |= l_65th.insert(mss_65thByte[i_initPattern][loop], 1, 3, 1); + if(l_ecmd_rc) + { + l_rc.setEcmdError(l_ecmd_rc); + return l_rc; + } - - if (i_initPattern == PATTERN_1) - { - FAPI_INF("loading PATTERN_1"); - } - + l_rc = fapiPutScom(iv_targetCentaur, maintBuffer65thRegs[loop][iv_mbaPosition], l_65th); + if(l_rc) return l_rc; + } FAPI_INF("EXIT mss_MaintCmd::loadPattern()"); @@ -1178,7 +1364,7 @@ mss_SuperFastInit::mss_SuperFastInit( const fapi::Target & i_target, const ecmdDataBufferBase & i_startAddr, const ecmdDataBufferBase & i_endAddr, PatternIndex i_initPattern, - StopCondition i_stopCondition, + uint32_t i_stopCondition, bool i_poll ) : mss_MaintCmd( i_target, i_startAddr, @@ -1310,7 +1496,7 @@ mss_SuperFastRandomInit::mss_SuperFastRandomInit( const fapi::Target & i_target, const ecmdDataBufferBase & i_startAddr, const ecmdDataBufferBase & i_endAddr, PatternIndex i_initPattern, - StopCondition i_stopCondition, + uint32_t i_stopCondition, bool i_poll ) : mss_MaintCmd( i_target, i_startAddr, @@ -1364,7 +1550,7 @@ fapi::ReturnCode mss_SuperFastRandomInit::setupAndExecuteCmd() // Disable 8B ECC check/correct on WRD data bus: MBA_WRD_MODE(0:1) = 11 // before a SuperFastRandomInit command is issued - l_rc = fapiGetScom(iv_target, MBA01_MBA_WRD_MODE_0x03010429, iv_saved_MBA_WRD_MODE); + l_rc = fapiGetScom(iv_target, MBA01_MBA_WRD_MODE_0x03010449, iv_saved_MBA_WRD_MODE); if(l_rc) return l_rc; ecmdDataBufferBase l_data(64); @@ -1376,7 +1562,7 @@ fapi::ReturnCode mss_SuperFastRandomInit::setupAndExecuteCmd() l_rc.setEcmdError(l_ecmd_rc); return l_rc; } - l_rc = fapiPutScom(iv_target, MBA01_MBA_WRD_MODE_0x03010429, l_data); + l_rc = fapiPutScom(iv_target, MBA01_MBA_WRD_MODE_0x03010449, l_data); if(l_rc) return l_rc; // Start the command: MBMCCQ @@ -1435,7 +1621,7 @@ fapi::ReturnCode mss_SuperFastRandomInit::cleanupCmd() // Clear maintenance command complete attention, scrub stats, etc... // Restore MBA_WRD_MODE - l_rc = fapiPutScom(iv_target, MBA01_MBA_WRD_MODE_0x03010429, iv_saved_MBA_WRD_MODE); + l_rc = fapiPutScom(iv_target, MBA01_MBA_WRD_MODE_0x03010449, iv_saved_MBA_WRD_MODE); if(l_rc) return l_rc; FAPI_INF("EXIT mss_SuperFastRandomInit::cleanupCmd()"); @@ -1458,7 +1644,7 @@ const mss_MaintCmd::CmdType mss_SuperFastRead::cv_cmdType = SUPERFAST_READ; mss_SuperFastRead::mss_SuperFastRead( const fapi::Target & i_target, const ecmdDataBufferBase & i_startAddr, const ecmdDataBufferBase & i_endAddr, - StopCondition i_stopCondition, + uint32_t i_stopCondition, bool i_poll ) : mss_MaintCmd( i_target, i_startAddr, @@ -1476,7 +1662,8 @@ fapi::ReturnCode mss_SuperFastRead::setupAndExecuteCmd() FAPI_INF("ENTER mss_SuperFastRead::setupAndExecuteCmd()"); fapi::ReturnCode l_rc; - + uint32_t l_ecmd_rc = 0; + // Gather data that needs to be stored. For testing purposes we will just // set an abitrary number. //l_rc = setSavedData( 0xdeadbeef ); if(l_rc) return l_rc; @@ -1497,6 +1684,29 @@ fapi::ReturnCode mss_SuperFastRead::setupAndExecuteCmd() // Load stop conditions: MBASCTLQ l_rc = loadStopCondMask(); if(l_rc) return l_rc; + // Need to set RRQ to fifo mode to ensure super fast read commands + // are done on order. Otherwise, if cmds get out of order we can't be sure + // the trapped address in MBMACA will be correct when we stop + // on error. That means we could unintentionally skip addresses if we just + // try to increment MBMACA and continue. + // NOTE: Cleanup needs to be done to restore settings done. + l_rc = fapiGetScom(iv_target, MBA01_MBA_RRQ0Q_0x0301040E, iv_saved_MBA_RRQ0); + if(l_rc) return l_rc; + + ecmdDataBufferBase l_data(64); + l_ecmd_rc |= l_data.insert(iv_saved_MBA_RRQ0, 0, 64, 0); + l_ecmd_rc |= l_data.clearBit(6,5); // Set 6:10 = 00000 (fifo mode) + l_ecmd_rc |= l_data.setBit(12); // Disable MBA RRQ fastpath + if(l_ecmd_rc) + { + l_rc.setEcmdError(l_ecmd_rc); + return l_rc; + } + l_rc = fapiPutScom(iv_target, MBA01_MBA_RRQ0Q_0x0301040E, l_data); + if(l_rc) return l_rc; + + + /* // DEBUG. Set hard CE threshold to 1: MBSTRQ FAPI_INF("\nDEBUG. Set hard CE threshold to 1: MBSTRQ"); @@ -1567,6 +1777,10 @@ fapi::ReturnCode mss_SuperFastRead::cleanupCmd() // Restore the saved data. //printf( "Saved data: 0x%08x\n", getSavedData() ); + // Undo rrq fifo mode + l_rc = fapiPutScom(iv_target, MBA01_MBA_RRQ0Q_0x0301040E, iv_saved_MBA_RRQ0); + if(l_rc) return l_rc; + FAPI_INF("EXIT mss_SuperFastRead::cleanupCmd()"); return l_rc; @@ -1625,6 +1839,9 @@ fapi::ReturnCode mss_AtomicInject::setupAndExecuteCmd() // Load start address: MBMACAQ l_rc = loadStartAddress(); if(l_rc) return l_rc; + // Load stop conditions: MBASCTLQ + l_rc = loadStopCondMask(); if(l_rc) return l_rc; + // Load inject type: MBECTLQ ecmdDataBufferBase l_injectType(64); l_rc = fapiGetScom(iv_target, MBA01_MBECTLQ_0x03010610, l_injectType); @@ -1727,6 +1944,9 @@ fapi::ReturnCode mss_Display::setupAndExecuteCmd() // Load start address: MBMACAQ l_rc = loadStartAddress(); if(l_rc) return l_rc; + + // Load stop conditions: MBASCTLQ + l_rc = loadStopCondMask(); if(l_rc) return l_rc; // Start the command: MBMCCQ l_rc = startMaintCmd(); if(l_rc) return l_rc; @@ -1766,6 +1986,13 @@ fapi::ReturnCode mss_Display::setupAndExecuteCmd() MAINT0_MBA_MAINT_BUFF3_DATA1_0x03010686, MAINT0_MBA_MAINT_BUFF3_DATA2_0x03010687, MAINT0_MBA_MAINT_BUFF3_DATA3_0x03010688}; + + static const uint32_t maintBufferRead65thByteRegs[4]={ + MAINT0_MBA_MAINT_BUFF_65TH_BYTE_64B_ECC0_0x03010695, + MAINT0_MBA_MAINT_BUFF_65TH_BYTE_64B_ECC1_0x03010696, + MAINT0_MBA_MAINT_BUFF_65TH_BYTE_64B_ECC2_0x03010697, + MAINT0_MBA_MAINT_BUFF_65TH_BYTE_64B_ECC3_0x03010698}; + uint32_t loop = 0; ecmdDataBufferBase l_data(64); @@ -1781,14 +2008,20 @@ fapi::ReturnCode mss_Display::setupAndExecuteCmd() if(l_rc) return l_rc; } + //---------------------------------------------------- + // Read the 65th byte: 4 loops + //---------------------------------------------------- + FAPI_INF("Read the 65th byte: 4 loops"); + + for(loop=0; loop<4; loop++ ) + { + l_rc = fapiGetScom(iv_target, maintBufferRead65thByteRegs[loop], l_data); + if(l_rc) return l_rc; + } + // Collect FFDC l_rc = collectFFDC(); if(l_rc) return l_rc; - // Clear MBECCFIR - l_data.flushTo0(); - l_rc = fapiPutScom(iv_targetCentaur, mss_mbeccfir[iv_mbaPosition], l_data); - if(l_rc) return l_rc; - FAPI_INF("EXIT Display::setupAndExecuteCmd()"); return l_rc; @@ -1899,7 +2132,7 @@ mss_TimeBaseScrub::mss_TimeBaseScrub( const fapi::Target & i_target, const ecmdDataBufferBase & i_startAddr, const ecmdDataBufferBase & i_endAddr, TimeBaseSpeed i_speed, - StopCondition i_stopCondition, + uint32_t i_stopCondition, bool i_poll ) : mss_MaintCmd( i_target, i_startAddr, @@ -2105,8 +2338,7 @@ fapi::ReturnCode mss_get_address_range( const fapi::Target & i_target, { // Create new log. FAPI_ERR("MBAXCRn[0:3] = 0, meaning no memory configured behind this MBA."); - // DEBUG - // FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_NO_MEM_CNFG); + FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_NO_MEM_CNFG); return l_rc; } @@ -2225,18 +2457,8 @@ fapi::ReturnCode mss_get_address_range( const fapi::Target & i_target, { FAPI_INF("ATTR_IS_SIMULATION = 1, Awan/HWSimulator, so use smaller address range."); - /* - l_ecmd_rc |= o_endAddr.flushTo0(); - l_ecmd_rc |= o_endAddr.setBit(36); - l_ecmd_rc |= o_endAddr.setBit(35); - l_ecmd_rc |= o_endAddr.setBit(34); // DEBUG - l_ecmd_rc |= o_endAddr.setBit(33); // DEBUG - l_ecmd_rc |= o_endAddr.setBit(32); // DEBUG - l_ecmd_rc |= o_endAddr.setBit(31); // DEBUG - l_ecmd_rc |= o_endAddr.setBit(30); // DEBUG - */ - - // DEBUG - try whole rank0, row0, all banks all cols + + // Do only rank0, row0, all banks all cols l_end_rank = 0; uint32_t l_row_zero = 0; l_ecmd_rc |= o_endAddr.flushTo0(); @@ -2284,18 +2506,29 @@ fapi::ReturnCode mss_get_address_range( const fapi::Target & i_target, // NOTE: If this rank is not valid, we should see MBAFIR[1]: invalid // maint address, when cmd started - // DEBUG: Set start address to 8 addresses away from end of rank - //l_ecmd_rc |= o_startAddr.flushTo0(); - //l_ecmd_rc |= o_startAddr.insert( i_rank, 0, 4, 8-4 ); - //l_ecmd_rc |= o_startAddr.insert( (uint32_t)l_bank, 7, 4, 32-4 ); - //l_ecmd_rc |= o_startAddr.insert( (uint32_t)l_row, 11, 17, 32-17 ); - //l_ecmd_rc |= o_startAddr.insert( (uint32_t)l_col, 28, 9, 32-9 ); - //l_ecmd_rc |= o_startAddr.clearBit(32); - //l_ecmd_rc |= o_startAddr.clearBit(33); - //l_ecmd_rc |= o_startAddr.clearBit(34); - //l_ecmd_rc |= o_startAddr.clearBit(35); - //l_ecmd_rc |= o_startAddr.clearBit(36); + + // DEBUG - run on last few address of the rank + /* + // Set end address to end of rank + l_ecmd_rc |= o_endAddr.flushTo0(); + l_ecmd_rc |= o_endAddr.insert( i_rank, 0, 4, 8-4 ); + l_ecmd_rc |= o_endAddr.insert( (uint32_t)l_bank, 7, 4, 32-4 ); + l_ecmd_rc |= o_endAddr.insert( (uint32_t)l_row, 11, 17, 32-17 ); + l_ecmd_rc |= o_endAddr.insert( (uint32_t)l_col, 28, 12, 32-12 ); + + + // Set start address so we do all banks/cols in last row of the rank + uint32_t l_bank_zero = 0; + uint32_t l_col_zero = 0; + l_ecmd_rc |= o_startAddr.flushTo0(); + l_ecmd_rc |= o_startAddr.insert( i_rank, 0, 4, 8-4 ); + l_ecmd_rc |= o_startAddr.insert( (uint32_t)l_bank_zero, 7, 4, 32-4 ); + l_ecmd_rc |= o_startAddr.insert( (uint32_t)l_row, 11, 17, 32-17 ); + l_ecmd_rc |= o_startAddr.insert( (uint32_t)l_col_zero, 28, 12, 32-12 ); + */ + // DEBUG - run on last few address of the rank + // Start address is just i_rank with row/col/bank all 0's l_ecmd_rc |= o_startAddr.flushTo0(); @@ -2316,12 +2549,6 @@ fapi::ReturnCode mss_get_address_range( const fapi::Target & i_target, l_ecmd_rc |= o_endAddr.insert( (uint32_t)l_row_zero, 11, 17, 32-17 ); // COL = 28:39, note: c2, c1, c0 always 0 l_ecmd_rc |= o_endAddr.insert( (uint32_t)l_col, 28, 12, 32-12 ); - //l_ecmd_rc |= o_endAddr.setBit(35); // DEBUG - //l_ecmd_rc |= o_endAddr.setBit(34); // DEBUG - //l_ecmd_rc |= o_endAddr.setBit(33); // DEBUG - //l_ecmd_rc |= o_endAddr.setBit(32); // DEBUG - //l_ecmd_rc |= o_endAddr.setBit(31); // DEBUG - //l_ecmd_rc |= o_endAddr.setBit(30); // DEBUG } // Else, set end address to be last address of i_rank @@ -2335,8 +2562,9 @@ fapi::ReturnCode mss_get_address_range( const fapi::Target & i_target, // ROW = 11:27 l_ecmd_rc |= o_endAddr.insert( (uint32_t)l_row, 11, 17, 32-17 ); // COL = 28:36 - l_ecmd_rc |= o_endAddr.insert( (uint32_t)l_col, 28, 9, 32-9 ); - } + l_ecmd_rc |= o_endAddr.insert( (uint32_t)l_col, 28, 12, 32-12 ); + } + } if(l_ecmd_rc) diff --git a/src/usr/hwpf/hwp/dram_initialization/mss_memdiag/mss_maint_cmds.H b/src/usr/hwpf/hwp/dram_initialization/mss_memdiag/mss_maint_cmds.H index af09ef0ef..642dc341b 100644 --- a/src/usr/hwpf/hwp/dram_initialization/mss_memdiag/mss_maint_cmds.H +++ b/src/usr/hwpf/hwp/dram_initialization/mss_memdiag/mss_maint_cmds.H @@ -1,27 +1,26 @@ -/* IBM_PROLOG_BEGIN_TAG - * This is an automatically generated prolog. - * - * $Source: src/usr/hwpf/hwp/dram_initialization/mss_maint_cmds/mss_maint_cmds.H $ - * - * IBM CONFIDENTIAL - * - * COPYRIGHT International Business Machines Corp. 2012 - * - * p1 - * - * Object Code Only (OCO) source materials - * Licensed Internal Code Source Materials - * IBM HostBoot Licensed Internal Code - * - * The source code for this program is not published or other- - * wise divested of its trade secrets, irrespective of what has - * been deposited with the U.S. Copyright Office. - * - * Origin: 30 - * - * IBM_PROLOG_END_TAG - */ -// $Id: mss_maint_cmds.H,v 1.8 2012/07/18 21:36:50 gollub Exp $ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/dram_initialization/mss_memdiag/mss_maint_cmds.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2012 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +// $Id: mss_maint_cmds.H,v 1.10 2012/09/07 21:32:14 gollub Exp $ //------------------------------------------------------------------------------ // Don't forget to create CVS comments when you check in your changes! //------------------------------------------------------------------------------ @@ -38,7 +37,13 @@ // | 07/13/12 | gollub | Updates from review. // 1.7 | 07/16/12 | bellows | added in Id tag // 1.8 | 07/18/12 | gollub | Updates for timebase scrub. - +// 1.9 | 08/15/12 | gollub | Added stop condition enums +// | | | STOP_IMMEDIATE +// | | | ENABLE_CMD_COMPLETE_ATTENTION_ON_CLEAN_AND_ERROR +// | | | Added iv_saved_MBA_WRD_MODE to allow +// | | | save/restore of setting for super fast read +// 1.10 | 09/07/12 | gollub | Updates from review. +// | | | Support for more patterns. #ifndef _MSS_MAINT_CMDS_H @@ -108,22 +113,17 @@ class mss_MaintCmd /** * @brief Index into array containing data patterns to load into memory */ - // TODO: Array doesn't exist yet. - // Currently just hardcodeding one pattern: all 0's. enum PatternIndex { - PATTERN_0, - PATTERN_1, - PATTERN_2, - PATTERN_3, - PATTERN_4, - PATTERN_5, - PATTERN_6, - PATTERN_7, - PATTERN_8, - PATTERN_9, - PATTERN_11, - PATTERN_RANDOM, + PATTERN_0 = 0, //0x00 + PATTERN_1 = 1, //0xFF + PATTERN_2 = 2, //0xF0 + PATTERN_3 = 3, //0x0F + PATTERN_4 = 4, //0xAA + PATTERN_5 = 5, //0x55 + PATTERN_6 = 6, //0xCC + PATTERN_7 = 7, //0x33 + PATTERN_RANDOM = 1, // NOTE: Using PATTERN_1 as random seed }; /** @@ -145,41 +145,49 @@ class mss_MaintCmd // Turn off all stop conditions NO_STOP_CONDITIONS = 0x0000, - // Stop at end of rank if stop condition hit - STOP_END_OF_RANK = 0x8000, + // Stop immediately if stop on error condition hit + STOP_IMMEDIATE = 0x8000, + + // Stop at end of rank if stop on error condition hit + STOP_END_OF_RANK = 0x4000, // Stop on hard new CE error threshlold equal - STOP_ON_HARD_NCE_ETE = 0x4000, + STOP_ON_HARD_NCE_ETE = 0x2000, // Stop on intermittent new CE error threshlold equal - STOP_ON_INT_NCE_ETE = 0x2000, + STOP_ON_INT_NCE_ETE = 0x1000, // Stop on soft new CE error threshlold equal - STOP_ON_SOFT_NCE_ETE = 0x1000, + STOP_ON_SOFT_NCE_ETE = 0x0800, // Stop on symbol corrected error (error on symbol already marked) - STOP_ON_SCE = 0x0800, + STOP_ON_SCE = 0x0400, // Stop on mark corrected error (error on chip already marked) - STOP_ON_MCE = 0x0400, + STOP_ON_MCE = 0x0200, // Stop on retry CE (UE that went away on retry) - STOP_ON_RETRY_CE = 0x0200, + STOP_ON_RETRY_CE = 0x0100, // Stop on mark placed error (hw placed a chip mark) - STOP_ON_MPE = 0x0100, + STOP_ON_MPE = 0x0080, // Stop on UE - STOP_ON_UE = 0x0080, + STOP_ON_UE = 0x0040, // Stop on SUE - STOP_ON_SUE = 0x0040, + STOP_ON_SUE = 0x0020, // Stop when MBMACAQ = MBMEAQ - STOP_ON_END_ADDRESS = 0x0020, + STOP_ON_END_ADDRESS = 0x0010, // Enable command complete attention - ENABLE_CMD_COMPLETE_ATTENTION = 0x0010, + ENABLE_CMD_COMPLETE_ATTENTION = 0x0008, + + // Enable command complete attention for both stop clean, and stop + // due to error + ENABLE_CMD_COMPLETE_ATTENTION_ON_CLEAN_AND_ERROR = 0x0004, + }; /** @@ -233,7 +241,7 @@ class mss_MaintCmd mss_MaintCmd( const fapi::Target & i_target, const ecmdDataBufferBase & i_startAddr, const ecmdDataBufferBase & i_endAddr, - StopCondition i_stopCondition, + uint32_t i_stopCondition, bool i_poll, CmdType i_cmdType ); @@ -368,7 +376,7 @@ class mss_MaintCmd fapi::Target iv_targetCentaur; // Centaur associated with this MBA ecmdDataBufferBase iv_startAddr; // Start address ecmdDataBufferBase iv_endAddr; // End address - StopCondition iv_stopCondition; // Mask of stop contitions + uint32_t iv_stopCondition; // Mask of stop contitions bool iv_poll; // Set true to wait for cmd complete const CmdType iv_cmdType; // Command type uint8_t iv_mbaPosition; // 0 = mba01, 1 = mba23 @@ -395,7 +403,7 @@ class mss_SuperFastInit : public mss_MaintCmd const ecmdDataBufferBase & i_startAddr, // Address cmd will start at const ecmdDataBufferBase & i_endAddr, // Address cmd will stop at PatternIndex i_initPattern, // Index into table containing patterns to load into memory - StopCondition i_stopCondition, // Mask of error conditions cmd should stop on + uint32_t i_stopCondition, // Mask of error conditions cmd should stop on bool i_poll ); // Set to true if you wait for command to complete public: @@ -450,7 +458,7 @@ class mss_SuperFastRandomInit : public mss_MaintCmd const ecmdDataBufferBase & i_startAddr, // Address cmd will start at const ecmdDataBufferBase & i_endAddr, // Address cmd will stop at PatternIndex i_initPattern, // Index into table containing pattern to use for random seed - StopCondition i_stopCondition, // Mask of error conditions cmd should stop on + uint32_t i_stopCondition, // Mask of error conditions cmd should stop on bool i_poll ); // Set to true if you wait for command to complete public: @@ -506,7 +514,7 @@ class mss_SuperFastRead : public mss_MaintCmd mss_SuperFastRead( const fapi::Target & i_target, // MBA target const ecmdDataBufferBase & i_startAddr, // Address cmd will start at const ecmdDataBufferBase & i_endAddr, // Address cmd will stop at - StopCondition i_stopCondition, // Mask of error conditions cmd should stop on + uint32_t i_stopCondition, // Mask of error conditions cmd should stop on bool i_poll ); // Set to true if you wait for command to complete public: @@ -543,6 +551,9 @@ class mss_SuperFastRead : public mss_MaintCmd // List of things to save may be cmd-specific, so keep it here for now uint32_t iv_savedData; + // Setting that had to be restored when done + ecmdDataBufferBase iv_saved_MBA_RRQ0; + }; @@ -668,7 +679,7 @@ class mss_TimeBaseScrub : public mss_MaintCmd const ecmdDataBufferBase & i_startAddr, // Address cmd will start at const ecmdDataBufferBase & i_endAddr, // Address cmd will stop at TimeBaseSpeed i_speed, // Fast as possible, or slow (all memory on the MBA in 12h) - StopCondition i_stopCondition, // Mask of error conditions cmd should stop on + uint32_t i_stopCondition, // Mask of error conditions cmd should stop on bool i_poll ); // Set to true if you wait for command to complete public: @@ -826,4 +837,6 @@ fapi::ReturnCode mss_put_steer_mux( const fapi::Target & i_target, uint8_t i_symbol ); + + #endif /* _MSS_MAINT_CMDS_H */ diff --git a/src/usr/hwpf/hwp/dram_training/mss_scominit/mss_scominit.C b/src/usr/hwpf/hwp/dram_training/mss_scominit/mss_scominit.C index 7750001dd..8f9d6fd8e 100644 --- a/src/usr/hwpf/hwp/dram_training/mss_scominit/mss_scominit.C +++ b/src/usr/hwpf/hwp/dram_training/mss_scominit/mss_scominit.C @@ -1,27 +1,26 @@ -/* IBM_PROLOG_BEGIN_TAG - * This is an automatically generated prolog. - * - * $Source: src/usr/hwpf/hwp/dram_training/mss_scominit/mss_scominit.C $ - * - * IBM CONFIDENTIAL - * - * COPYRIGHT International Business Machines Corp. 2012 - * - * p1 - * - * Object Code Only (OCO) source materials - * Licensed Internal Code Source Materials - * IBM HostBoot Licensed Internal Code - * - * The source code for this program is not published or other- - * wise divested of its trade secrets, irrespective of what has - * been deposited with the U.S. Copyright Office. - * - * Origin: 30 - * - * IBM_PROLOG_END_TAG - */ -// $Id: mss_scominit.C,v 1.8 2012/07/17 13:24:42 bellows Exp $ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/dram_training/mss_scominit/mss_scominit.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2012 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +// $Id: mss_scominit.C,v 1.11 2012/08/23 00:11:37 mwuu Exp $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 // *! All Rights Reserved -- Property of IBM @@ -42,10 +41,15 @@ //------------------------------------------------------------------------------ // Version:| Author: | Date: | Comment: //---------|----------|---------|----------------------------------------------- +// 1.11 | menlowuu |22-AUG-12| Added return code for mss_set_bbm_regs FN. +// 1.10 | menlowuu |21-AUG-12| Removed running *_mcbist files since it was +// moved into the *_def files. +// 1.9 | menlowuu |15-AUG-12| Added disable bit set FN, reused rc, added +// mbs/mba_mcbist.if to the scominit FN. // 1.8 | bellows |16-JUL-12| added in Id tag // 1.7 | menlowuu |14-JUN-12| Added fixes suggested by Mike, // replace rc_num with ReturnCode, created RC for when -// MBAs != 2, and return on all errors +// MBAs != 2, and return on all errors // 1.6 | menlowuu |08-JUN-12| Fixed inserting centaur vector & return code. // 1.5 | menlowuu |06-JUN-12| Added code to use // primary centaur target, secondary mba[0/1] for mbs.if; @@ -63,21 +67,219 @@ //---------------------------------------------------------------------- // Includes //---------------------------------------------------------------------- +#include <fapi.H> +#include <dimmBadDqBitmapFuncs.H> #include <fapiHwpExecInitFile.H> +//---------------------------------------------------------------------- +// Constants +//---------------------------------------------------------------------- +#define MAX_PORTS 2 +#define MAX_PRI_RANKS 4 +#define TOTAL_BYTES 10 + extern "C" { using namespace fapi; //****************************************************************************** +// expects i_target = functional MBA target, MBA position (uint8_t) +// sets bad bit mask (disable0) registers in the PHY with data from SPD +//****************************************************************************** +fapi::ReturnCode mss_set_bbm_regs (const fapi::Target & mba_target, + const uint8_t mba_pos) +{ + // DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_0_0x8000007C0301143F + const uint64_t base_addr = 0x8000007C0301143Full; + const uint8_t rg_invalid[] = { + ENUM_ATTR_EFF_PRIMARY_RANK_GROUP0_INVALID, + ENUM_ATTR_EFF_PRIMARY_RANK_GROUP1_INVALID, + ENUM_ATTR_EFF_PRIMARY_RANK_GROUP2_INVALID, + ENUM_ATTR_EFF_PRIMARY_RANK_GROUP3_INVALID, + }; + + ReturnCode rc; + uint64_t address = base_addr; + ecmdDataBufferBase data_buffer(64); + uint8_t prg[MAX_PRI_RANKS][MAX_PORTS]; // primary rank group values + + FAPI_INF("Running set bad bits FN:mss_set_bbm_regs on \nMBA%i," + " input Target: %s", mba_pos, mba_target.toEcmdString()); + + std::vector<Target> mba_dimms; + fapiGetAssociatedDimms(mba_target, mba_dimms); // functional dimms + + FAPI_INF("***-------- Found %i functional DIMMS in MBA%i --------***", + mba_dimms.size(), mba_pos); + + // 4 dimms per MBA, 2 per port +/* + RAW SPD 0 1 2 3 4 5 6 7 8 9 A B C D E F + b0: 0000 0000 0000 0000 0000 0000 0000 0000 + c0: 0000 0000 0000 0000 0000 0000 0000 0000 + d0: 0000 0000 0000 0000 0000 0000 0000 0000 + e0: 0000 0000 0000 0000 0000 0000 0000 00FE + f0: 0000 0000 0000 0000 0000 0000 0000 00FF +*/ +// uint8_t bad_dq_data[80] = { +// /* spd |------------ HEADER ----------------------------------------- +// * byte# |--- magic number ----|-ver-|---- reserved ----| +// * 0-7 */ 0xBA, 0xDD, 0x44, 0x71, 0x01, 0x00, 0x00, 0x00, +// /* |------------------- DATA --------------------| ECC |SPARE| +// * 0 1 2 3 4 5 6 7 8 9 +// * 8-17*/ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +// /* 18-27*/ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +// /* 28-37*/ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +// /* 38-47*/ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +// /* 48-49*/ 0x00, 0x00, +// /* 50-59*/ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +// /* 60-69*/ 0x00, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +// /* 70-79*/ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF +// }; +/* + for (uint8_t d = 0; d < 8; d++) + { + rc=FAPI_ATTR_SET(ATTR_SPD_BAD_DQ_DATA, &mba_dimms[0], bad_dq_data); + if (rc) + { + FAPI_ERR("Error performing FAPI_ATTR_SET on ATTR_SPD_BAD_DQ_DATA"); + } + } +*/ + // ATTR_EFF_PRIMARY_RANK_GROUP0[port], GROUP1[port], GROUP2[port], GROUP3[port] + rc=FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP0, &mba_target, prg[0]); + if(rc) return rc; + rc=FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP1, &mba_target, prg[1]); + if(rc) return rc; + rc=FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP2, &mba_target, prg[2]); + if(rc) return rc; + rc=FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP3, &mba_target, prg[3]); + if(rc) return rc; + + for (uint8_t port = 0; port < MAX_PORTS; port++ ) // [0:1] + { + uint8_t l_bbm[TOTAL_BYTES] = {0}; // bad bits + + // port 0 = 0x8000..., port 1 = 0x8001... + address = address | ((uint64_t)port << 48); + + // loop through primary ranks [0:3] + for (uint8_t prank = 0; prank < MAX_PRI_RANKS; prank++ ) + { + // 0x800p 0r7C 0301 143F + uint64_t r_addr = address | ((uint64_t)prank << 40); + uint8_t dimm = prg[prank][port] >> 2; + uint8_t rank = prg[prank][port] & 0x03; + uint8_t bbm_e = 0, bbm_o = 0; + +// uint8_t spd_data[10] = { +// // |-------------------- DATA ----------- --------| ECC |SPARE| +// //byte 0 1 2 3 4 5 6 7 8 9 +// 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +// }; +/* + rc = dimmSetBadDqBitmap(mba_target, port, dimm, rank, spd_data); + if (rc) + { + FAPI_ERR("Error from dimmSetBadDqBitmap on MBA%ip%i: dimm=%i, + rank=%i rc=%i", mba_pos, port, dimm, rank, + static_cast<uint32_t>(rc)); + return rc; + break; + } +*/ + if (prg[prank][port] != rg_invalid[prank]) // valid rank group + { + rc = dimmGetBadDqBitmap(mba_target, port, dimm, rank, l_bbm); + if (rc) + { + FAPI_ERR("Error from dimmGetBadDqBitmap on MBA%ip%i: " + "dimm=%i, rank=%i rc=%i", mba_pos, port, dimm, rank, + static_cast<uint32_t>(rc)); + + return rc; + break; + } + } + + for ( uint8_t i=0; i < TOTAL_BYTES/2; i++ ) // [0:4] dp18 instances + { + uint64_t scom_addr = r_addr | ((uint64_t) i << 42); + uint64_t l_data = 0; + uint32_t l_ecmdRc = ECMD_DBUF_SUCCESS; + + if (prg[prank][port] == rg_invalid[prank]) // invalid rank + { + FAPI_INF("Primary rank group %i is invalid, prepare" + " broadcast write to all instances", prank); + + l_data = 0xFFFF; // invalidate data bits + // set address to broadcast to all instances in the rank + scom_addr = scom_addr | 0x00003C0000000000ull; + } + else + { // scom signifies port dimm rank byte + bbm_e = l_bbm[i*2]; // even byte data + bbm_o = l_bbm[(i*2)+1]; // odd byte data + l_data = (bbm_e << 8) | bbm_o; + if (l_data == 0) + { + // no need to set register since bits are good? + continue; // should double check! + } + } + + // ecmdDataBufferBase data_buffer(64); + l_ecmdRc = data_buffer.setDoubleWord(0, l_data); + + if (l_ecmdRc != ECMD_DBUF_SUCCESS) + { + FAPI_ERR("Error from ecmdDataBuffer setDoubleWord() " + "- rc 0x%.8X", l_ecmdRc); + + rc.setEcmdError(l_ecmdRc); + break; + } + + FAPI_INF("+++ Setting Bad Bit Mask in MBA%ip%i: PRG%i=%i," + " addr=0x%llx, data=0x%04llx", mba_pos, port, prank, + prg[prank][port], scom_addr, l_data); + + rc = fapiPutScom(mba_target, scom_addr, data_buffer); + if (rc) + { + FAPI_ERR("Error from fapiPutScom"); + break; + } + if (prg[prank][port] == rg_invalid[prank]) // invalid rank + { + FAPI_INF("Disabled primary rank group %i data bits" + " via broadcast continuing to next rank", prank); + + // did broadcast to all instances in rank move to next rank + break; + } + } // end byte loop + } // end primary rank loop + } // end port loop + return rc; +} // end mss_set_bbm_regs + +//****************************************************************************** // //****************************************************************************** ReturnCode mss_scominit(const Target & i_target) { ReturnCode rc; std::vector<Target> vector_targets; - const char* mbs_if = "mbs_def.if"; - const char* mba_if = "mba_def.if"; - const char* phy_if = "cen_ddrphy.if"; + const char* mbs_if[] = { + "mbs_def.if", + /* "mbs_mcbist.if" // moved into mbs_def file */ + }; + const char* mba_if[] = { + "mba_def.if", + /* "mba_mcbist.if", // moved into mba_def file */ + "cen_ddrphy.if" + }; FAPI_INF("Performing HWP: mss_scominit"); @@ -96,12 +298,11 @@ ReturnCode mss_scominit(const Target & i_target) { } else if (vector_targets.size() != 2) { - ReturnCode l_rc; FAPI_ERR("fapiGetChildChiplets returned present MBAs != 2"); - FAPI_SET_HWP_ERROR(l_rc, RC_MSS_NUM_MBA_ERROR); + FAPI_SET_HWP_ERROR(rc, RC_MSS_NUM_MBA_ERROR); FAPI_ERR("Present MBAs = %i, generating RC_MSS_NUM_MBA_ERROR = 0x%x", - vector_targets.size(), static_cast<uint32_t>(l_rc)); - return (l_rc); + vector_targets.size(), static_cast<uint32_t>(rc)); + return (rc); } else { @@ -109,17 +310,21 @@ ReturnCode mss_scominit(const Target & i_target) { vector_targets.insert(vector_targets.begin(),i_target); // run mbs initfile... - FAPI_EXEC_HWP(rc, fapiHwpExecInitFile, vector_targets, mbs_if); - - if (rc) - { - FAPI_ERR(" !!! Error running MBS %s, RC = 0x%x", - mbs_if, static_cast<uint32_t>(rc)); - return (rc); - } - else + uint8_t num_mbs_files = sizeof(mbs_if)/sizeof(char*); + for (uint8_t itr=0; itr < num_mbs_files; itr++) { - FAPI_INF("MBS scom initfile %s passed", mbs_if); + FAPI_EXEC_HWP(rc, fapiHwpExecInitFile, vector_targets, mbs_if[itr]); + + if (rc) + { + FAPI_ERR(" !!! Error running MBS %s, RC = 0x%x", + mbs_if[itr], static_cast<uint32_t>(rc)); + return (rc); + } + else + { + FAPI_INF("MBS scom initfile %s passed", mbs_if[itr]); + } } } @@ -138,7 +343,7 @@ ReturnCode mss_scominit(const Target & i_target) { { uint8_t l_unitPos = 0; - FAPI_INF("Found %i MBA chiplets", vector_targets.size()); + FAPI_INF("Found %i functional MBA chiplets", vector_targets.size()); // Iterate through the returned chiplets for (uint32_t i = 0; i < vector_targets.size(); i++) @@ -161,39 +366,41 @@ ReturnCode mss_scominit(const Target & i_target) { mba_cen_targets.push_back(vector_targets[i]); mba_cen_targets.push_back(i_target); - // run mba and phy initfiles... - // Call Hwp to execute the mba_if file - FAPI_EXEC_HWP(rc, fapiHwpExecInitFile, mba_cen_targets, mba_if); - - if (rc) + // run mba initfiles... + uint8_t num_mba_files = sizeof(mba_if)/sizeof(char*); + for (uint8_t itr=0; itr < num_mba_files; itr++) { - FAPI_ERR(" !!! Error running MBA%i %s, RC = 0x%x", - l_unitPos, mba_if, static_cast<uint32_t>(rc)); - return (rc); - } - else - { - FAPI_INF("MBA%i initfile %s passed", l_unitPos, mba_if); - } + FAPI_EXEC_HWP(rc, fapiHwpExecInitFile, mba_cen_targets, + mba_if[itr]); - // Call Hwp to execute the phy_if file - FAPI_EXEC_HWP(rc, fapiHwpExecInitFile, mba_cen_targets, phy_if); + if (rc) + { + FAPI_ERR(" !!! Error running MBA %s, RC = 0x%x", + mba_if[itr], static_cast<uint32_t>(rc)); + return (rc); + } + else + { + FAPI_INF("MBA scom initfile %s passed", mba_if[itr]); + } + } // end for loop, running MBA/PHY initfiles + // set bad bits from SPD into disable bit registers + rc=mss_set_bbm_regs(vector_targets[i], l_unitPos); if (rc) { - FAPI_ERR(" !!! Error running MBA%i %s, RC = 0x%x", - l_unitPos, phy_if, static_cast<uint32_t>(rc)); + FAPI_INF("Error setting disable bit mask registers"); return (rc); } else { - FAPI_INF("MBA%i PHY initfile %s passed", l_unitPos, phy_if); + FAPI_INF("mss_set_bbm_regs FN passed on MBA%i", l_unitPos); } - } // end MBA/PHY fapiHwpExecInitFile - } // valid chip unit pos + } // end else, MBA fapiHwpExecInitFile + } // end for loop, valid chip unit pos } // found functional MBAs return (rc); -} +} // end mss_scominit } // extern "C" diff --git a/src/usr/hwpf/hwp/dram_training/mss_scominit/mss_scominit.H b/src/usr/hwpf/hwp/dram_training/mss_scominit/mss_scominit.H index 8c3b03aa5..7319bfd6f 100644 --- a/src/usr/hwpf/hwp/dram_training/mss_scominit/mss_scominit.H +++ b/src/usr/hwpf/hwp/dram_training/mss_scominit/mss_scominit.H @@ -1,27 +1,26 @@ -/* IBM_PROLOG_BEGIN_TAG - * This is an automatically generated prolog. - * - * $Source: src/usr/hwpf/hwp/dram_training/mss_scominit/mss_scominit.H $ - * - * IBM CONFIDENTIAL - * - * COPYRIGHT International Business Machines Corp. 2012 - * - * p1 - * - * Object Code Only (OCO) source materials - * Licensed Internal Code Source Materials - * IBM HostBoot Licensed Internal Code - * - * The source code for this program is not published or other- - * wise divested of its trade secrets, irrespective of what has - * been deposited with the U.S. Copyright Office. - * - * Origin: 30 - * - * IBM_PROLOG_END_TAG - */ -// $Id: mss_scominit.H,v 1.5 2012/07/17 13:23:28 bellows Exp $ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/dram_training/mss_scominit/mss_scominit.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2012 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +// $Id: mss_scominit.H,v 1.6 2012/08/15 23:07:26 mwuu Exp $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 // *! All Rights Reserved -- Property of IBM @@ -42,6 +41,7 @@ //------------------------------------------------------------------------------ // Version:| Author: | Date: | Comment: //---------|----------|---------|----------------------------------------------- +// 1.6 | menlowuu |15-AUG-12| added bad bitmask function // 1.5 |bellows |16-JUL-12| added in Id tag // 1.4 | menlowuu |20-JUN-12| added type to the typedef // 1.3 | menlowuu |13-JUN-12| added & to reference i_target in FP_t function @@ -64,6 +64,8 @@ #include <fapi.H> typedef fapi::ReturnCode (*mss_scominit_FP_t)(const fapi::Target & i_target); +typedef fapi::ReturnCode (*mss_set_bbm_regs_FP_t)(const fapi::Target + & mba_target, const uint8_t mba_pos); extern "C" { @@ -76,6 +78,18 @@ extern "C" { fapi::ReturnCode mss_scominit(const fapi::Target & i_target); + +//****************************************************************************** +// mss_set_bbm_regs +//****************************************************************************** +// mss_set_bbm_regs procedure [Sets disable bits in PHY registers for bad bit lanes] +// param[in] i_target [Reference to target, expecting MBA target], +// mba_pos [mba position, 0=mba01, 1=mba23] +// return ReturnCode + +fapi::ReturnCode mss_set_bbm_regs(const fapi::Target & mba_target, + const uint8_t mba_pos); + } // extern "C" #endif // MSS_SCOMINIT_H_ diff --git a/src/usr/hwpf/hwp/include/cen_scom_addresses.H b/src/usr/hwpf/hwp/include/cen_scom_addresses.H index cfb40a942..0b69218b0 100755 --- a/src/usr/hwpf/hwp/include/cen_scom_addresses.H +++ b/src/usr/hwpf/hwp/include/cen_scom_addresses.H @@ -1,27 +1,26 @@ -/* IBM_PROLOG_BEGIN_TAG - * This is an automatically generated prolog. - * - * $Source: src/usr/hwpf/hwp/include/cen_scom_addresses.H $ - * - * IBM CONFIDENTIAL - * - * COPYRIGHT International Business Machines Corp. 2012 - * - * p1 - * - * Object Code Only (OCO) source materials - * Licensed Internal Code Source Materials - * IBM HostBoot Licensed Internal Code - * - * The source code for this program is not published or other- - * wise divested of its trade secrets, irrespective of what has - * been deposited with the U.S. Copyright Office. - * - * Origin: 30 - * - * IBM_PROLOG_END_TAG - */ -// $Id: cen_scom_addresses.H,v 1.22 2012/06/18 01:58:44 jmcgill Exp $ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/include/cen_scom_addresses.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2012 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +// $Id: cen_scom_addresses.H,v 1.28 2012/09/10 14:34:14 jdsloat Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/cen_scom_addresses.H,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 @@ -46,6 +45,20 @@ // Version:| Author: | Date: | Comment: //---------|----------|---------|----------------------------------------------- // | | | +// 1.28 | jdsloat |10-Sep-12| Fixed MBA CAL Names +// 1.27 | gollub |07-Sep-12| Fixed address for MBA01_MBA_WRD_MODE +// | | | Added Maint Read Buffers 65th Byte +// 1.26 | jdsloat |06-Sep-12| Added MBA CAL Registers +// 1.25 | gollub |31-Aug-12| Added MBACALFIR Registers +// | | | Added MBSFIR Registers +// | | | Added MBAFIR Registers +// | | | Added MBSPA Registers +// | | | Added MBECCFIR Registers +// | | | Added SCAC Registers +// 1.24 | jdsloat |20-Aug-12| Added Primary Rank Pair MRS Shadow Regs +// 1.23 | gollub |27-Jul-12| Added MBS FIR Registers +// | | | Added DDRPHY FIR Registers +// | | | Added MBA_RRQ Register // 1.22 | jmcgill |17-Jun-12| Added trace related SCOM addresses // 1.21 | gollub |23-May-12| Added regs needed for mss_maint_cmds // 1.20 | jdsloat |17-May-12| Added MBA/MBS level PM, REF register addresses @@ -318,6 +331,22 @@ CONST_UINT64_T( DPHY01_DDRPHY_PC_RESETS_P0_0x8000C00E0301143F, CONST_UINT64_T( DPHY01_DDRPHY_PC_RESETS_P1_0x8001C00E0301143F, ULL(0x8001C00E0301143F) ); CONST_UINT64_T( DPHY01_DDRPHY_PC_IO_PVT_FET_CONTROL_P0_0x8000C0140301143F, ULL(0x8000C0140301143F) ); CONST_UINT64_T( DPHY01_DDRPHY_PC_IO_PVT_FET_CONTROL_P1_0x8001C0140301143F, ULL(0x8001C0140301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_PC_MR0_PRI_RP0_P0_0x8000C01C0301143F, ULL(0x8000C01C0301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_PC_MR1_PRI_RP0_P0_0x8000C01D0301143F, ULL(0x8000C01D0301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_PC_MR2_PRI_RP0_P0_0x8000C01E0301143F, ULL(0x8000C01E0301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_PC_MR3_PRI_RP0_P0_0x8000C01F0301143F, ULL(0x8000C01F0301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_PC_MR0_PRI_RP1_P0_0x8000C11C0301143F, ULL(0x8000C11C0301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_PC_MR1_PRI_RP1_P0_0x8000C11D0301143F, ULL(0x8000C11D0301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_PC_MR2_PRI_RP1_P0_0x8000C11E0301143F, ULL(0x8000C11E0301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_PC_MR3_PRI_RP1_P0_0x8000C11F0301143F, ULL(0x8000C11F0301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_PC_MR0_PRI_RP2_P0_0x8000C21C0301143F, ULL(0x8000C21C0301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_PC_MR1_PRI_RP2_P0_0x8000C21D0301143F, ULL(0x8000C21D0301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_PC_MR2_PRI_RP2_P0_0x8000C21E0301143F, ULL(0x8000C21E0301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_PC_MR3_PRI_RP2_P0_0x8000C21F0301143F, ULL(0x8000C21F0301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_PC_MR0_PRI_RP3_P0_0x8000C31C0301143F, ULL(0x8000C31C0301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_PC_MR1_PRI_RP3_P0_0x8000C31D0301143F, ULL(0x8000C31D0301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_PC_MR2_PRI_RP3_P0_0x8000C31E0301143F, ULL(0x8000C31E0301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_PC_MR3_PRI_RP3_P0_0x8000C31F0301143F, ULL(0x8000C31F0301143F) ); //------------------------------------------------------------------------------ // CALIBRATION SCOM ADDRESSES (DPHY REGISTERS) @@ -347,6 +376,11 @@ CONST_UINT64_T( DPHY01_DDRPHY_PC_PER_ZCAL_CONFIG_P1_0x8001C00F0301143F, // MBA Fault Isolation Register //------------------------------------------------------------------------------ CONST_UINT64_T( MBA01_MBAFIRQ_0x03010600 , ULL(0x03010600) ); +CONST_UINT64_T( MBA01_MBAFIRMASK_0x03010603 , ULL(0x03010603) ); +CONST_UINT64_T( MBA01_MBAFIRMASK_AND_0x03010604 , ULL(0x03010604) ); +CONST_UINT64_T( MBA01_MBAFIRMASK_OR_0x03010605 , ULL(0x03010605) ); +CONST_UINT64_T( MBA01_MBAFIRACT0_0x03010606 , ULL(0x03010606) ); +CONST_UINT64_T( MBA01_MBAFIRACT1_0x03010607 , ULL(0x03010607) ); //------------------------------------------------------------------------------ // MBA Maintenance Command Type Register @@ -387,31 +421,43 @@ CONST_UINT64_T( MBA01_MBECTLQ_0x03010610 , ULL(0x03010610) ); // MBA Special Attention Register //------------------------------------------------------------------------------ CONST_UINT64_T( MBA01_MBSPAQ_0x03010611 , ULL(0x03010611) ); +CONST_UINT64_T( MBA01_MBSPAMSKQ_0x03010614 , ULL(0x03010614) ); //------------------------------------------------------------------------------ // MBA Maint Read Buffers corresponding to ports 0/1 //------------------------------------------------------------------------------ +// Maint Read Buffer0 CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF0_DATA0_0x03010655 , ULL(0x03010655) ); CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF0_DATA1_0x03010656 , ULL(0x03010656) ); CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF0_DATA2_0x03010657 , ULL(0x03010657) ); CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF0_DATA3_0x03010658 , ULL(0x03010658) ); +// Maint Read Buffer1 CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF1_DATA0_0x03010665 , ULL(0x03010665) ); CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF1_DATA1_0x03010666 , ULL(0x03010666) ); CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF1_DATA2_0x03010667 , ULL(0x03010667) ); CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF1_DATA3_0x03010668 , ULL(0x03010668) ); +// Maint Read Buffer2 CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF2_DATA0_0x03010675 , ULL(0x03010675) ); CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF2_DATA1_0x03010676 , ULL(0x03010676) ); CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF2_DATA2_0x03010677 , ULL(0x03010677) ); CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF2_DATA3_0x03010678 , ULL(0x03010678) ); +// Maint Read Buffer3 CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF3_DATA0_0x03010685 , ULL(0x03010685) ); CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF3_DATA1_0x03010686 , ULL(0x03010686) ); CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF3_DATA2_0x03010687 , ULL(0x03010687) ); CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF3_DATA3_0x03010688 , ULL(0x03010688) ); +// Maint Read Buffers 65th Byte +CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF_65TH_BYTE_64B_ECC0_0x03010695 , ULL(0x03010695) ); +CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF_65TH_BYTE_64B_ECC1_0x03010696 , ULL(0x03010696) ); +CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF_65TH_BYTE_64B_ECC2_0x03010697 , ULL(0x03010697) ); +CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF_65TH_BYTE_64B_ECC3_0x03010698 , ULL(0x03010698) ); + + //------------------------------------------------------------------------------ // MBA Write Bit Steer Control Registers //------------------------------------------------------------------------------ @@ -425,14 +471,19 @@ CONST_UINT64_T( MBA01_MBABS6_0x03010446 , ULL(0x03010446) ); CONST_UINT64_T( MBA01_MBABS7_0x03010447 , ULL(0x03010447) ); //------------------------------------------------------------------------------ -// MBA CAL FIR Register +// MBA CAL FIR Registers //------------------------------------------------------------------------------ CONST_UINT64_T( MBA01_MBACALFIR_0x03010400 , ULL(0x03010400) ); +CONST_UINT64_T( MBA01_MBACALFIR_MASK_0x03010403 , ULL(0x03010403) ); +CONST_UINT64_T( MBA01_MBACALFIR_MASK_AND_0x03010404 , ULL(0x03010404) ); +CONST_UINT64_T( MBA01_MBACALFIR_MASK_OR_0x03010405 , ULL(0x03010405) ); +CONST_UINT64_T( MBA01_MBACALFIR_ACTION0_0x03010406 , ULL(0x03010406) ); +CONST_UINT64_T( MBA01_MBACALFIR_ACTION1_0x03010407 , ULL(0x03010407) ); //------------------------------------------------------------------------------ // MBA WRD Mode Register //------------------------------------------------------------------------------ -CONST_UINT64_T( MBA01_MBA_WRD_MODE_0x03010429 , ULL(0x03010429) ); +CONST_UINT64_T( MBA01_MBA_WRD_MODE_0x03010449 , ULL(0x03010449) ); @@ -448,7 +499,18 @@ CONST_UINT64_T( MBAXCR23Q_0x0201140C , ULL(0x0201140C) ); // MBS ECC Decoder FIR Registers //------------------------------------------------------------------------------ CONST_UINT64_T( MBS_ECC0_MBECCFIR_0x02011440 , ULL(0x02011440) ); +CONST_UINT64_T( MBS_ECC0_MBECCFIR_MASK_0x02011443 , ULL(0x02011443) ); +CONST_UINT64_T( MBS_ECC0_MBECCFIR_MASK_AND_0x02011444 , ULL(0x02011444) ); +CONST_UINT64_T( MBS_ECC0_MBECCFIR_MASK_OR_0x02011445 , ULL(0x02011445) ); +CONST_UINT64_T( MBS_ECC0_MBECCFIR_ACTION0_0x02011446 , ULL(0x02011446) ); +CONST_UINT64_T( MBS_ECC0_MBECCFIR_ACTION1_0x02011447 , ULL(0x02011447) ); + CONST_UINT64_T( MBS_ECC1_MBECCFIR_0x02011480 , ULL(0x02011480) ); +CONST_UINT64_T( MBS_ECC1_MBECCFIR_MASK_0x02011483 , ULL(0x02011483) ); +CONST_UINT64_T( MBS_ECC1_MBECCFIR_MASK_AND_0x02011484 , ULL(0x02011484) ); +CONST_UINT64_T( MBS_ECC1_MBECCFIR_MASK_OR_0x02011485 , ULL(0x02011485) ); +CONST_UINT64_T( MBS_ECC1_MBECCFIR_ACTION0_0x02011486 , ULL(0x02011486) ); +CONST_UINT64_T( MBS_ECC1_MBECCFIR_ACTION1_0x02011487 , ULL(0x02011487) ); //------------------------------------------------------------------------------ // MBS Memory ECC Mark Store Registers @@ -611,9 +673,69 @@ CONST_UINT64_T( MBS_ECC1_MBSECCQ_0x0201148A , ULL(0x0201148A) ); //------------------------------------------------------------------------------ // MBS Memory Scrub/Read Error Threshold Registers //------------------------------------------------------------------------------ -CONST_UINT64_T( MBS01_MBSTRQ_0x02011655 , ULL(02011655) ); -CONST_UINT64_T( MBS23_MBSTRQ_0x02011755 , ULL(02011755) ); +CONST_UINT64_T( MBS01_MBSTRQ_0x02011655 , ULL(0x02011655) ); +CONST_UINT64_T( MBS23_MBSTRQ_0x02011755 , ULL(0x02011755) ); + +//------------------------------------------------------------------------------ +// MBS FIR Registers +//------------------------------------------------------------------------------ +CONST_UINT64_T( MBS_FIR_REG_0x02011400 , ULL(0x02011400) ); +CONST_UINT64_T( MBS_FIR_MASK_REG_0x02011403 , ULL(0x02011403) ); +CONST_UINT64_T( MBS_FIR_MASK_REG_AND_0x02011404 , ULL(0x02011404) ); +CONST_UINT64_T( MBS_FIR_MASK_REG_OR_0x02011405 , ULL(0x02011405) ); +CONST_UINT64_T( MBS_FIR_ACTION0_REG_0x02011406 , ULL(0x02011406) ); +CONST_UINT64_T( MBS_FIR_ACTION1_REG_0x02011407 , ULL(0x02011407) ); + +//------------------------------------------------------------------------------ +// DDRPHY FIR Registers +//------------------------------------------------------------------------------ +CONST_UINT64_T( PHY01_DDRPHY_FIR_REG_0x800200900301143f , ULL(0x800200900301143f) ); +CONST_UINT64_T( PHY01_DDRPHY_FIR_MASK_REG_0x800200930301143f , ULL(0x800200930301143f) ); +CONST_UINT64_T( PHY01_DDRPHY_FIR_MASK_REG_AND_0x800200940301143f , ULL(0x800200940301143f) ); +CONST_UINT64_T( PHY01_DDRPHY_FIR_MASK_REG_OR_0x800200950301143f , ULL(0x800200950301143f) ); +CONST_UINT64_T( PHY01_DDRPHY_FIR_ACTION0_REG_0x800200960301143f , ULL(0x800200960301143f) ); +CONST_UINT64_T( PHY01_DDRPHY_FIR_ACTION1_REG_0x800200970301143f , ULL(0x800200970301143f) ); + +//------------------------------------------------------------------------------ +// MBA RRQ0 Register - DDR read command parameters +//------------------------------------------------------------------------------ +CONST_UINT64_T( MBA01_MBA_RRQ0Q_0x0301040E , ULL(0x0301040e) ); +//------------------------------------------------------------------------------ +// MBA CAL Registers - DDR CAL REGs +//------------------------------------------------------------------------------ +CONST_UINT64_T( MBA01_MBA_CAL0Q_0x0301040F , ULL(0x0301040F) ); +CONST_UINT64_T( MBA01_MBA_CAL1Q_0x03010410 , ULL(0x03010410) ); +CONST_UINT64_T( MBA01_MBA_CAL2Q_0x03010411 , ULL(0x03010411) ); +CONST_UINT64_T( MBA01_MBA_CAL3Q_0x03010412 , ULL(0x03010412) ); + + +//------------------------------------------------------------------------------ +// MBSFIR Registers +//------------------------------------------------------------------------------ +CONST_UINT64_T( MBS01_MBSFIRQ_0x02011600 , ULL(0x02011600) ); +CONST_UINT64_T( MBS01_MBSFIRMASK_0x02011603 , ULL(0x02011603) ); +CONST_UINT64_T( MBS01_MBSFIRMASK_AND_0x02011604 , ULL(0x02011604) ); +CONST_UINT64_T( MBS01_MBSFIRMASK_OR_0x02011605 , ULL(0x02011605) ); +CONST_UINT64_T( MBS01_MBSFIRACT0_0x02011606 , ULL(0x02011606) ); +CONST_UINT64_T( MBS01_MBSFIRACT1_0x02011607 , ULL(0x02011607) ); + +CONST_UINT64_T( MBS23_MBSFIRQ_0x02011700 , ULL(0x02011700) ); +CONST_UINT64_T( MBS23_MBSFIRMASK_0x02011703 , ULL(0x02011703) ); +CONST_UINT64_T( MBS23_MBSFIRMASK_AND_0x02011704 , ULL(0x02011704) ); +CONST_UINT64_T( MBS23_MBSFIRMASK_OR_0x02011705 , ULL(0x02011705) ); +CONST_UINT64_T( MBS23_MBSFIRACT0_0x02011706 , ULL(0x02011706) ); +CONST_UINT64_T( MBS23_MBSFIRACT1_0x02011707 , ULL(0x02011707) ); + +//------------------------------------------------------------------------------ +// SCAC Registers +//------------------------------------------------------------------------------ +CONST_UINT64_T( SCAC_LFIR_0x020115C0 , ULL(0x020115C0) ); +CONST_UINT64_T( SCAC_FIRMASK_0x020115C3 , ULL(0x020115C3) ); +CONST_UINT64_T( SCAC_FIRMASK_AND_0x020115C4 , ULL(0x020115C4) ); +CONST_UINT64_T( SCAC_FIRMASK_OR_0x020115C5 , ULL(0x020115C5) ); +CONST_UINT64_T( SCAC_FIRACTION0_0x020115C6 , ULL(0x020115C6) ); +CONST_UINT64_T( SCAC_FIRACTION1_0x020115C7 , ULL(0x020115C7) ); /******************************************************************************/ @@ -636,6 +758,30 @@ This section is automatically updated by CVS when you check in this file. Be sure to create CVS comments when you commit so that they can be included here. $Log: cen_scom_addresses.H,v $ +Revision 1.28 2012/09/10 14:34:14 jdsloat +Fixed MBA CAL Names + +Revision 1.27 2012/09/07 21:29:39 gollub + +Fixed address for MBA01_MBA_WRD_MODE +Added Maint Read Buffers 65th Byte + +Revision 1.26 2012/09/06 18:39:34 jdsloat +Added MBA CAL Registers + +Revision 1.25 2012/09/06 13:28:25 gollub + +Added more FIR registers. + +Revision 1.24 2012/08/20 17:12:23 jdsloat +Added Primary Rank Pair MRS Shadow Regs + +Revision 1.23 2012/08/17 20:15:03 gollub + +Added MBS FIR Registers +Added DDRPHY FIR Registers +Added MBA_RRQ Register + Revision 1.22 2012/06/18 01:58:44 jmcgill added trace related SCOM addresses diff --git a/src/usr/hwpf/hwp/initfiles/mba_def.initfile b/src/usr/hwpf/hwp/initfiles/mba_def.initfile index c359841fd..44ad8471f 100644 --- a/src/usr/hwpf/hwp/initfiles/mba_def.initfile +++ b/src/usr/hwpf/hwp/initfiles/mba_def.initfile @@ -1,9 +1,11 @@ -#-- $Id: mba_def.initfile,v 1.10 2012/08/01 15:08:50 mwuu Exp $ +#-- $Id: mba_def.initfile,v 1.11 2012/08/20 16:00:27 yctschan Exp $ #-- CHANGE HISTORY: #-------------------------------------------------------------------------------- #-- Version:|Author: | Date: | Comment: #-- --------|--------|--------|-------------------------------------------------- +#-- 1.11|tschang |08/20/12|added mba mcbist setup values for simple write and read test +#-- 1.10|menlowuu|08/01/12|add/fixed comments in refresh section, missed a line #-- 1.10|menlowuu|08/01/12|add/fixed comments in refresh section, missed a line #-- 1.9 |menlowuu|07/30/12|add/fixed comments in refresh section #-- 1.8 |tschang |07/28/12|set refresh interval value and refresh check interval values @@ -1419,3 +1421,152 @@ scom 0x03010433 { } + +########################################################################################### +# MBA MCBIST SETUP SECTION # +########################################################################################### + +################################### +# MCBIST Memory Register +################################### +# Name = MBA01.MBA_MCBIST.SCOMFIR.MCBMR0Q_Q(0:63) (scomdef) +# Setup subtest tests +# Setup subtest 0 is a write with fixed data +# Setup subtest 1 is a read with fixed data + +scom 0x030106A8 { + bits , scom_data , expr; + 0:2 , 0b000, any; # cfg_test00_op_type is a write + 3 , 0b0, any; # cfg_test00_compl_1st_cmd + 4 , 0b0, any; # cfg_test00_compl_2nd_cmd + 5 , 0b0, any; # cfg_test00_compl_3rd_cmd + 6:7 , 0b00, any; # cfg_test00_addr_mode + 8:10 , 0b000, any; # cfg_test00_data_mode + 11 , 0b0 , any; # cfg_test00_done + 12:13 , 0b00, any; # cfg_test00_data_sel + 14:15 , 0b00, any; # cfg_test00_addr_sel + 16:18 , 0b001, any; # cfg_test01_op_type is a read + 19 , 0b0, any; # cfg_test01_compl_1st_cmd + 20 , 0b0, any; # cfg_test01_compl_2nd_cmd + 21 , 0b0, any; # cfg_test01_compl_3rd_cmd + 22:23 , 0b00, any; # cfg_test01_addr_mode + 24:26 , 0b000, any; # cfg_test01_data_mode + 27 , 0b1 , any; # cfg_test01_done is set + 28:29 , 0b00, any; # cfg_test01_data_sel + 30:31 , 0b00, any; # cfg_test01_addr_sel + 32:34 , 0b000, any; # cfg_test02_op_type + 35 , 0b0, any; # cfg_test02_compl_1st_cmd + 36 , 0b0, any; # cfg_test02_compl_2nd_cmd + 37 , 0b0, any; # cfg_test02_compl_3rd_cmd + 38:39 , 0b00, any; # cfg_test02_addr_mode + 40:42 , 0b000, any; # cfg_test02_data_mode + 43 , 0b0 , any; # cfg_test02_done + 44:45 , 0b00, any; # cfg_test02_data_sel + 46:47 , 0b00, any; # cfg_test02_addr_sel + 48:50 , 0b000, any; # cfg_test03_op_type + 51 , 0b0, any; # cfg_test03_compl_1st_cmd + 52 , 0b0, any; # cfg_test03_compl_2nd_cmd + 53 , 0b0, any; # cfg_test03_compl_3rd_cmd + 54:55 , 0b00, any; # cfg_test03_addr_mode + 56:58 , 0b000, any; # cfg_test03_data_mode + 59 , 0b0 , any; # cfg_test03_done + 60:61 , 0b00, any; # cfg_test03_data_sel + 62:63 , 0b00, any; # cfg_test03_addr_sel +} + +################################### +# MCBIST Fixed data pattern +################################### +# Name = MBA01.MBA_MCBIST.SCOMFIR.MCBFD[0-7]Q_Q(0:63) (scomdef) +# Name = MBA01.MBA_MCBIST.SCOMFIR.MCBFDQ_Q(0:63) (scomdef) +# Name = MBA01.MBA_MCBIST.SCOMFIR.MCBFDSPQ_Q(0:63) (scomdef) + +scom 0x030106BE { + bits , scom_data , expr; + 0:63 , 0x1111111111111111, any; # Fixed data burst 0 +} + +scom 0x030106BF { + bits , scom_data , expr; + 0:63 , 0x2222222222222222, any; # Fixed data burst 1 +} + +scom 0x030106C0 { + bits , scom_data , expr; + 0:63 , 0x3333333333333333, any; # Fixed data burst 2 +} + +scom 0x030106C1 { + bits , scom_data , expr; + 0:63 , 0x4444444444444444, any; # Fixed data burst 3 +} + +scom 0x030106C2 { + bits , scom_data , expr; + 0:63 , 0x5555555555555555, any; # Fixed data burst 4 +} + +scom 0x030106C3 { + bits , scom_data , expr; + 0:63 , 0x6666666666666666, any; # Fixed data burst 5 +} + +scom 0x030106C4 { + bits , scom_data , expr; + 0:63 , 0x7777777777777777, any; # Fixed data burst 6 +} + +scom 0x030106C5 { + bits , scom_data , expr; + 0:63 , 0x8888888888888888, any; # Fixed data burst 7 +} + +scom 0x030106C6 { + bits , scom_data , expr; + 0:63 , 0x9999999999999999, any; # Fixed data burst 0-7 ECC bits +} + +scom 0x030106C7 { + bits , scom_data , expr; + 0:63 , 0xAAAAAAAAAAAAAAAA, any; # Fixed data burst 0-7 SPARE bits +} + + +################################### +# MCBIST Fixed Addr A0 Start/End +################################### + +# Name = MBA01.MBA_MCBIST.SCOMFIR.MCBSAARA0Q_Q (scomdef) +# Name = MBA01.MBA_MCBIST.SCOMFIR.MCBSEARA0Q_Q (scomdef) +# MBA_FARB1Q Slot0, Master Rank 0/2 chip select programming +# + +scom 0x030106D0 { + bits , scom_data , expr; + 0:35 , 0x000000000, any; # A0 start address + 36:37 , 0b00, any; # A0 start address +} + +scom 0x030106D2 { + bits , scom_data , expr; + 0:35 , 0x000000000, any; # A0 End address + 36:37 , 0b11, any; # A0 End address +} + +################################### +# MCBIST Addr Gen Cfg Reg +################################### + +# Name = MBA01.MBA_MCBIST.SCOMFIR.MCBSAARA0Q_Q (scomdef) +# Name = MBA01.MBA_MCBIST.SCOMFIR.MCBSEARA0Q_Q (scomdef) +# MBA_FARB1Q Slot0, Master Rank 0/2 chip select programming +# + +scom 0x030106D6 { + bits , scom_data , expr; + 24:25 , 0b10, any; # A0 setup only A0 address gen +} + + + + diff --git a/src/usr/hwpf/hwp/initfiles/mbs_def.initfile b/src/usr/hwpf/hwp/initfiles/mbs_def.initfile index 22ed495b0..c35a52288 100644 --- a/src/usr/hwpf/hwp/initfiles/mbs_def.initfile +++ b/src/usr/hwpf/hwp/initfiles/mbs_def.initfile @@ -1,8 +1,10 @@ -#-- $Id: mbs_def.initfile,v 1.17 2012/07/23 19:36:49 bellows Exp $ +#-- $Id: mbs_def.initfile,v 1.19 2012/08/21 23:01:12 mwuu Exp $ #-- CHANGE HISTORY: #-------------------------------------------------------------------------------- #-- Version:|Author: | Date: | Comment: #-- --------|--------|--------|-------------------------------------------------- +#-- 1.19 |menlowuu|08/21/12| fixed 2 address typo's +#-- 1.18 |tschang |08/20/12| added mbs mcbist setup values for simple write and read test #-- 1.17 |bellows |07/23/12| made ATTR_MSS_CACHE_ENABLE at centaur level instead of system #-- 1.16 |yctschan|07/05/12| Removed sticks for subtype B #-- 1.14 |yctschan|06/28/12| Cleanup define syntax and ()'s @@ -590,3 +592,67 @@ scom 0x0201140C { } + + +########################################################################################### +# MBS MCBIST SETUP SECTION # +########################################################################################### + +################################### +# MCBIST Fixed data pattern +################################### +# Name = MBA01.MBA_MCBIST.SCOMFIR.MCBFD[0-7]Q_Q(0:63) (scomdef) +# Name = MBA01.MBA_MCBIST.SCOMFIR.MCBFDQ_Q(0:63) (scomdef) +# Name = MBA01.MBA_MCBIST.SCOMFIR.MCBFDSPQ_Q(0:63) (scomdef) + +scom 0x02011681 { + bits , scom_data , expr; + 0:63 , 0x1111111111111111, any; # Fixed data burst 0 +} + +scom 0x02011682 { + bits , scom_data , expr; + 0:63 , 0x2222222222222222, any; # Fixed data burst 1 +} + +scom 0x02011683 { + bits , scom_data , expr; + 0:63 , 0x3333333333333333, any; # Fixed data burst 2 +} + +scom 0x02011684 { + bits , scom_data , expr; + 0:63 , 0x4444444444444444, any; # Fixed data burst 3 +} + +scom 0x02011685 { + bits , scom_data , expr; + 0:63 , 0x5555555555555555, any; # Fixed data burst 4 +} + +scom 0x02011686 { + bits , scom_data , expr; + 0:63 , 0x6666666666666666, any; # Fixed data burst 5 +} + +scom 0x02011687 { + bits , scom_data , expr; + 0:63 , 0x7777777777777777, any; # Fixed data burst 6 +} + +scom 0x02011688 { + bits , scom_data , expr; + 0:63 , 0x8888888888888888, any; # Fixed data burst 7 +} + +scom 0x02011689 { + bits , scom_data , expr; + 0:63 , 0x9999999999999999, any; # Fixed data burst 0-7 ECC bits +} + +scom 0x0201168A { + bits , scom_data , expr; + 0:63 , 0xAAAAAAAAAAAAAAAA, any; # Fixed data burst 0-7 SPARE bits +} + + diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config.C index 53f5723ce..0cc83b26e 100644 --- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config.C +++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config.C @@ -1,27 +1,26 @@ -/* IBM_PROLOG_BEGIN_TAG - * This is an automatically generated prolog. - * - * $Source: src/usr/hwpf/hwp/mc_init/mss_eff_config/mss_eff_config.C $ - * - * IBM CONFIDENTIAL - * - * COPYRIGHT International Business Machines Corp. 2012 - * - * p1 - * - * Object Code Only (OCO) source materials - * Licensed Internal Code Source Materials - * IBM HostBoot Licensed Internal Code - * - * The source code for this program is not published or other- - * wise divested of its trade secrets, irrespective of what has - * been deposited with the U.S. Copyright Office. - * - * Origin: 30 - * - * IBM_PROLOG_END_TAG - */ -// $Id: mss_eff_config.C,v 1.9 2012/06/07 01:16:03 asaetow Exp $ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2012 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +// $Id: mss_eff_config.C,v 1.10 2012/08/02 18:31:50 bellows Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_eff_config.C,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 @@ -43,7 +42,7 @@ //------------------------------------------------------------------------------ // Version:| Author: | Date: | Comment: //---------|----------|---------|----------------------------------------------- -// 1.10 | | | +// 1.10 | bellows |02-AUG-12| Added in DIMM functional vector for Daniel // 1.9 | asaetow |29-MAY-12| Added divide by 0 check for mss_freq. // | | | Added 9 new attributes from memory_attributes.xml v1.23 // | | | Changed plug_config to my_attr_eff_num_drops_per_port. @@ -140,6 +139,8 @@ fapi::ReturnCode mss_eff_config(const fapi::Target i_target_mba) { uint8_t cur_dimm_spd_valid_u8array[PORT_SIZE][DIMM_SIZE] = {{0}}; uint8_t cur_mba_port = 0; uint8_t cur_mba_dimm = 0; + uint8_t dimm_functional_vector = 0x00; + uint8_t dimm_functional=0; uint8_t cur_dram_density = 0; uint32_t mss_freq = 0; uint32_t mss_volt = 0; @@ -297,6 +298,13 @@ fapi::ReturnCode mss_eff_config(const fapi::Target i_target_mba) { rc = FAPI_ATTR_GET(ATTR_MBA_DIMM, &l_target_dimm_array[dimm_index], cur_mba_dimm); if(rc) return rc; cur_dimm_spd_valid_u8array[cur_mba_port][cur_mba_dimm] = VALID; + rc = FAPI_ATTR_GET(ATTR_FUNCTIONAL, &l_target_dimm_array[dimm_index], dimm_functional); if(rc) return rc; + if(dimm_functional == fapi::ENUM_ATTR_FUNCTIONAL_FUNCTIONAL) + dimm_functional=1; + else + dimm_functional=0; + dimm_functional_vector |= dimm_functional << ((4*(1-cur_mba_port))+(4-cur_mba_dimm)-1); + rc = FAPI_ATTR_GET(ATTR_SPD_DRAM_DEVICE_TYPE, &l_target_dimm_array[dimm_index], spd_dram_device_type_u8array[cur_mba_port][cur_mba_dimm]); if(rc) return rc; rc = FAPI_ATTR_GET(ATTR_SPD_MODULE_TYPE, &l_target_dimm_array[dimm_index], spd_module_type_u8array[cur_mba_port][cur_mba_dimm]); if(rc) return rc; rc = FAPI_ATTR_GET(ATTR_SPD_SDRAM_BANKS, &l_target_dimm_array[dimm_index], spd_sdram_banks_u8array[cur_mba_port][cur_mba_dimm]); if(rc) return rc; @@ -673,7 +681,7 @@ fapi::ReturnCode mss_eff_config(const fapi::Target i_target_mba) { rc = FAPI_ATTR_SET(ATTR_EFF_SCHMOO_TEST_VALID, &i_target_mba, my_attr_eff_schmoo_test_valid); if(rc) return rc; rc = FAPI_ATTR_SET(ATTR_EFF_STACK_TYPE, &i_target_mba, my_attr_eff_stack_type); if(rc) return rc; rc = FAPI_ATTR_SET(ATTR_EFF_ZQCAL_INTERVAL, &i_target_mba, my_attr_eff_zqcal_interval); if(rc) return rc; - + rc = FAPI_ATTR_SET(ATTR_MSS_EFF_DIMM_FUNCTIONAL_VECTOR, &i_target_mba, dimm_functional_vector); if(rc) return rc; // Calls to sub-procedures rc = mss_eff_config_rank_group(i_target_mba); if(rc) return rc; diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_rank_group.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_rank_group.C index 399a91e09..01ab2b3e0 100644 --- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_rank_group.C +++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_rank_group.C @@ -1,27 +1,26 @@ -/* IBM_PROLOG_BEGIN_TAG - * This is an automatically generated prolog. - * - * $Source: src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_rank_group.C $ - * - * IBM CONFIDENTIAL - * - * COPYRIGHT International Business Machines Corp. 2012 - * - * p1 - * - * Object Code Only (OCO) source materials - * Licensed Internal Code Source Materials - * IBM HostBoot Licensed Internal Code - * - * The source code for this program is not published or other- - * wise divested of its trade secrets, irrespective of what has - * been deposited with the U.S. Copyright Office. - * - * Origin: 30 - * - * IBM_PROLOG_END_TAG - */ -// $Id: mss_eff_config_rank_group.C,v 1.6 2012/04/30 15:11:46 asaetow Exp $ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_rank_group.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2012 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +// $Id: mss_eff_config_rank_group.C,v 1.8 2012/08/30 03:07:27 asaetow Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_eff_config_rank_group.C,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 @@ -47,7 +46,9 @@ //------------------------------------------------------------------------------ // Version:| Author: | Date: | Comment: //---------|----------|---------|----------------------------------------------- -// 1.7 | | | +// 1.9 | | | +// 1.8 | asaetow |29-AUG-12| Fixed variable init for rank_group to INVALID for PORT1. +// 1.7 | asaetow |24-AUG-12| Fixed variable init for rank_group to INVALID. // 1.6 | asaetow |30-APR-12| Fixed "fapi::" for hostboot, added "const", renamed "i_target_mba", and changed comments. // | | | Changed message to standardized format. // | | | Changed BACKUP to Mark Bellows. @@ -179,13 +180,15 @@ fapi::ReturnCode mss_eff_config_rank_group(const fapi::Target i_target_mba) { } primary_rank_group0_u8array[cur_port] = 0; primary_rank_group1_u8array[cur_port] = 4; + primary_rank_group2_u8array[cur_port] = INVALID; + primary_rank_group3_u8array[cur_port] = INVALID; + secondary_rank_group0_u8array[cur_port] = INVALID; + secondary_rank_group1_u8array[cur_port] = INVALID; + secondary_rank_group2_u8array[cur_port] = INVALID; + secondary_rank_group3_u8array[cur_port] = INVALID; if (num_ranks_per_dimm_u8array[cur_port][0] == 2) { primary_rank_group2_u8array[cur_port] = 1; primary_rank_group3_u8array[cur_port] = 5; - secondary_rank_group0_u8array[cur_port] = INVALID; - secondary_rank_group1_u8array[cur_port] = INVALID; - secondary_rank_group2_u8array[cur_port] = INVALID; - secondary_rank_group3_u8array[cur_port] = INVALID; } else if (num_ranks_per_dimm_u8array[cur_port][0] == 4) { primary_rank_group2_u8array[cur_port] = 2; primary_rank_group3_u8array[cur_port] = 6; diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_thermal.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_thermal.C index 64809e94a..e8c23eda6 100644 --- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_thermal.C +++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_thermal.C @@ -1,27 +1,26 @@ -/* IBM_PROLOG_BEGIN_TAG - * This is an automatically generated prolog. - * - * $Source: src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_thermal.C $ - * - * IBM CONFIDENTIAL - * - * COPYRIGHT International Business Machines Corp. 2012 - * - * p1 - * - * Object Code Only (OCO) source materials - * Licensed Internal Code Source Materials - * IBM HostBoot Licensed Internal Code - * - * The source code for this program is not published or other- - * wise divested of its trade secrets, irrespective of what has - * been deposited with the U.S. Copyright Office. - * - * Origin: 30 - * - * IBM_PROLOG_END_TAG - */ -// $Id: mss_eff_config_thermal.C,v 1.7 2012/05/04 15:53:44 pardeik Exp $ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_thermal.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2012 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +// $Id: mss_eff_config_thermal.C,v 1.8 2012/06/13 20:53:57 pardeik Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_eff_config_thermal.C,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 @@ -38,14 +37,12 @@ // The purpose of this procedure is to set the default throttle and power attributes for dimms in a given system // -- The throttles here are intended to be the thermal runtime throttles for dimm/channel N/M // -- The power attributes are the slope/intercept values. Note that these values are in cW. -// -- The values are determined by system based on power/thermal characterization +// -- The power values are determined by DRAM Generation and Width (with various uplifts/adders applied) +// and will be derived from the model and then verified with hardware measurements +// -- Power will be per rank for a given dram generation and width +// -- Uplifts will be applied for dimm type, number of ranks // -- Thermal values are system dependent and will need to come from the machine readable workbook -// -- Power values are going to be based on measurements and uplifted as needed based on voltage, frequency, termination, etc. // -// TODO: -// 1. Thermal attributes (IPL and Runtime Throttles) need to come from machine readable workbook -// 2. Uplifts need to be done based on volt, freq, termination, etc. -// 3. Power values need to be updated/added for the dimms that will be supported // //------------------------------------------------------------------------------ // Don't forget to create CVS comments when you check in your changes! @@ -54,6 +51,7 @@ //------------------------------------------------------------------------------ // Version:| Author: | Date: | Comment: //---------|----------|---------|----------------------------------------------- +// 1.8 | pardeik |13-JUN-12| Major rewrite to have dimm power determined by dram generation and width, with uplifts applied (not based on dimm size lookup table any longer) // 1.7 | pardeik |04-MAY-12| removed typedef from structures, use fapi to define dimm type enums // 1.6 | pardeik |10-APR-12| update cdimm power/int default, change power_thermal_values_t to use int32_t instead of uint32_t in order to identify a negative value correctly, added dimm config to the messages printed out // 1.5 | pardeik |03-APR-12| fix cdimm size/rank addition to cycle through both mba's @@ -96,204 +94,276 @@ extern "C" { RDIMM = fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM, UDIMM = fapi::ENUM_ATTR_EFF_DIMM_TYPE_UDIMM, LRDIMM = fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM, + DDR3 = fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR3, + DDR4 = fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR4, + X4 = fapi::ENUM_ATTR_EFF_DRAM_WIDTH_X4, + X8 = fapi::ENUM_ATTR_EFF_DRAM_WIDTH_X8, }; -// number of dimms on channel/port - enum +// Structure types for the table that holds dimm power and adjustment values that will be used + + struct dimm_power_t { - SINGLEDROP = 0, - DOUBLEDROP = 1, - DIMM_CONFIG_TYPES = 2, // count of all possible various dimm configurations on port + uint32_t idle; + uint32_t max; }; - -// Structure type for the table that holds dimm power slope and intercept values -// use int32_t for slope and intercept in case values are entered wrong (ie. negative values will then be flagged) - struct power_thermal_values_t + struct dimm_type_t + { + int32_t udimm; + int32_t lrdimm; + int32_t rdimm; + int32_t cdimm; + }; + struct dimm_voltage_t { - int32_t power_slope; - int32_t power_int; + int8_t volt1500; + int8_t volt1350; + int8_t volt1200; }; - struct power_thermal_data_t + struct dimm_frequency_t { - uint32_t dimm_type; - uint32_t dimm_size; - uint8_t dimm_ranks; - power_thermal_values_t data[DIMM_CONFIG_TYPES]; + int8_t freq1066; + int8_t freq1333; + int8_t freq1600; }; + struct power_data_t + { + uint8_t dram_generation; + uint8_t dram_width; + uint8_t dimm_ranks; + dimm_power_t rank_master_power; + dimm_type_t dimm_type_adder; + dimm_power_t rank_slave_adder; + dimm_voltage_t dimm_voltage_adder; + dimm_frequency_t dimm_frequency_adder; + }; + +power_data_t l_power_table[] = +{ +// Master Ranks column uses the values in the same table entry for the number of master ranks specified. Default is to have it use same power for each master rank, so that is why master ranks = 1. If we need to separate power based on number of master ranks, then have the table setup for descending master rank values. We always need an entry for master ranks of 1. Table lookup will stop after first matching entry is found (DRAM Generation, DRAM Width, and Master Ranks = l_dimm_master_ranks_array OR 1) +// +// Note: Slave rank full bw is set to idle, since the active power for full bw will be acounted for the master rank (ie. only one rank active at a time). Set slave rank full bw to the slave rank idle bw power value. +// +// DRAM DRAM Master MasterRankPower DIMMTypeAdder SlaveRankAdder VoltageAdder FrequencyAdder +// Generation Width Ranks (cW) (cW) (cW) (%) (%) +// DDR3 X4 1 idle,full UDIMM,LRDIMM, idle,full 1.5,1.35,1.2 1066,1333,1600 +// or or RDIMM,CDIMM +// DDR4 X8 +// + +// TODO: Finalize these values against model. These are just place holders for now and will work for the time being. + { DDR3, X4, 1, { 65,650}, {0,50,100,0}, { 65,65}, {10,0,-10}, {0,10,20} }, + { DDR3, X8, 1, { 50,500}, {0,50,100,0}, { 50,50}, {10,0,-10}, {0,10,20} }, + { DDR4, X4, 1, { 65,650}, {0,50,100,0}, { 65,65}, {10,0,-10}, {0,10,20} }, + { DDR4, X8, 1, { 50,500}, {0,50,100,0}, { 50,50}, {10,0,-10}, {0,10,20} }, +}; + // Default values defined here const uint8_t l_num_ports = 2; // number of ports per MBA const uint8_t l_num_dimms = 2; // number of dimms per MBA port - const uint32_t l_dimm_power_slope_default = 800; // default power slope for rdimm, udimm, lrdimm - const uint32_t l_dimm_power_int_default = 900; // default power intercept for rdimm, udimm, lrdimm - const uint32_t l_cdimm_power_slope_default = 2000; // default power slope for cdimm - const uint32_t l_cdimm_power_int_default = 700; // default power intercept for cdimm + const uint32_t l_dimm_power_slope_default = 940; // default power slope (cW/utilization) + const uint32_t l_dimm_power_int_default = 900; // default power intercept (cW) const uint32_t l_dimm_throttle_n_default = 100; // default dimm throttle numerator const uint32_t l_dimm_throttle_d_default = 100; // default dimm throttle denominator const uint32_t l_channel_throttle_n_default = 100; // default channel throttle numerator const uint32_t l_channel_throttle_d_default = 100; // default channel throttle denominator + const uint8_t l_idle_dimm_utilization = 0; // DRAM data bus utilization for the idle power defined in table below + const uint8_t l_max_dimm_utilization = 100; // DRAM data bus utilization for the active power defined in table below + // other variables used in this procedure + fapi::Target l_targetCentaur; + std::vector<fapi::Target> l_targetDimm; uint8_t port; uint8_t dimm; uint8_t entry; uint8_t l_dimm_type; - uint8_t l_dimm_size_array[l_num_ports][l_num_dimms]; uint8_t l_dimm_ranks_array[l_num_ports][l_num_dimms]; - uint32_t l_half_cdimm_size = 0; - uint8_t l_half_cdimm_ranks = 0; uint32_t l_list_sz; uint32_t l_power_slope_array[l_num_ports][l_num_dimms]; uint32_t l_power_int_array[l_num_ports][l_num_dimms]; - uint32_t l_power_int_uplift; uint32_t l_dimm_throttle_n_array[l_num_ports][l_num_dimms]; uint32_t l_dimm_throttle_d_array[l_num_ports][l_num_dimms]; uint32_t l_channel_throttle_n_array[l_num_ports]; uint32_t l_channel_throttle_d_array[l_num_ports]; uint8_t l_found_entry_in_table; - uint8_t l_dimm_config[l_num_ports]; + uint8_t l_dram_width; + uint8_t l_dram_gen; + uint32_t l_dimm_voltage; + uint32_t l_dimm_frequency; + uint8_t l_dimm_ranks_configed_array[l_num_ports][l_num_dimms]; + uint8_t l_dimm_master_ranks_array[l_num_ports][l_num_dimms]; + int32_t l_dimm_power_adder_type; + int8_t l_dimm_power_adder_volt; + int8_t l_dimm_power_adder_freq; + uint32_t l_dimm_idle_power_adder_slave; + uint32_t l_dimm_max_power_adder_slave; + int32_t l_dimm_idle_power; + int32_t l_dimm_max_power; + uint8_t l_dimm_num_slave_ranks; -// This sets up the power curve values for the DIMMs -// NOTE: If a value of zero is in the slope or intercept fields, then the default settings will be used -// NOTE: Power Slope and Intercept values are in cW -// NOTE: For CDIMM, the power values need to be based on the dimm within the CDIMM (not based on power for whole CDIMM) -// DIMM, Size, Ranks, Double drop config power slope and intercept, Single drop config power slope and intercept - - power_thermal_data_t l_power_thermal_values[]= - { -// SINGLE DOUBLE -// DROP DROP -// Type, Size, Ranks, slope,int, slope,int -// RDIMMs - data from P7 based ISDIMMs (1066MHz and 1.35V) - { RDIMM, 2, 1, {{ 522, 154}, { 526, 153}}}, // example RDIMM 2GB 1Rx8 2Gb - { RDIMM, 4, 2, {{ 472, 187}, { 512, 182}}}, // example RDIMM 4GB 2Rx8 2Gb - { RDIMM, 4, 1, {{ 472, 187}, { 512, 182}}}, // example RDIMM 4GB 1Rx8 4Gb - { RDIMM, 8, 4, {{ 654, 274}, { 657, 262}}}, // example RDIMM 8GB 4Rx8 2Gb - { RDIMM, 8, 2, {{ 654, 274}, { 657, 262}}}, // example RDIMM 8GB 2Rx4 2Gb OR 8GB 2Rx8 4Gb - { RDIMM, 16, 4, {{ 770, 458}, { 738, 479}}}, // example RDIMM 16GB 4Rx4 2Gb - { RDIMM, 16, 2, {{ 770, 458}, { 738, 479}}}, // example RDIMM 16GB 2Rx4 4Gb - { RDIMM, 32, 4, {{ 770, 458}, { 738, 479}}}, // example RDIMM 32GB 4Rx4 4Gb -// CDIMMs - projections based on Warren's dimm support table + 3% spread + 10% uplift -// power values here are HALF of the cdimm power (since we handle one mba at a time) - need to divide this up and give each dimm an equal power amount -// SingleDrop DoubleDrop -// TYPE Size/X, Ranks/X, Slope,Int, Slope, Int -// where X=number of MBA port pairs populated on CDIMM - { CDIMM, 16/2, 4/2, {{ 957, 153}, { 957, 153}}}, // example short CDIMM 16GB 4Rx8 4Gb OR 8GB 2Rx8 4Gb (Channel A/B populated) - { CDIMM, 32/2, 8/2, {{1130, 254}, {1130, 254}}}, // example short CDIMM 32GB 4Rx8 4Gb - { CDIMM, 64/2, 8/2, {{1763, 469}, {1763, 469}}}, // example short CDIMM 64GB 4Rx4 4Gb - { CDIMM, 128/2, 8/2, {{1763, 599}, {1763, 599}}}, // example tall CDIMM 128GB 4Rx4 4Gb (2H 3DS) -// UDIMMs -// LRDIMMs - }; - l_list_sz = (sizeof(l_power_thermal_values))/(sizeof(power_thermal_data_t)); + l_list_sz = (sizeof(l_power_table))/(sizeof(power_data_t)); // Get input attributes + l_rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_GEN, &i_target, l_dram_gen); + if(l_rc) return l_rc; l_rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target, l_dimm_type); if(l_rc) return l_rc; - l_rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_SIZE, &i_target, l_dimm_size_array); + l_rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target, l_dram_width); if(l_rc) return l_rc; l_rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target, l_dimm_ranks_array); if(l_rc) return l_rc; + l_rc = FAPI_ATTR_GET(ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM, &i_target, l_dimm_master_ranks_array); + if(l_rc) return l_rc; + l_rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_RANKS_CONFIGED, &i_target, l_dimm_ranks_configed_array); + if(l_rc) return l_rc; +// TODO: Get Attributes for number of registers on ISDIMM and Termination settings being used -// Add up DIMM Size and Ranks if a CDIMM - this will be for half of the cdimm - and dimm config for each mba port (1 or 2 dimms per channel) - for (port=0; port < l_num_ports; port++) +// Get Centaur target for the given MBA +// Get voltage and frequency attributes + l_rc = fapiGetParentChip(i_target, l_targetCentaur); + if(l_rc) { - l_dimm_config[port] = 0; - for (dimm=0; dimm < l_num_dimms; dimm++) - { - if ((l_dimm_type == CDIMM) && (l_dimm_ranks_array[port][dimm] > 0)) - { - l_half_cdimm_size = l_half_cdimm_size + l_dimm_size_array[port][dimm]; - l_half_cdimm_ranks = l_half_cdimm_ranks + l_dimm_ranks_array[port][dimm]; - } - if (l_dimm_ranks_array[port][dimm] > 0) - { - l_dimm_config[port]++; - } - } - if (l_dimm_config[port] == 1) - { - l_dimm_config[port] = SINGLEDROP; - } - else if (l_dimm_config[port] == 2) - { - l_dimm_config[port] = DOUBLEDROP; - } - else - { - l_dimm_config[port] = DIMM_CONFIG_TYPES; - } + FAPI_ERR("Error getting Centaur parent target for the given MBA"); + return l_rc; } + l_rc = FAPI_ATTR_GET(ATTR_MSS_VOLT, &l_targetCentaur, l_dimm_voltage); + if(l_rc) return l_rc; + l_rc = FAPI_ATTR_GET(ATTR_MSS_FREQ, &l_targetCentaur, l_dimm_frequency); + if(l_rc) return l_rc; // iterate through the MBA ports to define power and thermal attributes for (port=0; port < l_num_ports; port++) { -// initialize entries to zero +// initialize channel entries to zero l_channel_throttle_n_array[port] = 0; l_channel_throttle_d_array[port] = 0; +// iterate through the dimms on each port for (dimm=0; dimm < l_num_dimms; dimm++) { -// initialize entries to zero +// initialize dimm entries to zero l_dimm_throttle_n_array[port][dimm] = 0; l_dimm_throttle_d_array[port][dimm] = 0; l_power_slope_array[port][dimm] = 0; l_power_int_array[port][dimm] = 0; -// only update values for dimms that are physically present (with default value or table entry value) +// only update values for dimms that are physically present if (l_dimm_ranks_array[port][dimm] > 0) { -// TODO: Placeholder for thermal attributes from machine readable workbook (runtime throttles) - Hardcode these for now. IPL throttles will need to be added into an initfile once available. -// Can remove this section once infrastructure is in place to get these from the MRW (probably done in a different firmware procedure) +// TODO: Placeholder for thermal attributes that will come from machine readable workbook (runtime throttles) - Hardcode these to the default values for now. +// TODO: IPL throttles will need to be added into an initfile once available. l_dimm_throttle_n_array[port][dimm] = l_dimm_throttle_n_default; l_dimm_throttle_d_array[port][dimm] = l_dimm_throttle_d_default; l_channel_throttle_n_array[port] = l_channel_throttle_n_default; l_channel_throttle_d_array[port] = l_channel_throttle_d_default; -// Look up DIMM in Table, get size and ranks first, set slope/int to default values first in case entry is not found in table -// If table entry is less than zero, then set value to default values - if (l_dimm_type == CDIMM) - { - l_dimm_size_array[port][dimm] = l_half_cdimm_size; - l_dimm_ranks_array[port][dimm] = l_half_cdimm_ranks; - l_power_slope_array[port][dimm] = l_cdimm_power_slope_default; - l_power_int_array[port][dimm] = l_cdimm_power_int_default; - } - else - { - l_power_slope_array[port][dimm] = l_dimm_power_slope_default; - l_power_int_array[port][dimm] = l_dimm_power_int_default; - } + +// Get the dimm power from table and add on any adjustments (if not found in table - should never happen, then default values will be used) + l_power_slope_array[port][dimm] = l_dimm_power_slope_default; + l_power_int_array[port][dimm] = l_dimm_power_int_default; l_found_entry_in_table = 0; for (entry = 0; entry < l_list_sz; entry++) { - if ((l_power_thermal_values[entry].dimm_type == l_dimm_type) && (l_power_thermal_values[entry].dimm_size == l_dimm_size_array[port][dimm]) && (l_power_thermal_values[entry].dimm_ranks == l_dimm_ranks_array[port][dimm])) + if ((l_power_table[entry].dram_generation == l_dram_gen) && (l_power_table[entry].dram_width == l_dram_width) && ((l_power_table[entry].dimm_ranks == l_dimm_master_ranks_array[port][dimm]) || (l_power_table[entry].dimm_ranks == 1))) { - if ((l_power_thermal_values[entry].data[l_dimm_config[port]].power_slope > 0) && (l_power_thermal_values[entry].data[l_dimm_config[port]].power_int > 0)) +// get adder for dimm type + if (l_dimm_type == UDIMM) { + l_dimm_power_adder_type = l_power_table[entry].dimm_type_adder.udimm; + } + else if (l_dimm_type == LRDIMM) + { + l_dimm_power_adder_type = l_power_table[entry].dimm_type_adder.lrdimm; + } + else if (l_dimm_type == CDIMM) + { + l_dimm_power_adder_type = l_power_table[entry].dimm_type_adder.cdimm; + } + else if ( l_dimm_type == RDIMM ) + { + l_dimm_power_adder_type = l_power_table[entry].dimm_type_adder.rdimm; + } + else + { + FAPI_ERR("UNKNOWN DIMM TYPE FOUND: ldimm_type"); + l_dimm_power_adder_type = 0; + } +// TODO: Use attribute for number of registers for RDIMM when available - via SPD byte 63 bits 1:0 +// TODO: Remove the double uplift below when SPD byte 63 is used + // double the uplift for additional register if dimm has more than 2 ranks + if ((l_dimm_master_ranks_array[port][dimm] > 2) && (l_dram_width == X4) && ((l_dimm_type == LRDIMM) || (l_dimm_type == RDIMM))) + { + l_dimm_power_adder_type = l_dimm_power_adder_type * 2; + } +// get adder for dimm voltage + if (l_dimm_voltage == 1200) + { + l_dimm_power_adder_volt = l_power_table[entry].dimm_voltage_adder.volt1200; + } + else if (l_dimm_voltage == 1350) + { + l_dimm_power_adder_volt = l_power_table[entry].dimm_voltage_adder.volt1350; + } + else if (l_dimm_voltage == 1500) + { + l_dimm_power_adder_volt = l_power_table[entry].dimm_voltage_adder.volt1500; + } + else + { + FAPI_ERR("UNKNOWN DIMM VOLTAGE FOUND: l_dimm_voltage"); + l_dimm_power_adder_volt = 0; + } +// get adder for dimm frequency + if (l_dimm_frequency == 1066) + { + l_dimm_power_adder_freq = l_power_table[entry].dimm_frequency_adder.freq1066; + } + else if (l_dimm_frequency == 1333) + { + l_dimm_power_adder_freq = l_power_table[entry].dimm_frequency_adder.freq1333; + } + else if (l_dimm_frequency == 1600) { - l_power_slope_array[port][dimm]=l_power_thermal_values[entry].data[l_dimm_config[port]].power_slope; - l_power_int_array[port][dimm]=l_power_thermal_values[entry].data[l_dimm_config[port]].power_int; - FAPI_INF("Found DIMM Entry in Power Table [%d:%d:%d:%d:%d:%d][%d:%d]", port, dimm, l_dimm_type, l_dimm_size_array[port][dimm], l_dimm_ranks_array[port][dimm], l_dimm_config[port], l_power_slope_array[port][dimm], l_power_int_array[port][dimm]); + l_dimm_power_adder_freq = l_power_table[entry].dimm_frequency_adder.freq1600; } else { - FAPI_ERR( "DIMM Entry in Power Table not greater than zero, so default values will be used [%d:%d:%d:%d:%d:%d][%d:%d]", port, dimm, l_dimm_type, l_dimm_size_array[port][dimm], l_dimm_ranks_array[port][dimm], l_dimm_config[port], l_power_slope_array[port][dimm], l_power_int_array[port][dimm]); + FAPI_ERR("UNKNOWN DIMM FREQ FOUND: l_dimm_frequency"); + l_dimm_power_adder_freq = 0; + } +// get adder for slave ranks + l_dimm_num_slave_ranks=l_dimm_ranks_array[port][dimm] - l_dimm_master_ranks_array[port][dimm]; + if (l_dimm_num_slave_ranks > 0) + { + l_dimm_idle_power_adder_slave = l_power_table[entry].rank_slave_adder.idle * l_dimm_num_slave_ranks; + l_dimm_max_power_adder_slave = l_dimm_idle_power_adder_slave + (l_power_table[entry].rank_slave_adder.max - l_power_table[entry].rank_slave_adder.idle); } -// break out since first match was found + else + { + l_dimm_idle_power_adder_slave = 0; + l_dimm_max_power_adder_slave = 0; + } +// get adder for termination using equation +// TODO: Need to add this in once equations are available for termination adder + +// calculate idle and max dimm power + l_dimm_idle_power = int((l_power_table[entry].rank_master_power.idle * l_dimm_master_ranks_array[port][dimm] + l_dimm_power_adder_type + l_dimm_idle_power_adder_slave) * (1 + float(l_dimm_power_adder_volt + l_dimm_power_adder_freq) / 100)); + l_dimm_max_power = int(((l_power_table[entry].rank_master_power.idle * l_dimm_master_ranks_array[port][dimm] + l_power_table[entry].rank_master_power.max - l_power_table[entry].rank_master_power.idle) + l_dimm_power_adder_type + l_dimm_max_power_adder_slave) * (1 + float(l_dimm_power_adder_volt + l_dimm_power_adder_freq) / 100)); +// caculcate dimm power slope and intercept + l_power_slope_array[port][dimm] = int((l_dimm_max_power - l_dimm_idle_power) / (float(l_max_dimm_utilization - l_idle_dimm_utilization) / 100)); + l_power_int_array[port][dimm] = l_dimm_idle_power; + l_found_entry_in_table = 1; + FAPI_INF("FOUND ENTRY: GEN=%d WIDTH=%d RANK=%d IDLE=%d MAX=%d ADDER[SLAVE_IDLE=%d SLAVE_MAX=%d TYPE=%d VOLT=%d FREQ=%d]", l_power_table[entry].dram_generation, l_power_table[entry].dram_width, l_power_table[entry].dimm_ranks, l_power_table[entry].rank_master_power.idle, l_power_table[entry].rank_master_power.max, l_power_table[entry].rank_slave_adder.idle, l_power_table[entry].rank_slave_adder.max, l_dimm_power_adder_type, l_dimm_power_adder_volt, l_dimm_power_adder_freq); + FAPI_INF("DIMM Power Calculated [P%d:D%d:R%d/%d][IDLE=%d:MAX=%d cW][SLOPE=%d:INT=%d cW]", port, dimm, l_dimm_master_ranks_array[port][dimm], l_dimm_num_slave_ranks, l_dimm_idle_power, l_dimm_max_power, l_power_slope_array[port][dimm], l_power_int_array[port][dimm]); break; } + } -// Apply any uplifts to the Slope or intercept values based on various parameters if entry is found in table -// TODO: What uplifts do we need to do (Frequency, Voltage, Termination, etc) - Use zero uplift for now. - if (l_found_entry_in_table == 1) - { - l_power_int_uplift = 0; - l_power_int_array[port][dimm] = l_power_int_array[port][dimm] + l_power_int_uplift; - } -// post error if entry was not found - else + if (l_found_entry_in_table == 0) { - FAPI_ERR( "Failed to Find DIMM Entry in Power Table, so default values will be used [%d:%d:%d:%d:%d:%d][%d:%d]", port, dimm, l_dimm_type, l_dimm_size_array[port][dimm], l_dimm_ranks_array[port][dimm], l_dimm_config[port], l_power_slope_array[port][dimm], l_power_int_array[port][dimm] ); + FAPI_ERR( "WARNING: Failed to Find DIMM Power Values, so default values will be used [%d:%d][%d:%d]", port, dimm, l_power_slope_array[port][dimm], l_power_int_array[port][dimm] ); } } } } + // write output attributes l_rc = FAPI_ATTR_SET(ATTR_MSS_POWER_SLOPE, &i_target, l_power_slope_array); if(l_rc) return l_rc; diff --git a/src/usr/hwpf/hwp/memory_attributes.xml b/src/usr/hwpf/hwp/memory_attributes.xml index 608c2b4a9..c52c348bc 100644 --- a/src/usr/hwpf/hwp/memory_attributes.xml +++ b/src/usr/hwpf/hwp/memory_attributes.xml @@ -1,25 +1,25 @@ -<!-- IBM_PROLOG_BEGIN_TAG - This is an automatically generated prolog. - - $Source: src/usr/hwpf/hwp/memory_attributes.xml $ - - IBM CONFIDENTIAL - - COPYRIGHT International Business Machines Corp. 2012 - - p1 - - Object Code Only (OCO) source materials - Licensed Internal Code Source Materials - IBM HostBoot Licensed Internal Code - - The source code for this program is not published or other- - wise divested of its trade secrets, irrespective of what has - been deposited with the U.S. Copyright Office. - - Origin: 30 - IBM_PROLOG_END_TAG --> - +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/usr/hwpf/hwp/memory_attributes.xml $ --> +<!-- --> +<!-- IBM CONFIDENTIAL --> +<!-- --> +<!-- COPYRIGHT International Business Machines Corp. 2012 --> +<!-- --> +<!-- p1 --> +<!-- --> +<!-- Object Code Only (OCO) source materials --> +<!-- Licensed Internal Code Source Materials --> +<!-- IBM HostBoot Licensed Internal Code --> +<!-- --> +<!-- The source code for this program is not published or otherwise --> +<!-- divested of its trade secrets, irrespective of what has been --> +<!-- deposited with the U.S. Copyright Office. --> +<!-- --> +<!-- Origin: 30 --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> <attributes> <!-- DO NOT EDIT THIS FILE DIRECTLY PLEASE UPDATE THE ODS FILE AND FOLLOW THE INSTRUCTION TAB --> <!-- PLEASE SEE MARK BELLOWS (BELLOWS.IBM.COM) OR OTHERS ON MEMORY TEAM FOR HELP --> @@ -406,6 +406,29 @@ firmware notes: none</description> </attribute> <attribute> + <id>ATTR_EFF_CKE_MAP</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Rank to CKE map. Used in various locations and is computed in mss_eff_cnfg_cke. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. creator: mss_eff_cnfg_cke consumer: various firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <odmVisable/> + <odmChangeable/> + <array> 2 2 4</array> +</attribute> + +<attribute> + <id>ATTR_EFF_DIMM_SPARE</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Spare DRAM availability. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. creator: mss_eff_cnfg consumer: various firmware notes: load from spd</description> + <valueType>uint8</valueType> + <enum>NO_SPARE = 0, LOW_NIBBLE = 1, HIGH_NIBBLE = 2, FULL_BYTE = 3</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> + <array> 2 2 4</array> +</attribute> + +<attribute> <id>ATTR_EFF_DRAM_RON</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> <description>DRAM Ron. Used in various locations and is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. @@ -1094,6 +1117,56 @@ firmware notes: none</description> </attribute> <attribute> + <id>ATTR_EFF_SCHMOO_WR_EYE_MIN_MARGIN</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Specifies the schmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.</description> + <valueType>uint8</valueType> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_SCHMOO_RD_EYE_MIN_MARGIN</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Specifies the schmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.</description> + <valueType>uint8</valueType> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_SCHMOO_DQS_CLK_MIN_MARGIN</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Specifies the schmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.</description> + <valueType>uint8</valueType> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_SCHMOO_RD_GATE_MIN_MARGIN</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Specifies the schmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.</description> + <valueType>uint8</valueType> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_SCHMOO_ADDR_CMD_MIN_MARGIN</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Specifies the schmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.</description> + <valueType>uint8</valueType> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> <id>ATTR_EFF_MEMCAL_INTERVAL</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> <description>Specifies the memcal interval in clocks.</description> @@ -1184,20 +1257,6 @@ firmware notes: none</description> </attribute> <attribute> - <id>ATTR_MSS_SPARE_BYTE</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>This says that the system can have a 10th byte -creator: mss_eff_cnfg - may come from VPD -consumer: mss_eff_cnfg -firmware notes: load from spd</description> - <valueType>uint8</valueType> - <enum>NONE =0, X4_SPARE=1, X4_X2_SPARE = 2, X8_SPARE = 3</enum> - <writeable/> - <odmVisable/> - <odmChangeable/> -</attribute> - -<attribute> <id>ATTR_MSS_THROTTLE_NUMERATOR</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> <description>Each DIMM can have a throttle amount. This is the numerator @@ -1370,7 +1429,6 @@ firmware notes: none</description> <persistRuntime/> </attribute> -<!-- Commented out for now <attribute> <id>ATTR_MSS_INTERLEAVE_ENABLE</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> @@ -1380,7 +1438,6 @@ firmware notes: none</description> <odmVisable/> <odmChangeable/> </attribute> ---> <attribute> <id>ATTR_MSS_MEMSIZE_MBA</id> @@ -1457,19 +1514,6 @@ Hash modes values are 0,1 and 2. Used in the intifile </description> <odmChangeable/> </attribute> -<!-- TODO Hostboot note: - These platInit attributes have not been requested yet. Hostboot does - not yet support -<attribute> - <id>ATTR_MBA_POS</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Which MBA we are working on, either 0 for MBA01 and 1 for MBA23</description> - <valueType>uint8</valueType> - <platInit/> - <odmVisable/> -</attribute> ---> - <attribute> <id>ATTR_MSS_LAB_OVERRIDE_FOR_MEM_PLL</id> <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> @@ -1491,6 +1535,77 @@ firmware notes: none</description> <odmVisable/> <odmChangeable/> <array>8</array> + <persistRuntime/> +</attribute> + +<attribute> + <id>ATTR_MSS_MCS_GROUP_32</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>Data Structure from eff grouping to setup bars to help determine different groups + Non- Mirroring [0-7] 0 -- MCS size //1-- No of MCS/group //2-- Total group size //3 -- Base address// 4-11 - MCS ID number// 12 --Alter.Bar //13 - A.Group Size // 14 - A.Base address + // Mirroring [8-15] 0 -- MCS size //1-- No of MCS/group //2-- Total group size //3 -- Base address// 4-11 - MCS ID number// 12 --Alter.Bar //13 - A.Group Size // 14 - A.Base address +Measured in GB</description> + <valueType>uint32</valueType> + <writeable/> + <odmVisable/> + <odmChangeable/> + <array>16 16</array> +</attribute> + +<attribute> + <id>ATTR_MSS_MCS_GROUP</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>Data Structure from eff grouping to setup bars to help determine different groups + Non- Mirroring [0-7] 0 -- MCS size //1-- No of MCS/group //2-- Total group size //3 -- Base address// 4-11 - MCS ID number// 12 --Alter.Bar //13 - A.Group Size // 14 - A.Base address + // Mirroring [8-15] 0 -- MCS size //1-- No of MCS/group //2-- Total group size //3 -- Base address// 4-11 - MCS ID number// 12 --Alter.Bar //13 - A.Group Size // 14 - A.Base address +Measured in GB - THIS ATTRIBUTE WILL EVENTUALLY BE OBSOLETE. USE MSS_MCS_GROUP_32</description> + <valueType>uint8</valueType> + <writeable/> + <odmVisable/> + <odmChangeable/> + <array>16 16</array> +</attribute> + +<attribute> + <id>ATTR_MSS_EFF_DIMM_FUNCTIONAL_VECTOR</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>A bit vector (per Dean's request) specifying if a DIMM is functional. DIMM attributes, such as SIZE, are qualified by this bit vector. The attribute ANDed 0x80 means port 0, DIMM 0 is functional, 0x40 means port 0, DIMM 1 is functional. 0x08 means port 1, DIMM 0 is functional and 0x04 means port 1 DIMM 1 is functional. A fully populated system would have the value of 0xCC. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. creator: mss_eff_cnfg consumer: various firmware notes: none +This factors in functionality</description> + <valueType>uint8</valueType> + <writeable/> + <odmVisable/> + <odmChangeable/> + <persistRuntime/> +</attribute> + +<attribute> + <id>ATTR_MSS_CAL_STEP_ENABLE</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>A bit vector denoting valid cal steps to run during dram_init_train. [0] EXT_ZQCAL +[1] WR_LEVEL +[2] DQS_ALIGN +[3] RDCLK_ALIGN +[4] READ_CTR +[5] WRITE_CTR +[6] COARSE_WR +[7] COARSE_RD +bits6:7 will be consumed together to form COARSE_LVL. </description> + <valueType>uint8</valueType> + <writeable/> + <odmVisable/> + <odmChangeable/> + <persistRuntime/> +</attribute> + +<attribute> + <id>ATTR_MSS_MEM_IPL_COMPLETE</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>A numerical number indicating if the memory procedures are complete. written by mss_setup_bars when the bars are now functional in the processor. </description> + <valueType>uint8</valueType> + <writeable/> + <odmVisable/> + <odmChangeable/> + <persistRuntime/> </attribute> <!-- DO NOT EDIT THIS FILE DIRECTLY PLEASE UPDATE THE ODS FILE AND FOLLOW THE INSTRUCTION TAB --> diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_revert_sbe_mcs_setup/proc_revert_sbe_mcs_setup.C b/src/usr/hwpf/hwp/slave_sbe/proc_revert_sbe_mcs_setup/proc_revert_sbe_mcs_setup.C index af93f6006..d6e7ff5a9 100644 --- a/src/usr/hwpf/hwp/slave_sbe/proc_revert_sbe_mcs_setup/proc_revert_sbe_mcs_setup.C +++ b/src/usr/hwpf/hwp/slave_sbe/proc_revert_sbe_mcs_setup/proc_revert_sbe_mcs_setup.C @@ -1,27 +1,26 @@ -/* IBM_PROLOG_BEGIN_TAG - * This is an automatically generated prolog. - * - * $Source: src/usr/hwpf/hwp/slave_sbe/proc_revert_sbe_mcs_setup/proc_revert_sbe_mcs_setup.C $ - * - * IBM CONFIDENTIAL - * - * COPYRIGHT International Business Machines Corp. 2012 - * - * p1 - * - * Object Code Only (OCO) source materials - * Licensed Internal Code Source Materials - * IBM HostBoot Licensed Internal Code - * - * The source code for this program is not published or other- - * wise divested of its trade secrets, irrespective of what has - * been deposited with the U.S. Copyright Office. - * - * Origin: 30 - * - * IBM_PROLOG_END_TAG - */ -// $Id: proc_revert_sbe_mcs_setup.C,v 1.2 2012/06/29 06:15:33 jmcgill Exp $ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/slave_sbe/proc_revert_sbe_mcs_setup/proc_revert_sbe_mcs_setup.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2012 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +// $Id: proc_revert_sbe_mcs_setup.C,v 1.3 2012/07/23 14:16:04 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_revert_sbe_mcs_setup.C,v $ //------------------------------------------------------------------------------ // *| @@ -40,6 +39,7 @@ //------------------------------------------------------------------------------ // Includes //------------------------------------------------------------------------------ +#include "p8_scom_addresses.H" #include "proc_revert_sbe_mcs_setup.H" extern "C" diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_revert_sbe_mcs_setup/proc_revert_sbe_mcs_setup.H b/src/usr/hwpf/hwp/slave_sbe/proc_revert_sbe_mcs_setup/proc_revert_sbe_mcs_setup.H index f2aeb162b..f52ed6400 100644 --- a/src/usr/hwpf/hwp/slave_sbe/proc_revert_sbe_mcs_setup/proc_revert_sbe_mcs_setup.H +++ b/src/usr/hwpf/hwp/slave_sbe/proc_revert_sbe_mcs_setup/proc_revert_sbe_mcs_setup.H @@ -1,27 +1,26 @@ -/* IBM_PROLOG_BEGIN_TAG - * This is an automatically generated prolog. - * - * $Source: src/usr/hwpf/hwp/slave_sbe/proc_revert_sbe_mcs_setup/proc_revert_sbe_mcs_setup.H $ - * - * IBM CONFIDENTIAL - * - * COPYRIGHT International Business Machines Corp. 2012 - * - * p1 - * - * Object Code Only (OCO) source materials - * Licensed Internal Code Source Materials - * IBM HostBoot Licensed Internal Code - * - * The source code for this program is not published or other- - * wise divested of its trade secrets, irrespective of what has - * been deposited with the U.S. Copyright Office. - * - * Origin: 30 - * - * IBM_PROLOG_END_TAG - */ -// $Id: proc_revert_sbe_mcs_setup.H,v 1.1 2012/06/05 07:03:39 jmcgill Exp $ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/slave_sbe/proc_revert_sbe_mcs_setup/proc_revert_sbe_mcs_setup.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2012 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +// $Id: proc_revert_sbe_mcs_setup.H,v 1.2 2012/07/23 14:16:07 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_revert_sbe_mcs_setup.H,v $ //------------------------------------------------------------------------------ // *| @@ -52,8 +51,6 @@ #include <vector> #include <fapi.H> -#include "p8_scom_addresses.H" - //------------------------------------------------------------------------------ // Constant definitions diff --git a/src/usr/targeting/common/xmltohb/attribute_types.xml b/src/usr/targeting/common/xmltohb/attribute_types.xml index 47214785c..efeae371c 100644 --- a/src/usr/targeting/common/xmltohb/attribute_types.xml +++ b/src/usr/targeting/common/xmltohb/attribute_types.xml @@ -4356,4 +4356,243 @@ <!-- ===== ===== End Memory Map ===== ===== ===== ===== ===== ===== --> +<attribute> + <id>MSS_MCS_GROUP</id> + <description>Data Structure from eff grouping to setup bars to help determine different groups + Non- Mirroring [0-7] 0 -- MCS size //1-- No of MCS/group //2-- Total group size //3 -- Base address// 4-11 - MCS ID number// 12 --Alter.Bar //13 - A.Group Size // 14 - A.Base address + // Mirroring [8-15] 0 -- MCS size //1-- No of MCS/group //2-- Total group size //3 -- Base address// 4-11 - MCS ID number// 12 --Alter.Bar //13 - A.Group Size // 14 - A.Base address +Measured in GB</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + <array>16,16</array> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_MSS_MCS_GROUP</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>MSS_MCS_GROUP_32</id> + <description>Data Structure from eff grouping to setup bars to help determine different groups + Non- Mirroring [0-7] 0 -- MCS size //1-- No of MCS/group //2-- Total group size //3 -- Base address// 4-11 - MCS ID number// 12 --Alter.Bar //13 - A.Group Size // 14 - A.Base address + // Mirroring [8-15] 0 -- MCS size //1-- No of MCS/group //2-- Total group size //3 -- Base address// 4-11 - MCS ID number// 12 --Alter.Bar //13 - A.Group Size // 14 - A.Base address +Measured in GB</description> + <simpleType> + <uint32_t> + <default>0</default> + </uint32_t> + <array>16,16</array> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_MSS_MCS_GROUP_32</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>MSS_EFF_DIMM_FUNCTIONAL_VECTOR</id> + <description>A bit vector (per Dean's request) specifying if a DIMM is functional. DIMM attributes, such as SIZE, are qualified by this bit vector. The attribute ANDed 0x80 means port 0, DIMM 0 is functional, 0x40 means port 0, DIMM 1 is functional. 0x08 means port 1, DIMM 0 is functional and 0x04 means port 1 DIMM 1 is functional. A fully populated system would have the value of 0xCC. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. creator: mss_eff_cnfg consumer: various firmware notes: none +This factors in functionality</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_MSS_EFF_DIMM_FUNCTIONAL_VECTOR</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>MSS_INTERLEAVE_ENABLE</id> + <description>Used in the setting of groups. It is a bit vector. If the value BITWISE_AND 1 = 1 then groups of 1 are enabled with special checkerboard modes needed, if the value BITWISE_AND 2 = 2, then groups of 2 are possible; if value BITWISE_AND 4, the groups of 4 are possible; if value BITWISE_AND 8, the groups of 8 are possible. If no groups can formed according to this input, then an error will be thrown.</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <hwpfToHbAttrMap> + <id>ATTR_MSS_INTERLEAVE_ENABLE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_CKE_MAP</id> + <description>Rank to CKE map. Used in various locations and is computed in mss_eff_cnfg_cke. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. creator: mss_eff_cnfg_cke consumer: various firmware notes: none</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + <array>2,2,4</array> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_CKE_MAP</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_DIMM_SPARE</id> + <description>Spare DRAM availability. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. creator: mss_eff_cnfg consumer: various firmware notes: load from spd</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + <array>2,2,4</array> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_DIMM_SPARE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_SCHMOO_WR_EYE_MIN_MARGIN</id> + <description>Specifies the schmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_SCHMOO_WR_EYE_MIN_MARGIN</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_SCHMOO_RD_EYE_MIN_MARGIN</id> + <description>Specifies the schmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_SCHMOO_RD_EYE_MIN_MARGIN</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_SCHMOO_DQS_CLK_MIN_MARGIN</id> + <description>Specifies the schmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_SCHMOO_DQS_CLK_MIN_MARGIN</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_SCHMOO_RD_GATE_MIN_MARGIN</id> + <description>Specifies the schmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_SCHMOO_RD_GATE_MIN_MARGIN</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_SCHMOO_ADDR_CMD_MIN_MARGIN</id> + <description>Specifies the schmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_SCHMOO_ADDR_CMD_MIN_MARGIN</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>MSS_CAL_STEP_ENABLE</id> + <description>A bit vector denoting valid cal steps to run during dram_init_train. [0] EXT_ZQCAL +[1] WR_LEVEL +[2] DQS_ALIGN +[3] RDCLK_ALIGN +[4] READ_CTR +[5] WRITE_CTR +[6] COARSE_WR +[7] COARSE_RD +bits6:7 will be consumed together to form COARSE_LVL. </description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_MSS_CAL_STEP_ENABLE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>MSS_MEM_IPL_COMPLETE</id> + <description>A numerical number indicating if the memory procedures are complete. written by mss_setup_bars when the bars are now functional in the processor. </description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_MSS_MEM_IPL_COMPLETE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + </attributes> diff --git a/src/usr/targeting/common/xmltohb/target_types.xml b/src/usr/targeting/common/xmltohb/target_types.xml index 942861b5b..95dd09a47 100644 --- a/src/usr/targeting/common/xmltohb/target_types.xml +++ b/src/usr/targeting/common/xmltohb/target_types.xml @@ -1,25 +1,25 @@ -<!-- IBM_PROLOG_BEGIN_TAG - This is an automatically generated prolog. - - $Source: src/usr/targeting/common/xmltohb/target_types.xml $ - - IBM CONFIDENTIAL - - COPYRIGHT International Business Machines Corp. 2011-2012 - - p1 - - Object Code Only (OCO) source materials - Licensed Internal Code Source Materials - IBM HostBoot Licensed Internal Code - - The source code for this program is not published or other- - wise divested of its trade secrets, irrespective of what has - been deposited with the U.S. Copyright Office. - - Origin: 30 - - IBM_PROLOG_END_TAG --> +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/usr/targeting/common/xmltohb/target_types.xml $ --> +<!-- --> +<!-- IBM CONFIDENTIAL --> +<!-- --> +<!-- COPYRIGHT International Business Machines Corp. 2011,2012 --> +<!-- --> +<!-- p1 --> +<!-- --> +<!-- Object Code Only (OCO) source materials --> +<!-- Licensed Internal Code Source Materials --> +<!-- IBM HostBoot Licensed Internal Code --> +<!-- --> +<!-- The source code for this program is not published or otherwise --> +<!-- divested of its trade secrets, irrespective of what has been --> +<!-- deposited with the U.S. Copyright Office. --> +<!-- --> +<!-- Origin: 30 --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> <attributes> @@ -208,6 +208,7 @@ <!-- new attribute for isteps 15 & 16 --> <attribute><id>SLW_IMAGE_ADDR</id></attribute> <attribute><id>SLW_IMAGE_SIZE</id></attribute> + <attribute><id>MSS_INTERLEAVE_ENABLE</id></attribute> </targetType> <targetType> @@ -741,6 +742,7 @@ <attribute><id>EFF_NUM_PACKAGES_PER_RANK</id></attribute> <attribute><id>EFF_NUM_DIES_PER_PACKAGE</id></attribute> <attribute><id>MSS_SPARE_BYTE</id></attribute> + <attribute><id>MSS_EFF_DIMM_FUNCTIONAL_VECTOR</id></attribute> </targetType> <targetType> |
