diff options
Diffstat (limited to 'src/usr/intr')
| -rw-r--r-- | src/usr/intr/intrrp.C | 12 | ||||
| -rw-r--r-- | src/usr/intr/test/intrtest.H | 50 |
2 files changed, 12 insertions, 50 deletions
diff --git a/src/usr/intr/intrrp.C b/src/usr/intr/intrrp.C index b374c9f7d..39ea2d470 100644 --- a/src/usr/intr/intrrp.C +++ b/src/usr/intr/intrrp.C @@ -35,6 +35,7 @@ #include <sys/mmio.h> #include <sys/misc.h> #include <kernel/console.H> +#include <kernel/ipc.H> #include <sys/task.h> #include <vmmconst.h> #include <targeting/common/targetservice.H> @@ -181,6 +182,17 @@ errlHndl_t IntrRp::_init() TRACFCOMP(g_trac_intr,"INTR: vAddr = %lx",iv_baseAddr); + // Set up the IPC message Data area + TARGETING::Target * sys = NULL; + TARGETING::targetService().getTopLevelTarget( sys ); + assert(sys != NULL); + uint64_t hrmor_base = + sys->getAttr<TARGETING::ATTR_HB_HRMOR_NODAL_BASE>(); + + KernelIpc::ipc_data_area.pir = iv_masterCpu.word; + KernelIpc::ipc_data_area.hrmor_base = hrmor_base; + KernelIpc::ipc_data_area.msg_queue_id = 0; + // Set the BAR scom reg err = setBAR(procTarget,iv_masterCpu); diff --git a/src/usr/intr/test/intrtest.H b/src/usr/intr/test/intrtest.H index 56670329e..c653d6609 100644 --- a/src/usr/intr/test/intrtest.H +++ b/src/usr/intr/test/intrtest.H @@ -133,56 +133,6 @@ class IntrTest: public CxxTest::TestSuite } } - /** - * @brief Register an interrupt message queue, force an interrupt, - * then handle the interrupt. - */ - void test_intr( void ) - { - - // DISABLE in VBU - if( TARGETING::is_vpo() ) - { - return; - } - - errlHndl_t err = NULL; - - // Need to register a msgq - msg_q_t msgQ = msg_q_create(); - err = INTR::registerMsgQ(msgQ,0,INTR::ISN_INTERPROC); - if(err) - { - TS_FAIL("Errl from INTR::registerMsgQ()"); - delete err; - err = NULL; - } - - // Force an interrupt by writing to the MFFR on master - volatile uint8_t * mfrr = - reinterpret_cast<uint8_t *>(iv_masterAddr+12); - *(mfrr) = 0x55; - - TRACFCOMP(g_trac_intr,"Waiting for IPI interrupt"); - msg_t* msg = msg_wait(msgQ); // wait for interrupt msg - TRACFCOMP(g_trac_intr,"Interrupt handled! Type=%lx",msg->data[0]); - if(msg->data[0] != INTR::INTERPROC_XISR) - { - TS_FAIL("INTR::unexpected interrupt type %lx",msg->data[0]); - } - msg_respond(msgQ,msg); - - msgQ = INTR::unRegisterMsgQ(INTR::ISN_INTERPROC); - if(msgQ) - { - msg_q_destroy(msgQ); - } - else - { - TS_FAIL("INTR::unRegisterMsgQ failed"); - } - } - // This checks the enablePsiIntr. Even though the master proc // is already configured it does not use this interface // and there are no other processor currently configured in simics |
