diff options
Diffstat (limited to 'src/usr/hwpf')
6 files changed, 571 insertions, 109 deletions
diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp.C b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp.C index 5d98e2d88..f7955914e 100644 --- a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp.C +++ b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_build_smp.C,v 1.10 2013/09/26 18:14:05 jmcgill Exp $ +// $Id: proc_build_smp.C,v 1.13 2013/11/13 01:44:13 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_build_smp.C,v $ //------------------------------------------------------------------------------ // *| @@ -73,7 +73,7 @@ extern "C" // RC_PROC_BUILD_SMP_CORE_FLOOR_FREQ_RATIO_ERR if cache/nest frequency // ratio is unsupported, // RC_PROC_FAB_SMP_ASYNC_SAFE_MODE_ATTR_ERR if attribute value is -// invalid, +// invalid, // else error //------------------------------------------------------------------------------ fapi::ReturnCode proc_build_smp_process_system( @@ -89,7 +89,8 @@ fapi::ReturnCode proc_build_smp_process_system( do { - // TODO: link to attribute if PB AVP mode support is needed + + // ToDO: link to attribute if PB AVP mode support is needed io_smp.avp_mode = false; // get PB frequency attribute @@ -127,12 +128,45 @@ fapi::ReturnCode proc_build_smp_process_system( // get core floor frequency attribute FAPI_DBG("proc_build_smp_process_system: Querying core floor frequency attribute"); - rc = FAPI_ATTR_GET(ATTR_BOOT_FREQ_MHZ, + rc = FAPI_ATTR_GET(ATTR_FREQ_CORE_FLOOR, NULL, io_smp.freq_core_floor); if (!rc.ok()) { - FAPI_ERR("proc_build_smp_process_system: Error from FAPI_ATTR_GET (ATTR_BOOT_FREQ_MHZ"); + FAPI_ERR("proc_build_smp_process_system: Error from FAPI_ATTR_GET (ATTR_FREQ_CORE_FLOOR)"); + break; + } + + // get core nominal frequency attribute + FAPI_DBG("proc_build_smp_process_system: Querying core nominal frequency attribute"); + rc = FAPI_ATTR_GET(ATTR_FREQ_CORE_NOMINAL, + NULL, + io_smp.freq_core_nom); + if (!rc.ok()) + { + FAPI_ERR("proc_build_smp_process_system: Error from FAPI_ATTR_GET (ATTR_FREQ_CORE_NOMINAL)"); + break; + } + + // get core ceiling frequency attribute + FAPI_DBG("proc_build_smp_process_system: Querying core ceiling frequency attribute"); + rc = FAPI_ATTR_GET(ATTR_FREQ_CORE_MAX, + NULL, + io_smp.freq_core_ceiling); + if (!rc.ok()) + { + FAPI_ERR("proc_build_smp_process_system: Error from FAPI_ATTR_GET (ATTR_FREQ_CORE_MAX)"); + break; + } + + if (!((io_smp.freq_core_ceiling >= io_smp.freq_core_nom) && + (io_smp.freq_core_nom >= io_smp.freq_core_floor))) + { + const uint32_t& CEILING = io_smp.freq_core_ceiling; + const uint32_t& NOM = io_smp.freq_core_nom; + const uint32_t& FLOOR = io_smp.freq_core_floor; + FAPI_SET_HWP_ERROR(rc, + RC_PROC_BUILD_SMP_CORE_FREQ_RANGE_ERR); break; } @@ -414,32 +448,32 @@ fapi::ReturnCode proc_build_smp_process_system( FAPI_DBG("proc_build_smp_process_system: Calculating core floor to nest frequency ratio"); if ((io_smp.freq_core_floor) >= (2 * io_smp.freq_pb)) { - io_smp.core_floor_ratio = PROC_BUILD_SMP_CORE_FLOOR_RATIO_8_8; + io_smp.core_floor_ratio = PROC_BUILD_SMP_CORE_RATIO_8_8; } // breakpoint ratio: core floor 4.2, pb 2.4 (cache floor :: pb = 7/8) else if ((4 * io_smp.freq_core_floor) >= (7 * io_smp.freq_pb)) { - io_smp.core_floor_ratio = PROC_BUILD_SMP_CORE_FLOOR_RATIO_7_8; + io_smp.core_floor_ratio = PROC_BUILD_SMP_CORE_RATIO_7_8; } // breakpoint ratio: core floor 3.6, pb 2.4 (cache floor :: pb = 6/8) else if ((2 * io_smp.freq_core_floor) >= (3 * io_smp.freq_pb)) { - io_smp.core_floor_ratio = PROC_BUILD_SMP_CORE_FLOOR_RATIO_6_8; + io_smp.core_floor_ratio = PROC_BUILD_SMP_CORE_RATIO_6_8; } // breakpoint ratio: core floor 3.0, pb 2.4 (cache floor :: pb = 5/8) else if ((4 * io_smp.freq_core_floor) >= (5 * io_smp.freq_pb)) { - io_smp.core_floor_ratio = PROC_BUILD_SMP_CORE_FLOOR_RATIO_5_8; + io_smp.core_floor_ratio = PROC_BUILD_SMP_CORE_RATIO_5_8; } // breakpoint ratio: core floor 2.4, pb 2.4 (cache floor :: pb = 4/8) else if (io_smp.freq_core_floor >= io_smp.freq_pb) { - io_smp.core_floor_ratio = PROC_BUILD_SMP_CORE_FLOOR_RATIO_4_8; + io_smp.core_floor_ratio = PROC_BUILD_SMP_CORE_RATIO_4_8; } // breakpoint ratio: core floor 1.2, pb 2.4 (cache floor :: pb = 2/8) else if ((2 * io_smp.freq_core_floor) >= io_smp.freq_pb) { - io_smp.core_floor_ratio = PROC_BUILD_SMP_CORE_FLOOR_RATIO_2_8; + io_smp.core_floor_ratio = PROC_BUILD_SMP_CORE_RATIO_2_8; } // under-range, raise error else @@ -451,6 +485,147 @@ fapi::ReturnCode proc_build_smp_process_system( FAPI_SET_HWP_ERROR(rc, RC_PROC_BUILD_SMP_CORE_FLOOR_FREQ_RATIO_ERR); break; } + + // determine table index based on pb/core ceiling frequency ratio + // breakpoint ratio: core ceiling 4.8, pb 2.4 (cache ceiling :: pb = 8/8) + FAPI_DBG("proc_build_smp_process_system: Calculating core ceiling to nest frequency ratio"); + if ((io_smp.freq_core_ceiling) >= (2 * io_smp.freq_pb)) + { + io_smp.core_ceiling_ratio = PROC_BUILD_SMP_CORE_RATIO_8_8; + } + // breakpoint ratio: core ceiling 4.2, pb 2.4 (cache ceiling :: pb = 7/8) + else if ((4 * io_smp.freq_core_ceiling) >= (7 * io_smp.freq_pb)) + { + io_smp.core_ceiling_ratio = PROC_BUILD_SMP_CORE_RATIO_7_8; + } + // breakpoint ratio: core ceiling 3.6, pb 2.4 (cache ceiling :: pb = 6/8) + else if ((2 * io_smp.freq_core_ceiling) >= (3 * io_smp.freq_pb)) + { + io_smp.core_ceiling_ratio = PROC_BUILD_SMP_CORE_RATIO_6_8; + } + // breakpoint ratio: core ceiling 3.0, pb 2.4 (cache ceiling :: pb = 5/8) + else if ((4 * io_smp.freq_core_ceiling) >= (5 * io_smp.freq_pb)) + { + io_smp.core_ceiling_ratio = PROC_BUILD_SMP_CORE_RATIO_5_8; + } + // breakpoint ratio: core ceiling 2.4, pb 2.4 (cache ceiling :: pb = 4/8) + else if (io_smp.freq_core_ceiling >= io_smp.freq_pb) + { + io_smp.core_ceiling_ratio = PROC_BUILD_SMP_CORE_RATIO_4_8; + } + // breakpoint ratio: core ceiling 1.2, pb 2.4 (cache ceiling :: pb = 2/8) + else if ((2 * io_smp.freq_core_ceiling) >= io_smp.freq_pb) + { + io_smp.core_ceiling_ratio = PROC_BUILD_SMP_CORE_RATIO_2_8; + } + // under-range, raise error + else + { + FAPI_ERR("proc_build_smp_process_system: Unsupported core ceiling/PB frequency ratio (=%d/%d)", + io_smp.freq_core_ceiling, io_smp.freq_pb); + const uint32_t& FREQ_PB = io_smp.freq_pb; + const uint32_t& FREQ_CORE_CEILING = io_smp.freq_core_ceiling; + FAPI_SET_HWP_ERROR(rc, RC_PROC_BUILD_SMP_CORE_CEILING_FREQ_RATIO_ERR); + break; + } + + // determine full CPU delay settings + FAPI_DBG("proc_build_smp_process_system: Calculating full CPU delay settings:"); + if ((2400 * io_smp.freq_core_ceiling) >= (4800 * io_smp.freq_pb)) + { + io_smp.full_cpu_delay = PROC_BUILD_SMP_CPU_DELAY_4800_2400; + } + else if ((2400 * io_smp.freq_core_ceiling) >= (4431 * io_smp.freq_pb)) + { + io_smp.full_cpu_delay = PROC_BUILD_SMP_CPU_DELAY_4431_2400; + } + else if ((2400 * io_smp.freq_core_ceiling) >= (4114 * io_smp.freq_pb)) + { + io_smp.full_cpu_delay = PROC_BUILD_SMP_CPU_DELAY_4114_2400; + } + else if ((2400 * io_smp.freq_core_ceiling) >= (3840 * io_smp.freq_pb)) + { + io_smp.full_cpu_delay = PROC_BUILD_SMP_CPU_DELAY_3840_2400; + } + else if ((2400 * io_smp.freq_core_ceiling) >= (3338 * io_smp.freq_pb)) + { + io_smp.full_cpu_delay = PROC_BUILD_SMP_CPU_DELAY_3338_2400; + } + else if ((2400 * io_smp.freq_core_ceiling) >= (3032 * io_smp.freq_pb)) + { + io_smp.full_cpu_delay = PROC_BUILD_SMP_CPU_DELAY_3032_2400; + } + else + { + io_smp.full_cpu_delay = PROC_BUILD_SMP_CPU_DELAY_2743_2400; + } + + // determine nominal CPU delay settings + FAPI_DBG("proc_build_smp_process_system: Calculating nominal CPU delay settings:"); + if ((2400 * io_smp.freq_core_nom) >= (4800 * io_smp.freq_pb)) + { + // shift to avoid equivalent index + io_smp.nom_cpu_delay = PROC_BUILD_SMP_CPU_DELAY_4431_2400; + } + else if ((2400 * io_smp.freq_core_nom) >= (4431 * io_smp.freq_pb)) + { + io_smp.nom_cpu_delay = PROC_BUILD_SMP_CPU_DELAY_4431_2400; + // shift to avoid equivalent index + if (io_smp.nom_cpu_delay == io_smp.full_cpu_delay) + { + io_smp.nom_cpu_delay = PROC_BUILD_SMP_CPU_DELAY_4114_2400; + } + } + else if ((2400 * io_smp.freq_core_nom) >= (4114 * io_smp.freq_pb)) + { + io_smp.nom_cpu_delay = PROC_BUILD_SMP_CPU_DELAY_4114_2400; + // shift to avoid equivalent index + if (io_smp.nom_cpu_delay == io_smp.full_cpu_delay) + { + io_smp.nom_cpu_delay = PROC_BUILD_SMP_CPU_DELAY_3840_2400; + } + } + else if ((2400 * io_smp.freq_core_nom) >= (3840 * io_smp.freq_pb)) + { + io_smp.nom_cpu_delay = PROC_BUILD_SMP_CPU_DELAY_3840_2400; + // shift to avoid equivalent index + if (io_smp.nom_cpu_delay == io_smp.full_cpu_delay) + { + io_smp.nom_cpu_delay = PROC_BUILD_SMP_CPU_DELAY_3338_2400; + } + } + else if ((2400 * io_smp.freq_core_nom) >= (3338 * io_smp.freq_pb)) + { + io_smp.nom_cpu_delay = PROC_BUILD_SMP_CPU_DELAY_3338_2400; + // shift to avoid equivalent index + if (io_smp.nom_cpu_delay == io_smp.full_cpu_delay) + { + io_smp.nom_cpu_delay = PROC_BUILD_SMP_CPU_DELAY_3032_2400; + } + } + else if ((2400 * io_smp.freq_core_nom) >= (3032 * io_smp.freq_pb)) + { + io_smp.nom_cpu_delay = PROC_BUILD_SMP_CPU_DELAY_3032_2400; + // shift to avoid equivalent index + if (io_smp.nom_cpu_delay == io_smp.full_cpu_delay) + { + io_smp.nom_cpu_delay = PROC_BUILD_SMP_CPU_DELAY_2743_2400; + } + } + else if ((2400 * io_smp.freq_core_nom) >= (2743 * io_smp.freq_pb)) + { + io_smp.nom_cpu_delay = PROC_BUILD_SMP_CPU_DELAY_2743_2400; + // shift to avoid equivalent index + if (io_smp.nom_cpu_delay == io_smp.full_cpu_delay) + { + io_smp.nom_cpu_delay = PROC_BUILD_SMP_CPU_DELAY_2504_2400; + } + } + else + { + io_smp.nom_cpu_delay = PROC_BUILD_SMP_CPU_DELAY_2504_2400; + } + } while(0); // mark function entry diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp.H b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp.H index ec9b01059..f7e24d68a 100644 --- a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp.H +++ b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp.H @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_build_smp.H,v 1.12 2013/10/18 21:36:02 jmcgill Exp $ +// $Id: proc_build_smp.H,v 1.13 2013/11/13 01:41:53 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_build_smp.H,v $ //------------------------------------------------------------------------------ // *| @@ -158,15 +158,15 @@ struct proc_build_smp_node proc_fab_smp_node_id node_id; }; -// core floor/nest frequency ratio cutpoints (epsilon) -enum proc_build_smp_core_floor_ratio +// core/nest frequency ratio cutpoints (epsilon) +enum proc_build_smp_core_ratio { - PROC_BUILD_SMP_CORE_FLOOR_RATIO_8_8 = 0, - PROC_BUILD_SMP_CORE_FLOOR_RATIO_7_8 = 1, - PROC_BUILD_SMP_CORE_FLOOR_RATIO_6_8 = 2, - PROC_BUILD_SMP_CORE_FLOOR_RATIO_5_8 = 3, - PROC_BUILD_SMP_CORE_FLOOR_RATIO_4_8 = 4, - PROC_BUILD_SMP_CORE_FLOOR_RATIO_2_8 = 5 + PROC_BUILD_SMP_CORE_RATIO_8_8 = 0, + PROC_BUILD_SMP_CORE_RATIO_7_8 = 1, + PROC_BUILD_SMP_CORE_RATIO_6_8 = 2, + PROC_BUILD_SMP_CORE_RATIO_5_8 = 3, + PROC_BUILD_SMP_CORE_RATIO_4_8 = 4, + PROC_BUILD_SMP_CORE_RATIO_2_8 = 5 }; // core floor/nest frequency ratio cutpoints (CPU delay) @@ -226,9 +226,10 @@ struct proc_build_smp_system uint32_t freq_core_nom; uint32_t freq_core_ceiling; uint32_t freq_pcie; - // core floor/pb frequency ratio - proc_build_smp_core_floor_ratio core_floor_ratio; - // CPU ratios + // core/pb frequency ratios + proc_build_smp_core_ratio core_floor_ratio; + proc_build_smp_core_ratio core_ceiling_ratio; + // CPU delay/RCMD highwater settings proc_build_smp_cpu_delay nom_cpu_delay; proc_build_smp_cpu_delay full_cpu_delay; @@ -287,6 +288,12 @@ extern "C" // invalid, // RC_PROC_BUILD_SMP_CORE_FLOOR_FREQ_RATIO_ERR if cache/nest frequency // ratio is unsupported, +// RC_PROC_BUILD_SMP_CORE_CEILING_FREQ_RATIO_ERR if cache/nest frequency +// ratio is unsupported, +// RC_PROC_BUILD_SMP_CORE_FLOOR_RATIO_ERR if cache/nest frequency +// ratio is unsupported, +// RC_PROC_BUILD_SMP_CORE_CEILING_RATIO_ERR if cache/nest frequency +// ratio is unsupported, // RC_PROC_FAB_SMP_ASYNC_SAFE_MODE_ATTR_ERR if attribute value is // invalid, // RC_PROC_FAB_SMP_PCIE_NOT_F_LINK_ATTR_ERR if attribute value is diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_errors.xml b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_errors.xml index 1203a3ae7..4d8783a95 100644 --- a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_errors.xml +++ b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_errors.xml @@ -20,7 +20,7 @@ <!-- Origin: 30 --> <!-- --> <!-- IBM_PROLOG_END_TAG --> -<!-- $Id: proc_build_smp_errors.xml,v 1.5 2013/09/26 18:16:09 jmcgill Exp $ --> +<!-- $Id: proc_build_smp_errors.xml,v 1.7 2013/11/13 13:59:51 jmcgill Exp $ --> <!-- Error definitions for proc_build_smp --> <hwpErrors> <!-- *********************************************************************** --> @@ -69,17 +69,35 @@ <description>Command rate pacing table lookup error.</description> </hwpError> <hwpError> + <rc>RC_PROC_BUILD_SMP_CORE_FREQ_RANGE_ERR</rc> + <description>Invalid relationship between ceiling/nominal/floor core frequency attributes.</description> + <ffdc>CEILING</ffdc> + <ffdc>NOM</ffdc> + <ffdc>FLOOR</ffdc> + </hwpError> + <hwpError> <rc>RC_PROC_BUILD_SMP_CORE_FLOOR_FREQ_RATIO_ERR</rc> <description>Unsupported core floor to PB frequency ratio.</description> <ffdc>FREQ_PB</ffdc> <ffdc>FREQ_CORE_FLOOR</ffdc> </hwpError> <hwpError> + <rc>RC_PROC_BUILD_SMP_CORE_CEILING_FREQ_RATIO_ERR</rc> + <description>Unsupported core ceiling to PB frequency ratio.</description> + <ffdc>FREQ_PB</ffdc> + <ffdc>FREQ_CORE_CEILING</ffdc> + </hwpError> + <hwpError> <rc>RC_PROC_BUILD_SMP_CORE_FLOOR_RATIO_ERR</rc> <description>Unsupported core floor frequency enumerated value.</description> <ffdc>CORE_FLOOR_RATIO</ffdc> </hwpError> <hwpError> + <rc>RC_PROC_BUILD_SMP_CORE_CEILING_RATIO_ERR</rc> + <description>Unsupported core ceiling frequency enumerated value.</description> + <ffdc>CORE_CEILING_RATIO</ffdc> + </hwpError> + <hwpError> <rc>RC_PROC_BUILD_SMP_INVALID_GROUP_SIZE_ERR</rc> <description>Invalid chips per group configuration detected.</description> <ffdc>SIZE</ffdc> diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_cd.C b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_cd.C index 3d7938537..27915f48a 100644 --- a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_cd.C +++ b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_cd.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_build_smp_fbc_cd.C,v 1.9 2013/06/20 21:19:02 jmcgill Exp $ +// $Id: proc_build_smp_fbc_cd.C,v 1.13 2013/11/13 01:51:47 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_build_smp_fbc_cd.C,v $ //------------------------------------------------------------------------------ // *| @@ -450,12 +450,99 @@ fapi::ReturnCode proc_build_smp_set_sconfig_c8( fapi::ReturnCode rc; uint32_t rc_ecmd = 0x0; ecmdDataBufferBase data(64); + uint8_t ver2 = 0x0; + uint8_t ver3 = 0x0; + uint32_t PB_SCONFIG_C8_HANG_CMD_RATE_START_BIT[PB_SCONFIG_NUM_HANG_LEVELS]; + uint32_t PB_SCONFIG_C8_HANG_CMD_RATE_END_BIT[PB_SCONFIG_NUM_HANG_LEVELS]; + uint32_t PB_SCONFIG_C8_CPO_JUMP_LEVEL_START_BIT; + uint32_t PB_SCONFIG_C8_CPO_JUMP_LEVEL_END_BIT; + uint32_t PB_SCONFIG_C8_CPO_RTY_LEVEL_START_BIT; + uint32_t PB_SCONFIG_C8_CPO_RTY_LEVEL_END_BIT; + uint32_t PB_SCONFIG_C8_P7_SLEEP_BACKOFF_START_BIT; + uint32_t PB_SCONFIG_C8_P7_SLEEP_BACKOFF_END_BIT; + uint32_t PB_SCONFIG_C8_RTY_PERCENTAGE_START_BIT; + uint32_t PB_SCONFIG_C8_RTY_PERCENTAGE_END_BIT; + uint32_t PB_SCONFIG_C8_INCLUDE_LPC_RTY_BIT; + proc_build_smp_sconfig_def pb_sconfig_c8_def; // mark function entry FAPI_DBG("proc_build_smp_set_sconfig_c8: Start"); do { + rc = FAPI_ATTR_GET(ATTR_CHIP_EC_FEATURE_FBC_SERIAL_SCOM_C8_VER2, + &(i_smp_chip.chip->this_chip), + ver2); + if (!rc.ok()) + { + FAPI_ERR("Error querying Chip EC feature: ATTR_CHIP_EC_FEATURE_FBC_SERIAL_SCOM_C8_VER2"); + break; + } + + rc = FAPI_ATTR_GET(ATTR_CHIP_EC_FEATURE_FBC_SERIAL_SCOM_C8_VER3, + &(i_smp_chip.chip->this_chip), + ver3); + if (!rc.ok()) + { + FAPI_ERR("Error querying Chip EC feature: ATTR_CHIP_EC_FEATURE_FBC_SERIAL_SCOM_C8_VER3"); + break; + } + + if (ver3) + { + for (uint8_t l = 0; l < PB_SCONFIG_NUM_HANG_LEVELS; l++) + { + PB_SCONFIG_C8_HANG_CMD_RATE_START_BIT[l] = PB_SCONFIG_C8_HANG_CMD_RATE_START_BIT_VER3[l]; + PB_SCONFIG_C8_HANG_CMD_RATE_END_BIT[l] = PB_SCONFIG_C8_HANG_CMD_RATE_END_BIT_VER3[l]; + } + PB_SCONFIG_C8_CPO_JUMP_LEVEL_START_BIT = PB_SCONFIG_C8_CPO_JUMP_LEVEL_START_BIT_VER3; + PB_SCONFIG_C8_CPO_JUMP_LEVEL_END_BIT = PB_SCONFIG_C8_CPO_JUMP_LEVEL_END_BIT_VER3; + PB_SCONFIG_C8_CPO_RTY_LEVEL_START_BIT = PB_SCONFIG_C8_CPO_RTY_LEVEL_START_BIT_VER3; + PB_SCONFIG_C8_CPO_RTY_LEVEL_END_BIT = PB_SCONFIG_C8_CPO_RTY_LEVEL_END_BIT_VER3; + PB_SCONFIG_C8_P7_SLEEP_BACKOFF_START_BIT = PB_SCONFIG_C8_P7_SLEEP_BACKOFF_START_BIT_VER3; + PB_SCONFIG_C8_P7_SLEEP_BACKOFF_END_BIT = PB_SCONFIG_C8_P7_SLEEP_BACKOFF_END_BIT_VER3; + PB_SCONFIG_C8_RTY_PERCENTAGE_START_BIT = PB_SCONFIG_C8_RTY_PERCENTAGE_START_BIT_VER3; + PB_SCONFIG_C8_RTY_PERCENTAGE_END_BIT = PB_SCONFIG_C8_RTY_PERCENTAGE_END_BIT_VER3; + PB_SCONFIG_C8_INCLUDE_LPC_RTY_BIT = PB_SCONFIG_C8_INCLUDE_LPC_RTY_BIT_VER3; + pb_sconfig_c8_def = PB_SCONFIG_C8_DEF_VER3; + } + else if (ver2) + { + for (uint8_t l = 0; l < PB_SCONFIG_NUM_HANG_LEVELS; l++) + { + PB_SCONFIG_C8_HANG_CMD_RATE_START_BIT[l] = PB_SCONFIG_C8_HANG_CMD_RATE_START_BIT_VER2[l]; + PB_SCONFIG_C8_HANG_CMD_RATE_END_BIT[l] = PB_SCONFIG_C8_HANG_CMD_RATE_END_BIT_VER2[l]; + } + PB_SCONFIG_C8_CPO_JUMP_LEVEL_START_BIT = PB_SCONFIG_C8_CPO_JUMP_LEVEL_START_BIT_VER2; + PB_SCONFIG_C8_CPO_JUMP_LEVEL_END_BIT = PB_SCONFIG_C8_CPO_JUMP_LEVEL_END_BIT_VER2; + PB_SCONFIG_C8_CPO_RTY_LEVEL_START_BIT = PB_SCONFIG_C8_CPO_RTY_LEVEL_START_BIT_VER2; + PB_SCONFIG_C8_CPO_RTY_LEVEL_END_BIT = PB_SCONFIG_C8_CPO_RTY_LEVEL_END_BIT_VER2; + PB_SCONFIG_C8_P7_SLEEP_BACKOFF_START_BIT = PB_SCONFIG_C8_P7_SLEEP_BACKOFF_START_BIT_VER2; + PB_SCONFIG_C8_P7_SLEEP_BACKOFF_END_BIT = PB_SCONFIG_C8_P7_SLEEP_BACKOFF_END_BIT_VER2; + PB_SCONFIG_C8_RTY_PERCENTAGE_START_BIT = 0xFF; + PB_SCONFIG_C8_RTY_PERCENTAGE_END_BIT = 0xFF; + PB_SCONFIG_C8_INCLUDE_LPC_RTY_BIT = 0xFF; + pb_sconfig_c8_def = PB_SCONFIG_C8_DEF_VER2; + } + else + { + for (uint8_t l = 0; l < PB_SCONFIG_NUM_HANG_LEVELS; l++) + { + PB_SCONFIG_C8_HANG_CMD_RATE_START_BIT[l] = PB_SCONFIG_C8_HANG_CMD_RATE_START_BIT_VER1[l]; + PB_SCONFIG_C8_HANG_CMD_RATE_END_BIT[l] = PB_SCONFIG_C8_HANG_CMD_RATE_END_BIT_VER1[l]; + } + PB_SCONFIG_C8_CPO_JUMP_LEVEL_START_BIT = PB_SCONFIG_C8_CPO_JUMP_LEVEL_START_BIT_VER1; + PB_SCONFIG_C8_CPO_JUMP_LEVEL_END_BIT = PB_SCONFIG_C8_CPO_JUMP_LEVEL_END_BIT_VER1; + PB_SCONFIG_C8_CPO_RTY_LEVEL_START_BIT = PB_SCONFIG_C8_CPO_RTY_LEVEL_START_BIT_VER1; + PB_SCONFIG_C8_CPO_RTY_LEVEL_END_BIT = PB_SCONFIG_C8_CPO_RTY_LEVEL_END_BIT_VER1; + PB_SCONFIG_C8_P7_SLEEP_BACKOFF_START_BIT = 0xFF; + PB_SCONFIG_C8_P7_SLEEP_BACKOFF_END_BIT = 0xFF; + PB_SCONFIG_C8_RTY_PERCENTAGE_START_BIT = 0xFF; + PB_SCONFIG_C8_RTY_PERCENTAGE_END_BIT = 0xFF; + PB_SCONFIG_C8_INCLUDE_LPC_RTY_BIT = 0xFF; + pb_sconfig_c8_def = PB_SCONFIG_C8_DEF_VER1; + } + // build register content // program hang command rates for (uint8_t l = 0; l < PB_SCONFIG_NUM_HANG_LEVELS; l++) @@ -481,6 +568,31 @@ fapi::ReturnCode proc_build_smp_set_sconfig_c8( (PB_SCONFIG_C8_CPO_RTY_LEVEL_END_BIT- PB_SCONFIG_C8_CPO_RTY_LEVEL_START_BIT+1)); + // p7_sleep_backoff + if (ver2 || ver3) + { + rc_ecmd |= data.insertFromRight( + PB_SCONFIG_C8_P7_SLEEP_BACKOFF, + PB_SCONFIG_C8_P7_SLEEP_BACKOFF_START_BIT, + (PB_SCONFIG_C8_P7_SLEEP_BACKOFF_END_BIT- + PB_SCONFIG_C8_P7_SLEEP_BACKOFF_START_BIT+1)); + } + + // rty_percentage + // include_lpc_rty + if (ver3) + { + rc_ecmd |= data.insertFromRight( + PB_SCONFIG_C8_RTY_PERCENTAGE, + PB_SCONFIG_C8_RTY_PERCENTAGE_START_BIT, + (PB_SCONFIG_C8_RTY_PERCENTAGE_END_BIT- + PB_SCONFIG_C8_RTY_PERCENTAGE_START_BIT+1)); + + rc_ecmd |= data.writeBit( + PB_SCONFIG_C8_INCLUDE_LPC_RTY_BIT, + PB_SCONFIG_C8_INCLUDE_LPC_RTY?1:0); + } + if (rc_ecmd) { FAPI_ERR("proc_build_smp_set_sconfig_c8: Error 0x%x setting up PB Serial Configuration load register data buffer", @@ -490,7 +602,10 @@ fapi::ReturnCode proc_build_smp_set_sconfig_c8( } // call common routine to program chain - rc = proc_build_smp_set_sconfig(i_smp_chip, PB_SCONFIG_C8_DEF, data); + rc = proc_build_smp_set_sconfig( + i_smp_chip, + pb_sconfig_c8_def, + data); if (!rc.ok()) { FAPI_ERR("proc_build_smp_set_sconfig_c8: Error from proc_build_smp_set_sconfig"); @@ -598,30 +713,105 @@ fapi::ReturnCode proc_build_smp_set_sconfig_c9( //------------------------------------------------------------------------------ // function: program PB serial SCOM chain (center #10) // parameters: i_smp_chip => structure encapsulating SMP chip +// i_smp => structure encapsulating SMP // returns: FAPI_RC_SUCCESS if register programming is successful, // else error //------------------------------------------------------------------------------ fapi::ReturnCode proc_build_smp_set_sconfig_c10( - const proc_build_smp_chip& i_smp_chip) + const proc_build_smp_chip& i_smp_chip, + const proc_build_smp_system& i_smp) { fapi::ReturnCode rc; uint32_t rc_ecmd = 0x0; ecmdDataBufferBase data(64); + uint8_t ver2; + uint32_t PB_SCONFIG_C10_CMD_CPU_RATIO_START_BIT[PB_SCONFIG_NUM_CPU_RATIOS]; + uint32_t PB_SCONFIG_C10_CMD_CPU_RATIO_END_BIT[PB_SCONFIG_NUM_CPU_RATIOS]; + uint32_t PB_SCONFIG_C10_DAT_X_LINK_HOLDOFF_ENABLE_BIT; + uint32_t PB_SCONFIG_C10_DAT_A_LINK_HOLDOFF_ENABLE_BIT; + uint32_t PB_SCONFIG_C10_DAT_LINK_HOLDOFF_MULTIPLIER_BIT; + proc_build_smp_sconfig_def pb_sconfig_c10_def; // mark function entry FAPI_DBG("proc_build_smp_set_sconfig_c10: Start"); do { + rc = FAPI_ATTR_GET(ATTR_CHIP_EC_FEATURE_FBC_SERIAL_SCOM_C10_VER2, + &(i_smp_chip.chip->this_chip), + ver2); + if (!rc.ok()) + { + FAPI_ERR("Error querying Chip EC feature: ATTR_CHIP_EC_FEATURE_FBC_SERIAL_SCOM_C10_VER2"); + break; + } + + if (ver2) + { + for (uint8_t l = 0; l < PB_SCONFIG_NUM_CPU_RATIOS; l++) + { + PB_SCONFIG_C10_CMD_CPU_RATIO_START_BIT[l] = PB_SCONFIG_C10_CMD_CPU_RATIO_START_BIT_VER2[l]; + PB_SCONFIG_C10_CMD_CPU_RATIO_END_BIT[l] = PB_SCONFIG_C10_CMD_CPU_RATIO_END_BIT_VER2[l]; + } + PB_SCONFIG_C10_DAT_X_LINK_HOLDOFF_ENABLE_BIT = PB_SCONFIG_C10_DAT_X_LINK_HOLDOFF_ENABLE_BIT_VER2; + PB_SCONFIG_C10_DAT_A_LINK_HOLDOFF_ENABLE_BIT = PB_SCONFIG_C10_DAT_A_LINK_HOLDOFF_ENABLE_BIT_VER2; + PB_SCONFIG_C10_DAT_LINK_HOLDOFF_MULTIPLIER_BIT = PB_SCONFIG_C10_DAT_LINK_HOLDOFF_MULTIPLIER_BIT_VER2; + pb_sconfig_c10_def = PB_SCONFIG_C10_DEF_VER2; + } + else + { + for (uint8_t l = 0; l < PB_SCONFIG_NUM_CPU_RATIOS; l++) + { + PB_SCONFIG_C10_CMD_CPU_RATIO_START_BIT[l] = PB_SCONFIG_C10_CMD_CPU_RATIO_START_BIT_VER1[l]; + PB_SCONFIG_C10_CMD_CPU_RATIO_END_BIT[l] = PB_SCONFIG_C10_CMD_CPU_RATIO_END_BIT_VER1[l]; + } + PB_SCONFIG_C10_DAT_X_LINK_HOLDOFF_ENABLE_BIT = 0xFF; + PB_SCONFIG_C10_DAT_A_LINK_HOLDOFF_ENABLE_BIT = 0xFF; + PB_SCONFIG_C10_DAT_LINK_HOLDOFF_MULTIPLIER_BIT = 0xFF; + pb_sconfig_c10_def = PB_SCONFIG_C10_DEF_VER1; + } + // build register content - // program hang command rates - for (uint8_t l = 0; l < PB_SCONFIG_NUM_CPU_RATIOS; l++) + rc_ecmd |= data.insertFromRight( + PB_SCONFIG_C10_CMD_CPU_RATIO_QUARTER, + PB_SCONFIG_C10_CMD_CPU_RATIO_START_BIT[0], + (PB_SCONFIG_C10_CMD_CPU_RATIO_END_BIT[0]- + PB_SCONFIG_C10_CMD_CPU_RATIO_START_BIT[0]+1)); + + rc_ecmd |= data.insertFromRight( + PB_SCONFIG_C10_CMD_CPU_RATIO_HALF, + PB_SCONFIG_C10_CMD_CPU_RATIO_START_BIT[1], + (PB_SCONFIG_C10_CMD_CPU_RATIO_END_BIT[1]- + PB_SCONFIG_C10_CMD_CPU_RATIO_START_BIT[1]+1)); + + rc_ecmd |= data.insertFromRight( + PB_SCONFIG_C10_CMD_CPU_RATIO_TABLE[i_smp.nom_cpu_delay], + PB_SCONFIG_C10_CMD_CPU_RATIO_START_BIT[2], + (PB_SCONFIG_C10_CMD_CPU_RATIO_END_BIT[2]- + PB_SCONFIG_C10_CMD_CPU_RATIO_START_BIT[2]+1)); + + rc_ecmd |= data.insertFromRight( + PB_SCONFIG_C10_CMD_CPU_RATIO_TABLE[i_smp.full_cpu_delay], + PB_SCONFIG_C10_CMD_CPU_RATIO_START_BIT[3], + (PB_SCONFIG_C10_CMD_CPU_RATIO_END_BIT[3]- + PB_SCONFIG_C10_CMD_CPU_RATIO_START_BIT[3]+1)); + + // x_link_holdoff_enable + // a_link_holdoff_enable + // link_holdoff_mutlipler + if (ver2) { - rc_ecmd |= data.insertFromRight( - PB_SCONFIG_C10_CMD_CPU_RATIO[l], - PB_SCONFIG_C10_CMD_CPU_RATIO_START_BIT[l], - (PB_SCONFIG_C10_CMD_CPU_RATIO_END_BIT[l]- - PB_SCONFIG_C10_CMD_CPU_RATIO_START_BIT[l]+1)); + rc_ecmd |= data.writeBit( + PB_SCONFIG_C10_DAT_X_LINK_HOLDOFF_ENABLE_BIT, + PB_SCONFIG_C10_DAT_X_LINK_HOLDOFF_ENABLE); + + rc_ecmd |= data.writeBit( + PB_SCONFIG_C10_DAT_A_LINK_HOLDOFF_ENABLE_BIT, + PB_SCONFIG_C10_DAT_A_LINK_HOLDOFF_ENABLE); + + rc_ecmd |= data.writeBit( + PB_SCONFIG_C10_DAT_LINK_HOLDOFF_MULTIPLIER_BIT, + PB_SCONFIG_C10_DAT_LINK_HOLDOFF_MULTIPLIER); } if (rc_ecmd) @@ -633,7 +823,7 @@ fapi::ReturnCode proc_build_smp_set_sconfig_c10( } // call common routine to program chain - rc = proc_build_smp_set_sconfig(i_smp_chip, PB_SCONFIG_C10_DEF, data); + rc = proc_build_smp_set_sconfig(i_smp_chip, pb_sconfig_c10_def, data); if (!rc.ok()) { FAPI_ERR("proc_build_smp_set_sconfig_c10: Error from proc_build_smp_set_sconfig"); @@ -650,11 +840,13 @@ fapi::ReturnCode proc_build_smp_set_sconfig_c10( //------------------------------------------------------------------------------ // function: program PB serial SCOM chain (center #11) // parameters: i_smp_chip => structure encapsulating SMP chip +// i_smp => structure encapsulating SMP // returns: FAPI_RC_SUCCESS if register programming is successful, // else error //------------------------------------------------------------------------------ fapi::ReturnCode proc_build_smp_set_sconfig_c11( - const proc_build_smp_chip& i_smp_chip) + const proc_build_smp_chip& i_smp_chip, + const proc_build_smp_system& i_smp) { fapi::ReturnCode rc; uint32_t rc_ecmd = 0x0; @@ -666,15 +858,29 @@ fapi::ReturnCode proc_build_smp_set_sconfig_c11( do { // build register content - // program hang command rates - for (uint8_t l = 0; l < PB_SCONFIG_NUM_CPU_RATIOS; l++) - { - rc_ecmd |= data.insertFromRight( - PB_SCONFIG_C11_RSP_CPU_RATIO[l], - PB_SCONFIG_C11_RSP_CPU_RATIO_START_BIT[l], - (PB_SCONFIG_C11_RSP_CPU_RATIO_END_BIT[l]- - PB_SCONFIG_C11_RSP_CPU_RATIO_START_BIT[l]+1)); - } + rc_ecmd |= data.insertFromRight( + PB_SCONFIG_C11_RSP_CPU_RATIO_QUARTER, + PB_SCONFIG_C11_RSP_CPU_RATIO_START_BIT[0], + (PB_SCONFIG_C11_RSP_CPU_RATIO_END_BIT[0]- + PB_SCONFIG_C11_RSP_CPU_RATIO_START_BIT[0]+1)); + + rc_ecmd |= data.insertFromRight( + PB_SCONFIG_C11_RSP_CPU_RATIO_HALF, + PB_SCONFIG_C11_RSP_CPU_RATIO_START_BIT[1], + (PB_SCONFIG_C11_RSP_CPU_RATIO_END_BIT[1]- + PB_SCONFIG_C11_RSP_CPU_RATIO_START_BIT[1]+1)); + + rc_ecmd |= data.insertFromRight( + PB_SCONFIG_C11_RSP_CPU_RATIO_TABLE[i_smp.nom_cpu_delay], + PB_SCONFIG_C11_RSP_CPU_RATIO_START_BIT[2], + (PB_SCONFIG_C11_RSP_CPU_RATIO_END_BIT[2]- + PB_SCONFIG_C11_RSP_CPU_RATIO_START_BIT[2]+1)); + + rc_ecmd |= data.insertFromRight( + PB_SCONFIG_C11_RSP_CPU_RATIO_TABLE[i_smp.full_cpu_delay], + PB_SCONFIG_C11_RSP_CPU_RATIO_START_BIT[3], + (PB_SCONFIG_C11_RSP_CPU_RATIO_END_BIT[3]- + PB_SCONFIG_C11_RSP_CPU_RATIO_START_BIT[3]+1)); if (rc_ecmd) { @@ -704,7 +910,7 @@ fapi::ReturnCode proc_build_smp_set_sconfig_c11( // parameters: i_smp_chip => structure encapsulating SMP chip // i_smp => structure encapsulating SMP // returns: FAPI_RC_SUCCESS if register programming is successful, -// RC_PROC_BUILD_SMP_CORE_FLOOR_RATIO_ERR if cache/nest frequency +// RC_PROC_BUILD_SMP_CORE_CEILING_RATIO_ERR if cache/nest frequency // ratio is unsupported, // else error //------------------------------------------------------------------------------ @@ -740,29 +946,30 @@ fapi::ReturnCode proc_build_smp_set_sconfig_we0( data_c2i_dctr_launch = 0x3; // rc rcmd_i2c_dval_launch = 0x3; // wc - switch (i_smp.core_floor_ratio) + switch (i_smp.core_ceiling_ratio) { - // dial back if over 2x - case PROC_BUILD_SMP_CORE_FLOOR_RATIO_8_8: - if (i_smp.freq_core_floor > (2 * i_smp.freq_pb)) + // dial back if ceiling is over 2x + case PROC_BUILD_SMP_CORE_RATIO_8_8: + if (i_smp.freq_core_ceiling > (2 * i_smp.freq_pb)) { + FAPI_DBG("proc_build_smp_set_sconfig_we0: Clamping CRSP/RCMD/DATA i2c dval to safe mode based on ceiling frequency"); crsp_i2c_dval_launch = 0x0; // rc_p1 rcmd_i2c_dval_launch = 0x0; // rc_p1 data_i2c_dval_launch = 0x3; // wc } break; - case PROC_BUILD_SMP_CORE_FLOOR_RATIO_7_8: - case PROC_BUILD_SMP_CORE_FLOOR_RATIO_6_8: - case PROC_BUILD_SMP_CORE_FLOOR_RATIO_5_8: - case PROC_BUILD_SMP_CORE_FLOOR_RATIO_4_8: - case PROC_BUILD_SMP_CORE_FLOOR_RATIO_2_8: + case PROC_BUILD_SMP_CORE_RATIO_7_8: + case PROC_BUILD_SMP_CORE_RATIO_6_8: + case PROC_BUILD_SMP_CORE_RATIO_5_8: + case PROC_BUILD_SMP_CORE_RATIO_4_8: + case PROC_BUILD_SMP_CORE_RATIO_2_8: break; default: FAPI_ERR("proc_build_smp_set_sconfig_we0: Unsupported core floor frequency ratio enum (%d)", i_smp.core_floor_ratio); - const uint32_t& CORE_FLOOR_RATIO = i_smp.core_floor_ratio; + const uint32_t& CORE_CEILING_RATIO = i_smp.core_floor_ratio; FAPI_SET_HWP_ERROR(rc, - RC_PROC_BUILD_SMP_CORE_FLOOR_RATIO_ERR); + RC_PROC_BUILD_SMP_CORE_CEILING_RATIO_ERR); break; } } @@ -941,19 +1148,19 @@ fapi::ReturnCode proc_build_smp_set_sconfig_we0( PB_SCONFIG_WE0_FP_C2I_SPARE_MODE_BIT, PB_SCONFIG_WE0_FP_C2I_SPARE_MODE?1:0); - // cpu_ratio_table_full + // cpu_delay_full rc_ecmd |= data.insertFromRight( - PB_SCONFIG_WE0_CPU_RATIO_TABLE_FULL, - PB_SCONFIG_WE0_CPU_RATIO_TABLE_FULL_START_BIT, - (PB_SCONFIG_WE0_CPU_RATIO_TABLE_FULL_END_BIT- - PB_SCONFIG_WE0_CPU_RATIO_TABLE_FULL_START_BIT+1)); + PB_SCONFIG_WE0_CPU_DELAY_TABLE[i_smp.full_cpu_delay], + PB_SCONFIG_WE0_CPU_DELAY_FULL_START_BIT, + (PB_SCONFIG_WE0_CPU_DELAY_FULL_END_BIT- + PB_SCONFIG_WE0_CPU_DELAY_FULL_START_BIT+1)); - // cpu_ratio_table_half + // cpu_delay_nom rc_ecmd |= data.insertFromRight( - PB_SCONFIG_WE0_CPU_RATIO_TABLE_NOM, - PB_SCONFIG_WE0_CPU_RATIO_TABLE_NOM_START_BIT, - (PB_SCONFIG_WE0_CPU_RATIO_TABLE_NOM_END_BIT- - PB_SCONFIG_WE0_CPU_RATIO_TABLE_NOM_START_BIT+1)); + PB_SCONFIG_WE0_CPU_DELAY_TABLE[i_smp.nom_cpu_delay], + PB_SCONFIG_WE0_CPU_DELAY_NOM_START_BIT, + (PB_SCONFIG_WE0_CPU_DELAY_NOM_END_BIT- + PB_SCONFIG_WE0_CPU_DELAY_NOM_START_BIT+1)); if (rc_ecmd) { @@ -1024,22 +1231,22 @@ fapi::ReturnCode proc_build_smp_set_sconfig_we1( switch (i_smp.core_floor_ratio) { - case PROC_BUILD_SMP_CORE_FLOOR_RATIO_8_8: - case PROC_BUILD_SMP_CORE_FLOOR_RATIO_7_8: - case PROC_BUILD_SMP_CORE_FLOOR_RATIO_6_8: - case PROC_BUILD_SMP_CORE_FLOOR_RATIO_5_8: + case PROC_BUILD_SMP_CORE_RATIO_8_8: + case PROC_BUILD_SMP_CORE_RATIO_7_8: + case PROC_BUILD_SMP_CORE_RATIO_6_8: + case PROC_BUILD_SMP_CORE_RATIO_5_8: cmd_c2i_dval_launch = 0x3; // wc data_i2c_dctr_launch = 0x1; // rc_m2 data_c2i_dval_launch = 0x2; // wc_m1 attr_proc_pbiex_async_sel = fapi::ENUM_ATTR_PROC_PBIEX_ASYNC_SEL_SEL0; break; - case PROC_BUILD_SMP_CORE_FLOOR_RATIO_4_8: + case PROC_BUILD_SMP_CORE_RATIO_4_8: cmd_c2i_dval_launch = 0x3; // wc data_i2c_dctr_launch = 0x2; // rc_m1 data_c2i_dval_launch = 0x3; // wc attr_proc_pbiex_async_sel = fapi::ENUM_ATTR_PROC_PBIEX_ASYNC_SEL_SEL1; break; - case PROC_BUILD_SMP_CORE_FLOOR_RATIO_2_8: + case PROC_BUILD_SMP_CORE_RATIO_2_8: cmd_c2i_dval_launch = 0x0; // wc_p1 data_i2c_dctr_launch = 0x3; // rc data_c2i_dval_launch = 0x0; // wc_p1 @@ -1273,13 +1480,12 @@ fapi::ReturnCode proc_build_smp_set_sconfig_we5( do { -//@thi - Patch this per Joe's suggestion rc = FAPI_ATTR_GET(ATTR_CHIP_EC_FEATURE_FBC_SERIAL_SCOM_WE5_VER2, &(i_smp_chip.chip->this_chip), ver2); if (!rc.ok()) { - FAPI_ERR("Error querying Chip EC feature: ATTR_CHIP_EC_FEATURE_FBC_SERIAL_SCOM_CENT5_VER2"); + FAPI_ERR("Error querying Chip EC feature: ATTR_CHIP_EC_FEATURE_FBC_SERIAL_SCOM_WE5_VER2"); break; } @@ -1604,14 +1810,14 @@ fapi::ReturnCode proc_build_smp_set_fbc_cd( break; } - rc = proc_build_smp_set_sconfig_c10(p_iter->second); + rc = proc_build_smp_set_sconfig_c10(p_iter->second, i_smp); if (!rc.ok()) { FAPI_ERR("proc_build_smp_set_fbc_cd: Error from proc_build_smp_set_sconfig_c10"); break; } - rc = proc_build_smp_set_sconfig_c11(p_iter->second); + rc = proc_build_smp_set_sconfig_c11(p_iter->second, i_smp); if (!rc.ok()) { FAPI_ERR("proc_build_smp_set_fbc_cd: Error from proc_build_smp_set_sconfig_c11"); diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_cd.H b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_cd.H index f847b0f9b..240da6adc 100644 --- a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_cd.H +++ b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_cd.H @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_build_smp_fbc_cd.H,v 1.11 2013/09/26 18:01:39 jmcgill Exp $ +// $Id: proc_build_smp_fbc_cd.H,v 1.15 2013/11/13 01:52:36 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_build_smp_fbc_cd.H,v $ //------------------------------------------------------------------------------ // *| @@ -192,19 +192,46 @@ const bool PB_SCONFIG_C7_SLOW_GO_RATE = true; // PBH_CMD_SNOOPER (center, chain #8) field/bit definitions // -const proc_build_smp_sconfig_def PB_SCONFIG_C8_DEF = { 0x8, 37, false, { false, true, false } }; - -const uint32_t PB_SCONFIG_C8_HANG_CMD_RATE_START_BIT[PB_SCONFIG_NUM_HANG_LEVELS] = { 27, 31, 35, 39, 43, 47, 51 }; -const uint32_t PB_SCONFIG_C8_HANG_CMD_RATE_END_BIT[PB_SCONFIG_NUM_HANG_LEVELS] = { 30, 34, 38, 42, 46, 50, 54 }; -const uint32_t PB_SCONFIG_C8_CPO_JUMP_LEVEL_START_BIT = 55; -const uint32_t PB_SCONFIG_C8_CPO_JUMP_LEVEL_END_BIT = 57; -const uint32_t PB_SCONFIG_C8_CPO_RTY_LEVEL_START_BIT = 58; -const uint32_t PB_SCONFIG_C8_CPO_RTY_LEVEL_END_BIT = 63; - -const uint8_t PB_SCONFIG_C8_HANG_CMD_RATE[PB_SCONFIG_NUM_HANG_LEVELS] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; -const uint32_t PB_SCONFIG_C8_CPO_JUMP_LEVEL = 0x3; -const uint32_t PB_SCONFIG_C8_CPO_RTY_LEVEL = 0xF; - +const proc_build_smp_sconfig_def PB_SCONFIG_C8_DEF_VER1 = { 0x8, 37, false, { false, true, false } }; +const proc_build_smp_sconfig_def PB_SCONFIG_C8_DEF_VER2 = { 0x8, 39, false, { false, true, false } }; +const proc_build_smp_sconfig_def PB_SCONFIG_C8_DEF_VER3 = { 0x8, 43, false, { false, true, false } }; + +const uint32_t PB_SCONFIG_C8_HANG_CMD_RATE_START_BIT_VER1[PB_SCONFIG_NUM_HANG_LEVELS] = { 27, 31, 35, 39, 43, 47, 51 }; +const uint32_t PB_SCONFIG_C8_HANG_CMD_RATE_END_BIT_VER1[PB_SCONFIG_NUM_HANG_LEVELS] = { 30, 34, 38, 42, 46, 50, 54 }; +const uint32_t PB_SCONFIG_C8_CPO_JUMP_LEVEL_START_BIT_VER1 = 55; +const uint32_t PB_SCONFIG_C8_CPO_JUMP_LEVEL_END_BIT_VER1 = 57; +const uint32_t PB_SCONFIG_C8_CPO_RTY_LEVEL_START_BIT_VER1 = 58; +const uint32_t PB_SCONFIG_C8_CPO_RTY_LEVEL_END_BIT_VER1 = 63; + +const uint32_t PB_SCONFIG_C8_HANG_CMD_RATE_START_BIT_VER2[PB_SCONFIG_NUM_HANG_LEVELS] = { 25, 29, 33, 37, 41, 45, 49 }; +const uint32_t PB_SCONFIG_C8_HANG_CMD_RATE_END_BIT_VER2[PB_SCONFIG_NUM_HANG_LEVELS] = { 28, 32, 36, 40, 44, 48, 52 }; +const uint32_t PB_SCONFIG_C8_CPO_JUMP_LEVEL_START_BIT_VER2 = 53; +const uint32_t PB_SCONFIG_C8_CPO_JUMP_LEVEL_END_BIT_VER2 = 55; +const uint32_t PB_SCONFIG_C8_CPO_RTY_LEVEL_START_BIT_VER2 = 56; +const uint32_t PB_SCONFIG_C8_CPO_RTY_LEVEL_END_BIT_VER2 = 61; +const uint32_t PB_SCONFIG_C8_P7_SLEEP_BACKOFF_START_BIT_VER2 = 62; +const uint32_t PB_SCONFIG_C8_P7_SLEEP_BACKOFF_END_BIT_VER2 = 63; + +const uint32_t PB_SCONFIG_C8_HANG_CMD_RATE_START_BIT_VER3[PB_SCONFIG_NUM_HANG_LEVELS] = { 21, 25, 29, 33, 37, 41, 45 }; +const uint32_t PB_SCONFIG_C8_HANG_CMD_RATE_END_BIT_VER3[PB_SCONFIG_NUM_HANG_LEVELS] = { 24, 28, 32, 36, 40, 44, 48 }; +const uint32_t PB_SCONFIG_C8_CPO_JUMP_LEVEL_START_BIT_VER3 = 49; +const uint32_t PB_SCONFIG_C8_CPO_JUMP_LEVEL_END_BIT_VER3 = 51; +const uint32_t PB_SCONFIG_C8_CPO_RTY_LEVEL_START_BIT_VER3 = 52; +const uint32_t PB_SCONFIG_C8_CPO_RTY_LEVEL_END_BIT_VER3 = 57; +const uint32_t PB_SCONFIG_C8_P7_SLEEP_BACKOFF_START_BIT_VER3 = 58; +const uint32_t PB_SCONFIG_C8_P7_SLEEP_BACKOFF_END_BIT_VER3 = 59; +const uint32_t PB_SCONFIG_C8_RTY_PERCENTAGE_START_BIT_VER3 = 60; +const uint32_t PB_SCONFIG_C8_RTY_PERCENTAGE_END_BIT_VER3 = 62; +const uint32_t PB_SCONFIG_C8_INCLUDE_LPC_RTY_BIT_VER3 = 63; + +const uint8_t PB_SCONFIG_C8_HANG_CMD_RATE[PB_SCONFIG_NUM_HANG_LEVELS] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; +const uint8_t PB_SCONFIG_C8_CPO_JUMP_LEVEL = 0x3; +const uint8_t PB_SCONFIG_C8_CPO_RTY_LEVEL = 0x4; + +const uint8_t PB_SCONFIG_C8_P7_SLEEP_BACKOFF = 0x2; // backoff_1k + +const uint8_t PB_SCONFIG_C8_RTY_PERCENTAGE = 0x0; // 000 +const uint8_t PB_SCONFIG_C8_INCLUDE_LPC_RTY = 0x0; // off // // PBH_CMD_CENTRAL_ARB (center, chain #9) field/bit definitions @@ -227,11 +254,11 @@ const uint32_t PB_SCONFIG_C9_UX_SCOPE_ARB_MODE_END_BIT = 61; const uint32_t PB_SCONFIG_C9_UX_LOCAL_ARB_MODE_START_BIT = 62; const uint32_t PB_SCONFIG_C9_UX_LOCAL_ARB_MODE_END_BIT = 63; -const uint8_t PB_SCONFIG_C9_CP_STARVE_LIMIT = 0x80; -const uint8_t PB_SCONFIG_C9_GP_STARVE_LIMIT = 0x80; -const uint8_t PB_SCONFIG_C9_RGP_STARVE_LIMIT = 0x80; -const uint8_t PB_SCONFIG_C9_SP_STARVE_LIMIT = 0x80; -const uint8_t PB_SCONFIG_C9_FP_STARVE_LIMIT = 0x80; +const uint8_t PB_SCONFIG_C9_CP_STARVE_LIMIT = 0x10; +const uint8_t PB_SCONFIG_C9_GP_STARVE_LIMIT = 0x10; +const uint8_t PB_SCONFIG_C9_RGP_STARVE_LIMIT = 0x10; +const uint8_t PB_SCONFIG_C9_SP_STARVE_LIMIT = 0x10; +const uint8_t PB_SCONFIG_C9_FP_STARVE_LIMIT = 0x10; const uint8_t PB_SCONFIG_C9_UX_SCOPE_ARB_MODE = 0x0; // LFSR_ONLY const uint8_t PB_SCONFIG_C9_UX_LOCAL_ARB_MODE = 0x2; // LFSR_ON_STARVATION_ELSE_RR @@ -240,12 +267,25 @@ const uint8_t PB_SCONFIG_C9_UX_LOCAL_ARB_MODE = 0x2; // LFSR_ON_STARVATION_ELSE_ // PBH_CMD_CENTRAL_ARB (center, chain #10) field/bit definitions // -const proc_build_smp_sconfig_def PB_SCONFIG_C10_DEF = { 0xA, 20, false, { false, true, false } }; +const proc_build_smp_sconfig_def PB_SCONFIG_C10_DEF_VER1 = { 0xA, 20, false, { false, true, false } }; +const proc_build_smp_sconfig_def PB_SCONFIG_C10_DEF_VER2 = { 0xA, 23, false, { false, true, false } }; + +const uint32_t PB_SCONFIG_C10_CMD_CPU_RATIO_START_BIT_VER1[PB_SCONFIG_NUM_CPU_RATIOS] = { 59, 54, 49, 44 }; +const uint32_t PB_SCONFIG_C10_CMD_CPU_RATIO_END_BIT_VER1[PB_SCONFIG_NUM_CPU_RATIOS] = { 63, 58, 53, 48 }; -const uint32_t PB_SCONFIG_C10_CMD_CPU_RATIO_START_BIT[PB_SCONFIG_NUM_CPU_RATIOS] = { 59, 54, 49, 44 }; -const uint32_t PB_SCONFIG_C10_CMD_CPU_RATIO_END_BIT[PB_SCONFIG_NUM_CPU_RATIOS] = { 63, 58, 53, 48 }; +const uint32_t PB_SCONFIG_C10_CMD_CPU_RATIO_START_BIT_VER2[PB_SCONFIG_NUM_CPU_RATIOS] = { 56, 51, 46, 41 }; +const uint32_t PB_SCONFIG_C10_CMD_CPU_RATIO_END_BIT_VER2[PB_SCONFIG_NUM_CPU_RATIOS] = { 60, 55, 50, 45 }; +const uint32_t PB_SCONFIG_C10_DAT_X_LINK_HOLDOFF_ENABLE_BIT_VER2 = 61; +const uint32_t PB_SCONFIG_C10_DAT_A_LINK_HOLDOFF_ENABLE_BIT_VER2 = 62; +const uint32_t PB_SCONFIG_C10_DAT_LINK_HOLDOFF_MULTIPLIER_BIT_VER2 = 63; -const uint8_t PB_SCONFIG_C10_CMD_CPU_RATIO[PB_SCONFIG_NUM_CPU_RATIOS] = { 3, 7, 11, 15 }; +const uint8_t PB_SCONFIG_C10_CMD_CPU_RATIO_TABLE[PROC_BUILD_SMP_CPU_DELAY_NUM_SETPOINTS] = { 15, 14, 13, 12, 11, 11, 10, 10, 9, 9, 8, 8, 7 }; + +const uint8_t PB_SCONFIG_C10_CMD_CPU_RATIO_QUARTER = 3; +const uint8_t PB_SCONFIG_C10_CMD_CPU_RATIO_HALF = 7; +const uint8_t PB_SCONFIG_C10_DAT_X_LINK_HOLDOFF_ENABLE = 0x0; // disable +const uint8_t PB_SCONFIG_C10_DAT_A_LINK_HOLDOFF_ENABLE = 0x0; // disable +const uint8_t PB_SCONFIG_C10_DAT_LINK_HOLDOFF_MULTIPLIER = 0x0; // x2 // @@ -257,8 +297,10 @@ const proc_build_smp_sconfig_def PB_SCONFIG_C11_DEF = { 0xB, 20, false, { false, const uint32_t PB_SCONFIG_C11_RSP_CPU_RATIO_START_BIT[PB_SCONFIG_NUM_CPU_RATIOS] = { 59, 54, 49, 44 }; const uint32_t PB_SCONFIG_C11_RSP_CPU_RATIO_END_BIT[PB_SCONFIG_NUM_CPU_RATIOS] = { 63, 58, 53, 48 }; -const uint8_t PB_SCONFIG_C11_RSP_CPU_RATIO[PB_SCONFIG_NUM_CPU_RATIOS] = { 4, 8, 12, 16 }; +const uint8_t PB_SCONFIG_C11_RSP_CPU_RATIO_TABLE[PROC_BUILD_SMP_CPU_DELAY_NUM_SETPOINTS] = { 16, 15, 14, 13, 12, 12, 11, 11, 10, 10, 9, 9, 8 }; +const uint8_t PB_SCONFIG_C11_RSP_CPU_RATIO_QUARTER = 4; +const uint8_t PB_SCONFIG_C11_RSP_CPU_RATIO_HALF = 8; // // PBH_PBIEX_EH (east/west, chain #0) field/bit definitions @@ -306,12 +348,12 @@ const uint32_t PB_SCONFIG_WE0_FP_I2C_HSHAKE_BIT = 50; const uint32_t PB_SCONFIG_WE0_FP_I2C_SPARE_MODE_BIT = 51; const uint32_t PB_SCONFIG_WE0_FP_C2I_DONE_LAUNCH_BIT = 52; const uint32_t PB_SCONFIG_WE0_FP_C2I_SPARE_MODE_BIT = 53; -const uint32_t PB_SCONFIG_WE0_CPU_RATIO_TABLE_FULL_START_BIT = 54; -const uint32_t PB_SCONFIG_WE0_CPU_RATIO_TABLE_FULL_END_BIT = 58; -const uint32_t PB_SCONFIG_WE0_CPU_RATIO_TABLE_NOM_START_BIT = 59; -const uint32_t PB_SCONFIG_WE0_CPU_RATIO_TABLE_NOM_END_BIT = 63; +const uint32_t PB_SCONFIG_WE0_CPU_DELAY_FULL_START_BIT = 54; +const uint32_t PB_SCONFIG_WE0_CPU_DELAY_FULL_END_BIT = 58; +const uint32_t PB_SCONFIG_WE0_CPU_DELAY_NOM_START_BIT = 59; +const uint32_t PB_SCONFIG_WE0_CPU_DELAY_NOM_END_BIT = 63; -const uint8_t PB_SCONFIG_WE0_CMD_C2I_LATE_RD_MODE = true; // on +const bool PB_SCONFIG_WE0_CMD_C2I_LATE_RD_MODE = true; // on const uint8_t PB_SCONFIG_WE0_CMD_C2I_DELAY_SP_RD = 0x0; // rc_p1 const bool PB_SCONFIG_WE0_CMD_C2I_SPARE_MODE = false; // spare const uint8_t PB_SCONFIG_WE0_PRSP_C2I_DONE_LAUNCH = 0x0; // rc_p1 @@ -335,8 +377,8 @@ const uint8_t PB_SCONFIG_WE0_FP_I2C_HSHAKE = false; // off const bool PB_SCONFIG_WE0_FP_I2C_SPARE_MODE = false; // spare const uint8_t PB_SCONFIG_WE0_FP_C2I_DONE_LAUNCH = 0x0; // rc_p1 const bool PB_SCONFIG_WE0_FP_C2I_SPARE_MODE = false; // spare -const uint32_t PB_SCONFIG_WE0_CPU_RATIO_TABLE_FULL = 0x0E; // 14 -const uint32_t PB_SCONFIG_WE0_CPU_RATIO_TABLE_NOM = 0x12; // 18 + +const uint8_t PB_SCONFIG_WE0_CPU_DELAY_TABLE[PROC_BUILD_SMP_CPU_DELAY_NUM_SETPOINTS] = { 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26 }; // @@ -500,6 +542,8 @@ extern "C" // registers are equivalent, // RC_PROC_BUILD_SMP_CORE_FLOOR_RATIO_ERR if cache/nest frequency // ratio is unsupported, +// RC_PROC_BUILD_SMP_CORE_CEILING_RATIO_ERR if cache/nest frequency +// ratio is unsupported, // else error //------------------------------------------------------------------------------ fapi::ReturnCode proc_build_smp_set_fbc_cd( diff --git a/src/usr/hwpf/hwp/freq_attributes.xml b/src/usr/hwpf/hwp/freq_attributes.xml index 973f03a23..588a02434 100644 --- a/src/usr/hwpf/hwp/freq_attributes.xml +++ b/src/usr/hwpf/hwp/freq_attributes.xml @@ -20,7 +20,7 @@ <!-- Origin: 30 --> <!-- --> <!-- IBM_PROLOG_END_TAG --> -<!-- $Id: freq_attributes.xml,v 1.7 2013/08/09 15:14:59 mjjones Exp $ --> +<!-- $Id: freq_attributes.xml,v 1.8 2013/10/16 20:42:30 jmcgill Exp $ --> <!-- XML file specifying HWPF attributes. These are frequency attributes. @@ -81,6 +81,18 @@ </attribute> <!-- ********************************************************************* --> <attribute> + <id>ATTR_FREQ_CORE_NOMINAL</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description> + The nominal core frequency in MHz. + This is the same for all cores in the system. + Provided by the Machine Readable Workbook. + </description> + <valueType>uint32</valueType> + <platInit/> + </attribute> + <!-- ********************************************************************* --> + <attribute> <id>ATTR_FREQ_PB</id> <targetType>TARGET_TYPE_SYSTEM</targetType> <description> |
