diff options
Diffstat (limited to 'src/usr/hwpf')
6 files changed, 175 insertions, 53 deletions
diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pfet_init.C b/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pfet_init.C index 541ac824d..20ce0452d 100644 --- a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pfet_init.C +++ b/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pfet_init.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: p8_pfet_init.C,v 1.9 2013/08/02 19:05:49 stillgs Exp $ +// $Id: p8_pfet_init.C,v 1.10 2013/10/11 23:01:57 stillgs Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pfet_init.C,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 @@ -237,13 +237,12 @@ pfet_init(const Target& i_target, uint32_t i_mode) FAPI_INF("Executing pfet_config..."); - // Harcoded defaults that don't come via attribute - // Vret (not supported) = "off" (stage 0 = 0xB) for bits 0:3 - // Voff = "off" (stage 01 = 0xB) for bits 4:7 - // \todo The scan0 values are zeros which indicate that the - // power won't go off. Double check the setting below!!! - core_vret_voff_value = 0xBB; - eco_vret_voff_value = 0xBB; + // VRET settings need to be "ON" as PFET VRET is not supported + // The iVRM hardware will tell the PFET controller to go 'OFF" + // in its support of Vret. These values do not pertain in that + // case. + core_vret_voff_value = 0x00; + eco_vret_voff_value = 0x00; // ****************************************************************** // Get Attributes for pFET Delay diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_set_pore_bar.C b/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_set_pore_bar.C index 0c78cf414..f36ca2fcf 100644 --- a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_set_pore_bar.C +++ b/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_set_pore_bar.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: p8_set_pore_bar.C,v 1.6 2013/09/04 14:53:16 dcrowell Exp $ +// $Id: p8_set_pore_bar.C,v 1.7 2013/10/04 19:30:36 stillgs Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_set_pore_bar.C,v $ //------------------------------------------------------------------------------- // *! (C) Copyright International Business Machines Corp. 2011 @@ -171,6 +171,9 @@ p8_set_pore_bar( const fapi::Target& i_target, const uint32_t pba_slave = PBA_SLAVE2; const uint64_t slw_pba_cmd_scope = 0x2; // Set to system + + SbeXipItem slw_control_vector_info; + uint32_t slw_control_vector_offset; // ----------------------------------------------------------------- @@ -186,6 +189,10 @@ p8_set_pore_bar( const fapi::Target& i_target, if(i_mem_bar != 0) { FAPI_ERR("SLW Size is 0 but BAR is non-zero: 0x%16llx", i_mem_bar ); + const fapi::Target & CHIP = i_target; + const uint64_t & IMAGEADDR = (uint64_t)i_image; + const uint32_t & MEMSIZE = i_mem_size; + const uint64_t & MEMBAR = i_mem_bar; FAPI_SET_HWP_ERROR(rc, RC_PROCPM_POREBAR_SIZE0_ERROR); break; } @@ -217,11 +224,40 @@ p8_set_pore_bar( const fapi::Target& i_target, if (l_ecmdRc) { FAPI_ERR("Get XIP of slw_branch_table failed. rc = %x\n", l_ecmdRc); + const fapi::Target & CHIP = i_target; + const uint64_t & IMAGEADDR = (uint64_t)i_image; + const uint32_t & XIPRC = l_ecmdRc; + const uint64_t & BRANCHTABLEADDRESS = slw_branch_table_address; FAPI_SET_HWP_ERROR(rc, RC_PROCPM_POREBAR_IMAGE_BRANCH_VALUE_ERROR); break; } FAPI_DBG("slw_branch_table_address: %16llX", slw_branch_table_address); + // Get the SLW Control Vector offset from the image + l_ecmdRc = sbe_xip_find((void*) i_image, + "slw_control_vector", + &slw_control_vector_info); + if (l_ecmdRc) + { + FAPI_ERR("XIP Find of slw_control_vector failed. rc = %x\n", l_ecmdRc); + const fapi::Target & CHIP = i_target; + const uint64_t & IMAGEADDR = (uint64_t)i_image; + const uint32_t & XIPRC = l_ecmdRc; + const uint64_t & SLWCONTROLVECTOR = (uint64_t)slw_control_vector_info.iv_address; + FAPI_SET_HWP_ERROR(rc, RC_PROCPM_POREBAR_IMAGE_SLW_CONTROL_VECTOR_ERROR); + break; + } + + slw_control_vector_offset = slw_control_vector_info.iv_address; + FAPI_DBG("slw_control_vector offset: %16llX", (uint64_t)slw_control_vector_info.iv_address); + + + SETATTR(rc, + ATTR_PM_SLW_CONTROL_VECTOR_OFFSET, + "ATTR_PM_SLW_CONTROL_VECTOR_OFFSET", + NULL, + slw_control_vector_offset); + // Initialize the ecmdDataBuffer l_ecmdRc |= data.clear(); l_ecmdRc |= data.setBitLength(64); @@ -232,7 +268,6 @@ p8_set_pore_bar( const fapi::Target& i_target, break; } - // Setup the the table base address register // // Table Base Address Register layout @@ -362,6 +397,9 @@ p8_set_pore_bar( const fapi::Target& i_target, if (region_masked_address != 0 ) { FAPI_ERR("SLW BAR address is not 1MB aligned: 0x%16llx", i_mem_bar ); + const fapi::Target & CHIP = i_target; + const uint64_t & MEMBAR = i_mem_bar; + const uint64_t & REGIONMASKEDADDR = region_masked_address; FAPI_SET_HWP_ERROR(rc, RC_PROCPM_POREBAR_PBABAR_ERROR); break; } @@ -416,7 +454,11 @@ p8_set_pore_bar( const fapi::Target& i_target, if (l_ecmdRc) { FAPI_ERR("Get of XIP Image size failed"); - FAPI_SET_HWP_ERROR(rc, RC_PROCPM_POREBAR_IMAGE_SIZE_ERROR); + const fapi::Target & CHIP = i_target; + const uint64_t & IMAGEADDR = (uint64_t)i_image; + const uint32_t & XIPRC = l_ecmdRc; + const uint64_t & IMAGESIZE = image_size; + FAPI_SET_HWP_ERROR(rc, RC_PROCPM_POREBAR_XIP_IMAGE_SIZE_ERROR); break; } @@ -434,6 +476,8 @@ p8_set_pore_bar( const fapi::Target& i_target, else { FAPI_ERR("Invalid image location passed %x ", i_mem_type); + const fapi::Target & CHIP = i_target; + const uint64_t & MEMLOC = i_mem_type; FAPI_SET_HWP_ERROR(rc, RC_PROCPM_POREBAR_LOC_ERROR); break; } @@ -600,6 +644,11 @@ bar_pba_slave_reset(const fapi::Target& i_target, uint32_t id) poll_count++; if (poll_count == PBA_SLAVE_RESET_TIMEOUT) { + const fapi::Target & CHIP = i_target; + const uint32_t & POLLCOUNT = poll_count; + const uint32_t & TIMEOUTVALUE = PBA_SLAVE_RESET_TIMEOUT; + const uint64_t & PSR = psr.value; + const uint32_t & SLVID = id; FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PBA_SLVRST_TIMED_OUT); break; } diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_set_pore_bar_errors.xml b/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_set_pore_bar_errors.xml index 4efeb55bc..35131e9ee 100644 --- a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_set_pore_bar_errors.xml +++ b/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_set_pore_bar_errors.xml @@ -20,38 +20,96 @@ <!-- Origin: 30 --> <!-- --> <!-- IBM_PROLOG_END_TAG --> -<!-- $Id: p8_set_pore_bar_errors.xml,v 1.3 2013/05/23 18:44:35 stillgs Exp $ --> +<!-- $Id: p8_set_pore_bar_errors.xml,v 1.4 2013/10/04 19:28:12 stillgs Exp $ --> <!-- Error definitions for p8_set_pore_bar procedure --> <hwpErrors> <!-- *********************************************************************** --> <hwpError> <rc>RC_PROCPM_POREBAR_IMAGE_BRANCH_VALUE_ERROR</rc> <description>XIP access of branch table failed in p8_set_pore_bar</description> + <ffdc>CHIP</ffdc> + <ffdc>IMAGEADDR</ffdc> + <ffdc>XIPRC</ffdc> + <ffdc>BRANCHTABLEADDRESS</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + </hwpError> <!-- *********************************************************************** --> <hwpError> <rc>RC_PROCPM_POREBAR_LOC_ERROR</rc> <description>Invalid image location passed to p8_set_pore_bar</description> + <ffdc>CHIP</ffdc> + <ffdc>MEMLOC</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> </hwpError> <!-- *********************************************************************** --> <hwpError> <rc>RC_PROCPM_POREBAR_PBABAR_ERROR</rc> <description>PBA BAR image location passed to p8_set_pore_bar</description> + <ffdc>CHIP</ffdc> + <ffdc>MEMBAR</ffdc> + <ffdc>REGIONMASKEDADDR</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> </hwpError> <!-- *********************************************************************** --> <hwpError> <rc>RC_PROCPM_PBA_SLVRST_TIMED_OUT</rc> <description>PBA Slave Reset timed out in p8_set_pore_bar</description> + <ffdc>POLLCOUNT</ffdc> + <ffdc>TIMEOUTVALUE</ffdc> + <ffdc>PSR</ffdc> + <ffdc>SLVID</ffdc> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROCPM_POREBAR_XIP_IMAGE_SIZE_ERROR</rc> + <description>Get of XIP Image size failed in p8_set_pore_bar</description> + <ffdc>CHIP</ffdc> + <ffdc>IMAGEADDR</ffdc> + <ffdc>XIPRC</ffdc> + <ffdc>IMAGESIZE</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> </hwpError> <!-- *********************************************************************** --> <hwpError> <rc>RC_PROCPM_POREBAR_IMAGE_SIZE_ERROR</rc> <description>Image address plus image size overflows PBA region in p8_set_pore_bar</description> + <ffdc>IMAGEADDR</ffdc> + <ffdc>XIPRC</ffdc> + <ffdc>BRANCHTABLEADDRESS</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> </hwpError> <!-- *********************************************************************** --> <hwpError> <rc>RC_PROCPM_POREBAR_SIZE0_ERROR</rc> <description>An image size of 0 was specified to p8_set_pore_bar but the BAR was not 0</description> + <ffdc>CHIP</ffdc> + <ffdc>IMAGEADDR</ffdc> + <ffdc>MEMSIZE</ffdc> + <ffdc>MEMBAR</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> </hwpError> <!-- *********************************************************************** --> <hwpError> @@ -61,6 +119,19 @@ <!-- *********************************************************************** --> <hwpError> <rc>RC_PROCPM_POREBAR_IMAGE_ADDR_ERROR</rc> - <description>Image address not in PBA BAR region in p8_set_pore_bar</description> + <description>Find of XIP of slw_control_vector failed in p8_set_pore_bar</description> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROCPM_POREBAR_IMAGE_SLW_CONTROL_VECTOR_ERROR</rc> + <description>XIP Find of slw_control_vector failed in p8_set_pore_bar</description> + <ffdc>CHIP</ffdc> + <ffdc>IMAGEADDR</ffdc> + <ffdc>XIPRC</ffdc> + <ffdc>SLWCONTROLVECTOR</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> </hwpError> </hwpErrors> diff --git a/src/usr/hwpf/hwp/getPllRingAttr.C b/src/usr/hwpf/hwp/getPllRingAttr.C index eae618be4..ebb239f0a 100755 --- a/src/usr/hwpf/hwp/getPllRingAttr.C +++ b/src/usr/hwpf/hwp/getPllRingAttr.C @@ -230,31 +230,31 @@ extern "C" case fapi::ATTR_MEMB_TP_BNDY_PLL_FLUSH: case fapi::ATTR_MEMB_TP_BNDY_PLL_LENGTH: case fapi::ATTR_MEMB_TP_BNDY_PLL_FOR_DCCAL_DATA: -// case fapi::ATTR_MEMB_TP_BNDY_PLL_FOR_DCCAL_FLUSH: +// case fapi::ATTR_MEMB_TP_BNDY_PLL_FOR_DCCAL_FLUSH: case fapi::ATTR_MEMB_TP_BNDY_PLL_FOR_DCCAL_LENGTH: case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA: -// case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_FLUSH: +// case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_FLUSH: case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_LENGTH: case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA: -// case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_FLUSH: +// case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_FLUSH: case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_LENGTH: case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA: -// case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_FLUSH: +// case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_FLUSH: case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_LENGTH: case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA: -// case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_FLUSH: +// case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_FLUSH: case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_LENGTH: case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA: -// case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_FLUSH: +// case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_FLUSH: case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_LENGTH: case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA: -// case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_FLUSH: +// case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_FLUSH: case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_LENGTH: case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA: -// case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_FLUSH: +// case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_FLUSH: case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_LENGTH: case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA: -// case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_FLUSH: +// case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_FLUSH: case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_LENGTH: // Set entry size l_numKeys = 2; @@ -328,6 +328,7 @@ extern "C" } break; case fapi::ATTR_PROC_AB_BNDY_PLL_FOR_DCCAL_DATA: + case fapi::ATTR_PROC_AB_BNDY_PLL_FOR_DCCAL_LENGTH: // Is chip type Murano or Venice if (l_chipType == ENUM_ATTR_NAME_MURANO) { // Establish default array to S1 EC 10 array @@ -490,7 +491,7 @@ extern "C" } break; case fapi::ATTR_MEMB_TP_BNDY_PLL_FOR_DCCAL_DATA: -// case fapi::ATTR_MEMB_TP_BNDY_PLL_FOR_DCCAL_FLUSH: +// case fapi::ATTR_MEMB_TP_BNDY_PLL_FOR_DCCAL_FLUSH: case fapi::ATTR_MEMB_TP_BNDY_PLL_FOR_DCCAL_LENGTH: // Establish default array to Centaur EC 10 array l_pllArrayPtr = reinterpret_cast<PLL_RING_ATTR_WITH_4_KEYS *>(&Centaur_10_ATTR_MEMB_TP_BNDY_PLL_FOR_DCCAL_DATA_array); @@ -503,7 +504,7 @@ extern "C" } break; case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA: -// case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_FLUSH: +// case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_FLUSH: case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_LENGTH: // Establish default array to Centaur EC 10 array l_pllArrayPtr = reinterpret_cast<PLL_RING_ATTR_WITH_4_KEYS *>(&Centaur_10_ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA_array); @@ -516,7 +517,7 @@ extern "C" } break; case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA: -// case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_FLUSH: +// case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_FLUSH: case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_LENGTH: // Establish default array to Centaur EC 10 array l_pllArrayPtr = reinterpret_cast<PLL_RING_ATTR_WITH_4_KEYS *>(&Centaur_10_ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA_array); @@ -529,7 +530,7 @@ extern "C" } break; case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA: -// case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_FLUSH: +// case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_FLUSH: case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_LENGTH: // Establish default array to Centaur EC 10 array l_pllArrayPtr = reinterpret_cast<PLL_RING_ATTR_WITH_4_KEYS *>(&Centaur_10_ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA_array); @@ -542,7 +543,7 @@ extern "C" } break; case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA: -// case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_FLUSH: +// case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_FLUSH: case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_LENGTH: // Establish default array to Centaur EC 10 array l_pllArrayPtr = reinterpret_cast<PLL_RING_ATTR_WITH_4_KEYS *>(&Centaur_10_ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA_array); @@ -555,7 +556,7 @@ extern "C" } break; case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA: -// case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_FLUSH: +// case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_FLUSH: case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_LENGTH: // Establish default array to Centaur EC 10 array l_pllArrayPtr = reinterpret_cast<PLL_RING_ATTR_WITH_4_KEYS *>(&Centaur_10_ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA_array); @@ -568,7 +569,7 @@ extern "C" } break; case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA: -// case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_FLUSH: +// case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_FLUSH: case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_LENGTH: // Establish default array to Centaur EC 10 array l_pllArrayPtr = reinterpret_cast<PLL_RING_ATTR_WITH_4_KEYS *>(&Centaur_10_ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA_array); @@ -581,7 +582,7 @@ extern "C" } break; case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA: -// case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_FLUSH: +// case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_FLUSH: case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_LENGTH: // Establish default array to Centaur EC 10 array l_pllArrayPtr = reinterpret_cast<PLL_RING_ATTR_WITH_4_KEYS *>(&Centaur_10_ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA_array); @@ -596,7 +597,7 @@ extern "C" } break; case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA: -// case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_FLUSH: +// case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_FLUSH: case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_LENGTH: // Establish default array to Centaur EC 10 array l_pllArrayPtr = reinterpret_cast<PLL_RING_ATTR_WITH_4_KEYS *>(&Centaur_10_ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA_array); @@ -675,9 +676,9 @@ extern "C" } break; case fapi::ATTR_PROC_AB_BNDY_PLL_FLUSH: -// case fapi::ATTR_PROC_AB_BNDY_PLL_FOR_DCCAL_FLUSH: +// case fapi::ATTR_PROC_AB_BNDY_PLL_FOR_DCCAL_FLUSH: case fapi::ATTR_PROC_PB_BNDY_DMIPLL_FLUSH: -// case fapi::ATTR_PROC_PB_BNDY_DMIPLL_FOR_DCCAL_FLUSH: +// case fapi::ATTR_PROC_PB_BNDY_DMIPLL_FOR_DCCAL_FLUSH: case fapi::ATTR_PROC_PCI_BNDY_PLL_FLUSH: // Copy flush data for (uint16_t i = 0; @@ -736,15 +737,15 @@ extern "C" } break; case fapi::ATTR_MEMB_TP_BNDY_PLL_FLUSH: -// case fapi::ATTR_MEMB_TP_BNDY_PLL_FOR_DCCAL_FLUSH: -// case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_FLUSH: -// case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_FLUSH: -// case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_FLUSH: -// case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_FLUSH: -// case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_FLUSH: -// case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_FLUSH: -// case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_FLUSH: -// case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_FLUSH: +// case fapi::ATTR_MEMB_TP_BNDY_PLL_FOR_DCCAL_FLUSH: +// case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_FLUSH: +// case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_FLUSH: +// case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_FLUSH: +// case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_FLUSH: +// case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_FLUSH: +// case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_FLUSH: +// case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_FLUSH: +// case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_FLUSH: // Copy flush data for (uint16_t i = 0; i < (l_2KeyPllArrayPtr->l_ATTR_PLL_RING_BYTE_LENGTH); diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_oha_firinit.C b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_oha_firinit.C index e73fda5fe..5e1f278c3 100644 --- a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_oha_firinit.C +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_oha_firinit.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: p8_pm_oha_firinit.C,v 1.12 2013/05/24 13:07:01 pchatnah Exp $ +// $Id: p8_pm_oha_firinit.C,v 1.13 2013/09/25 22:35:00 stillgs Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pm_oha_firinit.C,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 @@ -105,16 +105,7 @@ p8_pm_oha_firinit(const fapi::Target &i_target , uint32_t mode ) std::vector<Target>::iterator itr; - enum OHA_FIRS - { - OHA21_PPT_TIMEOUT_ERR =0 , - NOT_CPM_BIT_SYNCED =1 , - AISS_HANG_CONDITION =2 , - TC_TC_THERM_TRIP0 =3 , - TC_TC_THERM_TRIP1 =4 , - PCB_ERR_TO_FIR =5 - }; FAPI_INF("Executing proc_pm_oha_firinit ..."); diff --git a/src/usr/hwpf/hwp/runtime_attributes/pm_hwp_attributes.xml b/src/usr/hwpf/hwp/runtime_attributes/pm_hwp_attributes.xml index 1e02c4f46..cb849dd43 100644 --- a/src/usr/hwpf/hwp/runtime_attributes/pm_hwp_attributes.xml +++ b/src/usr/hwpf/hwp/runtime_attributes/pm_hwp_attributes.xml @@ -20,7 +20,7 @@ <!-- Origin: 30 --> <!-- --> <!-- IBM_PROLOG_END_TAG --> -<!-- $Id: pm_hwp_attributes.xml,v 1.8 2013/07/18 22:03:52 stillgs Exp $ --> +<!-- $Id: pm_hwp_attributes.xml,v 1.9 2013/09/13 21:07:46 stillgs Exp $ --> <!-- XML file specifying Power Management HWPF attributes. These attributes are initialized to zero by the platform and set to a @@ -785,5 +785,16 @@ Divider for the 1us PBAX hang pulse. A hang is detected after two divided hang <writeable/> </attribute> +<attribute> + <id>ATTR_PM_SLW_CONTROL_VECTOR_OFFSET</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description> + Stores the offset in SLW image of this control vector for later use by scripts to control error injection. + This value is added to the contents of PBABAR2 for given chip to calculated the memory address for this vector per chip. + </description> + <valueType>uint32</valueType> + <writeable/> +</attribute> + </attributes> |
