diff options
Diffstat (limited to 'src/usr/hwpf/hwp/mvpd_accessors/getMBvpdAttrData.C')
| -rw-r--r-- | src/usr/hwpf/hwp/mvpd_accessors/getMBvpdAttrData.C | 167 |
1 files changed, 167 insertions, 0 deletions
diff --git a/src/usr/hwpf/hwp/mvpd_accessors/getMBvpdAttrData.C b/src/usr/hwpf/hwp/mvpd_accessors/getMBvpdAttrData.C new file mode 100644 index 000000000..6aa2b1c39 --- /dev/null +++ b/src/usr/hwpf/hwp/mvpd_accessors/getMBvpdAttrData.C @@ -0,0 +1,167 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/mvpd_accessors/getMBvpdAttrData.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2013,2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +// $Id: getMBvpdAttrData.C,v 1.1 2014/12/11 13:39:02 whs Exp $ +/** + * @file getMBvpdAttrData.C + * + * @brief get Attribute Data from MBvpd + * + */ +#include <stdint.h> + +// fapi support +#include <fapi.H> +#include <fapiUtil.H> +#include <getMBvpdAttr.H> + +using namespace fapi; +using namespace getAttrData; + +namespace fapi +{ +namespace getAttrData +{ + +// ---------------------------------------------------------------------------- +// Attribute definition table +// ---------------------------------------------------------------------------- + +// Attribute defintions +const MBvpdAttrDef g_MBVPD_ATTR_DEF_array [] = +{ + +// Planar ISDIMM changes in V61 (ascii 11) and V63 (ascii 13) + {ATTR_VPD_DIMM_RCD_IBT,ISDIMM,V13,MBVPD_KEYWORD_MT,34,UINT32_BY2_BY2|UINT8_DATA,0}, + {ATTR_VPD_DIMM_RCD_IBT,ISDIMM,VBASE,MBVPD_KEYWORD_MT,34,UINT32_BY2_BY2|DEFAULT_VALUE,0x64}, + {ATTR_VPD_DIMM_RCD_IBT,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MT,34,UINT32_BY2_BY2|DEFAULT_VALUE,0}, + + {ATTR_VPD_DIMM_RCD_OUTPUT_TIMING,ISDIMM,V13,MBVPD_KEYWORD_MT,36,UINT8_BY2_BY2,0}, + {ATTR_VPD_DIMM_RCD_OUTPUT_TIMING,ISDIMM,VBASE,MBVPD_KEYWORD_MT,35,UINT8_BY2_BY2|DEFAULT_VALUE,1}, + {ATTR_VPD_DIMM_RCD_OUTPUT_TIMING,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MT,36,UINT8_BY2_BY2|DEFAULT_VALUE,0}, + + {ATTR_VPD_DRAM_WR_VREF,ISDIMM,V13,MBVPD_KEYWORD_MT,38,UINT32_BY2|UINT8_DATA|XLATE_RD_VREF,0}, + +// CDIMM changes in V60 (ascii 10) + {ATTR_VPD_TSYS_ADR,CDIMM,V10,MBVPD_KEYWORD_MR,49,UINT8_BY2|PORT00,0}, + {ATTR_VPD_TSYS_ADR,CDIMM,VBASE,MBVPD_KEYWORD_MR,51,UINT8_BY2|PORT00,0}, + + {ATTR_VPD_TSYS_DP18,CDIMM,V10,MBVPD_KEYWORD_MR,49,UINT8_BY2|PORT11,0}, + {ATTR_VPD_TSYS_DP18,CDIMM,VBASE,MBVPD_KEYWORD_MR,51,UINT8_BY2|PORT11,0}, + + {ATTR_VPD_RLO,CDIMM,V10,MBVPD_KEYWORD_MT,60,UINT8_BY2|LOW_NIBBLE,0}, + {ATTR_VPD_RLO,CDIMM,VBASE,MBVPD_KEYWORD_MR,49,UINT8_BY2|LOW_NIBBLE,0}, + + {ATTR_VPD_WLO,CDIMM,V10,MBVPD_KEYWORD_MT,60,UINT8_BY2|HIGH_NIBBLE,0}, + {ATTR_VPD_WLO,CDIMM,VBASE,MBVPD_KEYWORD_MR,49,UINT8_BY2|HIGH_NIBBLE,0}, + + {ATTR_VPD_GPO,CDIMM,V10,MBVPD_KEYWORD_MT,61,UINT8_BY2,0}, + {ATTR_VPD_GPO,CDIMM,VBASE,MBVPD_KEYWORD_MR,50,UINT8_BY2,0}, + +// Base Term Data definitions to be used if no other version exceptions + {ATTR_VPD_DRAM_RON,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MT,0,UINT8_BY2_BY2|XLATE_DRAM_RON,0}, + {ATTR_VPD_DRAM_RTT_NOM,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MT,2,UINT8_BY2_BY2_BY4|XLATE_RTT_NOM,0}, + {ATTR_VPD_DRAM_RTT_WR,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MT,10,UINT8_BY2_BY2_BY4|XLATE_RTT_WR,0}, + {ATTR_VPD_ODT_RD,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MT,18,UINT8_BY2_BY2_BY4,0}, + {ATTR_VPD_ODT_WR,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MT,26,UINT8_BY2_BY2_BY4,0}, + {ATTR_VPD_CEN_RD_VREF,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MT,37,UINT32_BY2|UINT8_DATA|XLATE_RD_VREF,0}, + {ATTR_VPD_DRAM_WR_VREF,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MT,38,UINT32_BY2|XLATE_WR_VREF,0}, + {ATTR_VPD_DRAM_WRDDR4_VREF,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MT,42,UINT8_BY2,0}, + {ATTR_VPD_CEN_RCV_IMP_DQ_DQS,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MT,43,UINT8_BY2,0}, + {ATTR_VPD_CEN_DRV_IMP_DQ_DQS,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MT,44,UINT8_BY2,0}, + {ATTR_VPD_CEN_DRV_IMP_CNTL,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MT,45,UINT8_BY2,0}, + {ATTR_VPD_CEN_DRV_IMP_ADDR,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MT,46,UINT8_BY2,0}, + {ATTR_VPD_CEN_DRV_IMP_CLK,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MT,47,UINT8_BY2,0}, + {ATTR_VPD_CEN_DRV_IMP_SPCKE,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MT,48,UINT8_BY2,0}, + {ATTR_VPD_CEN_SLEW_RATE_DQ_DQS,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MT,49,UINT8_BY2|XLATE_SLEW,0}, + {ATTR_VPD_CEN_SLEW_RATE_CNTL,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MT,50,UINT8_BY2|XLATE_SLEW,0}, + {ATTR_VPD_CEN_SLEW_RATE_ADDR,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MT,51,UINT8_BY2|XLATE_SLEW,0}, + {ATTR_VPD_CEN_SLEW_RATE_CLK,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MT,52,UINT8_BY2|XLATE_SLEW,0}, + {ATTR_VPD_CEN_SLEW_RATE_SPCKE,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MT,53,UINT8_BY2|XLATE_SLEW,0}, + {ATTR_VPD_CKE_PRI_MAP,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MT,54,UINT32_BY2|UINT16_DATA,0}, + {ATTR_VPD_CKE_PWR_MAP,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MT,56,UINT64|MERGE,0}, + {ATTR_VPD_RLO,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MT,60,UINT8_BY2|LOW_NIBBLE,0}, + {ATTR_VPD_WLO,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MT,60,UINT8_BY2|HIGH_NIBBLE,0}, + {ATTR_VPD_GPO,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MT,61,UINT8_BY2,0}, + +// Base Phase Rotator definitions to be used if no other version exceptions + {ATTR_VPD_CEN_PHASE_ROT_M0_CLK_P0,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,0,UINT8_BY2,0}, + {ATTR_VPD_CEN_PHASE_ROT_M0_CLK_P1,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,1,UINT8_BY2,0}, + {ATTR_VPD_CEN_PHASE_ROT_M1_CLK_P0,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,2,UINT8_BY2,0}, + {ATTR_VPD_CEN_PHASE_ROT_M1_CLK_P1,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,3,UINT8_BY2,0}, + {ATTR_VPD_CEN_PHASE_ROT_M_CMD_A0,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,4,UINT8_BY2,0}, + {ATTR_VPD_CEN_PHASE_ROT_M_CMD_A1,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,5,UINT8_BY2,0}, + {ATTR_VPD_CEN_PHASE_ROT_M_CMD_A2,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,6,UINT8_BY2,0}, + {ATTR_VPD_CEN_PHASE_ROT_M_CMD_A3,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,7,UINT8_BY2,0}, + {ATTR_VPD_CEN_PHASE_ROT_M_CMD_A4,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,8,UINT8_BY2,0}, + {ATTR_VPD_CEN_PHASE_ROT_M_CMD_A5,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,9,UINT8_BY2,0}, + {ATTR_VPD_CEN_PHASE_ROT_M_CMD_A6,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,10,UINT8_BY2,0}, + {ATTR_VPD_CEN_PHASE_ROT_M_CMD_A7,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,11,UINT8_BY2,0}, + {ATTR_VPD_CEN_PHASE_ROT_M_CMD_A8,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,12,UINT8_BY2,0}, + {ATTR_VPD_CEN_PHASE_ROT_M_CMD_A9,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,13,UINT8_BY2,0}, + {ATTR_VPD_CEN_PHASE_ROT_M_CMD_A10,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,14,UINT8_BY2,0}, + {ATTR_VPD_CEN_PHASE_ROT_M_CMD_A11,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,15,UINT8_BY2,0}, + {ATTR_VPD_CEN_PHASE_ROT_M_CMD_A12,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,16,UINT8_BY2,0}, + {ATTR_VPD_CEN_PHASE_ROT_M_CMD_A13,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,17,UINT8_BY2,0}, + {ATTR_VPD_CEN_PHASE_ROT_M_CMD_A14,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,18,UINT8_BY2,0}, + {ATTR_VPD_CEN_PHASE_ROT_M_CMD_A15,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,19,UINT8_BY2,0}, + {ATTR_VPD_CEN_PHASE_ROT_M_CMD_BA0,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,20,UINT8_BY2,0}, + {ATTR_VPD_CEN_PHASE_ROT_M_CMD_BA1,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,21,UINT8_BY2,0}, + {ATTR_VPD_CEN_PHASE_ROT_M_CMD_BA2,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,22,UINT8_BY2,0}, + {ATTR_VPD_CEN_PHASE_ROT_M_CMD_CASN,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,23,UINT8_BY2,0}, + {ATTR_VPD_CEN_PHASE_ROT_M_CMD_RASN,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,24,UINT8_BY2,0}, + {ATTR_VPD_CEN_PHASE_ROT_M_CMD_WEN,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,25,UINT8_BY2,0}, + {ATTR_VPD_CEN_PHASE_ROT_M_PAR,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,26,UINT8_BY2,0}, + {ATTR_VPD_CEN_PHASE_ROT_M_ACTN,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,27,UINT8_BY2,0}, + {ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CKE0,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,28,UINT8_BY2,0}, + {ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CKE1,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,29,UINT8_BY2,0}, + {ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CKE2,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,30,UINT8_BY2,0}, + {ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CKE3,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,31,UINT8_BY2,0}, + {ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CSN0,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,32,UINT8_BY2,0}, + {ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CSN1,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,33,UINT8_BY2,0}, + {ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CSN2,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,34,UINT8_BY2,0}, + {ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CSN3,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,35,UINT8_BY2,0}, + {ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_ODT0,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,36,UINT8_BY2,0}, + {ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_ODT1,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,37,UINT8_BY2,0}, + {ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CKE0,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,38,UINT8_BY2,0}, + {ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CKE1,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,39,UINT8_BY2,0}, + {ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CKE2,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,40,UINT8_BY2,0}, + {ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CKE3,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,41,UINT8_BY2,0}, + {ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CSN0,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,42,UINT8_BY2,0}, + {ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CSN1,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,43,UINT8_BY2,0}, + {ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CSN2,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,44,UINT8_BY2,0}, + {ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CSN3,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,45,UINT8_BY2,0}, + {ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_ODT0,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,46,UINT8_BY2,0}, + {ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_ODT1,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,47,UINT8_BY2,0}, + {ATTR_VPD_DRAM_2N_MODE_ENABLED,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,48,UINT8_BY2,0}, + {ATTR_VPD_TSYS_ADR,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,49,UINT8_BY2|PORT00,0}, + {ATTR_VPD_TSYS_DP18,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,49,UINT8_BY2|PORT11,0}, +}; + +const uint32_t g_MBVPD_ATTR_DEF_array_size = + sizeof(g_MBVPD_ATTR_DEF_array) / + sizeof(MBvpdAttrDef); + +} // namespace getAttrData +} // namespace fapi |
