diff options
Diffstat (limited to 'src/usr/hwpf/hwp/lab_dimm_spd_attributes.xml')
| -rwxr-xr-x[-rw-r--r--] | src/usr/hwpf/hwp/lab_dimm_spd_attributes.xml | 713 |
1 files changed, 610 insertions, 103 deletions
diff --git a/src/usr/hwpf/hwp/lab_dimm_spd_attributes.xml b/src/usr/hwpf/hwp/lab_dimm_spd_attributes.xml index 01d90c997..8e4af3c93 100644..100755 --- a/src/usr/hwpf/hwp/lab_dimm_spd_attributes.xml +++ b/src/usr/hwpf/hwp/lab_dimm_spd_attributes.xml @@ -5,7 +5,7 @@ <!-- --> <!-- OpenPOWER HostBoot Project --> <!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2014 --> +<!-- Contributors Listed Below - COPYRIGHT 2014,2015 --> <!-- [+] International Business Machines Corp. --> <!-- --> <!-- --> @@ -22,7 +22,7 @@ <!-- permissions and limitations under the License. --> <!-- --> <!-- IBM_PROLOG_END_TAG --> -<!-- $Id: dimm_spd_attributes.xml,v 1.35 2014/05/23 16:33:05 whs Exp $ --> +<!-- $Id: lab_dimm_spd_attributes.xml,v 1.25 2015/09/28 12:09:12 mklight Exp $ --> <!-- XML file specifying DIMM SPD attributes used by HW Procedures. --> <attributes> @@ -53,7 +53,7 @@ The following attributes can be queried from both DDR3 and DDR4 DIMMs Note that CDIMM designation here is obsolete. See ATTR_SPD_CUSTOM </description> <valueType>uint8</valueType> - <enum>CDIMM = 0x00, RDIMM = 0x01, UDIMM = 0x02, SO_DIMM=0x03, LRDIMM = 0x0b</enum> + <enum>CDIMM = 0x00, RDIMM = 0x01, UDIMM = 0x02, SO_DIMM=0x03, LRDIMM = 0x0b, INVALID = 0xff</enum> <platInit/> </attribute> @@ -76,6 +76,14 @@ The following attributes can be queried from both DDR3 and DDR4 DIMMs <description> DRAM Density. Located in DDR3/DDR4 SPD byte 4, bits 3-0. + 0x00 = 256MB + 0x01 = 512MB + 0x02 = 1GB + 0x03 = 2GB + 0x04 = 4GB + 0x05 = 8GB + 0x06 = 16GB + 0x07 = 32GB </description> <valueType>uint8</valueType> <enum> @@ -95,6 +103,8 @@ The following attributes can be queried from both DDR3 and DDR4 DIMMs The raw data has different meanings for DDR3 and DDR4. HWPs must use this DDR neutral enumeration to decode. Platform support must call an Accessor HWP. + For DDR4 , Values can be B4 and B8 based on bits 5-4 + For DDR3 , Values can be B8,B16,B32,B64 based on bits 6-4 </description> <valueType>uint8</valueType> <enum>B8 = 0x00, B16 = 0x01, B32 = 0x02, B64 = 0x03, B4 = 0x04, UNKNOWN = 0xff</enum> @@ -109,7 +119,7 @@ The following attributes can be queried from both DDR3 and DDR4 DIMMs Located in DDR3/DDR4 SPD byte 5, bits 5-3. </description> <valueType>uint8</valueType> - <enum>R12 = 0x00, R13 = 0x01, R14 = 0x02, R15 = 0x03, + <enum>R12 = 0x00, R13 = 0x01, R14 = 0x02, R15 = 0x03, R16 = 0x04, R17 = 0x05, R18 = 0x06 </enum> <platInit/> @@ -137,6 +147,8 @@ The following attributes can be queried from both DDR3 and DDR4 DIMMs The raw data has different meanings for DDR3 and DDR4. HWPs must use this DDR neutral enumeration to decode. Platform support must call an Accessor HWP. + For DDR3, values would be NOTOP1_5,OP1_35,OP1_2X based on byte 6, bits 2-0 + For DDR4, values would be OP1_2V,END1_2V, based on byte 6, bits 5-0 </description> <valueType>uint8</valueType> <enum> @@ -158,6 +170,7 @@ The following attributes can be queried from both DDR3 and DDR4 DIMMs Located in DDR4 SPD byte 12, bits 5-3. </description> <valueType>uint8</valueType> + <!-- RX means an invalid value, only used to init vars --> <enum>R1 = 0x00, R2 = 0x01, R4 = 0x03, RX = 0xFF</enum> <platInit/> </attribute> @@ -215,6 +228,8 @@ The following attributes can be queried from both DDR3 and DDR4 DIMMs The raw data has different meanings for DDR3 and DDR4. HWPs must use this DDR neutral enumeration to decode. Platform support must call an Accessor HWP. + For DDR3, the values would be from CL_4 through CL_18 + For DDR4, the values would be from CL_7 through CL_24 </description> <valueType>uint32</valueType> <enum> @@ -459,7 +474,7 @@ The following attributes can be queried from both DDR3 and DDR4 DIMMs <description> Number of Registers used on RDIMM. Located in DDR3 SPD byte 63 bits 1-0. - </description> + </description> <valueType>uint8</valueType> <platInit/> </attribute> @@ -592,6 +607,44 @@ The following attributes can be queried from both DDR3 and DDR4 DIMMs <writeable/> </attribute> +<attribute> + <id>ATTR_SPD_DIMM_RCD_CNTL_WORD_0_15</id> + <targetType>TARGET_TYPE_DIMM</targetType> + <description>RCD Control Word. Supplied by SPD, used by mss_eff_config.C and mss_draminit.C . Each dimm will have a value. + consumer: mss_dram_init, mss_eff_config firmware notes: In order to make this readable to the OpenPower: It is necessary + to swap the nibbles for a given byte. IE this is pulled from SPD bytes 69 - 76. (DDR3) + The attribute would contain byte 69 nibble 1, followed by byte 69 nibble 0, followed by byte 70 nibble 1, and so forth. + </description> + <valueType>uint64</valueType> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_VPD_DIMM_RCD_CNTL_WORD_0_15</id> + <targetType>TARGET_TYPE_DIMM</targetType> + <description>This will be replaced by ATTR_SPD_DIMM_RCD_CNTL_WORD_0_15. Until migration is complete USE as is. (Will be deleted soon) + IE this is pulled from SPD bytes 69 - 76. (DDR3) + The attribute would contain byte 69 nibble 1, followed by byte 69 nibble 0, followed by byte 70 nibble 1, and so forth. + </description> + <valueType>uint64</valueType> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_VPD_DIMM_RCD_OUTPUT_TIMING</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>RCD Timing. Supplied by VPD, used by mss_eff_config.C. Each dimm will have a value. + consumer: mss_eff_config + </description> + <valueType>uint8</valueType> + <enum>1T = 0x01, 3T = 0x03</enum> + <odmVisable/> + <odmChangeable/> + <array> 2 2</array> +</attribute> + <!-- ******************************************************************************* The following attributes can be queried from DDR3 DIMMs only @@ -1051,7 +1104,7 @@ Querying them from DDR3 DIMMs will result in an error <targetType>TARGET_TYPE_DIMM</targetType> <description> Minimum SDRAM Refresh Recovery Time Delay in medium timebase (MTB) units - Located in DDR4 SPD bytes 30(MSB) and 31(LSB). + Located in DDR4 SPD bytes 31(MSB) bits 15-8 and SPD byte 30(LSB) 7-0. </description> <valueType>uint32</valueType> <platInit/> @@ -1062,7 +1115,7 @@ Querying them from DDR3 DIMMs will result in an error <targetType>TARGET_TYPE_DIMM</targetType> <description> Minimum SDRAM Refresh Recovery Time Delay in medium timebase (MTB) units - Located in DDR4 SPD bytes 32(MSB) and 33(LSB). + Located in DDR4 SPD bytes 33(MSB) bits 15-8 and SPD byte 32(LSB) 7-0. </description> <valueType>uint32</valueType> <platInit/> @@ -1073,7 +1126,7 @@ Querying them from DDR3 DIMMs will result in an error <targetType>TARGET_TYPE_DIMM</targetType> <description> Minimum SDRAM Refresh Recovery Time Dealy in medium timebase (MTB) units. - Located in DDR4 SPD byte 34(LSB) bits 15-8 and SPD byte 35(MSB) 7-0. + Located in DDR4 SPD byte 35(MSB) bits 15-8 and SPD byte 34(LSB) 7-0. </description> <valueType>uint32</valueType> <platInit/> @@ -1083,10 +1136,10 @@ Querying them from DDR3 DIMMs will result in an error <id>ATTR_SPD_TRRDSMIN_DDR4</id> <targetType>TARGET_TYPE_DIMM</targetType> <description> - The minimum SDRAM Activate to Activate Delay Time to different bank - groups in medium timebase (MTB) units. Controller designers must also + The minimum SDRAM Activate to Activate Delay Time to different bank + groups in medium timebase (MTB) units. Controller designers must also note that at some frequencies, a minimum number of clocks may be required - resulting in a larger tRRD_Smin value than indicated in the SPD. + resulting in a larger tRRD_Smin value than indicated in the SPD. For example, tRRD_Smin for DDR4-1600 must be 4 clocks. Located in DDR4 SPD byte 38 </description> @@ -1098,10 +1151,10 @@ Querying them from DDR3 DIMMs will result in an error <id>ATTR_SPD_TRRDLMIN_DDR4</id> <targetType>TARGET_TYPE_DIMM</targetType> <description> - The minimum SDRAM Activate to Activate Delay Time to same bank - groups in medium timebase (MTB) units. Controller designers must also + The minimum SDRAM Activate to Activate Delay Time to same bank + groups in medium timebase (MTB) units. Controller designers must also note that at some frequencies, a minimum number of clocks may be required - resulting in a larger tRRD_Smin value than indicated in the SPD. + resulting in a larger tRRD_Smin value than indicated in the SPD. For example, tRRD_Lmin for DDR4-1600 must be 4 clocks. Located in DDR4 SPD byte 39 </description> @@ -1113,12 +1166,12 @@ Querying them from DDR3 DIMMs will result in an error <id>ATTR_SPD_TCCDLMIN_DDR4</id> <targetType>TARGET_TYPE_DIMM</targetType> <description> - The minimum SDRAM CAS to CAS Delay Time to same bank - groups in medium timebase (MTB) units. Controller designers must also + The minimum SDRAM CAS to CAS Delay Time to same bank + groups in medium timebase (MTB) units. Controller designers must also note that at some frequencies, a minimum number of clocks may be required - resulting in a larger tCCD_Lmin value than indicated in the SPD. + resulting in a larger tCCD_Lmin value than indicated in the SPD. For example, tCCD_Lmin for DDR4-2133 must be 6 clocks. - Located in DDR4 SPD byte 40 + Located in DDR4 SPD byte 40 </description> <valueType>uint8</valueType> <platInit/> @@ -1128,11 +1181,11 @@ Querying them from DDR3 DIMMs will result in an error <id>ATTR_SPD_FINE_OFFSET_TCCDLMIN_DDR4</id> <targetType>TARGET_TYPE_DIMM</targetType> <description> - Modifies the calculation of SPD Byte 40 with a fine correction - using FTB units. The value of tCCD_Lmin comes from the SDRAM data - sheet. This value is a two.s complement multiplier for FTB units, + Modifies the calculation of SPD Byte 40 with a fine correction + using FTB units. The value of tCCD_Lmin comes from the SDRAM data + sheet. This value is a two.s complement multiplier for FTB units, ranging from +127 to -128. - Located in DDR4 SPD byte 117 + Located in DDR4 SPD byte 117 </description> <valueType>uint8</valueType> <platInit/> @@ -1142,11 +1195,11 @@ Querying them from DDR3 DIMMs will result in an error <id>ATTR_SPD_FINE_OFFSET_TRRDLMIN_DDR4</id> <targetType>TARGET_TYPE_DIMM</targetType> <description> - Modifies the calculation of SPD Byte 39 with a fine correction using - FTB units. The value of tRRD_Lmin comes from the SDRAM data sheet. - This value is a two.s complement multiplier for FTB units, + Modifies the calculation of SPD Byte 39 with a fine correction using + FTB units. The value of tRRD_Lmin comes from the SDRAM data sheet. + This value is a two.s complement multiplier for FTB units, ranging from +127 to -128. - Located in DDR4 SPD byte 118 + Located in DDR4 SPD byte 118 </description> <valueType>uint8</valueType> <platInit/> @@ -1156,11 +1209,11 @@ Querying them from DDR3 DIMMs will result in an error <id>ATTR_SPD_FINE_OFFSET_TRRDSMIN_DDR4</id> <targetType>TARGET_TYPE_DIMM</targetType> <description> - Modifies the calculation of SPD Byte 38 (MTB units) with a fine - correction using FTB units. The value of tRRD_Smin comes from the - SDRAM data sheet. This value is a two.s complement multiplier for + Modifies the calculation of SPD Byte 38 (MTB units) with a fine + correction using FTB units. The value of tRRD_Smin comes from the + SDRAM data sheet. This value is a two.s complement multiplier for FTB units, ranging from +127 to -128. - Located in DDR4 SPD byte 119 + Located in DDR4 SPD byte 119 </description> <valueType>uint8</valueType> <platInit/> @@ -1193,7 +1246,7 @@ Querying them from DDR3 DIMMs will result in an error <targetType>TARGET_TYPE_DIMM</targetType> <description> Defines the vendor die revision level (often called the .stepping.) - of the DRAMs on the module. This byte is optional. + of the DRAMs on the module. This byte is optional. For modules without DRAM stepping information, this byte should be programmed to 0xFF. Located in DDR4 SPD byte 352 @@ -1217,15 +1270,285 @@ Querying them from DDR3 DIMMs will result in an error <id>ATTR_VPD_VERSION</id> <targetType>TARGET_TYPE_DIMM</targetType> <description> - The VPD Version of this DIMM. The version number can be an indication of when different DIMM keywords are valid and is loaded from the platform. A version number of zero is unknown. + The VPD Version of this DIMM. The version number can be an indication of when different DIMM keywords are valid and is loaded from the platform. The version represented here represents one of three distinct vintages of parts : unknown/error, early build CDIMMs with VZ less than 10, everything else. In other words, this attribute does NOT equate to the VZ keyword. </description> <valueType>uint32</valueType> + <!-- Values are ASCII numbers to match previous VZ usage --> + <enum>UNKNOWN = 0x3030, OLD_CDIMM = 0x3031, CURRENT = 0x3230</enum> <platInit/> <writeable/> </attribute> <!-- ******************************************************************************* +The following attributes can be queried from LRDIMM type DDR4 DIMMs only +******************************************************************************* +--> + +<attribute> + <id>ATTR_SPD_DIMM_MODULE_ATTRIBUTES</id> + <targetType>TARGET_TYPE_DIMM</targetType> + <description> + Indicates number of registers used and number of rows of DRAM's on LRDIMM. + Byte 131, Bits 1-0 for # of registers used on LRDIMM. + 00 - Undefined , 01 - 1 Register , 10,11 -Reserved. + Byte 131, Bits 3-2 for # of rows of DRAM's on LRDIMM + 00,11- Undefined, 01- 1 Row, 10 - 2 Rows. + </description> + <valueType>uint8</valueType> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_SPD_REGISTER_MANF_ID</id> + <targetType>TARGET_TYPE_DIMM</targetType> + <description> + Manufacturer of the memory buffer on DIMM module. + Located in DDR4 SPD bytes 133(LSB) and 134(MSB). + </description> + <valueType>uint32</valueType> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_SPD_ADDR_MAP_REG_TO_DRAM</id> + <targetType>TARGET_TYPE_DIMM</targetType> + <description> + Address mapping from Register to DRAM and Drive strength. + Located in DDR4 SPD bytes 136 and 137. + Byte 136 bit 0, 0 - Standard, 1 - Mirrored. + Byte 137 has drive strength for control and command/Address. + </description> + <valueType>uint32</valueType> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_SPD_REG_OUTPUT_DRV_STRENGTH_CK</id> + <targetType>TARGET_TYPE_DIMM</targetType> + <description> + Drive strength for clock outputs of the registering clock driver. + Located in DDR4 SPD bytes 138. + </description> + <valueType>uint8</valueType> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_SPD_LR_DRAM_VREF_DQ_RANK0</id> + <targetType>TARGET_TYPE_DIMM</targetType> + <description> + VREFDQ value for the package rank 0 DRAM's. + Located in DDR4 SPD bytes 140. + </description> + <valueType>uint8</valueType> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_SPD_LR_DRAM_VREF_DQ_RANK1</id> + <targetType>TARGET_TYPE_DIMM</targetType> + <description> + VREFDQ value for the package rank 1 DRAM's. + Located in DDR4 SPD bytes 141. + </description> + <valueType>uint8</valueType> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_SPD_LR_DRAM_VREF_DQ_RANK2</id> + <targetType>TARGET_TYPE_DIMM</targetType> + <description> + VREFDQ value for the package rank 2 DRAM's. + Located in DDR4 SPD bytes 142. + </description> + <valueType>uint8</valueType> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_SPD_LR_DRAM_VREF_DQ_RANK3</id> + <targetType>TARGET_TYPE_DIMM</targetType> + <description> + VREFDQ value for the package rank 3 DRAM's. + Located in DDR4 SPD bytes 143. + </description> + <valueType>uint8</valueType> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_SPD_LR_BUF_VREF_DQ_FOR_DRAM</id> + <targetType>TARGET_TYPE_DIMM</targetType> + <description> + VREFDQ value for the data buffer component. + Located in DDR4 SPD bytes 144. + </description> + <valueType>uint8</valueType> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_SPD_LR_BUF_MDQ_DRV_LESS_THAN_1866</id> + <targetType>TARGET_TYPE_DIMM</targetType> + <description> + Data Buffer MDQ Drive strength and RTT for data rate less than 1866. + Located in DDR4 SPD bytes 145. + Bits 2-0 for MDQ Read Termination strength. + Bits 6-4 for MDQ Drive strength. + </description> + <valueType>uint8</valueType> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_SPD_LR_BUF_MDQ_DRV_1866_2400</id> + <targetType>TARGET_TYPE_DIMM</targetType> + <description> + Data Buffer MDQ Drive strength and RTT for data rate between 1866 and 2400. + Located in DDR4 SPD bytes 146. + Bits 2-0 for MDQ Read Termination strength. + Bits 6-4 for MDQ Drive strength. + </description> + <valueType>uint8</valueType> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_SPD_LR_BUF_MDQ_DRV_2400_3200</id> + <targetType>TARGET_TYPE_DIMM</targetType> + <description> + Data Buffer MDQ Drive strength and RTT for data rate between 2400 and 3200. + Located in DDR4 SPD bytes 147. + Bits 2-0 for MDQ Read Termination strength. + Bits 6-4 for MDQ Drive strength. + </description> + <valueType>uint8</valueType> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_SPD_LR_DRAM_DRV_STRENGTH</id> + <targetType>TARGET_TYPE_DIMM</targetType> + <description> + DRAM Drive strength for all the data rates between 1866 and 3200. + Located in DDR4 SPD bytes 148. + Bits 1-0 for Datarate less than 1866. + Bits 3-2 for Data rate between 1866 and 2400. + Bits 5-4 for data rate between 2400 and 3200. + </description> + <valueType>uint8</valueType> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_SPD_LR_DRAM_ODT_RTT_WR_LESS_THAN_1866</id> + <targetType>TARGET_TYPE_DIMM</targetType> + <description> + DRAM ODT (RTT_WR) for data rates less than 1866 + Located in DDR4 SPD bytes 149 bits 2-0. + </description> + <valueType>uint8</valueType> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_SPD_LR_DRAM_ODT_RTT_NOM_LESS_THAN_1866</id> + <targetType>TARGET_TYPE_DIMM</targetType> + <description> + DRAM ODT (RTT_NOM)for data rates less than 1866 + Located in DDR4 SPD bytes 149 bits 5-3. + </description> + <valueType>uint8</valueType> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_SPD_LR_DRAM_ODT_RTT_WR_1866_2400</id> + <targetType>TARGET_TYPE_DIMM</targetType> + <description> + DRAM ODT (RTT_WR) for data rates between 1866 and 2400. + Located in DDR4 SPD bytes 150 bits 2-0. + </description> + <valueType>uint8</valueType> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_SPD_LR_DRAM_ODT_RTT_NOM_1866_2400</id> + <targetType>TARGET_TYPE_DIMM</targetType> + <description> + DRAM ODT (RTT_NOM)for data rates between 1866 and 2400. + Located in DDR4 SPD bytes 150 bits 5-3. + </description> + <valueType>uint8</valueType> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_SPD_LR_DRAM_ODT_RTT_WR_2400_3200</id> + <targetType>TARGET_TYPE_DIMM</targetType> + <description> + DRAM ODT (RTT_WR) for data rates between 2400 and 3200. + Located in DDR4 SPD bytes 151 bits 2-0. + </description> + <valueType>uint8</valueType> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_SPD_LR_DRAM_ODT_RTT_NOM_2400_3200</id> + <targetType>TARGET_TYPE_DIMM</targetType> + <description> + DRAM ODT (RTT_NOM)for data rates between 2400 and 3200. + Located in DDR4 SPD bytes 151 bits 5-3. + </description> + <valueType>uint8</valueType> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_SPD_LR_DRAM_ODT_RTT_PARK_LESS_THAN_1866</id> + <targetType>TARGET_TYPE_DIMM</targetType> + <description> + DRAM ODT (RTT_PARK)for data rates less than 1866. + Located in DDR4 SPD bytes 152. + Bit 2-0 for package ranks 0 and 1. + Bit 5-3 for package ranks 2 and 3. + </description> + <valueType>uint8</valueType> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_SPD_LR_DRAM_ODT_RTT_PARK_1866_2400</id> + <targetType>TARGET_TYPE_DIMM</targetType> + <description> + DRAM ODT (RTT_PARK)for data rates between 1866 and 2400. + Located in DDR4 SPD bytes 153. + Bit 2-0 for package ranks 0 and 1. + Bit 5-3 for package ranks 2 and 3. + </description> + <valueType>uint8</valueType> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_SPD_LR_DRAM_ODT_RTT_PARK_2400_3200</id> + <targetType>TARGET_TYPE_DIMM</targetType> + <description> + DRAM ODT (RTT_PARK)for data rates between 2400 and 3200. + Located in DDR4 SPD bytes 154. + Bit 2-0 for package ranks 0 and 1. + Bit 5-3 for package ranks 2 and 3. + </description> + <valueType>uint8</valueType> + <platInit/> +</attribute> + +<!-- +******************************************************************************* The following attributes are DDR3 specific. Regular HWPs should query the DDR neutral attribute, these attributes should only be queried by the Accessor HWP that handles the DDR neutral attribute. @@ -1412,8 +1735,8 @@ file RANK3_MIRRORED = 0x01 </enum> <platInit/> - <array> 2 2</array> <writeable/> + <array> 2 2</array> </attribute> <!-- Attributes added to support the VPD which was formally using the EFF settings --> @@ -1427,10 +1750,10 @@ consumer: various.C files and initfiles firmware notes: none</description> <valueType>uint8</valueType> <platInit/> + <writeable/> <odmVisable/> <odmChangeable/> <array> 2 2 4</array> - <writeable/> </attribute> <attribute> @@ -1442,10 +1765,10 @@ consumer: various.C and initfile firmware notes: none</description> <valueType>uint8</valueType> <platInit/> + <writeable/> <odmVisable/> <odmChangeable/> <array> 2 2 4</array> - <writeable/> </attribute> <attribute> @@ -1477,10 +1800,10 @@ This Attribute is to be interpreted as an Integer</description> <valueType>uint8</valueType> <enum>DISABLE = 0, OHM20 = 20, OHM30 = 30, OHM34 = 34, OHM40 = 40, OHM48 = 48, OHM60 = 60, OHM80 = 80, OHM120 = 120, OHM240 = 240</enum> <platInit/> + <writeable/> <odmVisable/> <odmChangeable/> <array> 2 2 4</array> - <writeable/> </attribute> <attribute> @@ -1494,10 +1817,27 @@ This Attribute is to be interpreted as an Integer</description> <valueType>uint8</valueType> <enum>DISABLE = 0, OHM60 = 60, OHM120 = 120, OHM240 = 240, HIGHZ = 1</enum> <platInit/> + <writeable/> + <odmVisable/> + <odmChangeable/> + <array> 2 2 4</array> +</attribute> + +<attribute> + <id>ATTR_VPD_DRAM_RTT_PARK</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>DRAM Rtt_PARK. Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. + RTT_Park value. This is for DDR4 MRS5.Each memory channel will have a value. +Creator: VPD(MT), mss_eff_cnfg_termination +consumer: various.C files (no initfiles) +firmware notes: none +This Attribute is to be interpreted as an Integer</description> + <valueType>uint8</valueType> + <enum>DISABLE = 0, 60OHM = 60, 120OHM = 120, 40OHM = 40, 240OHM = 240, 48OHM = 48, 80OHM = 80, 34OHM = 34</enum> + <platInit/> <odmVisable/> <odmChangeable/> <array> 2 2 4</array> - <writeable/> </attribute> <attribute> @@ -1513,10 +1853,10 @@ This Attribute is to be interpreted as an Integer</description> <valueType>uint32</valueType> <enum>VDD420 = 420, VDD425 = 425, VDD430 = 430, VDD435 = 435, VDD440 = 440, VDD445 = 445, VDD450 = 450, VDD455 = 455, VDD460 = 460, VDD465 = 465, VDD470 = 470, VDD475 = 475, VDD480 = 480, VDD485 = 485, VDD490 = 490, VDD495 = 495, VDD500 = 500, VDD505 = 505, VDD510 = 510, VDD515 = 515, VDD520 = 520, VDD525 = 525, VDD530 = 530, VDD535 = 535, VDD540 = 540, VDD545 = 545, VDD550 = 550, VDD555 = 555, VDD560 = 560, VDD565 = 565, VDD570 = 570, VDD575 = 575</enum> <platInit/> + <writeable/> <odmVisable/> <odmChangeable/> <array> 2</array> - <writeable/> </attribute> <attribute> @@ -1531,10 +1871,10 @@ This is for DDR4 The value is from 0 to 50</description> <valueType>uint8</valueType> <platInit/> + <writeable/> <odmVisable/> <odmChangeable/> <array> 2</array> - <writeable/> </attribute> <attribute> @@ -1550,10 +1890,10 @@ This Attribute is to be interpreted as an Integer</description> <enum>OHM24_FFE0 = 0x0A, OHM30_FFE0 = 0x08, OHM30_FFE480 = 0x48, OHM30_FFE240 = 0x38, OHM30_FFE160 = 0x28, OHM30_FFE120 = 0x18, OHM34_FFE0 = 0x07, OHM34_FFE480 = 0x47, OHM34_FFE240 = 0x37, OHM34_FFE160 = 0x27, OHM34_FFE120 = 0x17, OHM40_FFE0 = 0x06, OHM40_FFE480 = 0x46, OHM40_FFE240 = 0x36, OHM40_FFE160 = 0x26, OHM40_FFE120 = 0x16</enum> <platInit/> + <writeable/> <odmVisable/> <odmChangeable/> <array> 2</array> - <writeable/> </attribute> <attribute> @@ -1568,10 +1908,10 @@ This Attribute is to be interpreted as an Integer</description> <valueType>uint8</valueType> <enum>OHM15 = 15, OHM20 = 20, OHM30 = 30, OHM40 = 40</enum> <platInit/> + <writeable/> <odmVisable/> <odmChangeable/> <array> 2</array> - <writeable/> </attribute> <attribute> @@ -1586,10 +1926,10 @@ This Attribute is to be interpreted as an Integer</description> <valueType>uint8</valueType> <enum>OHM15 = 15, OHM20 = 20, OHM30 = 30, OHM40 = 40</enum> <platInit/> + <writeable/> <odmVisable/> <odmChangeable/> <array> 2</array> - <writeable/> </attribute> <attribute> @@ -1604,10 +1944,10 @@ This Attribute is to be interpreted as an Integer</description> <valueType>uint8</valueType> <enum>OHM15 = 15, OHM20 = 20, OHM30 = 30, OHM40 = 40</enum> <platInit/> + <writeable/> <odmVisable/> <odmChangeable/> <array> 2</array> - <writeable/> </attribute> <attribute> @@ -1622,10 +1962,10 @@ This Attribute is to be interpreted as an Integer</description> <valueType>uint8</valueType> <enum>OHM15 = 15, OHM20 = 20, OHM30 = 30, OHM40 = 40</enum> <platInit/> + <writeable/> <odmVisable/> <odmChangeable/> <array> 2</array> - <writeable/> </attribute> <attribute> @@ -1640,10 +1980,10 @@ This Attribute is to be interpreted as an Integer</description> <valueType>uint8</valueType> <enum>OHM15 = 15, OHM20 = 20, OHM30 = 30, OHM40 = 40, OHM48 = 48, OHM60 = 60, OHM80 = 80, OHM120 = 120, OHM160 = 160, OHM240 = 240</enum> <platInit/> + <writeable/> <odmVisable/> <odmChangeable/> <array> 2</array> - <writeable/> </attribute> <attribute> @@ -1662,10 +2002,10 @@ SLEW_5V_NS = 5, SLEW_6V_NS = 6, SLEW_MAXV_NS = 7</enum> <platInit/> + <writeable/> <odmVisable/> <odmChangeable/> <array> 2</array> - <writeable/> </attribute> <attribute> @@ -1684,10 +2024,10 @@ SLEW_5V_NS = 5, SLEW_6V_NS = 6, SLEW_MAXV_NS = 7</enum> <platInit/> + <writeable/> <odmVisable/> <odmChangeable/> <array> 2</array> - <writeable/> </attribute> <attribute> @@ -1706,10 +2046,10 @@ SLEW_5V_NS = 5, SLEW_6V_NS = 6, SLEW_MAXV_NS = 7</enum> <platInit/> + <writeable/> <odmVisable/> <odmChangeable/> <array> 2</array> - <writeable/> </attribute> <attribute> @@ -1729,10 +2069,10 @@ SLEW_6V_NS = 6, SLEW_MAXV_NS = 7 </enum> <platInit/> + <writeable/> <odmVisable/> <odmChangeable/> <array> 2</array> - <writeable/> </attribute> <attribute> @@ -1752,10 +2092,10 @@ SLEW_6V_NS = 6, SLEW_MAXV_NS = 7 </enum> <platInit/> + <writeable/> <odmVisable/> <odmChangeable/> <array> 2</array> - <writeable/> </attribute> <attribute> @@ -1770,10 +2110,10 @@ This Attribute is to be interpreted as an Integer</description> <valueType>uint32</valueType> <enum>VDD40375 = 40375, VDD41750 = 41750, VDD43125 = 43125, VDD44500 = 44500, VDD45875 = 45875, VDD47250 = 47250, VDD48625 = 48625, VDD50000 = 50000, VDD51375 = 51375, VDD52750 = 52750, VDD54125 = 54125, VDD55500 = 55500, VDD56875 = 56875, VDD58250 = 58250, VDD59625 = 59625, VDD61000 = 61000, VDD60375 = 60375, VDD61750 = 61750, VDD63125 = 63125, VDD64500 = 64500, VDD65875 = 65875, VDD67250 = 67250, VDD68625 = 68625, VDD70000 = 70000, VDD71375 = 71375, VDD72750 = 72750, VDD74125 = 74125, VDD75500 = 75500, VDD76875 = 76875, VDD78250 = 78250, VDD79625 = 79625, VDD81000 = 81000</enum> <platInit/> + <writeable/> <odmVisable/> <odmChangeable/> <array> 2</array> - <writeable/> </attribute> <attribute> @@ -1782,10 +2122,10 @@ This Attribute is to be interpreted as an Integer</description> <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M0_CLK_P0</description> <valueType>uint8</valueType> <platInit/> + <writeable/> <odmVisable/> <odmChangeable/> <array> 2</array> - <writeable/> </attribute> <attribute> @@ -1794,10 +2134,10 @@ This Attribute is to be interpreted as an Integer</description> <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M0_CLK_P1</description> <valueType>uint8</valueType> <platInit/> + <writeable/> <odmVisable/> <odmChangeable/> <array> 2</array> - <writeable/> </attribute> <attribute> @@ -1806,10 +2146,10 @@ This Attribute is to be interpreted as an Integer</description> <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M1_CLK_P0</description> <valueType>uint8</valueType> <platInit/> + <writeable/> <odmVisable/> <odmChangeable/> <array> 2</array> - <writeable/> </attribute> <attribute> @@ -1818,10 +2158,10 @@ This Attribute is to be interpreted as an Integer</description> <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M1_CLK_P1</description> <valueType>uint8</valueType> <platInit/> + <writeable/> <odmVisable/> <odmChangeable/> <array> 2</array> - <writeable/> </attribute> <attribute> @@ -1830,10 +2170,10 @@ This Attribute is to be interpreted as an Integer</description> <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_A0</description> <valueType>uint8</valueType> <platInit/> + <writeable/> <odmVisable/> <odmChangeable/> <array> 2</array> - <writeable/> </attribute> <attribute> @@ -1842,10 +2182,10 @@ This Attribute is to be interpreted as an Integer</description> <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_A1</description> <valueType>uint8</valueType> <platInit/> + <writeable/> <odmVisable/> <odmChangeable/> <array> 2</array> - <writeable/> </attribute> <attribute> @@ -1854,10 +2194,10 @@ This Attribute is to be interpreted as an Integer</description> <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_A2</description> <valueType>uint8</valueType> <platInit/> + <writeable/> <odmVisable/> <odmChangeable/> <array> 2</array> - <writeable/> </attribute> <attribute> @@ -1866,10 +2206,10 @@ This Attribute is to be interpreted as an Integer</description> <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_A3</description> <valueType>uint8</valueType> <platInit/> + <writeable/> <odmVisable/> <odmChangeable/> <array> 2</array> - <writeable/> </attribute> <attribute> @@ -1878,10 +2218,10 @@ This Attribute is to be interpreted as an Integer</description> <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_A4</description> <valueType>uint8</valueType> <platInit/> + <writeable/> <odmVisable/> <odmChangeable/> <array> 2</array> - <writeable/> </attribute> <attribute> @@ -1890,10 +2230,10 @@ This Attribute is to be interpreted as an Integer</description> <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_A5</description> <valueType>uint8</valueType> <platInit/> + <writeable/> <odmVisable/> <odmChangeable/> <array> 2</array> - <writeable/> </attribute> <attribute> @@ -1902,10 +2242,10 @@ This Attribute is to be interpreted as an Integer</description> <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_A6</description> <valueType>uint8</valueType> <platInit/> + <writeable/> <odmVisable/> <odmChangeable/> <array> 2</array> - <writeable/> </attribute> <attribute> @@ -1914,10 +2254,10 @@ This Attribute is to be interpreted as an Integer</description> <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_A7</description> <valueType>uint8</valueType> <platInit/> + <writeable/> <odmVisable/> <odmChangeable/> <array> 2</array> - <writeable/> </attribute> <attribute> @@ -1926,10 +2266,10 @@ This Attribute is to be interpreted as an Integer</description> <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_A8</description> <valueType>uint8</valueType> <platInit/> + <writeable/> <odmVisable/> <odmChangeable/> <array> 2</array> - <writeable/> </attribute> <attribute> @@ -1938,10 +2278,10 @@ This Attribute is to be interpreted as an Integer</description> <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_A9</description> <valueType>uint8</valueType> <platInit/> + <writeable/> <odmVisable/> <odmChangeable/> <array> 2</array> - <writeable/> </attribute> <attribute> @@ -1950,10 +2290,10 @@ This Attribute is to be interpreted as an Integer</description> <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_A10</description> <valueType>uint8</valueType> <platInit/> + <writeable/> <odmVisable/> <odmChangeable/> <array> 2</array> - <writeable/> </attribute> <attribute> @@ -1962,10 +2302,10 @@ This Attribute is to be interpreted as an Integer</description> <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_A11</description> <valueType>uint8</valueType> <platInit/> + <writeable/> <odmVisable/> <odmChangeable/> <array> 2</array> - <writeable/> </attribute> <attribute> @@ -1974,10 +2314,10 @@ This Attribute is to be interpreted as an Integer</description> <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_A12</description> <valueType>uint8</valueType> <platInit/> + <writeable/> <odmVisable/> <odmChangeable/> <array> 2</array> - <writeable/> </attribute> <attribute> @@ -1986,10 +2326,10 @@ This Attribute is to be interpreted as an Integer</description> <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_A13</description> <valueType>uint8</valueType> <platInit/> + <writeable/> <odmVisable/> <odmChangeable/> <array> 2</array> - <writeable/> </attribute> <attribute> @@ -1998,10 +2338,10 @@ This Attribute is to be interpreted as an Integer</description> <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_A14</description> <valueType>uint8</valueType> <platInit/> + <writeable/> <odmVisable/> <odmChangeable/> <array> 2</array> - <writeable/> </attribute> <attribute> @@ -2010,10 +2350,10 @@ This Attribute is to be interpreted as an Integer</description> <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_A15</description> <valueType>uint8</valueType> <platInit/> + <writeable/> <odmVisable/> <odmChangeable/> <array> 2</array> - <writeable/> </attribute> <attribute> @@ -2022,10 +2362,10 @@ This Attribute is to be interpreted as an Integer</description> <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_BA0</description> <valueType>uint8</valueType> <platInit/> + <writeable/> <odmVisable/> <odmChangeable/> <array> 2</array> - <writeable/> </attribute> <attribute> @@ -2034,10 +2374,10 @@ This Attribute is to be interpreted as an Integer</description> <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_BA1</description> <valueType>uint8</valueType> <platInit/> + <writeable/> <odmVisable/> <odmChangeable/> <array> 2</array> - <writeable/> </attribute> <attribute> @@ -2046,10 +2386,10 @@ This Attribute is to be interpreted as an Integer</description> <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_BA2</description> <valueType>uint8</valueType> <platInit/> + <writeable/> <odmVisable/> <odmChangeable/> <array> 2</array> - <writeable/> </attribute> <attribute> @@ -2058,10 +2398,10 @@ This Attribute is to be interpreted as an Integer</description> <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_CASN</description> <valueType>uint8</valueType> <platInit/> + <writeable/> <odmVisable/> <odmChangeable/> <array> 2</array> - <writeable/> </attribute> <attribute> @@ -2070,10 +2410,10 @@ This Attribute is to be interpreted as an Integer</description> <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_RASN</description> <valueType>uint8</valueType> <platInit/> + <writeable/> <odmVisable/> <odmChangeable/> <array> 2</array> - <writeable/> </attribute> <attribute> @@ -2082,10 +2422,10 @@ This Attribute is to be interpreted as an Integer</description> <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_WEN</description> <valueType>uint8</valueType> <platInit/> + <writeable/> <odmVisable/> <odmChangeable/> <array> 2</array> - <writeable/> </attribute> <attribute> @@ -2094,10 +2434,10 @@ This Attribute is to be interpreted as an Integer</description> <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_PAR</description> <valueType>uint8</valueType> <platInit/> + <writeable/> <odmVisable/> <odmChangeable/> <array> 2</array> - <writeable/> </attribute> <attribute> @@ -2106,10 +2446,10 @@ This Attribute is to be interpreted as an Integer</description> <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_ACTN</description> <valueType>uint8</valueType> <platInit/> + <writeable/> <odmVisable/> <odmChangeable/> <array> 2</array> - <writeable/> </attribute> <attribute> @@ -2118,10 +2458,10 @@ This Attribute is to be interpreted as an Integer</description> <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M0_CNTL_CKE0</description> <valueType>uint8</valueType> <platInit/> + <writeable/> <odmVisable/> <odmChangeable/> <array> 2</array> - <writeable/> </attribute> <attribute> @@ -2130,10 +2470,10 @@ This Attribute is to be interpreted as an Integer</description> <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M0_CNTL_CKE1</description> <valueType>uint8</valueType> <platInit/> + <writeable/> <odmVisable/> <odmChangeable/> <array> 2</array> - <writeable/> </attribute> <attribute> @@ -2142,10 +2482,10 @@ This Attribute is to be interpreted as an Integer</description> <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M0_CNTL_CKE2</description> <valueType>uint8</valueType> <platInit/> + <writeable/> <odmVisable/> <odmChangeable/> <array> 2</array> - <writeable/> </attribute> <attribute> @@ -2154,10 +2494,10 @@ This Attribute is to be interpreted as an Integer</description> <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M0_CNTL_CKE3</description> <valueType>uint8</valueType> <platInit/> + <writeable/> <odmVisable/> <odmChangeable/> <array> 2</array> - <writeable/> </attribute> <attribute> @@ -2166,10 +2506,10 @@ This Attribute is to be interpreted as an Integer</description> <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M0_CNTL_CSN0</description> <valueType>uint8</valueType> <platInit/> + <writeable/> <odmVisable/> <odmChangeable/> <array> 2</array> - <writeable/> </attribute> <attribute> @@ -2178,10 +2518,10 @@ This Attribute is to be interpreted as an Integer</description> <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M0_CNTL_CSN1</description> <valueType>uint8</valueType> <platInit/> + <writeable/> <odmVisable/> <odmChangeable/> <array> 2</array> - <writeable/> </attribute> <attribute> @@ -2190,10 +2530,10 @@ This Attribute is to be interpreted as an Integer</description> <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M0_CNTL_CSN2</description> <valueType>uint8</valueType> <platInit/> + <writeable/> <odmVisable/> <odmChangeable/> <array> 2</array> - <writeable/> </attribute> <attribute> @@ -2202,10 +2542,10 @@ This Attribute is to be interpreted as an Integer</description> <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M0_CNTL_CSN3</description> <valueType>uint8</valueType> <platInit/> + <writeable/> <odmVisable/> <odmChangeable/> <array> 2</array> - <writeable/> </attribute> <attribute> @@ -2214,10 +2554,10 @@ This Attribute is to be interpreted as an Integer</description> <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M0_CNTL_ODT0</description> <valueType>uint8</valueType> <platInit/> + <writeable/> <odmVisable/> <odmChangeable/> <array> 2</array> - <writeable/> </attribute> <attribute> @@ -2226,10 +2566,10 @@ This Attribute is to be interpreted as an Integer</description> <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M0_CNTL_ODT1</description> <valueType>uint8</valueType> <platInit/> + <writeable/> <odmVisable/> <odmChangeable/> <array> 2</array> - <writeable/> </attribute> <attribute> @@ -2238,10 +2578,10 @@ This Attribute is to be interpreted as an Integer</description> <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M1_CNTL_CKE0</description> <valueType>uint8</valueType> <platInit/> + <writeable/> <odmVisable/> <odmChangeable/> <array> 2</array> - <writeable/> </attribute> <attribute> @@ -2250,10 +2590,10 @@ This Attribute is to be interpreted as an Integer</description> <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M1_CNTL_CKE1</description> <valueType>uint8</valueType> <platInit/> + <writeable/> <odmVisable/> <odmChangeable/> <array> 2</array> - <writeable/> </attribute> <attribute> @@ -2262,10 +2602,10 @@ This Attribute is to be interpreted as an Integer</description> <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M1_CNTL_CKE2</description> <valueType>uint8</valueType> <platInit/> + <writeable/> <odmVisable/> <odmChangeable/> <array> 2</array> - <writeable/> </attribute> <attribute> @@ -2274,10 +2614,10 @@ This Attribute is to be interpreted as an Integer</description> <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M1_CNTL_CKE3</description> <valueType>uint8</valueType> <platInit/> + <writeable/> <odmVisable/> <odmChangeable/> <array> 2</array> - <writeable/> </attribute> <attribute> @@ -2286,10 +2626,10 @@ This Attribute is to be interpreted as an Integer</description> <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M1_CNTL_CSN0</description> <valueType>uint8</valueType> <platInit/> + <writeable/> <odmVisable/> <odmChangeable/> <array> 2</array> - <writeable/> </attribute> <attribute> @@ -2298,10 +2638,10 @@ This Attribute is to be interpreted as an Integer</description> <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M1_CNTL_CSN1</description> <valueType>uint8</valueType> <platInit/> + <writeable/> <odmVisable/> <odmChangeable/> <array> 2</array> - <writeable/> </attribute> <attribute> @@ -2310,10 +2650,10 @@ This Attribute is to be interpreted as an Integer</description> <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M1_CNTL_CSN2</description> <valueType>uint8</valueType> <platInit/> + <writeable/> <odmVisable/> <odmChangeable/> <array> 2</array> - <writeable/> </attribute> <attribute> @@ -2322,10 +2662,10 @@ This Attribute is to be interpreted as an Integer</description> <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M1_CNTL_CSN3</description> <valueType>uint8</valueType> <platInit/> + <writeable/> <odmVisable/> <odmChangeable/> <array> 2</array> - <writeable/> </attribute> <attribute> @@ -2334,10 +2674,10 @@ This Attribute is to be interpreted as an Integer</description> <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M1_CNTL_ODT0</description> <valueType>uint8</valueType> <platInit/> + <writeable/> <odmVisable/> <odmChangeable/> <array> 2</array> - <writeable/> </attribute> <attribute> @@ -2346,10 +2686,22 @@ This Attribute is to be interpreted as an Integer</description> <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M1_CNTL_ODT1</description> <valueType>uint8</valueType> <platInit/> + <writeable/> + <odmVisable/> + <odmChangeable/> + <array> 2</array> +</attribute> + +<attribute> + <id>ATTR_VPD_PERIODIC_MEMCAL_MODE_OPTIONS</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Settings for periodic CAL - zcal 1, syscal 1, centering 0, rdclk 1, dqs align 1, rdclk_update_dis 0, dutycycle 0, and power dis (dqs) 1. Second byte has repeat as 000, mpr mode as 0, mba as 11, and the spares as 00 +</description> + <valueType>uint32</valueType> + <platInit/> <odmVisable/> <odmChangeable/> <array> 2</array> - <writeable/> </attribute> <!-- Spare attribute found in eclipz/hwpf/hwp/xml/attribute_info/dimm_attributes.xml --> @@ -2371,9 +2723,9 @@ This Attribute is to be interpreted as an Integer</description> <description>This value comes from the VPD keyword MT bytes 54 and 55 MT(54:55) for the Logical DIMM associated with port A. Bytes 118:119 for port B, 182:183 for port C and 246:247 for port D. In the end, the AB and CD portions form a 32 bit word for each mba to write into the corresponding ddrphy register</description> <valueType>uint32</valueType> <platInit/> - <writeable/> <odmVisable/> <array>2</array> + <writeable/> </attribute> <attribute> @@ -2392,9 +2744,9 @@ This Attribute is to be interpreted as an Integer</description> <description>This value comes from the VPD keyword MT bytes 61 MT(61) for the Logical DIMM associated with port A. Bytes 125 for port B, 189 for port C and 253 for port D</description> <valueType>uint8</valueType> <platInit/> + <writeable/> <odmVisable/> <array>2</array> - <writeable/> </attribute> <attribute> @@ -2403,9 +2755,9 @@ This Attribute is to be interpreted as an Integer</description> <description>This value comes from the VPD keyword MT byte 60 bits 4:7 for the Logical DIMM associated with port A. Byte 124 bits 4:7 for port B, 188 bits 4:7 for port C and 252 bits 4:7 for port D</description> <valueType>uint8</valueType> <platInit/> + <writeable/> <odmVisable/> <array>2</array> - <writeable/> </attribute> <attribute> @@ -2414,9 +2766,9 @@ This Attribute is to be interpreted as an Integer</description> <description>This value comes from the VPD keyword MT byte 60 bits 0:3 for the Logical DIMM associated with port A. Byte 124 bits 0:3 for port B, 188 bits 0:3 for port C and 252 bits 0:3 for port D</description> <valueType>uint8</valueType> <platInit/> + <writeable/> <odmVisable/> <array>2</array> - <writeable/> </attribute> <attribute> @@ -2497,6 +2849,7 @@ Comes from the VPD MW Keyword</description> <platInit/> <odmVisable/> <persistRuntime/> + <writeable/> </attribute> <attribute> @@ -2507,6 +2860,7 @@ Comes from the VPD MW Keyword</description> <platInit/> <odmVisable/> <persistRuntime/> + <writeable/> </attribute> <attribute> @@ -2517,6 +2871,7 @@ Comes from the VPD MW Keyword</description> <platInit/> <odmVisable/> <persistRuntime/> + <writeable/> </attribute> <attribute> @@ -2527,6 +2882,7 @@ Comes from the VPD MW Keyword</description> <platInit/> <odmVisable/> <persistRuntime/> + <writeable/> </attribute> <attribute> @@ -2542,6 +2898,70 @@ Data will be pulled from backplane VPD if IS DIMMs present.</description> </attribute> <attribute> + <id>ATTR_VPD_MT_VERSION_BYTE</id> + <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> + <description>Describes the Version of MT Keyword</description> + <valueType>uint8</valueType> + <platInit/> + <odmVisable/> + </attribute> + +<attribute> + <id>ATTR_VPD_MR_VERSION_BYTE</id> + <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> + <description>Describes the Version of MR Keyword</description> + <valueType>uint8</valueType> + <platInit/> + <odmVisable/> + </attribute> + + <attribute> + <id>ATTR_VPD_MR_DATA_CONTROL_BYTE</id> + <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> + <description>Describes the DATA control byte from MR</description> + <valueType>uint8</valueType> + <platInit/> + <odmVisable/> + </attribute> + + <attribute> + <id>ATTR_VPD_MT_DATA_CONTROL_BYTE</id> + <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> + <description>Describes the DATA control byte from MT</description> + <valueType>uint8</valueType> + <platInit/> + <odmVisable/> + </attribute> + + <attribute> + <id>ATTR_VPD_VM_KEYWORD</id> + <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> + <description>Fetches the VM Keyword</description> + <valueType>uint32</valueType> + <platInit/> + <odmVisable/> + </attribute> + + <attribute> + <id>ATTR_VPD_VD_KEYWORD</id> + <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> + <description>Fetch the VD keyword</description> + <valueType>uint32</valueType> + <platInit/> + <odmVisable/> + </attribute> + + <attribute> + <id>ATTR_VPD_DW_KEYWORD</id> + <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> + <description>Describes Centaur Voltage from DW keyword</description> + <valueType>uint32</valueType> + <platInit/> + <odmVisable/> + </attribute> + + +<attribute> <id>ATTR_SPD_MODSPEC_COM_REF_RAW_CARD_REV</id> <targetType>TARGET_TYPE_DIMM</targetType> <description> @@ -2568,5 +2988,92 @@ Data will be pulled from backplane VPD if IS DIMMs present.</description> <platInit/> </attribute> + <attribute> + <id>ATTR_VPD_POWER_CONTROL_CAPABLE</id> + <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> + <description>Capable power control settings.</description> + <valueType>uint8</valueType> + <enum>NONE = 0x00, SLOWEXIT_CAPABLE = 0x01, FASTEXIT_CAPABLE = 0x02, FASTSLOW_CAPABLE = 0x03</enum> + <platInit/> + <odmVisable/> + </attribute> + + <attribute> + <id>ATTR_VPD_DIMM_RCD_IBT</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>RCD IBT. Used in mss_dram_init and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each dimm will have a value. +creator: mss_eff_cnfg +consumer: mss_dram_init +firmware notes: none</description> + <valueType>uint32</valueType> + <enum>IBT_OFF = 0, IBT_100 = 100, IBT_150 = 150, IBT_200 = 200, IBT_300 = 300</enum> + <odmVisable/> + <odmChangeable/> + <array> 2 2</array> +</attribute> + + <attribute> + <id>ATTR_VPD_RD_CTR_WINDAGE_OFFSET</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Derived from calibration/characterization of read centering. Number of windage offset in units of pico-seconds[ps] with sign bit0 (0b0=positive, 0b1=negative) and value in bits1..31, so 0x80000023 for example would mean "-35ps". Can be overwritten by ODM vendors if done from VPD. Each port will have a value. +creator: VPD +consumer: mss_draminit_training_adv +firmware notes: none</description> + <valueType>uint32</valueType> + <platInit/> + <odmVisable/> + <odmChangeable/> + <array> 2</array> + <writeable/> +</attribute> + + +<attribute> + <id>ATTR_ISDIMM_MBVPD_INDEX</id> + <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> + <description>VPD index for associated chip's memory buffer VPD</description> + <valueType>uint8</valueType> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_CDIMM_VPD_MASTER_TOTAL_POWER_SLOPE</id> + <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> + <description>Master Total Power Slope that comes from the VPD MW Keyword</description> + <valueType>uint32</valueType> + <platInit/> + <odmVisable/> + <persistRuntime/> +</attribute> + +<attribute> + <id>ATTR_CDIMM_VPD_MASTER_TOTAL_POWER_INTERCEPT</id> + <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> + <description>Master Total Power Intercept that comes from the VPD MW Keyword</description> + <valueType>uint32</valueType> + <platInit/> + <odmVisable/> + <persistRuntime/> +</attribute> + +<attribute> + <id>ATTR_CDIMM_VPD_SUPPLIER_TOTAL_POWER_SLOPE</id> + <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> + <description>Supplier Total Power Slope that comes from the VPD MV Keyword</description> + <valueType>uint32</valueType> + <platInit/> + <odmVisable/> + <persistRuntime/> +</attribute> + +<attribute> + <id>ATTR_CDIMM_VPD_SUPPLIER_TOTAL_POWER_INTERCEPT</id> + <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> + <description>Supplier Total Power Intercept that comes from the VPD MV Keyword</description> + <valueType>uint32</valueType> + <platInit/> + <odmVisable/> + <persistRuntime/> +</attribute> </attributes> |
