diff options
Diffstat (limited to 'src/usr/hwpf/hwp/dram_training')
46 files changed, 0 insertions, 47076 deletions
diff --git a/src/usr/hwpf/hwp/dram_training/HBconfig b/src/usr/hwpf/hwp/dram_training/HBconfig deleted file mode 100644 index 56d064030..000000000 --- a/src/usr/hwpf/hwp/dram_training/HBconfig +++ /dev/null @@ -1,16 +0,0 @@ -config PALMETTO_VDDR - default n - help - Enable the Hostboot DRAM VDDR function for Palmetto - -config PCA95X_8BIT - default n - depends on (!PCA95X_16BIT) - help - Set the PCA95X support to an 8 bit chip. - -config PCA95X_16BIT - default y if (!PCA95X_8BIT) - depends on (!PCA95X_8BIT) - help - Set the PCA95X support to a 16 bit chip. diff --git a/src/usr/hwpf/hwp/dram_training/cen_stopclocks/cen_stopclocks.C b/src/usr/hwpf/hwp/dram_training/cen_stopclocks/cen_stopclocks.C deleted file mode 100644 index 4275e1e9e..000000000 --- a/src/usr/hwpf/hwp/dram_training/cen_stopclocks/cen_stopclocks.C +++ /dev/null @@ -1,1190 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/dram_training/cen_stopclocks/cen_stopclocks.C $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2013,2014 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: cen_stopclocks.C,v 1.16 2014/01/16 17:49:16 mfred Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/cen_stopclocks.C,v $ -//------------------------------------------------------------------------------ -// *! (C) Copyright International Business Machines Corp. 2011 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -//------------------------------------------------------------------------------ -// *! TITLE : cen_stopclocks -// *! DESCRIPTION : see additional comments below -// *! OWNER NAME : Mark Fredrickson Email: mfred@us.ibm.com -// *! BACKUP NAME : Mark Bellows Email: bellows@us.ibm.com -// *! SCREEN : pervasive_screen -// *! ADDITIONAL COMMENTS : -// -// The purpose of this procedure is to stop the clocks in the Centaur chip -// -//------------------------------------------------------------------------------ -// Don't forget to create CVS comments when you check in your changes! -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Includes -//------------------------------------------------------------------------------ -#include <cen_scom_addresses.H> -#include <cen_stopclocks.H> - -//------------------------------------------------------------------------------ -// Constant definitions -//------------------------------------------------------------------------------ -// CFAM FSI GP4 register bit/field definitions -const uint8_t FSI_GP4_MEMRESET_STABILITY_BIT = 2; -const uint8_t FSI_GP4_DPHY_PLLRESET_BIT = 4; - -// PERVGP3 register bit/field definitions -const uint8_t PERVGP3_VITL_CLKOFF_BIT = 16; - -// GP3 register bit/field definitions -const uint8_t GP3_VITAL_THOLD_BIT = 16; -const uint8_t GP3_FENCE_EN_BIT = 18; -const uint8_t GP3_EDRAM_ENABLE_BIT = 28; - -// GP0 register bit/field definitions -const uint8_t GP0_SYNCCLK_MUXSEL_BIT = 1; -const uint8_t GP0_FLUSHMODE_INHIBIT_BIT = 2; -const uint8_t GP0_FORCE_ALIGN_BIT = 3; -const uint8_t GP0_SCAN_DIS_DC_B_BIT = 6; -const uint8_t GP0_ABIST_MODE_BIT = 11; -const uint8_t GP0_PERV_FENCE_BIT = 63; - -// FSIGP3 register bit/field definitions -const uint8_t FSIGP3_PIB2PCB_BYPASS_BIT = 20; -const uint8_t FSIGP3_FSI_FENCE4_BIT = 25; -const uint8_t FSIGP3_FSI_FENCE5_BIT = 26; - -// Global bit definitions for all CLK_REGIONS -const uint8_t CLK_REGION_CLOCK_CMD_BIT = 0; -const uint8_t CLK_REGION_CLOCK_CMD_LEN = 2; -const uint8_t CLK_REGION_CLOCK_CMD_STOP = 2; - -const uint8_t TP_CLK_STAT_NET_SL = 3; -const uint8_t TP_CLK_STAT_NET_NSL = 4; -const uint8_t TP_CLK_STAT_NET_ARY = 5; -const uint8_t TP_CLK_STAT_PIB_SL = 6; -const uint8_t TP_CLK_STAT_PIB_NSL = 7; -const uint8_t TP_CLK_STAT_PIB_ARY = 8; - - -// Clock Region Register clock stop data patterns -// const uint64_t CLK_REGION_REG_DATA_TO_STOP_NSL_ARY = 0x8FE0060000000000ull; -const uint64_t CLK_REGION_REG_DATA_TO_STOP_ALL = 0x8FE00E0000000000ull; -// const uint64_t CLK_REGION_STOP_NSL_ARY_W_REFRESH = 0x8FC0060000000000ull; -const uint64_t CLK_REGION_STOP_ALL_BUT_REFRESH = 0x8FC00E0000000000ull; -const uint64_t EXPECTED_CLOCK_STATUS = 0xFFFFFFFFFFFFFFFFull; -const uint64_t EXPECTED_CLOCK_STATUS_W_REFRESH = 0xFFFFFF1FFFFFFFFFull; // Bits 24,25,26 should be OFF for refresh clocks to be active. - -// Expected CLK_STAT after execution of stopclocks -const uint32_t FSI_SHIFT_SET_PULSE_LENGTH = 0x0000000F; - - - - -extern "C" { - -using namespace fapi; - -//------------------------------------------------------------------------------ -// Function definition: cen_stopclocks -// parameters: i_target => chip target -// i_stop_mem_clks => True to stop MEM chiplet clocks (should default TRUE) -// i_stop_nest_clks => True to stop NEST chiplet clocks (except DRAM refresh clk) (should default TRUE) -// i_stop_dram_rfrsh_clks => True to stop NEST chiplet DRAM refresh clocks (cache) (should default FALSE) -// i_stop_tp_clks => True to stop PERVASIVE (TP) chiplet clocks (should default FALSE) -// i_stop_vitl_clks => True to stop PERVASIVE VITL clocks (should default FALSE) -// returns: FAPI_RC_SUCCESS if operation was successful, else error -//------------------------------------------------------------------------------ -fapi::ReturnCode cen_stopclocks(const fapi::Target & i_target, - const bool i_stop_mem_clks, - const bool i_stop_nest_clks, - const bool i_stop_dram_rfrsh_clks, - const bool i_stop_tp_clks, - const bool i_stop_vitl_clks) -{ - // Target is centaur chip - - bool i2_stop_mem_clks; - bool i2_stop_nest_clks; - fapi::ReturnCode rc; - uint32_t rc_ecmd = 0; - ecmdDataBufferBase scom_data(64); - ecmdDataBufferBase cfam_data(32); - - FAPI_INF("********* cen_stopclocks start *********"); - do - { - // The instructions for coding this procedure came from Tobias Webel's Common POR Spreadsheet step 30.1 - // Start with instructions common to all eclipz chips - - // Set flushmode_inhibit in Chiplet GP0 - // Set force_align in Chiplet GP0 - // Write ClockControl, Scan Region Register, set all bits to zero prior clock stop - // Write ClockControl, Clock Region Register, Clock Stop command (arrays + nsl only, not refresh clock region) MEM chiplet - // Write ClockControl, Clock Region Register, Clock Stop command (sl + refresh clock region) MEM chiplet - // Read Clock Status Register (MEM chiplet) - // Write ClockControl, Clock Region Register, Clock Stop command (arrays + nsl only, not refresh clock region) NEST chiplet - // Write ClockControl, Clock Region Register, Clock Stop command (sl + refresh clock region) NEST chiplet - // Read Clock Status Register (NEST chiplet) - // Reset MemReset Stablilty Control - // Reset D3PHY PLL Control (Reset all PLLs) - // reset abist_mode_dc for core chiplets (core recovery) - // set synclk_muxsel (io_clk_sel) - // assert perv fence GP0.63 - // GP3(28) disable EDRAM (just chiplets with EDRAM logic)(skip this step if refresh clock domain stays running) - // assert fence GP3.18 - - // The following instructions were added by Jeshua Smith to put each chiplet in a good state for scanning: - // Set tc_scan_dis_dc_b to a '1' in each chiplet to allow rings to be scanned. - // TODO - compare these instructions agains the P7+ procedure to see if we are missing anything. - - // Note: This procedure should not do multicast to do all non-perv chiplets at the same time because the user could - // wish to skip some of the chiplets! - - - - - //----------------- - // Check options, VITL clock and PCB fabric clocks. @@@ - //----------------- - - i2_stop_mem_clks = i_stop_mem_clks; - i2_stop_nest_clks = i_stop_nest_clks; - - // Before attempting to stop the clocks in any chiplet, check to see that the pervasive VITL clocks are running. - // Do this by checking bit 16 of the PERV GP3 register. - FAPI_DBG("Checking PERV GPP3 Register bit 16 to see if the VITL clock is ON."); - rc = fapiGetCfamRegister(i_target, CFAM_FSI_GP3_MIRROR_0x0000101B, cfam_data); - if (rc) - { - FAPI_ERR("Error getting PERV GP3 via CFAM"); - break; - } - if (cfam_data.isBitSet(PERVGP3_VITL_CLKOFF_BIT)) - { - // The Pervasive VITL clock is OFF. So we cannot talk to the chiplets. There is nothing left to do, so just return. - FAPI_INF("The Pervasive VITL clock is OFF. The procedure cannot access the chiplets or check other clocks."); - break; - } - - // If we have gotten this far the Pervasive VITL clock must be ON. - // Check to see if the PCB fabric clocks are running. - // Do this by checking the PIB and NET clock regions in the TP chiplet (chiplet 01). - // Read Clock Status Register (TP chiplet) 0x0100008 - // Bits 3-8 should be ZERO if the PIB and NET clocks are running. - FAPI_DBG("Reading Clock Status Register in the TP chiplet to see if PIB and NET clocks are running. Bits 3-8 should be zero."); - rc = fapiGetScom( i_target, TP_CLK_STATUS_0x01030008, scom_data); - if (rc) - { - FAPI_ERR("Error reading TP chiplet Clock Status Register."); - break; - } - if ( scom_data.isBitSet(TP_CLK_STAT_NET_SL) || - scom_data.isBitSet(TP_CLK_STAT_NET_NSL) || - scom_data.isBitSet(TP_CLK_STAT_NET_ARY) || - scom_data.isBitSet(TP_CLK_STAT_PIB_SL) || - scom_data.isBitSet(TP_CLK_STAT_PIB_NSL) || - scom_data.isBitSet(TP_CLK_STAT_PIB_ARY) ) - { - // At least one of the NET or PIB clocks is NOT running. - FAPI_INF("At least one of the NET or PIB clocks is NOT running. May not be able to use the PCB fabric to access chiplets."); - FAPI_INF("Procedure will not attempt to turn off clocks in the individual chiplets.."); - i2_stop_mem_clks = false; - i2_stop_nest_clks = false; - } - - FAPI_INF(" Input parameters: "); - FAPI_INF(" stop_mem_clks = %s", i2_stop_mem_clks ? "true":"false"); - FAPI_INF(" stop_nest_clks = %s", i2_stop_nest_clks ? "true":"false"); - FAPI_INF(" stop_dram_rfrsh_clks = %s", i_stop_dram_rfrsh_clks ? "true":"false"); - FAPI_INF(" stop_tp_clks = %s", i_stop_tp_clks ? "true":"false"); - FAPI_INF(" stop_vitl_clks = %s", i_stop_vitl_clks ? "true":"false"); - - if ((!i2_stop_mem_clks) && - (!i2_stop_nest_clks) && - (!i_stop_tp_clks) && - (!i_stop_vitl_clks)) - { - FAPI_INF("Specified input options are set to skip both the NEST and MEM chiplets, so there is nothing to do. Returning."); - break; - } - - //----------------- - // MEM Chiplet @@@ 03 - //----------------- - if ( i2_stop_mem_clks ) - { - // FW team requested that we check to see if the vital clock region is running before stopping the clocks. - // If the vital clocks are not running, then other clocks are not running either, so we are done. - // If the vital clocks are running, then we should be able to access the necessary registers to stop the other clocks. - FAPI_DBG("Reading GP3 Register, bit 16, to see if VITAL clocks are running."); - rc = fapiGetScom( i_target, MEM_GP3_0x030F0012, scom_data); - if (rc) - { - FAPI_ERR("Error reading GP3 register in attempt to verify that VITAL clocks are running."); - break; - } - if (scom_data.isBitSet(GP3_VITAL_THOLD_BIT)) - { - // The VITAL thold is asserted, so no clocks are running in this chiplet. Nothing left to do, so just return. - FAPI_INF("The VITAL clocks are not running for this chiplet, so all other clocks should be already stopped."); - } - else - { - - // Start with instructions common to eclipz chips - - // Set flushmode_inhibit in Chiplet GP0 - // multicast address "0x[xx]00 0005 WOR codepoint" Data: bit(2) = 0b1 (0x2000 0000 0000 0000) - // MEM_GP0_OR_0x03000005 - FAPI_DBG("Setting flushmode_inhibit in MEM chiplet GP0 Register (bit 2)."); - rc_ecmd |= scom_data.flushTo0(); - rc_ecmd |= scom_data.setBit(GP0_FLUSHMODE_INHIBIT_BIT); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to set flushmode_inhibit in MEM chiplet GP0 Register.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom( i_target, MEM_GP0_OR_0x03000005, scom_data); - if (rc) - { - FAPI_ERR("Error writing GP0 registers in MEM chiplet to set flushmode inhibit (bit 2)."); - break; - } - - - // Set force_align in Chiplet GP0 - // multicast address "0x[xx]00 0005 WOR codepoint" Data: bit(3) = 0b1 (0x1000 0000 0000 0000) Cannot combine with previous step. - // MEM_GP0_OR_0x03000005 - FAPI_DBG("Setting force_align in MEM chiplet GP0 register (bit 3)."); - rc_ecmd |= scom_data.flushTo0(); - rc_ecmd |= scom_data.setBit(GP0_FORCE_ALIGN_BIT); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to Set force_align in MEM chiplet.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom( i_target, MEM_GP0_OR_0x03000005, scom_data); - if (rc) - { - FAPI_ERR("Error writing GP0 registers in MEM chiplet to set force_align (bit 3)."); - break; - } - - - // Write ClockControl, Scan Region Register, set all bits to zero prior clock stop - // multicast address 0x[xx]03 0007 Data: 0x0000 0000 0000 0000 - // MEM_CLK_SCANSEL_0x03030007 - FAPI_DBG("Writing Clock Control Scan Region Register to all zeros in MEM chiplet prior clock stop."); - rc_ecmd |= scom_data.flushTo0(); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to write CC Scan Region Register to all zeros..", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom( i_target, MEM_CLK_SCANSEL_0x03030007, scom_data); - if (rc) - { - FAPI_ERR("Error writing CC Scan Region Registers in MEM chiplet."); - break; - } - - - // Now do Centaur-specific instructions - - - - // Write ClockControl, Clock Region Register, Clock Stop command for MEM chiplet - // 0x0303 0006 Data: 0x8FE00E0000000000 - // MEM_CLK_REGION_0x03030006 - FAPI_DBG("Writing Clock Control Clock Region Register in MEM chiplet to stop the clocks."); - rc_ecmd |= scom_data.setDoubleWord(0, CLK_REGION_REG_DATA_TO_STOP_ALL); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to set general clock stop command in MEM chiplet CC Clock Region Register.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom( i_target, MEM_CLK_REGION_0x03030006, scom_data); - if (rc) - { - FAPI_ERR("Error writing MEM chiplet CC Clock Region Register to stop the clocks."); - break; - } - - - // Read Clock Status Register (MEM chiplet) - // 0x0303 0008 Data: expected value: 0xFFFF FFFF FFFF FFFF - // MEM_CLK_STATUS_0x03030008 - FAPI_DBG("Reading Clock Status Register in the MEM chiplet to see if clocks are stopped. Expected value = 0xFFFF FFFF FFFF FFFF."); - rc = fapiGetScom( i_target, MEM_CLK_STATUS_0x03030008, scom_data); - if (rc) - { - FAPI_ERR("Error reading MEM chiplet Clock Status Register."); - break; - } - uint64_t clock_status = scom_data.getDoubleWord(0); - if ( clock_status != EXPECTED_CLOCK_STATUS ) - { - FAPI_ERR("MEM chiplet clock status 0x%016llX was expected but read clock status = 0x%016llX", - EXPECTED_CLOCK_STATUS, clock_status); - const uint64_t & EXPECTED_STATUS = EXPECTED_CLOCK_STATUS; - const uint64_t & ACTUAL_STATUS = clock_status; - const fapi::Target & MEMBUF_CHIP_IN_ERROR = i_target; - FAPI_SET_HWP_ERROR(rc, RC_MSS_UNEXPECTED_MEM_CLOCK_STATUS); - break; - } - else - { - FAPI_INF("Expected clock status was read in MEM chiplet after stopping the clocks: 0x%016llX ", EXPECTED_CLOCK_STATUS); - } - - - - // Reset MemReset Stablilty Control - // CFAM 0x13 bit(02) = 0 - // CFAM_FSI_GP4_0x00001013 - FAPI_DBG("Clearing CFAM FSI GP4 Register, bit 2 to reset MemReset Stablilty Control."); - rc = fapiGetCfamRegister( i_target, CFAM_FSI_GP4_0x00001013, cfam_data); - if (rc) - { - FAPI_ERR("Error reading CFAM FSI GP4 Register."); - break; - } - rc_ecmd |= cfam_data.clearBit(FSI_GP4_MEMRESET_STABILITY_BIT); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to set MemReset Stability Control (FSI GP4 bit 2).", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutCfamRegister( i_target, CFAM_FSI_GP4_0x00001013, cfam_data); - if (rc) - { - FAPI_ERR("Error writing FSI GP4 Register to reset the MemReset Stability Control (bit2)."); - break; - } - - - // Reset D3PHY PLL Control (Reset all D3PHY PLLs) - // CFAM 0x13 bit(04) = 0 - // CFAM_FSI_GP4_0x00001013 - FAPI_DBG("Clearing CFAM FSI GP4 Register, bit 4 to reset D3PHY PLL Control (Reset all D3PHY PLLs)."); - rc = fapiGetCfamRegister( i_target, CFAM_FSI_GP4_0x00001013, cfam_data); - if (rc) - { - FAPI_ERR("Error reading CFAM FSI GP4 register."); - break; - } - rc_ecmd |= cfam_data.clearBit(FSI_GP4_DPHY_PLLRESET_BIT); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to reset the D3PHY PLLs .", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutCfamRegister( i_target, CFAM_FSI_GP4_0x00001013, cfam_data); - if (rc) - { - FAPI_ERR("Error writing FSI GP4 register to reset the D3PHY PLLs (by clearing bit 4)."); - break; - } - - - // Resume instructions that are common to eclipz chips. - - - // reset abist_mode_dc for core chiplets (core recovery) - // Does this make sense for Centaur? (Centaur has no cores.) - // Multicast address: "0x[xx]00 0004 WAND codepoint" Data: bit(11) = 0b0 0xFFEF FFFF FFFF FFFF - // MEM_GP0_AND_0x03000004 - FAPI_DBG("Clearing GP0 Register bit 11 in MEM chiplet to reset abist_mode_dc."); - rc_ecmd |= scom_data.flushTo1(); - rc_ecmd |= scom_data.clearBit(GP0_ABIST_MODE_BIT); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to clear bit 11 of the GP0 registers in the MEM chiplet.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom( i_target, MEM_GP0_AND_0x03000004, scom_data); - if (rc) - { - FAPI_ERR("Error writing the GP0 registers in the MEM chiplet to reset abist mode.."); - break; - } - - - // set synclk_muxsel (io_clk_sel) - // Multicast address: "0x[xx]00 0005 WOR codepoint" bit(1) = 0b1 0x4000 0000 0000 0000 - // MEM_GP0_OR_0x03000005 - // assert perv fence GP0.63 - // Multicast address: "0x[xx]00 0005 WOR codepoint" bit(63) = 0b1 0x4000 0000 0000 0001 (Can be combined with previous step) - // MEM_GP0_OR_0x03000005 - FAPI_DBG("Setting GP0 Register bit 1 in MEM chiplet to set synclk_muxsel (io_clk_sel)."); - FAPI_DBG("Setting GP0 Register bit 63 in MEM chiplet to assert the pervasive fence."); - rc_ecmd |= scom_data.flushTo0(); - rc_ecmd |= scom_data.setBit(GP0_SYNCCLK_MUXSEL_BIT); - rc_ecmd |= scom_data.setBit(GP0_PERV_FENCE_BIT); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to set syncclk_muxsel and pervasive fence in GP0 registers..", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom( i_target, MEM_GP0_OR_0x03000005, scom_data); - if (rc) - { - FAPI_ERR("Error writing GP0 registers in MEM chiplet to set syncclk_muxsel and pervasive fence.."); - break; - } - - - // GP3(28) disable EDRAM (just chiplets with EDRAM logic) - // Note: This action is probably un-needed for the MEM chiplet since it does not contain any EDRAM. - // Multicast address: "0x[xx]0F 0013 WAND codepoint" bit(28) = 0b0 0xFFFF FFF7 FFFF FFFF - // MEM_GP3_AND_0x030F0013 - FAPI_DBG("Clearing GP3 Register bit 28 in MEM chiplet to disable any EDRAM."); - rc_ecmd |= scom_data.flushTo1(); - rc_ecmd |= scom_data.clearBit(GP3_EDRAM_ENABLE_BIT); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to clear GP3(bit 28), to disable EDRAM in MEM chiplet.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom( i_target, MEM_GP3_AND_0x030F0013, scom_data); - if (rc) - { - FAPI_ERR("Error writing GP3 Registers in MEM chiplet to disable any EDRAM."); - break; - } - - - // assert fence GP3.18 - // Multicast address: "0x[xx]0F 0014 WOR codepoint" bit(18) = 0b1 0x0000 2000 0000 0000 - // MEM_GP3_OR_0x030F0014 - FAPI_DBG("Setting GP3 Regsiter bit 18 in MEM chiplet to assert the fence."); - rc_ecmd |= scom_data.flushTo0(); - rc_ecmd |= scom_data.setBit(GP3_FENCE_EN_BIT); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to set GP3(bit18) to assert the fence in the MEM chiplet.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom( i_target, MEM_GP3_OR_0x030F0014, scom_data); - if (rc) - { - FAPI_ERR("Error writing GP3 registers in MEM chiplet to assert the fence."); - break; - } - - // Set scan_dis_dc_b bit in Chiplet GP0 - // unicast address "0x[xx]00 0005 WOR codepoint" Data: bit(6) = 0b1 (0x0200 0000 0000 0000) - // MEM_GP0_OR_0x03000005 - FAPI_DBG("Setting MEM chiplet GP0 Register bit 6 to set scan_dis_dc_b to allow for scanning."); - rc_ecmd |= scom_data.flushTo0(); - rc_ecmd |= scom_data.setBit(GP0_SCAN_DIS_DC_B_BIT); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to set scan_dis_dc_b in MEM chiplet.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom( i_target, MEM_GP0_OR_0x03000005, scom_data); - if (rc) - { - FAPI_ERR("Error writing MEM chiplet GP0 register to set scan_dis_dc_b for scanning."); - break; - } - } // End of stop clock operations that are done if the vital clock is running. - } // End of MEM chiplet code - - - //----------------- - // NEST Chiplet @@@ 02 - //----------------- - if ( i2_stop_nest_clks ) - { - // FW team requested that we check to see if the vital clock region is running before stopping the clocks. - // If the vital clocks are not running, then other clocks are not running either, so we are done. - // If the vital clocks are running, then we should be able to access the necessary registers to stop the other clocks. - FAPI_DBG("Reading GP3 Register, bit 16, to see if VITAL clocks are running."); - rc = fapiGetScom( i_target, NEST_GP3_0x020F0012, scom_data); - if (rc) - { - FAPI_ERR("Error reading GP3 register in attempt to verify that VITAL clocks are running."); - break; - } - if (scom_data.isBitSet(GP3_VITAL_THOLD_BIT)) - { - // The VITAL thold is asserted, so no clocks are running in this chiplet. Nothing left to do, so just return. - FAPI_INF("The VITAL clocks are not running for this chiplet, so all other clocks should be already stopped."); - } - else - { - - // Start with instructions common to eclipz chips - - // Set flushmode_inhibit in Chiplet GP0 - // multicast address "0x[xx]00 0005 WOR codepoint" Data: bit(2) = 0b1 (0x2000 0000 0000 0000) - // NEST_GP0_OR_0x02000005 - FAPI_DBG("Setting flushmode_inhibit in NEST chiplet GP0 Register (bit 2)."); - rc_ecmd |= scom_data.flushTo0(); - rc_ecmd |= scom_data.setBit(GP0_FLUSHMODE_INHIBIT_BIT); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to set flushmode_inhibit in NEST chiplet GP0 Register.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom( i_target, NEST_GP0_OR_0x02000005, scom_data); - if (rc) - { - FAPI_ERR("Error writing GP0 registers in NEST chiplet to set flushmode inhibit (bit 2)."); - break; - } - - - // Set force_align in Chiplet GP0 - // multicast address "0x[xx]00 0005 WOR codepoint" Data: bit(3) = 0b1 (0x1000 0000 0000 0000) Cannot combine with previous step. - // NEST_GP0_OR_0x02000005 - FAPI_DBG("Setting force_align in NEST chiplet GP0 register (bit 3)."); - rc_ecmd |= scom_data.flushTo0(); - rc_ecmd |= scom_data.setBit(GP0_FORCE_ALIGN_BIT); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to Set force_align in NEST chiplet.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom( i_target, NEST_GP0_OR_0x02000005, scom_data); - if (rc) - { - FAPI_ERR("Error writing GP0 registers in NEST chiplet to set force_align (bit 3)."); - break; - } - - - // Write ClockControl, Scan Region Register, set all bits to zero prior clock stop - // multicast address 0x[xx]03 0007 Data: 0x0000 0000 0000 0000 - // NEST_CLK_SCANSEL_0x02030007 - FAPI_DBG("Writing Clock Control Scan Region Register to all zeros in NEST chiplet prior clock stop."); - rc_ecmd |= scom_data.flushTo0(); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to write CC Scan Region Register to all zeros..", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom( i_target, NEST_CLK_SCANSEL_0x02030007, scom_data); - if (rc) - { - FAPI_ERR("Error writing CC Scan Region Registers in NEST chiplet."); - break; - } - - - // Now do Centaur-specific instructions - - - - // Write ClockControl, Clock Region Register, Clock Stop command for NEST chiplet - // 0x0203 0006 Data: 0x8FE00E0000000000 - // NEST_CLK_REGION_0x02030006 - FAPI_DBG("Writing Clock Control Clock Region Register in NEST chiplet to stop the clocks."); - if ( i_stop_dram_rfrsh_clks ) - { - rc_ecmd |= scom_data.setDoubleWord(0, CLK_REGION_REG_DATA_TO_STOP_ALL); - } - else - { - rc_ecmd |= scom_data.setDoubleWord(0, CLK_REGION_STOP_ALL_BUT_REFRESH ); - } - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to set general clock stop command in NEST chiplet CC Clock Region Register.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom( i_target, NEST_CLK_REGION_0x02030006, scom_data); - if (rc) - { - FAPI_ERR("Error writing NEST chiplet CC Clock Region Register to stop the clocks."); - break; - } - - - // Read Clock Status Register (NEST chiplet) - // 0x0203 0008 Data: expected value: 0xFFFF FFFF FFFF FFFF - // NEST_CLK_STATUS_0x02030008 - if ( i_stop_dram_rfrsh_clks ) - { - FAPI_DBG("Reading Clock Status Register in the NEST chiplet to see if clocks are stopped. Expected value = 0xFFFF FFFF FFFF FFFF."); - rc = fapiGetScom( i_target, NEST_CLK_STATUS_0x02030008, scom_data); - if (rc) - { - FAPI_ERR("Error reading NEST chiplet Clock Status Register."); - break; - } - uint64_t clock_status = scom_data.getDoubleWord(0); - if ( clock_status != EXPECTED_CLOCK_STATUS ) - { - FAPI_ERR("NEST chiplet clock status 0x%016llX was expected but read clock status = 0x%016llX", - EXPECTED_CLOCK_STATUS, clock_status); - const uint64_t & EXPECTED_STATUS = EXPECTED_CLOCK_STATUS; - const uint64_t & ACTUAL_STATUS = clock_status; - const fapi::Target & MEMBUF_CHIP_IN_ERROR = i_target; - FAPI_SET_HWP_ERROR(rc, RC_MSS_UNEXPECTED_NEST_CLOCK_STATUS); - break; - } - else - { - FAPI_INF("Expected clock status was read in NEST chiplet after stopping the clocks: 0x%016llX ", EXPECTED_CLOCK_STATUS); - } - } - else - { - FAPI_DBG("Reading Clock Status Register in the NEST chiplet to see if clocks are stopped. Expected value = 0xFFFF FF1F FFFF FFFF."); - rc = fapiGetScom( i_target, NEST_CLK_STATUS_0x02030008, scom_data); - if (rc) - { - FAPI_ERR("Error reading NEST chiplet Clock Status Register."); - break; - } - uint64_t clock_status = scom_data.getDoubleWord(0); - if ( clock_status != EXPECTED_CLOCK_STATUS_W_REFRESH ) - { - FAPI_ERR("NEST chiplet clock status 0x%016llX was expected but read clock status = 0x%016llX", - EXPECTED_CLOCK_STATUS_W_REFRESH, clock_status); - const uint64_t & EXPECTED_STATUS = EXPECTED_CLOCK_STATUS_W_REFRESH; - const uint64_t & ACTUAL_STATUS = clock_status; - const fapi::Target & MEMBUF_CHIP_IN_ERROR = i_target; - FAPI_SET_HWP_ERROR(rc, RC_MSS_UNEXPECTED_NEST_CLOCK_STATUS); - break; - } - else - { - FAPI_INF("Expected clock status was read in NEST chiplet after stopping the clocks: 0x%016llX ", EXPECTED_CLOCK_STATUS_W_REFRESH); - } - } - - - // Resume instructions that are common to eclipz chips. - - - // reset abist_mode_dc for core chiplets (core recovery) - // Does this make sense for Centaur? (Centaur has no cores.) - // Multicast address: "0x[xx]00 0004 WAND codepoint" Data: bit(11) = 0b0 0xFFEF FFFF FFFF FFFF - // NEST_GP0_AND_0x02000004 - FAPI_DBG("Clearing GP0 Register bit 11 in NEST chiplet to reset abist_mode_dc."); - rc_ecmd |= scom_data.flushTo1(); - rc_ecmd |= scom_data.clearBit(GP0_ABIST_MODE_BIT); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to clear bit 11 of the GP0 registers in the NEST chiplet.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom( i_target, NEST_GP0_AND_0x02000004, scom_data); - if (rc) - { - FAPI_ERR("Error writing the GP0 registers in the NEST chiplet to reset abist mode.."); - break; - } - - - // set synclk_muxsel (io_clk_sel) - // Multicast address: "0x[xx]00 0005 WOR codepoint" bit(1) = 0b1 0x4000 0000 0000 0000 - // NEST_GP0_OR_0x02000005 - // assert perv fence GP0.63 - // Multicast address: "0x[xx]00 0005 WOR codepoint" bit(63) = 0b1 0x4000 0000 0000 0001 (Can be combined with previous step) - // NEST_GP0_OR_0x02000005 - FAPI_DBG("Setting GP0 Register bit 1 in NEST chiplet to set synclk_muxsel (io_clk_sel)."); - FAPI_DBG("Setting GP0 Register bit 63 in NEST chiplet to assert the pervasive fence."); - rc_ecmd |= scom_data.flushTo0(); - rc_ecmd |= scom_data.setBit(GP0_SYNCCLK_MUXSEL_BIT); - rc_ecmd |= scom_data.setBit(GP0_PERV_FENCE_BIT); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to set syncclk_muxsel and pervasive fence in GP0 registers..", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom( i_target, NEST_GP0_OR_0x02000005, scom_data); - if (rc) - { - FAPI_ERR("Error writing GP0 registers in NEST chiplet to set syncclk_muxsel and pervasive fence.."); - break; - } - - - // GP3(28) disable EDRAM (just chiplets with EDRAM logic) - // Note: (skip this step if refresh clock domain stays running) - // Multicast address: "0x[xx]0F 0013 WAND codepoint" bit(28) = 0b0 0xFFFF FFF7 FFFF FFFF - // NEST_GP3_AND_0x020F0013 - if ( i_stop_dram_rfrsh_clks ) - { - FAPI_DBG("Clearing GP3 Register bit 28 in NEST chiplet to disable any EDRAM."); - rc_ecmd |= scom_data.flushTo1(); - rc_ecmd |= scom_data.clearBit(GP3_EDRAM_ENABLE_BIT); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to clear GP3(bit 28), to disable EDRAM in NEST chiplet.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom( i_target, NEST_GP3_AND_0x020F0013, scom_data); - if (rc) - { - FAPI_ERR("Error writing GP3 Registers in NEST chiplet to disable any EDRAM."); - break; - } - } - - - // assert fence GP3.18 - // Multicast address: "0x[xx]0F 0014 WOR codepoint" bit(18) = 0b1 0x0000 2000 0000 0000 - // NEST_GP3_OR_0x020F0014 - FAPI_DBG("Setting GP3 Regsiter bit 18 in NEST chiplet to assert the fence."); - rc_ecmd |= scom_data.flushTo0(); - rc_ecmd |= scom_data.setBit(GP3_FENCE_EN_BIT); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to set GP3(bit18) to assert the fence in the NEST chiplet.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom( i_target, NEST_GP3_OR_0x020F0014, scom_data); - if (rc) - { - FAPI_ERR("Error writing GP3 registers in NEST chiplet to assert the fence."); - break; - } - - // Set scan_dis_dc_b bit in Chiplet GP0 - // unicast address "0x[xx]00 0005 WOR codepoint" Data: bit(6) = 0b1 (0x0200 0000 0000 0000) - // NEST_GP0_OR_0x02000005 - FAPI_DBG("Setting NEST chiplet GP0 Register bit 6 to set scan_dis_dc_b to allow for scanning."); - rc_ecmd |= scom_data.flushTo0(); - rc_ecmd |= scom_data.setBit(GP0_SCAN_DIS_DC_B_BIT); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to set scan_dis_dc_b in NEST chiplet.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom( i_target, NEST_GP0_OR_0x02000005, scom_data); - if (rc) - { - FAPI_ERR("Error writing NEST chiplet GP0 register to set scan_dis_dc_b for scanning."); - break; - } - } // End of stop clock operations that are done if the vital clock is running. - } // End of NEST chiplet code - - - - //----------------- - // TP Chiplet @@@ 01 - //----------------- - - if (i_stop_tp_clks) - { - - // Set the length of the FSI shifter set pulse - // Do this in the CFAM FSI SHIFT_CONTROL_REGISTER_2. - FAPI_DBG("Setting length of the set pulse in the FSI SHIFT_CONTROL_REGISTER_2."); - rc_ecmd |= cfam_data.setWord(0,FSI_SHIFT_SET_PULSE_LENGTH); //Set cfam_data to 0x0000000F - if(rc_ecmd) - { - FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase for CFAM operation", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutCfamRegister(i_target, CFAM_FSI_SHIFT_CTRL_0x00000C10, cfam_data); - if (rc) - { - FAPI_ERR("Error attempting to set length of the set pulse in the FSI SHIFT_CONTROL_REGISTER_2."); - break; - } - - - // Go into PIB2PCB bypass path - // Set this in CFAM GP3 register. Read the register first to preserve other contents. - FAPI_DBG("Setting FSI GP3 bit 20 to go into PIB2PCB bypass."); - rc = fapiGetCfamRegister(i_target, CFAM_FSI_GP3_0x00001012, cfam_data); - if (rc) - { - FAPI_ERR("Error getting FSI_GP3 via CFAM"); - break; - } - rc_ecmd |= cfam_data.setBit(FSIGP3_PIB2PCB_BYPASS_BIT); //Set bit 20 to go into PIB2PCB bypass - if(rc_ecmd) - { - FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase for CFAM operation", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutCfamRegister(i_target, CFAM_FSI_GP3_0x00001012, cfam_data); - if (rc) - { - FAPI_ERR("Error attempting to go into PIB2PCB bypass."); - break; - } - - - // Set flushmode_inhibit in Chiplet GP0 - // unicast address "0x[xx]00 0005 WOR codepoint" Data: bit(2) = 0b1 (0x2000 0000 0000 0000) - // TP_GP0_OR_0x01000005 - FAPI_DBG("Setting TP chiplet GP0 Register bit 2 to set flushmode_inhibit."); - rc_ecmd |= scom_data.flushTo0(); - rc_ecmd |= scom_data.setBit(GP0_FLUSHMODE_INHIBIT_BIT); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to set flushmode_inhibit in TP chiplet.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom( i_target, TP_GP0_OR_0x01000005, scom_data); - if (rc) - { - FAPI_ERR("Error writing TP chiplet GP0 register to set flushmode inhibit."); - break; - } - - // Set force_align in Chiplet GP0 - // unicast address "0x[xx]00 0005 WOR codepoint" Data: bit(3) = 0b1 (0x1000 0000 0000 0000) Cannot combine with previous step. - // TP_GP0_OR_0x01000005 - FAPI_DBG("Setting TP chiplet GP0 Register bit 3 to set force_align."); - rc_ecmd |= scom_data.flushTo0(); - rc_ecmd |= scom_data.setBit(GP0_FORCE_ALIGN_BIT); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to set force_align in TP chiplet.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom( i_target, TP_GP0_OR_0x01000005, scom_data); - if (rc) - { - FAPI_ERR("Error writing TP chiplet GP0 register to set force_align."); - break; - } - - // Write ClockControl, Scan Region Register, set all bits to zero prior clock stop - // unicast address 0x[xx]03 0007 Data: 0x0000 0000 0000 0000 - // TP_CLK_SCANSEL_0x01030007 - FAPI_DBG("Writing TP chiplet Clock Control Scan Region Register to all zeros prior clock stop."); - rc_ecmd |= scom_data.flushTo0(); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to write CC Scan Region Register to all zeros in TP chiplet.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom( i_target, TP_CLK_SCANSEL_0x01030007, scom_data); - if (rc) - { - FAPI_ERR("Error writing TP chiplet CC Scan Region Register."); - break; - } - - // Write ClockControl, Clock Region Register, Clock Stop command (arrays + nsl only, not refresh clock region) TP chiplet - // TP_CLK_REGION_0x01030006 - FAPI_DBG("Writing Clock Control Clock Region Register in TP chiplet to stop the clocks."); - rc_ecmd |= scom_data.flushTo1(); - rc_ecmd |= scom_data.insertFromRight(CLK_REGION_CLOCK_CMD_STOP, - CLK_REGION_CLOCK_CMD_BIT, - CLK_REGION_CLOCK_CMD_LEN); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to set general clock stop command in TP chiplet CC Clock Region Register.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom( i_target, TP_CLK_REGION_0x01030006, scom_data); - if (rc) - { - FAPI_ERR("Error writing TP chiplet CC Clock Region Register to stop the clocks."); - break; - } - - // Read Clock Status Register (TP chiplet) - // 0x0103 0008 Data: expected value: FFFFFFFFFFFFFFFF - // TP_CLK_STATUS_0x01030008 - FAPI_DBG("Reading Clock Status Register in the TP chiplet to see if clocks are stopped. Expected value = 0x%016llX.", EXPECTED_CLOCK_STATUS); - rc = fapiGetScom( i_target, TP_CLK_STATUS_0x01030008, scom_data); - if (rc) - { - FAPI_ERR("Error reading TP chiplet Clock Status Register."); - break; - } - uint64_t clock_status = scom_data.getDoubleWord(0); - if ( clock_status != EXPECTED_CLOCK_STATUS ) - { - FAPI_ERR("TP chiplet clock status 0x%016llX was expected but read clock status = 0x%016llX.", - EXPECTED_CLOCK_STATUS, clock_status); - const uint64_t & EXPECTED_STATUS = EXPECTED_CLOCK_STATUS; - const uint64_t & ACTUAL_STATUS = clock_status; - const fapi::Target & MEMBUF_CHIP_IN_ERROR = i_target; - FAPI_SET_HWP_ERROR(rc, RC_MSS_UNEXPECTED_TP_CLOCK_STATUS); - break; - } - else - { - FAPI_INF("Expected clock status was read in TP chiplet after stopping the clocks: 0x%016llX ", EXPECTED_CLOCK_STATUS); - } - - - // Set L3 EDRAM fence in chiplet by setting bit(19) in chiplet GP0 registers (Fence only exists in EX chiplets.) - - - // Resume instructions that are common to all eclipz chips. - - - // reset abist_mode_dc for core chiplets only (core recovery) - - - // set synclk_muxsel (io_clk_sel) - // Unicast address: "0x[xx]00 0005 WOR codepoint" bit(1) = 0b1 0x4000 0000 0000 0000 - // TP_GP0_OR_0x01000005 - // assert perv fence GP0.63 - // Unicast address: "0x[xx]00 0005 WOR codepoint" bit(63) = 0b1 0x4000 0000 0000 0001 (Can be combined with previous step) - // TP_GP0_OR_0x01000005 - FAPI_DBG("Setting TP chiplet GP0 Register bit 1 to set synclk_muxsel (io_clk_sel)."); - FAPI_DBG("Setting TP chiplet GP0 Register bit 63 to assert the pervasive fence."); - rc_ecmd |= scom_data.flushTo0(); - rc_ecmd |= scom_data.setBit(GP0_SYNCCLK_MUXSEL_BIT); - rc_ecmd |= scom_data.setBit(GP0_PERV_FENCE_BIT); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to set syncclk_muxsel and pervasive fence in TP chiplet.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom( i_target, TP_GP0_OR_0x01000005, scom_data); - if (rc) - { - FAPI_ERR("Error writing TP chiplet GP0 register to set syncclk_muxsel and pervasive fence.."); - break; - } - - - // GP3(28) disable EDRAM (just chiplets with EDRAM logic) - - - // Instruction from Johannes Koesters 12 Sept, 2013 - // Leave this commented out for now. Seems to cause problems if we set the fence on the TP chiplet. - // - // Change this to use PERV GP3 Register (CFAM 101B) (Normal GP3 reg N/A in TP chiplet) ? - //// assert fence GP3.18 - //// Unicast address: "0x[xx]0F 0014 WOR codepoint" bit(18) = 0b1 0x0000 2000 0000 0000 - //// TP_GP3_OR_0x010F0014 - //FAPI_DBG("Setting TP chiplet GP3 Regsiter bit 18 to assert the fence."); - //rc_ecmd |= scom_data.flushTo0(); - //rc_ecmd |= scom_data.setBit(GP3_FENCE_EN_BIT); - //if (rc_ecmd) - //{ - // FAPI_ERR("Error 0x%x setting up ecmd data buffer to assert the fence in TP chiplet.", rc_ecmd); - // rc.setEcmdError(rc_ecmd); - // break; - //} - //rc = fapiPutScom( i_target, TP_GP3_OR_0x010F0014, scom_data); - //if (rc) - //{ - // FAPI_ERR("Error writing TP chiplet GP3 register to assert the fence."); - // break; - //} - - - // Set scan_dis_dc_b bit in Chiplet GP0 - // unicast address "0x[xx]00 0005 WOR codepoint" Data: bit(6) = 0b1 (0x0200 0000 0000 0000) - // TP_GP0_OR_0x01000005 - FAPI_DBG("Setting TP chiplet GP0 Register bit 6 to set scan_dis_dc_b to allow for scanning."); - rc_ecmd |= scom_data.flushTo0(); - rc_ecmd |= scom_data.setBit(GP0_SCAN_DIS_DC_B_BIT); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to set scan_dis_dc_b in TP chiplet.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom( i_target, TP_GP0_OR_0x01000005, scom_data); - if (rc) - { - FAPI_ERR("Error writing TP chiplet GP0 register to set scan_dis_dc_b for scanning."); - break; - } - } // End of TP Chiplet clock section - - - - //----------------- - // VITL Clocks @@@ 00 - //----------------- - - if (i_stop_vitl_clks) - { - - // Set the length of the FSI shifter set pulse - // Do this in the CFAM FSI SHIFT_CONTROL_REGISTER_2. - FAPI_DBG("Setting length of the set pulse in the FSI SHIFT_CONTROL_REGISTER_2."); - rc_ecmd |= cfam_data.setWord(0,FSI_SHIFT_SET_PULSE_LENGTH); //Set cfam_data to 0x0000000F - if(rc_ecmd) - { - FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase for CFAM operation", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutCfamRegister(i_target, CFAM_FSI_SHIFT_CTRL_0x00000C10, cfam_data); - if (rc) - { - FAPI_ERR("Error attempting to set length of the set pulse in the FSI SHIFT_CONTROL_REGISTER_2."); - break; - } - - - // Disable the VITL clocks - // Set this in PERV GP3 register. Read the register first to preserve other contents. - FAPI_DBG("Setting PERV GPP3 Register bit 16 to turn OFF the VITL clock."); - rc = fapiGetCfamRegister(i_target, CFAM_FSI_GP3_MIRROR_0x0000101B, cfam_data); - if (rc) - { - FAPI_ERR("Error getting PERV GP3 via CFAM"); - break; - } - rc_ecmd |= cfam_data.setBit(PERVGP3_VITL_CLKOFF_BIT); //Set bit 16 to turn OFF VITL clock - if(rc_ecmd) - { - FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase for CFAM operation", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutCfamRegister(i_target, CFAM_FSI_GP3_MIRROR_0x0000101B, cfam_data); - if (rc) - { - FAPI_ERR("Error attempting to set PERV GP3 Reg bit 16 to stop the VITL clocks."); - break; - } - - - // Set Some FSI fences - // Set this in CFAM GP3 register. Read the register first to preserve other contents. - FAPI_DBG("Setting FSI GP3 bits 25 and,26 to set FSI fences 4 and 5."); - rc = fapiGetCfamRegister(i_target, CFAM_FSI_GP3_0x00001012, cfam_data); - if (rc) - { - FAPI_ERR("Error getting FSI_GP3 via CFAM"); - break; - } - rc_ecmd |= cfam_data.setBit(FSIGP3_FSI_FENCE4_BIT); //Set bits 25 to set FSI fence 4 - rc_ecmd |= cfam_data.setBit(FSIGP3_FSI_FENCE5_BIT); //Set bits 26 to set FSI fence 5 - if(rc_ecmd) - { - FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase for CFAM operation", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutCfamRegister(i_target, CFAM_FSI_GP3_0x00001012, cfam_data); - if (rc) - { - FAPI_ERR("Error attempting to set FSI fences in FSI GP3 register."); - break; - } - } // End of VITL clock section - - - } while(0); - - FAPI_INF("********* cen_stopclocks complete *********"); - return rc; -} - -} //end extern C - - - - -/* -*************** Do not edit this area *************** -This section is automatically updated by CVS when you check in this file. -Be sure to create CVS comments when you commit so that they can be included here. - -$Log: cen_stopclocks.C,v $ -Revision 1.16 2014/01/16 17:49:16 mfred -Updates for error msgs, error handling, and removing newline chars from msgs. From Mike Jones. - -Revision 1.15 2013/10/16 14:39:32 mfred -Set the FSI shifter pulse width before stopping the TP or VITL clocks. - -Revision 1.14 2013/10/10 14:23:32 mfred -Updates from Gerrit review. Continue with other chiplet even if clocks are off in MEM chiplet. - -Revision 1.13 2013/09/27 16:44:50 mfred -Separate option to stop the VITL clks, and checks to avoid calling options that will cause failures. - -Revision 1.12 2013/03/04 17:56:33 mfred -Add some header comments for BACKUP and SCREEN. - -Revision 1.11 2013/02/27 21:16:30 mfred -Make change to stop all clock regions simultaneously. - -Revision 1.10 2013/01/17 21:38:55 mfred -Check vital clock before trying to stop clocks. Assert scan_dis_dc_b after stopping clocks. - -Revision 1.9 2012/10/05 20:10:43 mfred -Remove the use of multicast in case only one chiplet is selected. - -Revision 1.8 2012/08/30 12:09:29 mfred -Only disable EDRAM if the refresh clock was turned OFF. - -Revision 1.7 2012/08/30 11:56:08 mfred -Added input options to select chiplet and to stop refresh clock. - -Revision 1.6 2012/08/27 16:53:40 mfred -Exit when unexpected clock status is seen. - -Revision 1.5 2012/07/10 14:29:36 mfred -Removed some bad comments and some whitespace. - -Revision 1.4 2012/06/07 19:31:19 mfred -Fixed calls to CFAM registers. They are not scommable. - -Revision 1.3 2012/05/31 14:02:06 mfred -Committing updates for cen_stopclocks. - -Revision 1.2 2012/03/14 19:26:34 mfred -Replace prototype with functional code. - -Revision 1.1 2012/03/07 14:22:11 mfred -Adding prototype for cen_stopclocks. - -*/ - diff --git a/src/usr/hwpf/hwp/dram_training/cen_stopclocks/cen_stopclocks.H b/src/usr/hwpf/hwp/dram_training/cen_stopclocks/cen_stopclocks.H deleted file mode 100644 index 5d0bd5b7d..000000000 --- a/src/usr/hwpf/hwp/dram_training/cen_stopclocks/cen_stopclocks.H +++ /dev/null @@ -1,91 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/dram_training/cen_stopclocks/cen_stopclocks.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2013,2014 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: cen_stopclocks.H,v 1.5 2013/10/10 14:23:35 mfred Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/cen_stopclocks.H,v $ -//------------------------------------------------------------------------------ -// *! (C) Copyright International Business Machines Corp. 2011 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -//------------------------------------------------------------------------------ -// *! TITLE : cen_stopclocks.H -// *! DESCRIPTION : see additional comments below -// *! OWNER NAME : Mark Fredrickson Email: mfred@us.ibm.com -// *! BACKUP NAME : Mark Bellows Email: bellows@us.ibm.com -// *! ADDITIONAL COMMENTS : -// -// This is the header file for cen_stopclocks. -// -//------------------------------------------------------------------------------ -// Don't forget to create CVS comments when you check in your changes! -//------------------------------------------------------------------------------ - -#ifndef CEN_STOPCLOCKSHWPB_H_ -#define CEN_STOPCLOCKSHWPB_H_ - -#include <fapi.H> - - -// function pointer typedef definition for HWP call support -typedef fapi::ReturnCode (*cen_stopclocks_FP_t)(const fapi::Target &, - const bool, - const bool, - const bool, - const bool, - const bool); - - -//------------------------------------------------------------------------------ -// Function prototypes -//------------------------------------------------------------------------------ - -extern "C" -{ - // Target is centaur chip - -/** - * @brief cen_stopclocks procedure: The purpose of this procedure is to assert the tholds (stop the clocks) in the Centaur chip. - * - * @param[in] i_target Reference to centaur target - * @param[in] i_stop_mem_clks True if MEM chiplet clocks should be stopped, else false - * @param[in] i_stop_nest_clks True if NEST chiplet clocks (except for refresh clks) should be stopped, else false - * @param[in] i_stop_dram_rfrsh_clks If (i_stop_nest_clks==true) then true if NEST chiplet refresh clocks should be stopped, else false - * @param[in] i_stop_tp_clks True if PERV (TP) chiplet clocks should be stopped, else false - * @param[in] i_stop_vitl_clks True if PERV VITL clocks should be stopped, else false - * - * @return ReturnCode - */ - - fapi::ReturnCode cen_stopclocks(const fapi::Target& i_target, - const bool i_stop_mem_clks, - const bool i_stop_nest_clks, - const bool i_stop_dram_rfrsh_clks, - const bool i_stop_tp_clks, - const bool i_stop_vitl_clks); - - // Target is centaur chip - -} // extern "C" - -#endif // CEN_STOPCLOCKSHWPB_H_ diff --git a/src/usr/hwpf/hwp/dram_training/dram_training.H b/src/usr/hwpf/hwp/dram_training/dram_training.H deleted file mode 100644 index 11501cbfb..000000000 --- a/src/usr/hwpf/hwp/dram_training/dram_training.H +++ /dev/null @@ -1,286 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/dram_training/dram_training.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* COPYRIGHT International Business Machines Corp. 2012,2014 */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -#ifndef __DRAM_TRAINING_DRAM_TRAINING_H -#define __DRAM_TRAINING_DRAM_TRAINING_H - -/** - * @file dram_training.H - * - * Step 13 DRAM Training - * - * All of the following routines are "named isteps" - they are invoked as - * tasks by the @ref IStepDispatcher. - * - * ***************************************************************** - * THIS FILE WAS GENERATED ON 2012-02-27:2142 - * ***************************************************************** - * - * HWP_IGNORE_VERSION_CHECK - * - */ - -/* @tag isteplist - * @docversion v1.28 (12/03/12) - * @istepname dram_training - * @istepnum 13 - * @istepdesc Step 13 DRAM Training - * - * @{ - * @substepnum 1 - * @substepname host_disable_vddr - * @substepdesc : Disable VDDR on CanContinue loops - * @target_sched serial - * @} - * @{ - * @substepnum 2 - * @substepname mem_pll_initf - * @substepdesc : PLL initfile for MBAs - * @target_sched serial - * @} - - * @{ - * @substepnum 3 - * @substepname mem_pll_setup - * @substepdesc : Setup PLL for MBAs - * @target_sched serial - * @} - * @{ - * @substepnum 4 - * @substepname mem_startclocks - * @substepdesc : Start clocks on MBAs - * @target_sched serial - * @} - * @{ - * @substepnum 5 - * @substepname host_enable_vddr - * @substepdesc : Enable the VDDR3 Voltage Rail - * @target_sched serial - * @} - * @{ - * @substepnum 6 - * @substepname mss_scominit - * @substepdesc : Perform scom inits to MC and PHY - * @target_sched serial - * @} - * @{ - * @substepnum 7 - * @substepname mss_ddr_phy_reset - * @substepdesc : Soft reset of DDR PHY macros - * @target_sched serial - * @} - * @{ - * @substepnum 8 - * @substepname mss_draminit - * @substepdesc : Dram initialize - * @target_sched serial - * @} - * @{ - * @substepnum 9 - * @substepname mss_draminit_training - * @substepdesc : Dram training - * @target_sched serial - * @} - * @{ - * @substepnum 10 - * @substepname mss_draminit_trainadv - * @substepdesc : Advanced dram training - * @target_sched serial - * @} - * @{ - * @substepnum 11 - * @substepname mss_draminit_mc - * @substepdesc : Hand off control to MC - * @target_sched serial - * @} - */ -/******************************************************************************/ -// Includes -/******************************************************************************/ -#include <stdint.h> - -namespace DRAM_TRAINING -{ - -/** - * @brief host_disable_vddr - * - * Disable VDDR on CanContinue loops - * - * param[in,out] io_pArgs - (normally) a pointer to a TaskArgs struct, - * or NULL. - * return any errlogs to istep - * - */ -void* call_host_disable_vddr( void * io_pArgs ); - -/** - * @brief mem_pll_initf - * - * PLL init file for MBAs - * - * param[in,out] io_pArgs - (normally) a pointer to a TaskArgs struct, - * or NULL. - * return any errlogs to istep - * - */ -void* call_mem_pll_initf( void * io_pArgs ); - -/** - * @brief mem_pll_setup - * - * Setup PLL for MBAs - * - * param[in,out] io_pArgs - (normally) a pointer to a TaskArgs struct, - * or NULL. - * return any errlogs to istep - * - */ -void* call_mem_pll_setup( void * io_pArgs ); - - - -/** - * @brief mem_startclocks - * - * Start clocks on MBAs - * - * param[in,out] io_pArgs - (normally) a pointer to a TaskArgs struct, - * or NULL. - * return any errlogs to istep - * - */ -void* call_mem_startclocks( void * io_pArgs ); - - - -/** - * @brief host_enable_vddr - * - * Enable the VDDR3 Voltage Rail - * - * param[in,out] io_pArgs - (normally) a pointer to a TaskArgs struct, - * or NULL. - * return any errlogs to istep - - * - */ -void* call_host_enable_vddr( void * io_pArgs ); - - - -/** - * @brief mss_scominit - * - * Perform scom inits to MC and PHY - * - * param[in,out] io_pArgs - (normally) a pointer to a TaskArgs struct, - * or NULL. - * return any errlogs to istep - * - */ -void* call_mss_scominit( void * io_pArgs ); - - - -/** - * @brief mss_ddr_phy_reset - * - * Soft reset of DDR PHY macros - * - * param[in,out] io_pArgs - (normally) a pointer to a TaskArgs struct, - * or NULL. - * return any errlogs to istep - * - */ -void* call_mss_ddr_phy_reset( void * io_pArgs ); - - - -/** - * @brief mss_draminit - * - * Dram initialize - * - * param[in,out] io_pArgs - (normally) a pointer to a TaskArgs struct, - * or NULL. - * return any errlogs to istep - * - */ -void* call_mss_draminit( void * io_pArgs ); - - -/** - * @brief mss_draminit_training - * - * Dram training - * - * param[in,out] io_pArgs - (normally) a pointer to a TaskArgs struct, - * or NULL. - * return any errlogs to istep - * - */ -void* call_mss_draminit_training( void * io_pArgs ); - - - -/** - * @brief mss_draminit_trainadv - * - * Advanced dram training - * - * param[in,out] io_pArgs - (normally) a pointer to a TaskArgs struct, - * or NULL. - * return any errlogs to istep - * - */ -void* call_mss_draminit_trainadv( void * io_pArgs ); - - - -/** - * @brief mss_draminit_mc - * - * Hand off control to MC - * - * param[in,out] io_pArgs - (normally) a pointer to a TaskArgs struct, - * or NULL. - * return any errlogs to istep - * - */ -void* call_mss_draminit_mc( void * io_pArgs ); -/** - * @brief mss_dimm_power_test - * - * - * param[in,out] io_pArgs - (normally) a pointer to a TaskArgs struct, - * or NULL. - * return any errlogs to istep - * - */ -void* call_mss_dimm_power_test( void * io_pArgs ); - - -}; // end namespace - -#endif - diff --git a/src/usr/hwpf/hwp/dram_training/makefile b/src/usr/hwpf/hwp/dram_training/makefile deleted file mode 100644 index 11496a39b..000000000 --- a/src/usr/hwpf/hwp/dram_training/makefile +++ /dev/null @@ -1,99 +0,0 @@ -# IBM_PROLOG_BEGIN_TAG -# This is an automatically generated prolog. -# -# $Source: src/usr/hwpf/hwp/dram_training/makefile $ -# -# OpenPOWER HostBoot Project -# -# Contributors Listed Below - COPYRIGHT 2012,2015 -# [+] Google Inc. -# [+] International Business Machines Corp. -# -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -# implied. See the License for the specific language governing -# permissions and limitations under the License. -# -# IBM_PROLOG_END_TAG -ROOTPATH = ../../../../.. - -MODULE = dram_training - -CFLAGS += $(if $(CONFIG_VPD_GETMACRO_USE_EFF_ATTR), -D FAPI_MSSLABONLY -D FAPI_LRDIMM) -CFLAGS += -DFAPI_DDR4 - -## support for Targeting and fapi -EXTRAINCDIR += ${ROOTPATH}/src/include/usr/ecmddatabuffer -EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/fapi -EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/plat -EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/hwp - -## pointer to common HWP files -EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/include - -## NOTE: add the base istep dir here. -##@ EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/@istepname -EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training - -## Include sub dirs -## NOTE: add a new EXTRAINCDIR when you add a new HWP -##@ EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/??? -EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/mss_draminit_training -EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/mss_draminit_mc -EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/mss_draminit -EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset -EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/mem_startclocks -EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/mss_scominit -EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/mem_pll_setup -EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv -EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build -EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/mss_lrdimm_funcs -EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/cen_stopclocks -EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/proc_throttle_sync - -## NOTE: add new object files when you add a new HWP -OBJS += mss_draminit.o -OBJS += mss_funcs.o -OBJS += mss_draminit_mc.o -OBJS += mss_draminit_training.o -OBJS += mss_ddr_phy_reset.o -OBJS += mss_termination_control.o -OBJS += cen_mem_startclocks.o -OBJS += mss_scominit.o -OBJS += cen_mem_pll_initf.o -OBJS += cen_mem_pll_setup.o -OBJS += mss_draminit_training_advanced.o -OBJS += mss_access_delay_reg.o -OBJS += mss_generic_shmoo.o -OBJS += mss_mcbist.o -OBJS += mss_mcbist_common.o -OBJS += mss_mcbist_address.o -OBJS += mss_lrdimm_funcs.o -OBJS += cen_stopclocks.o -OBJS += mss_ddr4_pda.o -OBJS += mss_ddr4_funcs.o -OBJS += mss_mrs6_DDR4.o - -## NOTE: add a new directory onto the vpaths when you add a new HWP -##@ VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/??? -VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/mss_draminit_training -VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/mss_draminit_mc -VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/mss_draminit -VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset -VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/mem_startclocks -VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/mss_scominit -VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/mem_pll_setup -VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv -VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/mss_lrdimm_funcs -VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/cen_stopclocks - - -include ${ROOTPATH}/config.mk diff --git a/src/usr/hwpf/hwp/dram_training/mem_pll_setup/cen_mem_pll_initf.C b/src/usr/hwpf/hwp/dram_training/mem_pll_setup/cen_mem_pll_initf.C deleted file mode 100644 index 1e4c9fb6f..000000000 --- a/src/usr/hwpf/hwp/dram_training/mem_pll_setup/cen_mem_pll_initf.C +++ /dev/null @@ -1,598 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/dram_training/mem_pll_setup/cen_mem_pll_initf.C $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2012,2016 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: cen_mem_pll_initf.C,v 1.13 2014/09/23 21:53:45 jmcgill Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/cen_mem_pll_initf.C,v $ -//------------------------------------------------------------------------------ -// *! (C) Copyright International Business Machines Corp. 2012 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -//------------------------------------------------------------------------------ -// *! TITLE : cen_mem_pll_initf -// *! DESCRIPTION : see additional comments below -// *! OWNER NAME : Mark Fredrickson Email: mfred@us.ibm.com -// *! BACKUP NAME : Mark Bellows Email: bellows@us.ibm.com -// *! SCREEN : pervasive_screen -// #! ADDITIONAL COMMENTS : -// -// The purpose of this procedure is scan the correct values into the Centaur chip MEM PLL controller. -// -// The MEM PLL needs to be set to various frequency settings based on the value of some memory attributes. -// Here is some specific information in a 4/4/2012 note from Jeff Sabrowski: -// -// Hi Mark F, -// The valid values for Voltage are: 1350, 1250 and 1200. -// In the future, we may have a 900-ish value for low voltage DDR4, but the actual value won't be known for a year or more. -// One thing I am thinking about that will complicate things is how to run corners. -// This attribute will contain the nominal voltage. -// To margin the voltage, a second attribute (that is set before IPL) exists that indicates the percent offset (plus or minus) to the nominal. -// Power code will need to figure out the correct value from both those attributes. -// I suppose there's the possibility that the offset value will also be in millivolts, but we haven't talked to the firmware group about this recently, -// so this may be a good time to ping them on the offset piece again. -// -// For Frequency, we only have a few specific values we plan to support, although I plan to have a few extra "buckets" coded for lab bringup work. -// The supported frequencies are 1066, 1333 and 1600. I plan to code in 800, 1866 as well, and maybe 2133. -// These are all the nominal/standard DDR3 and DDR4 JEDEC speeds. -// Mark B will need to correct me if I am wrong, but I believe we are doing the same as voltage -// -- having an attribute for nominal frequency and a second attribute for margin (+/- percent of nominal). -// -// The reason for "nominal" attribute plus a "margin" attribute is due to our firmware procedures being designed to work with nominal voltage and frequency -// -- when at any margin, we don't want our code to recalculate "actuals" in order to properly stress parts. -// -// -Jeff -// -// Jeff Sabrowski (jsabrow@us.ibm.com) -// -// -// The supported frequencies listed above are the DDR frequencies. They also match the MEM PLL output B frequencies and the MBA frequencies. -// MEM PLL output A should be running at half of the output B frequency. -// MEM PLL output A drives the DDR phys. The DDR phys double the MEM PLL output A frequency to get back to the MEM PLL output B frequency. -// -//------------------------------------------------------------------------------ -// Don't forget to create CVS comments when you check in your changes! -//------------------------------------------------------------------------------ - -#include <fapi.H> -#include <cen_scom_addresses.H> -#include <cen_mem_pll_initf.H> - -#include <p8_delta_scan_rw.h> -#include <p8_ring_identification.H> - - -// Constants - -// Register values for using setpulse -const uint64_t OPCG_REG0_FOR_SETPULSE = 0x818C000000000000ull; -const uint64_t OPCG_REG2_FOR_SETPULSE = 0x0000000000002000ull; -const uint64_t OPCG_REG3_FOR_SETPULSE = 0x6000000000000000ull; -const uint64_t CLK_REGION_FOR_SETPULSE = 0x0010040000000000ull; - -const uint32_t MEMB_TP_BNDY_PLL_RING_ADDR = 0x01030088; - -// Pervasive LFIR Register field/bit definitions -const uint8_t PERV_LFIR_SCAN_COLLISION_BIT = 3; - -const bool MASK_SCAN_COLLISION = true; - -extern "C" { - -using namespace fapi; - - - -//------------------------------------------------------------------------------ -// cen_load_pll_ring_from_buffer -//------------------------------------------------------------------------------ -fapi::ReturnCode cen_load_pll_ring_from_buffer(const fapi::Target & i_target, - ecmdDataBufferBase i_scan_ring_data - ) -{ - // Target is centaur - - fapi::ReturnCode rc; - uint32_t rc_ecmd = 0; - ecmdDataBufferBase scom_data(64); - - - FAPI_INF("Starting subroutine: cen_load_pll_ring_from_buffer..."); - do - { - //------------------------------------------- - // Mask Pervasive LFIR - //------------------------------------------ - - if (MASK_SCAN_COLLISION) - { - FAPI_DBG("Masking Pervasive LFIR scan collision bit ..."); - rc_ecmd |= scom_data.flushTo0(); - rc_ecmd |= scom_data.setBit(PERV_LFIR_SCAN_COLLISION_BIT); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to set Pervasive LFIR Mask Register.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom(i_target, TP_PERV_LFIR_MASK_OR_0x0104000F, scom_data); - if (!rc.ok()) - { - FAPI_ERR("Error writing Pervasive LFIR Mask OR Register."); - break; - } - } - - //------------------------------------------- - // Set the OPCG to generate the setpulse - //------------------------------------------ - // Write SCOM address=0x01030002 data=0x818C000000000000 unicast, write TP OPCG Reg0 to generate setpulse - FAPI_DBG("Writing TP OPCG Register 0 to 0x818C000000000000 to generate setpulse ..."); - rc_ecmd |= scom_data.setDoubleWord(0, OPCG_REG0_FOR_SETPULSE); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to write TP OPCG Register 0.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom( i_target, TP_OPCG_CNTL0_0x01030002, scom_data); - if (rc) - { - FAPI_ERR("Error writing TP OPCG Register0 0x01030002 to 0x818C000000000000 to generate setpulse."); - break; - } - - // Write SCOM address=0x01030004 data=0x0000000000002000 unicast, write TP OPCG Reg2 to generate setpulse - FAPI_DBG("Writing TP OPCG Register 2 to 0x0000000000002000 to generate setpulse ..."); - rc_ecmd |= scom_data.setDoubleWord(0, OPCG_REG2_FOR_SETPULSE); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to write TP OPCG Register 2.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom( i_target, TP_OPCG_CNTL2_0x01030004, scom_data); - if (rc) - { - FAPI_ERR("Error writing TP OPCG Register2 0x01030004 to 0x0000000000002000 to generate setpulse."); - break; - } - - // Write SCOM address=0x01030005 data=0x6000000000000000 unicast, write TP OPCG Reg3 to generate setpulse - FAPI_DBG("Writing TP OPCG Register 3 to 0x6000000000000000 to generate setpulse ..."); - rc_ecmd |= scom_data.setDoubleWord(0, OPCG_REG3_FOR_SETPULSE); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to write TP OPCG Register 3.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom( i_target, TP_OPCG_CNTL3_0x01030005, scom_data); - if (rc) - { - FAPI_ERR("Error writing TP OPCG Register3 0x01030005 to 0x6000000000000000 to generate setpulse."); - break; - } - - // Write SCOM address=0x01030006 data=0x0010040000000000 unicast, write TP Clock Region Reg to generate setpulse - FAPI_DBG("Writing TP OPCG Clock Region Register to 0x0010040000000000 to generate setpulse ..."); - rc_ecmd |= scom_data.setDoubleWord(0, CLK_REGION_FOR_SETPULSE); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to write TP Clock Region Register.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom( i_target, TP_CLK_REGION_0x01030006, scom_data); - if (rc) - { - FAPI_ERR("Error writing TP Clock Region Register 0x01030006 to 0x0010040000000000 to generate setpulse."); - break; - } - - //------------------------------------------------ - // Scan new ring data into tp_pll_bndy scan ring. - //------------------------------------------------ - rc = fapiPutRing(i_target, MEMB_TP_BNDY_PLL_RING_ADDR, i_scan_ring_data, RING_MODE_SET_PULSE); - if (rc) - { - FAPI_ERR("fapiPutRing failed with rc = 0x%x", (uint32_t)rc); - break; - } - FAPI_DBG("Loading of the scan ring data for ring tp_pll_bndy is done.\n"); - - //------------------------------------------- - // Set the OPCG back to a good state - //------------------------------------------ - // Write SCOM address=0x01030005 data=0x0000000000000000 unicast, clear TP OPCG Reg3 - FAPI_DBG("Writing TP OPCG Register 3 to 0x0000000000000000 to clear setpulse ..."); - rc_ecmd |= scom_data.flushTo0(); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to clear TP OPCG Register 3.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom( i_target, TP_OPCG_CNTL3_0x01030005, scom_data); - if (rc) - { - FAPI_ERR("Error writing TP OPCG Register3 0x01030005 to 0x0000000000000000 to clear setpulse."); - break; - } - - // Write SCOM address=0x01030006 data=0x0000000000000000 unicast, clear TP Clock Region Reg - FAPI_DBG("Writing TP OPCG Clock Region Register to 0x0000000000000000 to clear setpulse ..."); - rc_ecmd |= scom_data.flushTo0(); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to clear TP Clock Region Register.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom( i_target, TP_CLK_REGION_0x01030006, scom_data); - if (rc) - { - FAPI_ERR("Error writing TP Clock Region Register 0x01030006 to 0x0000000000000000 to clear setpulse."); - break; - } - - //------------------------------------------- - // Clear & Unmask Pervasive LFIR - //------------------------------------------ - if (MASK_SCAN_COLLISION) - { - FAPI_DBG("Clearing Pervasive LFIR scan collision bit ..."); - rc_ecmd |= scom_data.flushTo1(); - rc_ecmd |= scom_data.clearBit(PERV_LFIR_SCAN_COLLISION_BIT); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to clear Pervasive LFIR Register.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom(i_target, TP_PERV_LFIR_AND_0x0104000B, scom_data); - if (!rc.ok()) - { - FAPI_ERR("Error writing Pervasive LFIR AND Register."); - break; - } - - // Change for SW245030. Leave this FIR masked. Feb. 4 2014 M.Fredrickson - //FAPI_DBG("Unmasking Pervasive LFIR scan collision bit ..."); - //rc = fapiPutScom(i_target, TP_PERV_LFIR_MASK_AND_0x0104000E, scom_data); - //if (!rc.ok()) - //{ - // FAPI_ERR("Error writing Pervasive LFIR Mask And Register."); - // break; - //} - } - - } while(0); - - FAPI_INF("Finished executing subroutine: cen_load_pll_ring_from_buffer"); - return rc; -} - -//------------------------------------------------------------------------------ -// cen_mem_pll_initf -//------------------------------------------------------------------------------ -fapi::ReturnCode cen_mem_pll_initf(const fapi::Target & i_target) -{ - // Target is centaur - fapi::ReturnCode rc; - uint32_t rc_ecmd = 0; - uint8_t is_simulation = 0; - uint32_t mss_freq = 0; - uint32_t nest_freq = 0; - uint32_t ring_length = 0; - uint32_t mem_pll_update_bit_offset = 0; - uint8_t attrRingData[80]={0}; // Set to 80 bytes to match length in XML file, not actual scan ring length. - ecmdDataBufferBase ring_data; - - FAPI_INF("********* cen_mem_pll_initf start *********"); - do - { - FAPI_DBG("Setting up the Centaur MEM PLL."); - - //------------------------------------------ - // Read attributes for setting the PLL data - //------------------------------------------ - - // The code that loads the PLL scan ring data should choose the correct data to load based on - // the DDR frequency and voltage settings and a lab override value. - // The supported frequencies are 800, 1066, 1333, 1600, 1866, and 2133 MHz - // (These are the DDR frequencies and the PLL output B frequencies.) - // The DDR frequency can be determined from attribute ATTR_MSS_FREQ (in MHz) - // The DDR voltage can be determined from attribute ATTR_MSS_VOLT (in millivolts) - // Get another attribute for selecting the "override" ring. Use CQ to request an attribute. - // (The selection of rings should include an "override ring that can be used in the lab") - - // Read the attributes - rc = FAPI_ATTR_GET( ATTR_IS_SIMULATION, NULL, is_simulation); - if (rc) - { - FAPI_ERR("Failed to get attribute: ATTR_IS_SIMULATION."); - break; - } - rc = FAPI_ATTR_GET( ATTR_MSS_FREQ, &i_target, mss_freq); - if (rc) - { - FAPI_ERR("Failed to get attribute: ATTR_MSS_FREQ."); - break; - } - // ATTR_FREQ_PB_MHZ is a "system" attribute, so use NULL as the target. - rc = FAPI_ATTR_GET( ATTR_FREQ_PB_MHZ, NULL, nest_freq); - if (rc) - { - FAPI_ERR("Failed to get attribute: ATTR_FREQ_PB_MHZ."); - break; - } - - FAPI_DBG("ATTR_IS_SIMULATION attribute is set to : %d.", is_simulation); - FAPI_DBG("DDR frequency is set to : %d.", mss_freq); - FAPI_DBG("NEST frequency is set to : %d.", nest_freq); - - // Read in the PLL Ring LENGTH based on the frequency attributes. - if ( is_simulation ) - { - rc = FAPI_ATTR_GET( ATTR_MEMB_TP_BNDY_PLL_LENGTH, &i_target, ring_length); - } - else if ( nest_freq == 2000 ) - { - switch (mss_freq) { - case 1066 : - rc = FAPI_ATTR_GET(ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_LENGTH, &i_target, ring_length); - break; - case 1333 : - rc = FAPI_ATTR_GET(ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_LENGTH, &i_target, ring_length); - break; - case 1600 : - rc = FAPI_ATTR_GET(ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_LENGTH, &i_target, ring_length); - break; - case 1866 : - rc = FAPI_ATTR_GET(ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_LENGTH, &i_target, ring_length); - break; - default : - FAPI_ERR("Un-Supported DDR frequency detected: %d.", mss_freq); - FAPI_ERR("DDR frequency of 1066, 1333, 1600, or 1866 expected."); - uint32_t & MSS_FREQ = mss_freq; - FAPI_SET_HWP_ERROR(rc, RC_CEN_MEM_PLL_INITF_UNSUPPORTED_MSS_FREQ); - } - } - else if ( nest_freq == 2400 ) - { - switch (mss_freq) { - case 1066 : - rc = FAPI_ATTR_GET(ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_LENGTH, &i_target, ring_length); - break; - case 1333 : - rc = FAPI_ATTR_GET(ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_LENGTH, &i_target, ring_length); - break; - case 1600 : - rc = FAPI_ATTR_GET(ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_LENGTH, &i_target, ring_length); - break; - case 1866 : - rc = FAPI_ATTR_GET(ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_LENGTH, &i_target, ring_length); - break; - default : - FAPI_ERR("Un-Supported DDR frequency detected: %d.", mss_freq); - FAPI_ERR("DDR frequency of 1066, 1333, 1600, or 1866 expected."); - uint32_t & MSS_FREQ = mss_freq; - FAPI_SET_HWP_ERROR(rc, RC_CEN_MEM_PLL_INITF_UNSUPPORTED_MSS_FREQ); - } - } - else - { - FAPI_ERR("Un-Supported NEST frequency detected: %d.", nest_freq); - FAPI_ERR("NEST frequency of 2000 or 2400 expected."); - uint32_t & NEST_FREQ = nest_freq; - FAPI_SET_HWP_ERROR(rc, RC_CEN_MEM_PLL_INITF_UNSUPPORTED_NEST_FREQ); - break; - } - if (rc) - { - FAPI_ERR("Failed to get the PLL ring LENGTH attribute."); - break; - } - FAPI_DBG("PLL ring LENGTH attribute is set to : %d.", ring_length); - - // Read in the PLL Ring DATA based on the frequency attributes. - if ( is_simulation ) - { - rc = FAPI_ATTR_GET( ATTR_MEMB_TP_BNDY_PLL_DATA, &i_target, attrRingData); - } - else if ( nest_freq == 2000 ) - { - switch (mss_freq) { - case 1066 : - rc = FAPI_ATTR_GET(ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA, &i_target, attrRingData); - break; - case 1333 : - rc = FAPI_ATTR_GET(ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA, &i_target, attrRingData); - break; - case 1600 : - rc = FAPI_ATTR_GET(ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA, &i_target, attrRingData); - break; - case 1866 : - rc = FAPI_ATTR_GET(ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA, &i_target, attrRingData); - break; - default : - FAPI_ERR("Un-Supported DDR frequency detected: %d.", mss_freq); - FAPI_ERR("DDR frequency of 1066, 1333, 1600, or 1866 expected."); - uint32_t & MSS_FREQ = mss_freq; - FAPI_SET_HWP_ERROR(rc, RC_CEN_MEM_PLL_INITF_UNSUPPORTED_MSS_FREQ); - } - } - else if ( nest_freq == 2400 ) - { - switch (mss_freq) { - case 1066 : - rc = FAPI_ATTR_GET( ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA, &i_target, attrRingData); - break; - case 1333 : - rc = FAPI_ATTR_GET( ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA, &i_target, attrRingData); - break; - case 1600 : - rc = FAPI_ATTR_GET( ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA, &i_target, attrRingData); - break; - case 1866 : - rc = FAPI_ATTR_GET( ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA, &i_target, attrRingData); - break; - default : - FAPI_ERR("Un-Supported DDR frequency detected: %d.", mss_freq); - FAPI_ERR("DDR frequency of 1066, 1333, 1600, or 1866 expected."); - uint32_t & MSS_FREQ = mss_freq; - FAPI_SET_HWP_ERROR(rc, RC_CEN_MEM_PLL_INITF_UNSUPPORTED_MSS_FREQ); - } - } - else - { - FAPI_ERR("Un-Supported NEST frequency detected: %d.", nest_freq); - FAPI_ERR("NEST frequency of 2000 or 2400 expected."); - uint32_t & NEST_FREQ = nest_freq; - FAPI_SET_HWP_ERROR(rc, RC_CEN_MEM_PLL_INITF_UNSUPPORTED_NEST_FREQ); - break; - } - if (rc) - { - FAPI_ERR("Failed to get the PLL ring DATA attribute."); - break; - } - - // set DMI PFD360 bit for runtime - uint32_t memb_dmi_cupll_pfd360_bit_offset; - rc = FAPI_ATTR_GET(ATTR_MEMB_DMI_CUPLL_PFD360_OFFSET, &i_target, memb_dmi_cupll_pfd360_bit_offset); - if (rc) - { - FAPI_ERR("Failed to get DMI PFD360 offset attribute"); - break; - } - FAPI_DBG("DMI PLL PFD360 offset is set to : %d.", memb_dmi_cupll_pfd360_bit_offset); - - rc = FAPI_ATTR_GET(ATTR_MEMB_MEM_PLL_CFG_UPDATE_OFFSET, &i_target, mem_pll_update_bit_offset); - if (rc) - { - FAPI_ERR("Failed to get the MEM PLL PLLCTR1(44) offset attribute"); - break; - } - FAPI_DBG("MEM PLL PLLCTR1(44) offset is set to : %d.", mem_pll_update_bit_offset); - - - // Set the ring_data buffer to the right length for the ring data - rc_ecmd |= ring_data.setBitLength(ring_length); // This length needs to match the real scan length in the scandef file (Required for hostboot.) - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting ecmd data buffer length. Buffer must be set to length of scan chain.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - - // in order to update its output frequency, the MEM PLL needs to see PLLCTRL1(44) toggle - // ensure output frequency changes by running three scans w/ setpulse (PLLCTRL1(44) = 0->1->0) - for (uint32_t scan_num = 0; scan_num < 3; scan_num++) - { - // Put the ring data from the attribute into the buffer - rc_ecmd |= ring_data.insert(attrRingData, 0, ring_length, 0); - - // clamp PFD360 bit to 0 for runtime - rc_ecmd |= ring_data.clearBit(memb_dmi_cupll_pfd360_bit_offset); - - // force desired value of MEM PLLCTR1(44) - if (scan_num % 2) { - rc_ecmd |= ring_data.setBit(mem_pll_update_bit_offset); - } - else { - rc_ecmd |= ring_data.clearBit(mem_pll_update_bit_offset); - } - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x loading scan chain attribute data into buffer (scan=%d).", rc_ecmd, scan_num); - rc.setEcmdError(rc_ecmd); - break; - } - - // Call the subroutine to load the data into the simulation or HW model - rc = cen_load_pll_ring_from_buffer ( i_target, ring_data ); - if (rc) - { - FAPI_ERR("Subroutine: cen_load_pll_ring_from_buffer failed (scan=%d)!", scan_num); - break; - } - } - if (rc) - { - break; - } - } while(0); - - FAPI_INF("********* cen_mem_pll_initf complete *********"); - return rc; -} - -} //end extern C - - - -/* -*************** Do not edit this area *************** -This section is automatically updated by CVS when you check in this file. -Be sure to create CVS comments when you commit so that they can be included here. -$Log: cen_mem_pll_initf.C,v $ -Revision 1.13 2014/09/23 21:53:45 jmcgill -add explicit clear for DMI PFD360 bit, based on change in base attribute values (SW279708) - -Revision 1.12 2014/02/04 21:08:46 mfred -Change to leave TP FIR bit 3 masked out. SW245030. - -Revision 1.11 2014/01/15 03:34:28 jmcgill -scan ring 3x to ensure toggle on MEM PLLCTR1(44), which will guarantee output frequency change - -Revision 1.10 2013/12/10 03:41:34 mfred -Make changes to support TP_BNDY scan chain addresses changing to chiplet 1 for zSeries. - -Revision 1.9 2013/11/15 16:29:56 mfred -Changes made by Mike Jones for gerrit review, mostly for improved error handling. - -Revision 1.8 2013/10/02 16:09:38 mfred -Mask FIR bit during scanning to resolve HW255774. Add code to load desired MEM PLL freq after determining DDR freq. - -Revision 1.7 2013/07/08 14:00:24 mfred -Back out accidental change. - -Revision 1.5 2013/03/04 17:56:24 mfred -Add some header comments for BACKUP and SCREEN. - -Revision 1.4 2013/01/29 21:50:52 mfred -Use new PLL ring attributes. - -Revision 1.3 2012/11/07 23:22:44 mfred -Updated MEM PLL settings for HW with values from Tim Diemoz. - -Revision 1.2 2012/08/27 16:05:20 mfred -committing minor updates as suggested by FW review. - -Revision 1.1 2012/08/13 17:16:08 mfred -Adding new hwp cen_mem_pll_initf. - - -*/ - diff --git a/src/usr/hwpf/hwp/dram_training/mem_pll_setup/cen_mem_pll_initf.H b/src/usr/hwpf/hwp/dram_training/mem_pll_setup/cen_mem_pll_initf.H deleted file mode 100644 index a2c444d2e..000000000 --- a/src/usr/hwpf/hwp/dram_training/mem_pll_setup/cen_mem_pll_initf.H +++ /dev/null @@ -1,73 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/dram_training/mem_pll_setup/cen_mem_pll_initf.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2012,2014 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: cen_mem_pll_initf.H,v 1.3 2013/11/15 16:29:59 mfred Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/cen_mem_pll_initf.H,v $ -//------------------------------------------------------------------------------ -// *! (C) Copyright International Business Machines Corp. 2011 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -//------------------------------------------------------------------------------ -// *! TITLE : cen_mem_pll_initf.H -// *! DESCRIPTION : see additional comments below -// *! OWNER NAME : Mark Fredrickson Email: mfred@us.ibm.com -// *! BACKUP NAME : Mark Bellows Email: bellows@us.ibm.com -// *! ADDITIONAL COMMENTS : -// -// Header file for cen_mem_pll_initf. -// -//------------------------------------------------------------------------------ -// Don't forget to create CVS comments when you check in your changes! -//------------------------------------------------------------------------------ -// CHANGE HISTORY: -//------------------------------------------------------------------------------ -// Version:| Author: | Date: | Comment: -//---------|----------|---------|----------------------------------------------- -// 1.0 | mfred | 08/09/12| Initial creation -// 1.3 | mjjones | 11/12/13| Deleted internal func prototype - -#ifndef CEN_MEM_PLL_INITF_H_ -#define CEN_MEM_PLL_INITF_H_ - -#include <fapi.H> - -typedef fapi::ReturnCode (*cen_mem_pll_initf_FP_t)(const fapi::Target& i_target); - -extern "C" -{ - -/** - * @brief cen_mem_pll_initf procedure. - * - * The purpose of this procedure is to scan the right values in to the Centaur - * MEM PLL controller.. - * - * @param[in] i_target Reference to centaur target - * @return ReturnCode - */ -fapi::ReturnCode cen_mem_pll_initf(const fapi::Target& i_target); - -} // extern "C" - -#endif // CEN_MEM_PLL_INITF_H_ diff --git a/src/usr/hwpf/hwp/dram_training/mem_pll_setup/cen_mem_pll_setup.C b/src/usr/hwpf/hwp/dram_training/mem_pll_setup/cen_mem_pll_setup.C deleted file mode 100644 index a65fbecb5..000000000 --- a/src/usr/hwpf/hwp/dram_training/mem_pll_setup/cen_mem_pll_setup.C +++ /dev/null @@ -1,233 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/dram_training/mem_pll_setup/cen_mem_pll_setup.C $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2012,2014 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: cen_mem_pll_setup.C,v 1.26 2014/03/19 13:58:05 mfred Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/cen_mem_pll_setup.C,v $ -//------------------------------------------------------------------------------ -// *! (C) Copyright International Business Machines Corp. 2012 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -//------------------------------------------------------------------------------ -// *! TITLE : cen_mem_pll_setup -// *! DESCRIPTION : see additional comments below -// *! OWNER NAME : Mark Fredrickson Email: mfred@us.ibm.com -// *! BACKUP NAME : Mark Bellows Email: bellows@us.ibm.com -// *! SCREEN : pervasive_screen -// #! ADDITIONAL COMMENTS : -// -// The purpose of this procedure is to make sure the Centaur MEM PLL locks. -// -//------------------------------------------------------------------------------ -// Don't forget to create CVS comments when you check in your changes! -//------------------------------------------------------------------------------ - -#include <fapi.H> -#include <cen_scom_addresses.H> -#include <cen_mem_pll_setup.H> - -// Constants -const uint64_t DELAY_100NS = 100; // General purpose 100 ns delay for HW mode (2000 sim cycles if simclk - 20ghz) -const uint64_t DELAY_2000SIMCYCLES = 2000; // General purpose 2000 sim cycle delay for sim mode (100 ns if simclk = 20Ghz) -const uint16_t POLL_COUNT_MAX = 50; // Number of times to poll for PLL lock before timing out. - -// CFAM FSI STATUS register bit/field definitions -const uint8_t FSI_STATUS_MEM_PLL_LOCK_BIT = 25; - -// TP LFIR bit/field definitions -const uint8_t TP_LFIR_ERRORS_FROM_NEST_PLL_LOCK_BIT = 19; -const uint8_t TP_LFIR_ERRORS_FROM_MEM_PLL_LOCK_BIT = 20; - -extern "C" { - -using namespace fapi; - -fapi::ReturnCode cen_mem_pll_setup(const fapi::Target & i_target) -{ - // Target is centaur - fapi::ReturnCode rc; - ecmdDataBufferBase cfam_data(32); - uint32_t rc_ecmd = 0; - ecmdDataBufferBase scom_data(64); - - uint32_t poll_count = 0; - uint32_t done_polling = 0; - - FAPI_INF("********* cen_mem_pll_setup start *********"); - do - { - //--------------------------------------- - // Poll for PLL lock bit - //--------------------------------------- - // Check MEM PLL lock bit (25) in CFAM FSI status register to see if PLL is locked - // Check bit 25 only. Bit 25 is for the MEM PLL. (Bit 24 is the PLL lock for NEST PLL) - FAPI_DBG("Polling on FSI STATUS register bit 25 to see if MEM PLL has locked....\n"); - done_polling = 0; - poll_count = 0; - do - { - rc = fapiDelay(DELAY_100NS, DELAY_2000SIMCYCLES); // wait 2000 simcycles (in sim mode) OR 100 nS (in hw mode) - if (rc) - { - FAPI_ERR("Error executing fapiDelay of 100ns or 2000simcycles."); - break; - } - - rc = fapiGetCfamRegister( i_target, CFAM_FSI_STATUS_0x00001007, cfam_data); - if (rc) - { - FAPI_ERR("Error reading FSI STATUS Regiter 0x00001007."); - break; - } - if ( cfam_data.isBitSet(FSI_STATUS_MEM_PLL_LOCK_BIT) ) done_polling = 1; - poll_count++; - - } while ((done_polling == 0) && (poll_count < POLL_COUNT_MAX)); // Poll until PLL is locked or max count is reached. - if (rc) break; // Go to end of proc if error found inside polling loop. - - if ( (poll_count == POLL_COUNT_MAX) && ( done_polling != 1 ) ) - { - FAPI_ERR("Centaur MEM PLL failed to lock! Polling timed out after %d loops.",POLL_COUNT_MAX); - ecmdDataBufferBase & CFAM_FSI_STATUS = cfam_data; - const fapi::Target & MEMBUF_CHIP_IN_ERROR = i_target; - FAPI_SET_HWP_ERROR(rc, RC_CEN_MEM_PLL_SETUP_PLL_LOCK_TIMEOUT); - break; - } - else - { - FAPI_INF("Centaur MEM PLL is now locked."); - } - - - FAPI_DBG("Clearing the FIR PLL lock error bits and unmasking TP LFIR PLL lock error bits ..."); - rc_ecmd |= scom_data.flushTo1(); - rc_ecmd |= scom_data.clearBit(TP_LFIR_ERRORS_FROM_NEST_PLL_LOCK_BIT); - rc_ecmd |= scom_data.clearBit(TP_LFIR_ERRORS_FROM_MEM_PLL_LOCK_BIT); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to clear TP LFIR PLL Lock bits.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom(i_target, TP_PERV_LFIR_AND_0x0104000B, scom_data); - if (!rc.ok()) - { - FAPI_ERR("Error writing Pervasive LFIR AND Register."); - break; - } - rc = fapiPutScom(i_target, TP_PERV_LFIR_MASK_AND_0x0104000E, scom_data); - if (!rc.ok()) - { - FAPI_ERR("Error writing Pervasive LFIR Mask AND Register."); - break; - } - - - } while(0); - - FAPI_INF("********* cen_mem_pll_setup complete *********"); - return rc; -} - -} //end extern C - - - -/* -*************** Do not edit this area *************** -This section is automatically updated by CVS when you check in this file. -Be sure to create CVS comments when you commit so that they can be included here. -$Log: cen_mem_pll_setup.C,v $ -Revision 1.26 2014/03/19 13:58:05 mfred -Update to clear and unmask the PLL lock FIR bits after the PLL locks. SW249390. - -Revision 1.25 2013/11/15 16:30:00 mfred -Changes made by Mike Jones for gerrit review, mostly for improved error handling. - -Revision 1.24 2013/03/04 17:56:26 mfred -Add some header comments for BACKUP and SCREEN. - -Revision 1.23 2012/08/13 17:16:16 mfred -Adding new hwp cen_mem_pll_initf. - -Revision 1.22 2012/07/12 21:16:53 mfred -Remove a lot of simulation-only code, use putspys to set the PLL control ring. - -Revision 1.21 2012/07/10 14:30:59 mfred -Commented out some lines. - -Revision 1.20 2012/07/05 20:06:43 mfred -But MEM PLL into bypass before scanning in new settings. - -Revision 1.19 2012/07/02 16:33:31 mfred -Added MEM PLL settings for simulation. - -Revision 1.18 2012/06/27 20:34:39 mfred -Updates to use real MEM PLL instead of var osc. - -Revision 1.17 2012/06/25 23:37:54 jeshua -Attempt to fix up the mem pll variable oscillators - -Revision 1.16 2012/06/14 19:25:13 mfred -Fixing spelling in comment. - -Revision 1.15 2012/06/14 19:07:51 mfred -Added more code for setting real PLL control chain. Values are still not final. - -Revision 1.14 2012/06/13 20:59:58 mfred -Some updates for using real PLL.cen_mem_pll_setup.C - -Revision 1.13 2012/06/07 13:52:23 jmcgill -use independent data buffers for cfam/scom accesses - -Revision 1.12 2012/06/06 20:05:03 jmcgill -change FSI GP3/GP4/status register accesses from SCOM->CFAM - -Revision 1.11 2012/05/31 18:29:17 mfred -Updates for RC checking and error messages, etc. - -Revision 1.10 2012/04/26 20:52:57 mfred -add additional comment - -Revision 1.9 2012/04/26 14:35:29 mfred -Some fixes. - -Revision 1.8 2012/04/06 15:58:20 mfred -Plugged in real error msgs, removed some unneeded actions. - -Revision 1.5 2012/04/03 21:35:57 mfred -Many updates for both sim and lab actions. - -Revision 1.4 2012/04/02 15:30:43 mfred -removing prcdUtils.H from this dir. - -Revision 1.3 2012/03/30 19:11:06 mfred -removing some obsolete files - -Revision 1.1 2012/03/23 20:36:03 mfred -Checking in a shell prototype for cen_mem_pll_setup. - - - -*/ - diff --git a/src/usr/hwpf/hwp/dram_training/mem_pll_setup/cen_mem_pll_setup.H b/src/usr/hwpf/hwp/dram_training/mem_pll_setup/cen_mem_pll_setup.H deleted file mode 100644 index a0f4a7b90..000000000 --- a/src/usr/hwpf/hwp/dram_training/mem_pll_setup/cen_mem_pll_setup.H +++ /dev/null @@ -1,73 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/dram_training/mem_pll_setup/cen_mem_pll_setup.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2012,2014 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: cen_mem_pll_setup.H,v 1.2 2012/08/27 16:05:25 mfred Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/cen_mem_pll_setup.H,v $ -//------------------------------------------------------------------------------ -// *! (C) Copyright International Business Machines Corp. 2011 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -//------------------------------------------------------------------------------ -// *! TITLE : cen_mem_pll_setup.H -// *! DESCRIPTION : see additional comments below -// *! OWNER NAME : Mark Fredrickson Email: mfred@us.ibm.com -// *! BACKUP NAME : Mark Bellows Email: bellows@us.ibm.com -// *! ADDITIONAL COMMENTS : -// -// Header file for cen_mem_pll_setup. -// -//------------------------------------------------------------------------------ -// Don't forget to create CVS comments when you check in your changes! -//------------------------------------------------------------------------------ -// CHANGE HISTORY: -//------------------------------------------------------------------------------ -// Version:| Author: | Date: | Comment: -//---------|----------|---------|----------------------------------------------- -// 1.0 | mfred | 03/21/12| Initial creation - -#ifndef CEN_MEM_PLL_SETUPHWPB_H_ -#define CEN_MEM_PLL_SETUPHWPB_H_ - -#include <fapi.H> - -typedef fapi::ReturnCode (*cen_mem_pll_setup_FP_t)(const fapi::Target& i_target); - -extern "C" -{ - // Target is centaur - -/** - * @brief cen_mem_pll_setup procedure. The purpose of this procedure is to make sure that the Centaur MEM PLL locks. - * - * @param[in] i_target Reference to centaur target - * - * @return ReturnCode - */ - - fapi::ReturnCode cen_mem_pll_setup(const fapi::Target& i_target); - // Target is centaur - -} // extern "C" - -#endif // CEN_MEM_PLL_SETUPHWPB_H_ diff --git a/src/usr/hwpf/hwp/dram_training/mem_startclocks/cen_mem_startclocks.C b/src/usr/hwpf/hwp/dram_training/mem_startclocks/cen_mem_startclocks.C deleted file mode 100644 index a2394f6a4..000000000 --- a/src/usr/hwpf/hwp/dram_training/mem_startclocks/cen_mem_startclocks.C +++ /dev/null @@ -1,465 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/dram_training/mem_startclocks/cen_mem_startclocks.C $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2012,2014 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: cen_mem_startclocks.C,v 1.13 2014/04/07 19:01:06 gollub Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/cen_mem_startclocks.C,v $ -//------------------------------------------------------------------------------ -// *! (C) Copyright International Business Machines Corp. 2012 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -//------------------------------------------------------------------------------ -// *! TITLE : cen_mem_startclocks -// *! DESCRIPTION : see additional comments below -// *! OWNER NAME : Mark Fredrickson Email: mfred@us.ibm.com -// *! BACKUP NAME : Mark Bellows Email: bellows@us.ibm.com -// *! SCREEN : pervasive_screen -// #! ADDITIONAL COMMENTS : See below -// -// The purpose of this procedure is to drop the fences and release the tholds associated with the Centaur chip MEM PLL. -// to allow propagation of MEM Centaur clocks to internal logic, arrays, and PHYs. -// See sepecific instructions below. -// -// Note: This procedure only starts the clocks in the MEM chiplet. -// Use the cen_sbe_tp_chiplet_init1.S procedure to start the clocks in the PERV chiplet. -// Use the cen_sbe_startclocks.S procedure to start the clocks in the NEST chiplet. -// -// The following details are from the Common POR spreadsheet sections 20.1 and 21.1 and from the Centaur Chip Spec. -// -// Common clock start actions: -// Write SCOM address 0x6B0F0013 bit(18)=0b0 multicast, drop fence in GP3 -// Write SCOM address 0x6B0F0014 bit(28)=0b1 multicast, enable EDRAM, just chiplets with EDRAM logic -// ---not centaur---Write SCOM address 0x6B0F0102 bit(40)=0b1 enable EDRAM GP0 -// Write SCOM address 0x6B000004 bit(63)=0b0 multicast, drop pervasive fence in GP0 -// Write SCOM address 0x6B000004 bit(0)=0b0, bit(1)=0b0 multicast, clear mux selects in GP0 -// Write SCOM address 0x6B000005 bit(11)=0b1 abist_mode_dc for core chiplets (core recovery) -// Write SCOM address 0x6B030007 0x0000000000000000 Write CC Scan Region Reg, set all bits='0' prior clk start -// -// Centaur-specific clock start actions: -// Write SCOM address 0x03030006 data=0x4FE0 0600 0000 0000 unicast, write CC clock region reg in MEM chiplet. start clocks -// Write SCOM address 0x03030006 data=0x4FE0 0E00 0000 0000 unicast, write CC clock region reg in MEM chiplet. start clocks -// Read SCOM address 0x03030008 expect=0x0000 001F FFFF FFFF unicast, read clock status reg in MEM chiplet -// Write SCOM address 0x02030006 data=0x4FE0 0600 0000 0000 unicast, write CC clock region reg in NEST chiplet. start clocks -// Write SCOM address 0x02030006 data=0x4FE0 0E00 0000 0000 unicast, write CC clock region reg in NEST chiplet. start clocks -// Read SCOM address 0x02030008 expect=0x0000 001F FFFF FFFF unicast, read clock status reg in NEST chiplet -// Write CFAM address 0x13 bit(02)=0b1 Set MemReset Stability Control -// Write CFAM address 0x13 bit(04)=0b1 Release D3PHY PLL Reset Control -// -// More common clock start actions: -// Write SCOM address 0x6B000004 bit(3)=0b0 multicast, clear force_align in all Chiplets in GP0 -// Write SCOM address 0x6B000004 bit(2)=0b0 multicast, clear flushmode_inhibit in Chiplet in GP0 -// -// Enable Drivers and Receivers -// Write CFAM address 0x13 bit(22:23)=0b11,bit(28:30)=0b111 Enable drivers and receivers -// -//------------------------------------------------------------------------------ -// Don't forget to create CVS comments when you check in your changes! -//------------------------------------------------------------------------------ - -#include <fapi.H> -#include <cen_scom_addresses.H> -#include <cen_mem_startclocks.H> -#include <mss_unmask_errors.H> - -// Constants -// CFAM FSI GP4 register bit/field definitions -const uint8_t FSI_GP4_MEMRESET_STABILITY_BIT = 2; -const uint8_t FSI_GP4_DPHY_PLLRESET_BIT = 4; - -// GP3 register bit/field definitions -const uint8_t GP3_FENCE_EN_BIT = 18; -const uint8_t GP3_EDRAM_ENABLE_BIT = 28; - -// GP0 register bit/field definitions -const uint8_t GP0_ABSTCLK_MUXSEL_BIT = 0; -const uint8_t GP0_SYNCCLK_MUXSEL_BIT = 1; -const uint8_t GP0_FLUSHMODE_INHIBIT_BIT = 2; -const uint8_t GP0_FORCE_ALIGN_BIT = 3; -const uint8_t GP0_ABIST_MODE_BIT = 11; -const uint8_t GP0_PERV_FENCE_BIT = 63; - -// Clock Region Register clock start data patterns -const uint64_t CLK_REGION_REG_DATA_TO_START_NSL_ARY = 0x4FE0060000000000ull; -const uint64_t CLK_REGION_REG_DATA_TO_START_ALL = 0x4FE00E0000000000ull; - -// Clock Status Register expected pattern -const uint64_t MEM_CLK_STATUS_REG_EXP_DATA = 0x0000001FFFFFFFFFull; - -// Chiplet FIR register expected pattern -const uint64_t MEM_XSTOP_FIR_REG_EXP_DATA = 0x0000000000000000ull; - - -extern "C" { - - -using namespace fapi; - -// Procedures in this file -fapi::ReturnCode cen_mem_startclocks_cloned(const fapi::Target & i_target); - -//------------------------------------------------------------------------------ -fapi::ReturnCode cen_mem_startclocks(const fapi::Target & i_target) -{ - // Target is centaur - - fapi::ReturnCode l_rc; - - l_rc = cen_mem_startclocks_cloned(i_target); - - // If mss_unmask_pervasive_errors gets it's own bad rc, - // it will commit the passed in rc (if non-zero), and return it's own bad rc. - // Else if mss_unmask_pervasive_errors runs clean, - // it will just return the passed in rc. - l_rc = mss_unmask_pervasive_errors(i_target, l_rc); - - return l_rc; -} - - -//------------------------------------------------------------------------------ -fapi::ReturnCode cen_mem_startclocks_cloned(const fapi::Target & i_target) -{ - // Target is centaur - - fapi::ReturnCode rc; - uint32_t rc_ecmd = 0; - ecmdDataBufferBase scom_data(64); - ecmdDataBufferBase cfam_data(32); - - - - FAPI_INF("********* cen_mem_startclocks start *********"); - do - { - // - // The following details are from the Common POR spreadsheet sections 20.1 and 21.1 and from the Centaur Chip Spec. - // - // Common clock start actions: - // - - - // Write SCOM address 0x030F0013 bit(18)=0b0 , drop fence in GP3 - FAPI_DBG("Writing GP3 AND mask to clear chiplet fence (bit 18) ..."); - rc_ecmd |= scom_data.flushTo1(); - rc_ecmd |= scom_data.clearBit(GP3_FENCE_EN_BIT); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to clear chiplet fence.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom( i_target, MEM_GP3_AND_0x030F0013, scom_data); - if (rc) - { - FAPI_ERR("Error writing GP3 AND mask 0x030F0013 (bit 18) to clear chiplet fence."); - break; - } - - - // Write SCOM address 0x030F0014 bit(28)=0b1 , enable EDRAM, just chiplets with EDRAM logic - FAPI_DBG("Writing GP3 OR mask to enable EDRAM (bit 28) ..."); - rc_ecmd |= scom_data.flushTo0(); - rc_ecmd |= scom_data.setBit(GP3_EDRAM_ENABLE_BIT); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to enable EDRAM.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom( i_target, MEM_GP3_OR_0x030F0014, scom_data); - if (rc) - { - FAPI_ERR("Error writing GP3 OR mask 0x030F0014 (bit 28) to enable EDRAM."); - break; - } - - - // ---not needed for centaur---Write SCOM address 0x6B0F0102 bit(40)=0b1 enable EDRAM GP0 - - - // Write SCOM address 0x03000004 bit(63)=0b0 , drop pervasive fence in GP0 - // Write SCOM address 0x03000004 bit(0)=0b0, bit(1)=0b0 , clear mux selects in GP0 - FAPI_DBG("Writing GP0 AND mask to drop pervasive fence (bit 63) ..."); - FAPI_DBG("Writing GP0 AND mask to clear mux selects (bits 0-1) ..."); - rc_ecmd |= scom_data.flushTo1(); - rc_ecmd |= scom_data.clearBit(GP0_ABSTCLK_MUXSEL_BIT); - rc_ecmd |= scom_data.clearBit(GP0_SYNCCLK_MUXSEL_BIT); - rc_ecmd |= scom_data.clearBit(GP0_PERV_FENCE_BIT); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to drop pervasive fence and clear mux selects.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom( i_target, MEM_GP0_AND_0x03000004, scom_data); - if (rc) - { - FAPI_ERR("Error writing GP0 AND mask 0x03000004 (bits 0,1,63) to drop pervasive fence and clear mux selects."); - break; - } - - - // Write SCOM address 0x03000005 bit(11)=0b1 abist_mode_dc for core chiplets (core recovery) - FAPI_DBG("Writing GP0 OR mask to set abist_mode_dc (bit 11) ..."); - rc_ecmd |= scom_data.flushTo0(); - rc_ecmd |= scom_data.setBit(GP0_ABIST_MODE_BIT); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to set abist_mode_dc.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom( i_target, MEM_GP0_OR_0x03000005, scom_data); - if (rc) - { - FAPI_ERR("Error writing GP0 OR mask 0x03000005 (bit 11) to set abist_mode_dc."); - break; - } - - - // Write SCOM address 0x03030007 0x0000000000000000 Write CC Scan Region Reg, set all bits='0' prior clk start - FAPI_DBG("Writing CC Scan Region Register to all zeros prior to clock start ..."); - rc_ecmd |= scom_data.flushTo0(); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to flush Scan Region Register.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom( i_target, MEM_CLK_SCANSEL_0x03030007, scom_data); - if (rc) - { - FAPI_ERR("Error writing CC Scan Region Register 0x03030007 to all zeros prior to clock start."); - break; - } - - - // - // Centaur-specific clock start actions: - - - // Write SCOM address 0x03030006 data=0x4FE0 0600 0000 0000 unicast, write CC clock region reg in MEM chiplet. start clocks - FAPI_DBG("Writing CC Clock Region Register to 0x4FE0060000000000 to start array and nsl clocks ..."); - rc_ecmd |= scom_data.setDoubleWord(0, CLK_REGION_REG_DATA_TO_START_NSL_ARY); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to start array and nsl clocks.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom( i_target, MEM_CLK_REGION_0x03030006, scom_data); - if (rc) - { - FAPI_ERR("Error writing CC Clock Region Register 0x03030006 to 0x4FE0060000000000 to start array and nsl clocks."); - break; - } - - - // Write SCOM address 0x03030006 data=0x4FE0 0E00 0000 0000 unicast, write CC clock region reg in MEM chiplet. start clocks - FAPI_DBG("Writing CC Clock Region Register to 0x4FE00E0000000000 to start sl clocks ..."); - rc_ecmd |= scom_data.setDoubleWord(0, CLK_REGION_REG_DATA_TO_START_ALL); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to start sl clocks.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom( i_target, MEM_CLK_REGION_0x03030006, scom_data); - if (rc) - { - FAPI_ERR("Error writing CC Clock Region Register 0x03030006 to 0x4FE00E0000000000 to start sl clocks."); - break; - } - - - // Read SCOM address 0x03030008 expect=0x0000 001F FFFF FFFF unicast, read clock status reg in MEM chiplet - FAPI_DBG("Reading CC Clock Status Register to see if clocks are running ..."); - rc = fapiGetScom( i_target, MEM_CLK_STATUS_0x03030008, scom_data); - if ( rc ) - { - FAPI_ERR("Error reading CC Clock Status Register 0x03030008."); - break; - } - if ( scom_data.getDoubleWord(0) != MEM_CLK_STATUS_REG_EXP_DATA ) - { - FAPI_ERR("Unexpected clock status! Clk Status Reg 0x03030008 = %16llX, but %16llX was expected.",scom_data.getDoubleWord(0),MEM_CLK_STATUS_REG_EXP_DATA); - uint64_t MEM_CLK_STATUS_REG = scom_data.getDoubleWord(0); - const fapi::Target & MEMBUF_CHIP_IN_ERROR = i_target; - FAPI_SET_HWP_ERROR(rc, RC_CEN_MEM_STARTCLOCKS_UNEXPECTED_CLOCK_STATUS); - break; - } - - - // The clocks for the NEST chiplet are started in the cen_sbe_startclocks.S procedure. So don't do them here! - // Write SCOM address 0x02030006 data=0x4FE0 0600 0000 0000 unicast, write CC clock region reg in NEST chiplet. start clocks - // Write SCOM address 0x02030006 data=0x4FE0 0E00 0000 0000 unicast, write CC clock region reg in NEST chiplet. start clocks - // Read SCOM address 0x02030008 expect=0x0000 001F FFFF FFFF unicast, read clock status reg in NEST chiplet - - - // Write CFAM address 0x13 bit(02)=0b1 Set MemReset Stability Control - FAPI_DBG("Writing FSI GP4 register (bit2) to set MemReset Stability control ..."); - rc = fapiGetCfamRegister( i_target, CFAM_FSI_GP4_0x00001013, cfam_data); - if (rc) - { - FAPI_ERR("Error reading FSI GP4 Regiter 0x00001013."); - break; - } - rc_ecmd |= cfam_data.setBit(FSI_GP4_MEMRESET_STABILITY_BIT); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to set MemReset Stability control.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutCfamRegister( i_target, CFAM_FSI_GP4_0x00001013, cfam_data); - if (rc) - { - FAPI_ERR("Error writing FSI GP4 0x00001013 (bit 2) to set MemReset Stability control."); - break; - } - - - // Write CFAM address 0x13 bit(04)=0b1 Release D3PHY PLL Reset Control - FAPI_DBG("Writing FSI GP4 register (bit4) to release D3PHY PLL Reset Control ..."); - rc = fapiGetCfamRegister( i_target, CFAM_FSI_GP4_0x00001013, cfam_data); - if (rc) - { - FAPI_ERR("Error reading FSI GP4 Regiter 0x00001013."); - break; - } - rc_ecmd |= cfam_data.setBit(FSI_GP4_DPHY_PLLRESET_BIT); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to release D3PHY PLL Reset Control.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutCfamRegister( i_target, CFAM_FSI_GP4_0x00001013, cfam_data); - if (rc) - { - FAPI_ERR("Error writing FSI GP4 0x00001013 (bit 4) to release D3PHY PLL Reset Control."); - break; - } - - - // - // More common clock start actions: - - - // Write SCOM address 0x03000004 bit(3)=0b0 clear force_align in all Chiplets in GP0 - FAPI_DBG("Writing GP0 AND mask to clear force_align (bit 3) ..."); - rc_ecmd |= scom_data.flushTo1(); - rc_ecmd |= scom_data.clearBit(GP0_FORCE_ALIGN_BIT); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to clear force_align.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom( i_target, MEM_GP0_AND_0x03000004, scom_data); - if (rc) - { - FAPI_ERR("Error writing GP0 AND mask 0x03000004 (bit 3) to clear force_align."); - break; - } - - - // Write SCOM address 0x03000004 bit(2)=0b0 clear flushmode_inhibit in Chiplet in GP0 - FAPI_DBG("Writing GP0 AND mask to clear flushmode_inhibit (bit 2) ..."); - rc_ecmd |= scom_data.flushTo1(); - rc_ecmd |= scom_data.clearBit(GP0_FLUSHMODE_INHIBIT_BIT); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to clear flushmode_inhibit.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom( i_target, MEM_GP0_AND_0x03000004, scom_data); - if (rc) - { - FAPI_ERR("Error writing GP0 AND mask 0x03000004 (bit 2) to clear flushmode_inhibit."); - break; - } - - - // The enablement of RI and DI is done in cen_sbe_startclocks. It does not need to be done here. - - - } while(0); - - FAPI_INF("********* cen_mem_startclocks complete *********"); - return rc; -} - -} //end extern C - - - - -/* -*************** Do not edit this area *************** -This section is automatically updated by CVS when you check in this file. -Be sure to create CVS comments when you commit so that they can be included here. -$Log: cen_mem_startclocks.C,v $ -Revision 1.13 2014/04/07 19:01:06 gollub - -#| 1.55 | gollub |07-APR-14| Added dependancy on mss_unmask_errors for cen_mem_startclocks.C - -Revision 1.12 2013/11/15 16:30:02 mfred -Changes made by Mike Jones for gerrit review, mostly for improved error handling. - -Revision 1.11 2013/07/08 13:38:27 mfred -Change one hwp_error usage from RC_MSS_UNEXPECTED_CLOCK_STATUS to RC_MSS_UNEXPECTED_MEM_CLK_STATUS. - -Revision 1.10 2013/03/04 17:56:29 mfred -Add some header comments for BACKUP and SCREEN. - -Revision 1.9 2012/06/07 13:52:27 jmcgill -use independent data buffers for cfam/scom accesses - -Revision 1.8 2012/06/06 20:04:59 jmcgill -change FSI GP3/GP4/status register accesses from SCOM->CFAM - -Revision 1.7 2012/05/31 18:29:20 mfred -Updates for RC checking and error messages, etc. - -Revision 1.6 2012/05/09 21:26:40 mfred -Removed setting of RI, DI. Added error checking to ecmdDataBuffer operations. Removed unneeded statements. - -Revision 1.5 2012/05/02 15:32:30 mfred -Take out some comments and unnecessary code - -Revision 1.4 2012/04/26 15:29:55 mfred -fix some messages and comment out FIR error for now. - -Revision 1.3 2012/04/26 14:35:34 mfred -Some fixes. - -Revision 1.2 2012/03/26 13:30:24 mfred -Replace place_holder error msgs with real error msgs. - -Revision 1.1 2012/03/23 20:34:32 mfred -Check in initial version of cen_mem_startclocks - -*/ - diff --git a/src/usr/hwpf/hwp/dram_training/mem_startclocks/cen_mem_startclocks.H b/src/usr/hwpf/hwp/dram_training/mem_startclocks/cen_mem_startclocks.H deleted file mode 100644 index b0a532852..000000000 --- a/src/usr/hwpf/hwp/dram_training/mem_startclocks/cen_mem_startclocks.H +++ /dev/null @@ -1,73 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/dram_training/mem_startclocks/cen_mem_startclocks.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2012,2014 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: cen_mem_startclocks.H,v 1.1 2012/03/23 20:34:38 mfred Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/cen_mem_startclocks.H,v $ -//------------------------------------------------------------------------------ -// *! (C) Copyright International Business Machines Corp. 2011 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -//------------------------------------------------------------------------------ -// *! TITLE : cen_mem_startclocks.H -// *! DESCRIPTION : see additional comments below -// *! OWNER NAME : Mark Fredrickson Email: mfred@us.ibm.com -// *! BACKUP NAME : Mark Bellows Email: bellows@us.ibm.com -// *! ADDITIONAL COMMENTS : -// -// Header file for cen_mem_startclocks. -// -//------------------------------------------------------------------------------ -// Don't forget to create CVS comments when you check in your changes! -//------------------------------------------------------------------------------ -// CHANGE HISTORY: -//------------------------------------------------------------------------------ -// Version:| Author: | Date: | Comment: -//---------|----------|---------|----------------------------------------------- -// 1.0 | mfred | 03/21/12| Initial creation - -#ifndef CEN_MEM_STARTCLOCKSHWPB_H_ -#define CEN_MEM_STARTCLOCKSHWPB_H_ - -#include <fapi.H> - -typedef fapi::ReturnCode (*cen_mem_startclocks_FP_t)(const fapi::Target& i_target); - -extern "C" -{ - // Target is centaur - -/** - * @brief cen_mem_startclocks procedure. The purpose of this procedure is release the tholds associated with the Centaur MEM PLL.. - * - * @param[in] i_target Reference to centaur target - * - * @return ReturnCode - */ - - fapi::ReturnCode cen_mem_startclocks(const fapi::Target& i_target); - // Target is centaur - -} // extern "C" - -#endif // CEN_MEM_STARTCLOCKSHWPB_H_ diff --git a/src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset/mss_ddr_phy_reset.C b/src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset/mss_ddr_phy_reset.C deleted file mode 100644 index 1716d7e7f..000000000 --- a/src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset/mss_ddr_phy_reset.C +++ /dev/null @@ -1,1286 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset/mss_ddr_phy_reset.C $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2012,2014 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ - -// $Id: mss_ddr_phy_reset.C,v 1.28 2014/01/31 15:09:03 mfred Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_ddr_phy_reset.C,v $ -//------------------------------------------------------------------------------ -// *! (C) Copyright International Business Machines Corp. 2011 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -//------------------------------------------------------------------------------ -// *! TITLE : mss_ddr_phy_reset -// *! DESCRIPTION : see additional comments below -// *! OWNER NAME : Mark Fredrickson Email: mfred@us.ibm.com -// *! BACKUP NAME : Mark Bellows Email: bellows@us.ibm.com -// *! SCREEN : memory_screen -// #! ADDITIONAL COMMENTS : -// -// The purpose of this procedure is to do a soft reset of the DDR PHY logic -// and to get the Centaur chip ready for DRAM initializaion. -// See sepecific instructions below. -// -//------------------------------------------------------------------------------ -// Don't forget to create CVS comments when you check in your changes! -//------------------------------------------------------------------------------ - -#include <fapi.H> -#include <cen_scom_addresses.H> -#include <mss_ddr_phy_reset.H> -#include <mss_termination_control.H> -#include <mss_unmask_errors.H> -#include <dimmBadDqBitmapFuncs.H> - -// Constants -const uint64_t DELAY_100NS = 100; // general purpose 100 ns delay for HW mode (2000 sim cycles if simclk = 20ghz) -const uint64_t DELAY_1US = 1000; // general purpose 1 usec delay for HW mode (20000 sim cycles if simclk = 20ghz) -const uint64_t DELAY_100US = 100000; // general purpose 100 usec delay for HW mode (2000000 sim cycles if simclk = 20ghz) -const uint64_t DELAY_2000SIMCYCLES = 2000; // general purpose 2000 sim cycle delay for sim mode (100 ns if simclk = 20Ghz) -const uint64_t DELAY_20000SIMCYCLES = 20000; // general purpose 20000 sim cycle delay for sim mode (1 usec if simclk = 20Ghz) -const uint64_t DELAY_2000000SIMCYCLES = 2000000; // general purpose 2000000 sim cycle delay for sim mode (100 usec if simclk = 20Ghz) - -const uint16_t DP18_PLL_EXP_LOCK_STATUS = 0xF800; // DP18 PLL lock status that is expected at the conclusion of this procedure. -const uint16_t AD32S_PLL_EXP_LOCK_STATUS = 0xC000; // AD32S PLL lock status that is expected at the conclusion of this procedure. -const uint16_t MAX_POLL_LOOPS = 10; // Loop 10 times during PLL lock polling - - -extern "C" { - - -using namespace fapi; - -// prototypes of functions called in phy reset -ReturnCode mss_deassert_force_mclk_low (const Target& i_target); -ReturnCode mss_ddr_phy_reset_cloned(const fapi::Target & i_target); -ReturnCode mss_ddr_phy_flush(const fapi::Target & i_target); - -fapi::ReturnCode mss_ddr_phy_reset(const fapi::Target & i_target) -{ - // Target is centaur.mba - - fapi::ReturnCode rc; - - rc = mss_ddr_phy_reset_cloned(i_target); - if (rc) { - FAPI_ERR(" mss_ddr_phy_reset_cloned failed! rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator()); - } - else // reset successful - { - rc = mss_slew_cal(i_target); - if (rc) { - FAPI_ERR(" mss_slew_cal failed! rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator()); - } - else // slew cal successful - { - rc = mss_ddr_phy_flush(i_target); - if (rc) { - FAPI_ERR(" mss_ddr_phy_flush failed! rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator()); - } - } - } // should exit early if any functions has a bad return code - - // If mss_unmask_ddrphy_errors gets it's own bad rc, - // it will commit the passed in rc (if non-zero), and return it's own bad rc. - // Else if mss_unmask_ddrphy_errors runs clean, - // it will just return the passed in rc. - rc = mss_unmask_ddrphy_errors(i_target, rc); - - return rc; -} - -fapi::ReturnCode mss_ddr_phy_reset_cloned(const fapi::Target & i_target) -{ - // Target is centaur.mba - - fapi::ReturnCode rc; - uint32_t rc_ecmd = 0; - uint32_t poll_count = 0; - uint32_t done_polling = 0; - uint8_t is_simulation = 0; - ecmdDataBufferBase i_data(64); - ecmdDataBufferBase dp_p0_lock_data(64); - ecmdDataBufferBase dp_p1_lock_data(64); - ecmdDataBufferBase ad_p0_lock_data(64); - ecmdDataBufferBase ad_p1_lock_data(64); - uint8_t l_dqBitmap[DIMM_DQ_RANK_BITMAP_SIZE]; // 10 byte array of bad bits - uint8_t valid_dimms = 0; - uint8_t valid_dimm[2][2]; - uint8_t num_mranks_per_dimm[2][2]; - uint8_t l_port = 0; - uint8_t l_dimm = 0; - uint8_t l_rank = 0; - bool new_error = false; - bool P0_DP0_reg_error = false; - bool P0_DP1_reg_error = false; - bool P0_DP2_reg_error = false; - bool P0_DP3_reg_error = false; - bool P0_DP4_reg_error = false; - bool P1_DP0_reg_error = false; - bool P1_DP1_reg_error = false; - bool P1_DP2_reg_error = false; - bool P1_DP3_reg_error = false; - bool P1_DP4_reg_error = false; - fapi::Target l_centaurTarget; - uint8_t continue_on_dp18_pll_lock_failure = 0; - - - FAPI_INF("********* mss_ddr_phy_reset start *********"); - do - { - - // - // Here are the specific instructions from section 14.7.3 of the Centaur Chip Specification: - // - // Run cen_ddr_phy_reset.C prepares the DDR PLLs. These PLLs were previously configured via scan init, but have - // been held in reset. At this point the PLL GP bit is deasserted to take the PLLs out of reset. - // - // The cen_ddr_phy_reset.C now resets the DDR PHY logic. This process will NOT destroy any configuration values - // previously loaded via the init file. The intent is for the initialized phase rotator configuration to remain valid after the - // soft reset completes. If this assumption fails to hold true, it will require replacing this step with a PHY hard reset, - // and then using inband configuration writes to restore all the DDR Configuration Registers. - // - // The following steps must be performed as part of the PHY reset procedure. - - - // PLL Lock cannot happen if mclk low is asserted - // this procedure was moved from draminit to: - // Deassert Force_mclk_low signal - // see CQ 216395 (HW217109) - rc = mss_deassert_force_mclk_low(i_target); - if (rc) - { - FAPI_ERR(" deassert_force_mclk_low Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator()); - break; - } - - - // - // 1. Drive all control signals to the PHY to their inactive state, idle state, or inactive value. - // (Note: The chip should already be in this state.) - FAPI_DBG("Step 1: All control signals to the PHYs should already be set to their inactive state, idle state, or inactive values.\n"); - - - - // - // 2. For DD0: Assert dfi_reset_all (GP4 bit 5 = "1") for at least 32 memory clock cycles. This signal DOES - // erradicate all DDR configuration register initialization, thereby requiring the DDR registers to be reprogrammed - // via SCOM after the PHY reset sequence completes. - // For DD1: Set mcbist_ddr_dfi_reset_recover ="1" (CCS_MODEQ(25) SCOM Addr: 0x030106A7 & 0x03010EA7) - // for at least 32 memory clock cycles. This signal does NOT reset the configuration registers - // within the PHY. - FAPI_DBG("Step 2: MBA CCS_MODEQ(25), Setting mcbist_ddr_dfi_reset_recover = 1 for DDR PHY soft reset.\n"); - rc = fapiGetScom( i_target, MEM_MBA01_CCS_MODEQ_0x030106A7, i_data); - if (rc) - { - FAPI_ERR("Error reading CCS_MODEQ register."); - break; - } - rc_ecmd |= i_data.setBit(25); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to set bit 25 of CCS_MODEQ register.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom( i_target, MEM_MBA01_CCS_MODEQ_0x030106A7, i_data); - if (rc) - { - FAPI_ERR("Error writing CCS_MODEQ register ."); - break; - } - rc = fapiDelay(DELAY_100NS, DELAY_2000SIMCYCLES); // wait 2000 simcycles (in sim mode) OR 100 nS (in hw mode) - if (rc) - { - FAPI_ERR("Error executing fapiDelay of 100ns or 2000simcycles."); - break; - } - - - - // - // 3. For DD0: Deassert dfi_reset_all (GP4 bit 5 = "0") - // For DD1: Deassert mcbist_ddr_dfi_reset_recover = "0" (CCS_MODEQ(25) SCOM Addr: 0x030106A7 0x03010EA7) - FAPI_DBG("Step 3: MBA CCS_MODEQ(25), Setting mcbist_ddr_dfi_reset_recover = 0 to release soft reset.\n"); - rc = fapiGetScom( i_target, MEM_MBA01_CCS_MODEQ_0x030106A7, i_data); - if (rc) - { - FAPI_ERR("Error reading CCS_MODEQ register ."); - break; - } - rc_ecmd |= i_data.clearBit(25); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to clear bit 25 of CCS_MODEQ register.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom( i_target, MEM_MBA01_CCS_MODEQ_0x030106A7, i_data); - if (rc) - { - FAPI_ERR("Error writing CCS_MODEQ register."); - break; - } - - - - // - // 4. Write 0x0010 to PC IO PVT N/P FET driver control registers to assert ZCTL reset and enable the internal impedance controller. - // (SCOM Addr: 0x8000C0140301143F, 0x8000C0140301183F, 0x8001C0140301143F, 0x8001C0140301183F) - FAPI_DBG("Step 4: Write 0x0010 to PC IO PVT N/P FET driver control registers to assert ZCTL reset.\n"); - rc_ecmd |= i_data.setDoubleWord(0, 0x0000000000000010ull); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to write 0x0010 into PC_IO_PVT_FET_CONTROL regs.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom( i_target, DPHY01_DDRPHY_PC_IO_PVT_FET_CONTROL_P0_0x8000C0140301143F, i_data); - if (rc) - { - FAPI_ERR("Error writing DPHY01_DDRPHY_PC_IO_PVT_FET_CONTROL_P0 register."); - break; - } - rc = fapiPutScom( i_target, DPHY01_DDRPHY_PC_IO_PVT_FET_CONTROL_P1_0x8001C0140301143F, i_data); - if (rc) - { - FAPI_ERR("Error writing DPHY01_DDRPHY_PC_IO_PVT_FET_CONTROL_P1 register."); - break; - } - - - - // - // 5. Write 0x0018 to PC IO PVT N/P FET driver control registers to deassert ZCTL reset while impedance controller is still enabled. - // (SCOM Addr: 0x8000C0140301143F, 0x8000C0140301183F, 0x8001C0140301143F, 0x8001C0140301183F) - FAPI_DBG("Step 5: Write 0x0018 to PC IO PVT N/P FET driver control registers to deassert ZCTL reset.\n"); - rc_ecmd |= i_data.setDoubleWord(0, 0x0000000000000018ull); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to write 0x0018 into PC_IO_PVT_FET_CONTROL regs.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom( i_target, DPHY01_DDRPHY_PC_IO_PVT_FET_CONTROL_P0_0x8000C0140301143F, i_data); - if (rc) - { - FAPI_ERR("Error writing DPHY01_DDRPHY_PC_IO_PVT_FET_CONTROL_P0 register."); - break; - } - rc = fapiPutScom( i_target, DPHY01_DDRPHY_PC_IO_PVT_FET_CONTROL_P1_0x8001C0140301143F, i_data); - if (rc) - { - FAPI_ERR("Error writing DPHY01_DDRPHY_PC_IO_PVT_FET_CONTROL_P1 register."); - break; - } - - - - // - // 6. Write 0x0008 to PC IO PVT N/P FET driver control registers to deassert the impedance controller. - // (SCOM Addr: 0x8000C0140301143F, 0x8000C0140301183F, 0x8001C0140301143F, 0x8001C0140301183F) - FAPI_DBG("Step 6: Write 0x0008 to PC IO PVT N/P FET driver control registers to deassert the impedance controller.\n"); - rc_ecmd |= i_data.setDoubleWord(0, 0x0000000000000008ull); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to write 0x0008 into PC_IO_PVT_FET_CONTROL regs.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom( i_target, DPHY01_DDRPHY_PC_IO_PVT_FET_CONTROL_P0_0x8000C0140301143F, i_data); - if (rc) - { - FAPI_ERR("Error writing DPHY01_DDRPHY_PC_IO_PVT_FET_CONTROL_P0 register."); - break; - } - rc = fapiPutScom( i_target, DPHY01_DDRPHY_PC_IO_PVT_FET_CONTROL_P1_0x8001C0140301143F, i_data); - if (rc) - { - FAPI_ERR("Error writing DPHY01_DDRPHY_PC_IO_PVT_FET_CONTROL_P1 register."); - break; - } - - - - // - // 7. Write 0x4000 into the PC Resets Registers. This deasserts the PLL_RESET and leaves the SYSCLK_RESET bit active - // (SCOM Addr: 0x8000C00E0301143F, 0x8001C00E0301143F, 0x8000C00E0301183F, 0x8001C00E0301183F) - FAPI_DBG("Step 7: Write 0x4000 into the PC Resets Regs. This deasserts the PLL_RESET and leaves the SYSCLK_RESET bit active.\n"); - rc_ecmd |= i_data.setDoubleWord(0, 0x0000000000004000ull); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to write 0x4000 into PC_RESETS registers.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom( i_target, DPHY01_DDRPHY_PC_RESETS_P0_0x8000C00E0301143F, i_data); - if (rc) - { - FAPI_ERR("Error writing DPHY01_DDRPHY_PC_RESETS_P0 register."); - break; - } - rc = fapiPutScom( i_target, DPHY01_DDRPHY_PC_RESETS_P1_0x8001C00E0301143F, i_data); - if (rc) - { - FAPI_ERR("Error writing DPHY01_DDRPHY_PC_RESETS_P1 register."); - break; - } - - - - // - // 8. Wait at least 1 millisecond to allow the PLLs to lock. Otherwise, poll the PC DP18 PLL Lock Status - // and the PC AD32S PLL Lock Status to determine if all PLLs have locked. - // PC DP18 PLL Lock Status should be 0xF800: (SCOM Addr: 0x8000C0000301143F, 0x8001C0000301143F, 0x8000C0000301183F, 0x8001C0000301183F) - // PC AD32S PLL Lock Status should be 0xC000: (SCOM Addr: 0x8000C0010301143F, 0x8001C0010301143F, 0x8000C0010301183F, 0x8001C0010301183F) - //------------------------ - // 8a - Poll for lock bits - FAPI_DBG("Step 8: Poll until DP18 and AD32S PLLs have locked....\n"); - do - { - rc = fapiDelay(DELAY_1US, DELAY_20000SIMCYCLES); // wait 20000 simcycles (in sim mode) OR 1 usec (in hw mode) - if (rc) - { - FAPI_ERR("Error executing fapiDelay of 1us or 20000simcycles."); - break; - } - done_polling = 1; - rc = fapiGetScom( i_target, DPHY01_DDRPHY_PC_DP18_PLL_LOCK_STATUS_P0_0x8000C0000301143F, dp_p0_lock_data); - if (rc) - { - FAPI_ERR("Error reading DPHY01_DDRPHY_PC_DP18_PLL_LOCK_STATUS_P0 register."); - break; - } - if ( dp_p0_lock_data.getHalfWord(3) != DP18_PLL_EXP_LOCK_STATUS ) done_polling = 0; - rc = fapiGetScom( i_target, DPHY01_DDRPHY_PC_DP18_PLL_LOCK_STATUS_P1_0x8001C0000301143F, dp_p1_lock_data); - if (rc) - { - FAPI_ERR("Error reading DPHY01_DDRPHY_PC_DP18_PLL_LOCK_STATUS_P1 register."); - break; - } - if ( dp_p1_lock_data.getHalfWord(3) != DP18_PLL_EXP_LOCK_STATUS ) done_polling = 0; - rc = fapiGetScom( i_target, DPHY01_DDRPHY_PC_AD32S_PLL_LOCK_STATUS_P0_0x8000C0010301143F, ad_p0_lock_data); - if (rc) - { - FAPI_ERR("Error reading DPHY01_DDRPHY_PC_AD32S_PLL_LOCK_STATUS_P0 register."); - break; - } - if ( ad_p0_lock_data.getHalfWord(3) != AD32S_PLL_EXP_LOCK_STATUS ) done_polling = 0; - rc = fapiGetScom( i_target, DPHY01_DDRPHY_PC_AD32S_PLL_LOCK_STATUS_P1_0x8001C0010301143F, ad_p1_lock_data); - if (rc) - { - FAPI_ERR("Error reading DPHY01_DDRPHY_PC_AD32S_PLL_LOCK_STATUS_P1 register."); - break; - } - if ( ad_p1_lock_data.getHalfWord(3) != AD32S_PLL_EXP_LOCK_STATUS ) done_polling = 0; - poll_count++; - } while ((done_polling == 0) && (poll_count < MAX_POLL_LOOPS)); // Poll until PLLs are locked. - if (rc) break; // Go to end of proc if error found inside polling loop. - - - if (poll_count == MAX_POLL_LOOPS) - { - - //------------------------------- - // Check to see if we should continue even if the DP18 PLL lock fails - rc = fapiGetParentChip(i_target, l_centaurTarget); - if (rc) - { - FAPI_ERR("Error getting Centaur parent target from the input MBA"); - break; - } - rc = FAPI_ATTR_GET( ATTR_CENTAUR_EC_MSS_CONTINUE_ON_DP18_PLL_LOCK_FAIL, &l_centaurTarget, continue_on_dp18_pll_lock_failure); - if (rc) - { - FAPI_ERR("Failed to get attribute: ATTR_CENTAUR_EC_MSS_CONTINUE_ON_DP18_PLL_LOCK_FAIL."); - break; - } - FAPI_DBG("Got attribute ATTR_CENTAUR_EC_MSS_CONTINUE_ON_DP18_PLL_LOCK_FAIL: value=%X.\n", continue_on_dp18_pll_lock_failure); - - //------------------------------- - // 8b - Check Port 0 DP lock bits - if ( dp_p0_lock_data.getHalfWord(3) != DP18_PLL_EXP_LOCK_STATUS ) - { - if ( dp_p0_lock_data.isBitClear(48) ) { FAPI_INF("Port 0 DP 0 PLL failed to lock!");} - if ( dp_p0_lock_data.isBitClear(49) ) { FAPI_INF("Port 0 DP 1 PLL failed to lock!");} - if ( dp_p0_lock_data.isBitClear(50) ) { FAPI_INF("Port 0 DP 2 PLL failed to lock!");} - if ( dp_p0_lock_data.isBitClear(51) ) { FAPI_INF("Port 0 DP 3 PLL failed to lock!");} - if ( dp_p0_lock_data.isBitClear(52) ) { FAPI_INF("Port 0 DP 4 PLL failed to lock!");} - if (!continue_on_dp18_pll_lock_failure) - { - FAPI_ERR("One or more DP18 port 0 (0x0C000) PLL failed to lock! Lock Status = %04X",dp_p0_lock_data.getHalfWord(3)); - FAPI_ERR("DP18 PLL lock failed and this chip does not have the known DP18 lock bug."); - const uint16_t & EXPECTED_STATUS = DP18_PLL_EXP_LOCK_STATUS; - const uint16_t ACTUAL_STATUS = dp_p0_lock_data.getHalfWord(3); - const fapi::Target & MBA_IN_ERROR = i_target; - const fapi::Target & MEMBUF_CHIP_IN_ERROR = l_centaurTarget; - FAPI_SET_HWP_ERROR(rc, RC_MSS_DP18_0_PLL_FAILED_TO_LOCK); - break; - } - // for DD1 parts that have the DP18 lock bug - keep going to initialize any other channels that might be good. - FAPI_INF("One or more DP18 port 0 (0x0C000) PLL failed to lock! Lock Status = %04X",dp_p0_lock_data.getHalfWord(3)); - FAPI_INF("Continuing anyway to initialize any other channels that might be good..."); - } - //------------------------------- - // 8c - Check Port 1 DP lock bits - if ( dp_p1_lock_data.getHalfWord(3) != DP18_PLL_EXP_LOCK_STATUS ) - { - if ( dp_p1_lock_data.isBitClear(48) ) { FAPI_INF("Port 1 DP 0 PLL failed to lock!");} - if ( dp_p1_lock_data.isBitClear(49) ) { FAPI_INF("Port 1 DP 1 PLL failed to lock!");} - if ( dp_p1_lock_data.isBitClear(50) ) { FAPI_INF("Port 1 DP 2 PLL failed to lock!");} - if ( dp_p1_lock_data.isBitClear(51) ) { FAPI_INF("Port 1 DP 3 PLL failed to lock!");} - if ( dp_p1_lock_data.isBitClear(52) ) { FAPI_INF("Port 1 DP 4 PLL failed to lock!");} - if (!continue_on_dp18_pll_lock_failure) - { - FAPI_ERR("One or more DP18 port 1 (0x1C000) PLL failed to lock! Lock Status = %04X",dp_p1_lock_data.getHalfWord(3)); - FAPI_ERR("DP18 PLL lock failed and this chip does not have the known DP18 lock bug."); - const uint16_t & EXPECTED_STATUS = DP18_PLL_EXP_LOCK_STATUS; - const uint16_t ACTUAL_STATUS = dp_p1_lock_data.getHalfWord(3); - const fapi::Target & MBA_IN_ERROR = i_target; - const fapi::Target & MEMBUF_CHIP_IN_ERROR = l_centaurTarget; - FAPI_SET_HWP_ERROR(rc, RC_MSS_DP18_1_PLL_FAILED_TO_LOCK); - break; - } - // for DD1 parts that have the DP18 lock bug - keep going to initialize any other channels that might be good. - FAPI_INF("One or more DP18 port 1 (0x1C000) PLL failed to lock! Lock Status = %04X",dp_p1_lock_data.getHalfWord(3)); - FAPI_INF("Continuing anyway to initialize any other channels that might be good..."); - } - //------------------------------- - // 8d - Check Port 0 AD lock bits - if ( ad_p0_lock_data.getHalfWord(3) != AD32S_PLL_EXP_LOCK_STATUS ) - { - FAPI_ERR("One or more AD32S port 0 (0x0C001) PLL failed to lock! Lock Status = %04X",ad_p0_lock_data.getHalfWord(3)); - const uint16_t & EXPECTED_STATUS = AD32S_PLL_EXP_LOCK_STATUS; - const uint16_t ACTUAL_STATUS = ad_p0_lock_data.getHalfWord(3); - const fapi::Target & MBA_IN_ERROR = i_target; - const fapi::Target & MEMBUF_CHIP_IN_ERROR = l_centaurTarget; - FAPI_SET_HWP_ERROR(rc, RC_MSS_AD32S_0_PLL_FAILED_TO_LOCK); - break; - } - //------------------------------- - // 8e - Check Port 1 AD lock bits - if ( ad_p1_lock_data.getHalfWord(3) != AD32S_PLL_EXP_LOCK_STATUS ) - { - FAPI_ERR("One or more AD32S port 1 (0x1C001) PLL failed to lock! Lock Status = %04X",ad_p1_lock_data.getHalfWord(3)); - const uint16_t & EXPECTED_STATUS = AD32S_PLL_EXP_LOCK_STATUS; - const uint16_t ACTUAL_STATUS = ad_p1_lock_data.getHalfWord(3); - const fapi::Target & MBA_IN_ERROR = i_target; - const fapi::Target & MEMBUF_CHIP_IN_ERROR = l_centaurTarget; - FAPI_SET_HWP_ERROR(rc, RC_MSS_AD32S_1_PLL_FAILED_TO_LOCK); - break; - } - } - else - { - FAPI_INF("AD32S PLLs are now locked. DP18 PLLs should also be locked."); - } - - - - // - // 9.Write '8024'x into the ADR SysClk Phase Rotator Control Registers and into the DP18 SysClk Phase Rotator Control Registers. - // This takes the dphy_nclk/SysClk alignment circuit out of reset and puts the dphy_nclk/SysClk alignment circuit into the Continuous Update Mode. - // ADR SysClk PR Control Registers : (SCOM Addr: 0x800080320301143F, 0x800084320301143F, 0x800180320301143F, 0x800184320301143F, - // 0x800080320301183F, 0x800084320301183F, 0x800180320301183F, 0x800184320301183F) - // DP18 SysClk PR Control Registers : (SCOM Addr: 0x800000070301143F, 0x800004070301143F, 0x800008070301143F, 0x80000C070301143F, 0x800010070301143F, - // 0x800000070301183F, 0x800004070301183F, 0x800008070301183F, 0x80000C070301183F, 0x800010070301183F, - // 0x800100070301143F, 0x800104070301143F, 0x800108070301143F, 0x80010C070301143F, 0x800110070301143F, - // 0x800100070301183F, 0x800104070301183F, 0x800108070301183F, 0x80010C070301183F, 0x800110070301183F) - FAPI_DBG("Step 9: Write '8024'x into the ADR SysClk Phase Rotator Control Regs and the DP18 SysClk Phase Rotator Control Regs.\n"); - rc_ecmd |= i_data.setDoubleWord(0, 0x0000000000008024ull); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to write 0x8024 into Phase Rotator Registers.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom( i_target, DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0_0x800080320301143F, i_data); - if (rc) - { - FAPI_ERR("Error writing DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0 register."); - break; - } - rc = fapiPutScom( i_target, DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S0_0x800180320301143F, i_data); - if (rc) - { - FAPI_ERR("Error writing DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S0 register."); - break; - } - rc = fapiPutScom( i_target, DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1_0x800084320301143F, i_data); - if (rc) - { - FAPI_ERR("Error writing DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1 register."); - break; - } - rc = fapiPutScom( i_target, DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S1_0x800184320301143F, i_data); - if (rc) - { - FAPI_ERR("Error writing DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S1 register."); - break; - } - - - - rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_0_0x800000070301143F, i_data); - if (rc) - { - FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_0 register."); - P0_DP0_reg_error = true; - } - rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_0_0x800100070301143F, i_data); - if (rc) - { - FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_0 register."); - P1_DP0_reg_error = true; - } - rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_1_0x800004070301143F, i_data); - if (rc) - { - FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_1 register."); - P0_DP1_reg_error = true; - } - rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_1_0x800104070301143F, i_data); - if (rc) - { - FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_1 register."); - P1_DP1_reg_error = true; - } - rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_2_0x800008070301143F, i_data); - if (rc) - { - FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_2 register."); - P0_DP2_reg_error = true; - } - rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_2_0x800108070301143F, i_data); - if (rc) - { - FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_2 register."); - P1_DP2_reg_error = true; - } - rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_3_0x80000C070301143F, i_data); - if (rc) - { - FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_3 register."); - P0_DP3_reg_error = true; - } - rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_3_0x80010C070301143F, i_data); - if (rc) - { - FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_3 register."); - P1_DP3_reg_error = true; - } - rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_4_0x800010070301143F, i_data); - if (rc) - { - FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_4 register."); - P0_DP4_reg_error = true; - } - rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_4_0x800110070301143F, i_data); - if (rc) - { - FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_4 register."); - P1_DP4_reg_error = true; - } - - - - // - // 10.Wait at least 5932 memory clock cycles to allow the clock alignment circuit to perform initial alignment. - FAPI_DBG("Step 10: Wait at least 5932 memory clock cycles to allow the clock alignment circuit to perform initial alignment.\n"); - rc = fapiDelay(DELAY_100US, DELAY_2000000SIMCYCLES); // wait 2000000 simcycles (in sim mode) OR 100 usec (in hw mode) - if (rc) - { - FAPI_ERR("Error executing fapiDelay of 100us or 2000000simcycles."); - break; - } - - - - // - // 11.Write 0x0000 into the PC Resets Register. This deasserts the SysClk Reset - // (SCOM Addr: 0x8000C00E0301143F, 0x8001C00E0301143F, 0x8000C00E0301183F, 0x8001C00E0301183F) - FAPI_DBG("Step 11: Write 0x0000 into the PC Resets Register. This deasserts the SysClk Reset.\n"); - rc_ecmd |= i_data.setDoubleWord(0, 0x0000000000000000ull); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to write 0x0000 into the PC Resets registers.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom( i_target, DPHY01_DDRPHY_PC_RESETS_P0_0x8000C00E0301143F, i_data); - if (rc) - { - FAPI_ERR("Error writing DPHY01_DDRPHY_PC_RESETS_P0 register."); - break; - } - rc = fapiPutScom( i_target, DPHY01_DDRPHY_PC_RESETS_P1_0x8001C00E0301143F, i_data); - if (rc) - { - FAPI_ERR("Error writing DPHY01_DDRPHY_PC_RESETS_P1 register."); - break; - } - - - - // - // 12.Write '8020'x into the ADR SysClk Phase Rotator Control Registers and into the DP18 SysClk Phase Rotator Control Registers. - // This takes the dphy_nclk/SysClk alignment circuit out of Continuous Update Mode. - // ADR SysClk PR Control Registers : (SCOM Addr: 0x800080320301143F, 0x800084320301143F, 0x800180320301143F, 0x800184320301143F, - // 0x800080320301183F, 0x800084320301183F, 0x800180320301183F, 0x800184320301183F) - // DP18 SysClk PR Control Registers : (SCOM Addr: 0x800000070301143F, 0x800004070301143F, 0x800008070301143F, 0x80000C070301143F, 0x800010070301143F, - // 0x800000070301183F, 0x800004070301183F, 0x800008070301183F, 0x80000C070301183F, 0x800010070301183F, - // 0x800100070301143F, 0x800104070301143F, 0x800108070301143F, 0x80010C070301143F, 0x800110070301143F, - // 0x800100070301183F, 0x800104070301183F, 0x800108070301183F, 0x80010C070301183F, 0x800110070301183F) - FAPI_DBG("Step 12: Write '8020'x into the ADR SysClk Phase Rotator Control Regs and the DP18 SysClk Phase Rotator Control Regs.\n"); - rc_ecmd |= i_data.setDoubleWord(0, 0x0000000000008020ull); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to write 0x8020 into the Phase Rotator registers.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom( i_target, DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0_0x800080320301143F, i_data); - if (rc) - { - FAPI_ERR("Error writing DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0 register."); - break; - } - rc = fapiPutScom( i_target, DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S0_0x800180320301143F, i_data); - if (rc) - { - FAPI_ERR("Error writing DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S0 register."); - break; - } - rc = fapiPutScom( i_target, DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1_0x800084320301143F, i_data); - if (rc) - { - FAPI_ERR("Error writing DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1 register."); - break; - } - rc = fapiPutScom( i_target, DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S1_0x800184320301143F, i_data); - if (rc) - { - FAPI_ERR("Error writing DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S1 register."); - break; - } - - - - rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_0_0x800000070301143F, i_data); - if (rc) - { - FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_0 register."); - P0_DP0_reg_error = true; - } - rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_0_0x800100070301143F, i_data); - if (rc) - { - FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_0 register."); - P1_DP0_reg_error = true; - } - rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_1_0x800004070301143F, i_data); - if (rc) - { - FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_1 register."); - P0_DP1_reg_error = true; - } - rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_1_0x800104070301143F, i_data); - if (rc) - { - FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_1 register."); - P1_DP1_reg_error = true; - } - rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_2_0x800008070301143F, i_data); - if (rc) - { - FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_2 register."); - P0_DP2_reg_error = true; - } - rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_2_0x800108070301143F, i_data); - if (rc) - { - FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_2 register."); - P1_DP2_reg_error = true; - } - rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_3_0x80000C070301143F, i_data); - if (rc) - { - FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_3 register."); - P0_DP3_reg_error = true; - } - rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_3_0x80010C070301143F, i_data); - if (rc) - { - FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_3 register."); - P1_DP3_reg_error = true; - } - rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_4_0x800010070301143F, i_data); - if (rc) - { - FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_4 register."); - P0_DP4_reg_error = true; - } - rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_4_0x800110070301143F, i_data); - if (rc) - { - FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_4 register."); - P1_DP4_reg_error = true; - } - - - - // Work-around required to get alignment in simulation - // Read the ATTR_IS_SIMULATION attribute - rc = FAPI_ATTR_GET( ATTR_IS_SIMULATION, NULL, is_simulation); - if (rc) - { - FAPI_ERR("Failed to get attribute: ATTR_IS_SIMULATION."); - break; - } - if (is_simulation) - { - FAPI_DBG("Step 12.1 (SIM ONLY): Write '8000'x into the ADR SysClk Phase Rotator Control Regs and the DP18 SysClk Phase Rotator Control Regs.\n"); - rc_ecmd |= i_data.setDoubleWord(0, 0x0000000000008000ull); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to write 0x8020 into the Phase Rotator registers.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom( i_target, DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0_0x800080320301143F, i_data); - if (rc) - { - FAPI_ERR("Error writing DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0 register."); - break; - } - rc = fapiPutScom( i_target, DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S0_0x800180320301143F, i_data); - if (rc) - { - FAPI_ERR("Error writing DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S0 register."); - break; - } - rc = fapiPutScom( i_target, DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1_0x800084320301143F, i_data); - if (rc) - { - FAPI_ERR("Error writing DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1 register."); - break; - } - rc = fapiPutScom( i_target, DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S1_0x800184320301143F, i_data); - if (rc) - { - FAPI_ERR("Error writing DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S1 register."); - break; - } - - - - rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_0_0x800000070301143F, i_data); - if (rc) - { - FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_0 register."); - P0_DP0_reg_error = true; - } - rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_0_0x800100070301143F, i_data); - if (rc) - { - FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_0 register."); - P1_DP0_reg_error = true; - } - rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_1_0x800004070301143F, i_data); - if (rc) - { - FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_1 register."); - P0_DP1_reg_error = true; - } - rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_1_0x800104070301143F, i_data); - if (rc) - { - FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_1 register."); - P1_DP1_reg_error = true; - } - rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_2_0x800008070301143F, i_data); - if (rc) - { - FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_2 register."); - P0_DP2_reg_error = true; - } - rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_2_0x800108070301143F, i_data); - if (rc) - { - FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_2 register."); - P1_DP2_reg_error = true; - } - rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_3_0x80000C070301143F, i_data); - if (rc) - { - FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_3 register."); - P0_DP3_reg_error = true; - } - rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_3_0x80010C070301143F, i_data); - if (rc) - { - FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_3 register."); - P1_DP3_reg_error = true; - } - rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_4_0x800010070301143F, i_data); - if (rc) - { - FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_4 register."); - P0_DP4_reg_error = true; - } - rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_4_0x800110070301143F, i_data); - if (rc) - { - FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_4 register."); - P1_DP4_reg_error = true; - } - - - FAPI_DBG("Step 12.2 (SIM ONLY): Write '8080'x into the ADR SysClk Phase Rotator Control Regs and the DP18 SysClk Phase Rotator Control Regs.\n"); - rc_ecmd |= i_data.setDoubleWord(0, 0x0000000000008080ull); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to write 0x8020 into the Phase Rotator registers.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom( i_target, DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0_0x800080320301143F, i_data); - if (rc) - { - FAPI_ERR("Error writing DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0 register."); - break; - } - rc = fapiPutScom( i_target, DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S0_0x800180320301143F, i_data); - if (rc) - { - FAPI_ERR("Error writing DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S0 register."); - break; - } - rc = fapiPutScom( i_target, DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1_0x800084320301143F, i_data); - if (rc) - { - FAPI_ERR("Error writing DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1 register."); - break; - } - rc = fapiPutScom( i_target, DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S1_0x800184320301143F, i_data); - if (rc) - { - FAPI_ERR("Error writing DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S1 register."); - break; - } - - - - rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_0_0x800000070301143F, i_data); - if (rc) - { - FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_0 register."); - P0_DP0_reg_error = true; - } - rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_0_0x800100070301143F, i_data); - if (rc) - { - FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_0 register."); - P1_DP0_reg_error = true; - } - rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_1_0x800004070301143F, i_data); - if (rc) - { - FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_1 register."); - P0_DP1_reg_error = true; - } - rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_1_0x800104070301143F, i_data); - if (rc) - { - FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_1 register."); - P1_DP1_reg_error = true; - } - rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_2_0x800008070301143F, i_data); - if (rc) - { - FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_2 register."); - P0_DP2_reg_error = true; - } - rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_2_0x800108070301143F, i_data); - if (rc) - { - FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_2 register."); - P1_DP2_reg_error = true; - } - rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_3_0x80000C070301143F, i_data); - if (rc) - { - FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_3 register."); - P0_DP3_reg_error = true; - } - rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_3_0x80010C070301143F, i_data); - if (rc) - { - FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_3 register."); - P1_DP3_reg_error = true; - } - rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_4_0x800010070301143F, i_data); - if (rc) - { - FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_4 register."); - P0_DP4_reg_error = true; - } - rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_4_0x800110070301143F, i_data); - if (rc) - { - FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_4 register."); - P1_DP4_reg_error = true; - } - } - - - // - // 13.Wait at least 32 memory clock cycles. - FAPI_DBG("Step 13: Wait at least 32 memory clock cycles.\n"); - rc = fapiDelay(DELAY_100NS, DELAY_2000SIMCYCLES); // wait 2000 simcycles (in sim mode) OR 100 nS (in hw mode) - if (rc) - { - FAPI_ERR("Error executing fapiDelay of 100ns or 2000simcycles."); - break; - } - - - - // - // 14.Write 0x0018 to PC IO PVT N/P FET driver control register to enable internal ZQ calibration. - // This step takes approximately 2112 (64 * 33) memory clock cycles. - // (SCOM Addr: 0x8000C0140301143F, 0x8000C0140301183F, 0x8001C0140301143F, 0x8001C0140301183F) - FAPI_DBG("Step 14: Write 0x0018 to PC IO PVT N/P FET driver control register to enable internal ZQ calibration.\n"); - rc_ecmd |= i_data.setDoubleWord(0, 0x0000000000000018ull); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to write 0x0018 into the PC_IO_PVT_FET_CONTROL registers.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom( i_target, DPHY01_DDRPHY_PC_IO_PVT_FET_CONTROL_P0_0x8000C0140301143F, i_data); - if (rc) - { - FAPI_ERR("Error writing DPHY01_DDRPHY_PC_IO_PVT_FET_CONTROL_P0 register."); - break; - } - rc = fapiPutScom( i_target, DPHY01_DDRPHY_PC_IO_PVT_FET_CONTROL_P1_0x8001C0140301143F, i_data); - if (rc) - { - FAPI_ERR("Error writing DPHY01_DDRPHY_PC_IO_PVT_FET_CONTROL_P1 register."); - break; - } - - - - - - // - // Now do some error checking and mark bad channels - // Check to see if there were any register access problems on DP registers, or corresponding PLLs that did not lock. - // If so, mark the DP pairs as bad. - - // Loop through only valid (functional) dimms. - // For each valid dimm, loop through all the ranks belonging to that dimm. - // If there was either a register access error, or if the PLL did not lock, then mark the DP pair as bad. - // Do this by setting the dqBitmap attribute for all dimms and ranks associated with that PLL or register. - // Read the dqBitmap first, so that you do not clear values that may already be set. - // (Some DP channels may already be marked as bad.) - - // Find out which dimms are functional - rc = FAPI_ATTR_GET(ATTR_MSS_EFF_DIMM_FUNCTIONAL_VECTOR, &i_target, valid_dimms); - if (rc) - { - FAPI_ERR("Failed to get attribute: ATTR_MSS_EFF_DIMM_FUNCTIONAL_VECTOR"); - break; - } - valid_dimm[0][0] = (valid_dimms & 0x80); - valid_dimm[0][1] = (valid_dimms & 0x40); - valid_dimm[1][0] = (valid_dimms & 0x08); - valid_dimm[1][1] = (valid_dimms & 0x04); - - // Find out how many ranks are on each dimm - rc = FAPI_ATTR_GET( ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM, &i_target, num_mranks_per_dimm); - if (rc) - { - FAPI_ERR("Failed to get attribute: ATTR_EFF_NUM_RANKS_PER_DIMM."); - break; - } - - - // Loop through each PORT (0,1) - for(l_port=0; l_port<1; l_port++ ) - { - // Loop through each DIMM:(0,1) - for(l_dimm=0; l_dimm<DIMM_DQ_MAX_MBAPORT_DIMMS; l_dimm++ ) - { - if (valid_dimm[l_port][l_dimm]) - { - // Ok, this DIMM is functional. So loop through the RANKs of this dimm. - for(l_rank=0; l_rank<num_mranks_per_dimm[l_port][l_dimm]; l_rank++ ) - { - // Get the bad DQ Bitmap for l_port, l_dimm, l_rank - rc = dimmGetBadDqBitmap(i_target, - l_port, - l_dimm, - l_rank, - l_dqBitmap); - if (rc) - { - FAPI_ERR("Error from dimmGetBadDqBitmap"); - break; - } - - // Mark the bad bits for each register that had problems or PLL that did not lock - new_error = false; - if ( l_port == 0 ) - { - if (( P0_DP0_reg_error ) || ( dp_p0_lock_data.isBitClear(48) )) { l_dqBitmap[0] = 0xff; l_dqBitmap[1] = 0xff; new_error = true; } - if (( P0_DP1_reg_error ) || ( dp_p0_lock_data.isBitClear(49) )) { l_dqBitmap[2] = 0xff; l_dqBitmap[3] = 0xff; new_error = true; } - if (( P0_DP2_reg_error ) || ( dp_p0_lock_data.isBitClear(50) )) { l_dqBitmap[4] = 0xff; l_dqBitmap[5] = 0xff; new_error = true; } - if (( P0_DP3_reg_error ) || ( dp_p0_lock_data.isBitClear(51) )) { l_dqBitmap[6] = 0xff; l_dqBitmap[7] = 0xff; new_error = true; } - if (( P0_DP4_reg_error ) || ( dp_p0_lock_data.isBitClear(52) )) { l_dqBitmap[8] = 0xff; l_dqBitmap[9] = 0xff; new_error = true; } - } else { - if (( P1_DP0_reg_error ) || ( dp_p1_lock_data.isBitClear(48) )) { l_dqBitmap[0] = 0xff; l_dqBitmap[1] = 0xff; new_error = true; } - if (( P1_DP1_reg_error ) || ( dp_p1_lock_data.isBitClear(49) )) { l_dqBitmap[2] = 0xff; l_dqBitmap[3] = 0xff; new_error = true; } - if (( P1_DP2_reg_error ) || ( dp_p1_lock_data.isBitClear(50) )) { l_dqBitmap[4] = 0xff; l_dqBitmap[5] = 0xff; new_error = true; } - if (( P1_DP3_reg_error ) || ( dp_p1_lock_data.isBitClear(51) )) { l_dqBitmap[6] = 0xff; l_dqBitmap[7] = 0xff; new_error = true; } - if (( P1_DP4_reg_error ) || ( dp_p1_lock_data.isBitClear(52) )) { l_dqBitmap[8] = 0xff; l_dqBitmap[9] = 0xff; new_error = true; } - } - - // If there are new errors, write back the bad DQ Bitmap for l_port, l_dimm, l_rank - if ( new_error ) - { - rc = dimmSetBadDqBitmap(i_target, - l_port, - l_dimm, - l_rank, - l_dqBitmap); - if (rc) - { - FAPI_ERR("Error from dimmPutBadDqBitmap"); - break; - } - } - } // End of loop over RANKs - if (rc) break; // Go to end of proc if error found inside loop. - } - } // End of loop over DIMMs - if (rc) break; // Go to end of proc if error found inside loop. - } // End of loop over PORTs - - - } while(0); - - FAPI_INF("********* mss_ddr_phy_reset complete *********"); - - return rc; -} - - -// function moved from draminit because we need mclk low not asserted for pll locking -ReturnCode mss_deassert_force_mclk_low (const Target& i_target) -{ - ReturnCode rc; - uint32_t rc_num = 0; - ecmdDataBufferBase data_buffer(64); - - FAPI_INF( "+++++++++++++++++++++ DEASSERTING FORCE MCLK LOW +++++++++++++++++++++"); - - - rc = fapiGetScom(i_target, MEM_MBA01_CCS_MODEQ_0x030106A7, data_buffer); - if(rc) return rc; - rc_num = data_buffer.setBit(63); - rc.setEcmdError( rc_num); - if(rc) return rc; - rc = fapiPutScom(i_target, MEM_MBA01_CCS_MODEQ_0x030106A7, data_buffer); - if(rc) return rc; - - return rc; -} - -fapi::ReturnCode mss_ddr_phy_flush(const fapi::Target & i_target) -{ - fapi::ReturnCode rc; - uint32_t rc_ecmd = 0; - ecmdDataBufferBase i_data(64); - ecmdDataBufferBase l_mask(64); - - FAPI_INF(" Performing mss_ddr_phy_flush routine"); - - FAPI_INF("ADR/DP18 FLUSH: 1) set PC_POWERDOWN_1 register, powerdown enable(48), flush bit(58)"); - rc_ecmd = i_data.flushTo0(); // clear data buffer - rc_ecmd |= i_data.setBit(48); // set MASTER_PD_CNTL bit - rc_ecmd |= i_data.setBit(58); // set WR_FIFO_STAB bit - - rc_ecmd |= l_mask.flushTo0(); // clear mask buffer - rc_ecmd |= l_mask.setBit(48); // set MASTER_PD_CNTL bit - rc_ecmd |= l_mask.setBit(58); // set WR_FIFO_STAB mask bit - if (rc_ecmd) - { - rc.setEcmdError(rc_ecmd); - return rc; - } - - rc = fapiPutScomUnderMask(i_target, DPHY01_DDRPHY_PC_POWERDOWN_1_P0_0x8000C0100301143F, i_data, l_mask); - if(rc) return rc; - - rc = fapiPutScomUnderMask(i_target, DPHY01_DDRPHY_PC_POWERDOWN_1_P1_0x8001C0100301143F, i_data, l_mask); - if(rc) return rc; - - rc = fapiDelay(DELAY_100NS, DELAY_2000SIMCYCLES); // wait 2000 simcycles (in sim mode) OR 100 nS (in hw mode) - if(rc) return rc; - - FAPI_INF("ADR/DP18 FLUSH: 2) clear PC_POWERDOWN_1 register, powerdown enable(48), flush bit(58)"); - rc_ecmd = i_data.flushTo0(); // clear data buffer - - rc_ecmd |= l_mask.flushTo0(); // clear mask buffer - rc_ecmd |= l_mask.setBit(48); // set MASTER_PD_CNTL bit - rc_ecmd |= l_mask.setBit(58); // set WR_FIFO_STAB mask bit - if (rc_ecmd) - { - rc.setEcmdError(rc_ecmd); - return rc; - } - - rc = fapiPutScomUnderMask(i_target, DPHY01_DDRPHY_PC_POWERDOWN_1_P0_0x8000C0100301143F, i_data, l_mask); - if(rc) return rc; - - rc = fapiPutScomUnderMask(i_target, DPHY01_DDRPHY_PC_POWERDOWN_1_P1_0x8001C0100301143F, i_data, l_mask); - if(rc) return rc; - - return rc; -} - -} //end extern C - - -/* -*************** Do not edit this area *************** -This section is automatically updated by CVS when you check in this file. -Be sure to create CVS comments when you commit so that they can be included here. - -$Log: mss_ddr_phy_reset.C,v $ -Revision 1.28 2014/01/31 15:09:03 mfred -Mike Jones added statements to pass target into XML for callouts. - -Revision 1.27 2014/01/16 20:54:48 mfred -Updates for passing more data to error handler. From Mike Jones. - -Revision 1.26 2013/09/16 20:17:57 mwuu -Cleanup of the calling functions so first fail will run unmask function. - -Revision 1.25 2013/06/26 17:40:56 mwuu -Submitting Mark Fredrickson's clean up from FW review. - -Revision 1.24 2013/06/19 20:07:53 mwuu -Implemented new ADR flush procedure via powerdown1 register. - -Revision 1.22 2013/06/14 17:44:49 mwuu -Backed out the ADR flush workaround. - -Revision 1.21 2013/06/12 23:17:19 mwuu -Removed DP18 flush section, fixed ADR toggle flush loop. - -Revision 1.20 2013/06/12 20:58:17 mwuu -Fixed loop control structure for toggling the 0,1,0 in ADR block of flush FN. - -Revision 1.19 2013/06/11 19:05:27 mwuu -Update to use master ranks for bad bitmap, and added flush function for ADR/DP18 workaround. - -Revision 1.18 2013/03/18 19:38:48 mfred -Update to not continue if DP18 PLL fails to lock and EC is DD2. - -Revision 1.17 2012/12/03 15:49:27 mfred -Fixed bug to allow exit from loops in case of error. - -Revision 1.16 2012/11/29 23:02:53 mfred -Fix for ZQ_CAL workaround and support for partial set of dimms. - -Revision 1.15 2012/11/16 16:36:20 mfred -Update code to return an error from mss_slew_cal, if any, unless there is an error from mss_ddr_phy_reset. - -Revision 1.14 2012/11/14 23:42:43 mfred -Call mss_slew_cal after the ddr_phy_reset steps. - -Revision 1.13 2012/10/19 20:27:26 mfred -Added support for sub-partial-good operation when only a subset of DPs are good. - -Revision 1.12 2012/09/06 15:01:46 gollub - -Calling mss_unmask_ddrphy_errors after mss_ddr_phy_reser_cloned. - -Revision 1.11 2012/07/27 16:43:25 bellows -CQ216395 hardware needs force mclk low in phy reset procedure - -Revision 1.10 2012/07/24 17:11:02 mfred -Removed confusing comment. - -Revision 1.9 2012/07/18 16:27:39 mfred -Check for ATTR_IS_SIMULATION attribute instead of use compiler switch. - -Revision 1.8 2012/06/07 22:30:25 jmcgill -add sim only inits for phase rotator alignment (wrapped in SIM_ONLY ifdef for now) - -Revision 1.7 2012/05/31 18:27:54 mfred -Removing some config settings that are now done in config file. See Gary Van Huben note May 3, 2012 - -Revision 1.6 2012/03/21 18:16:25 mfred -Remove some commented out lines. - -Revision 1.5 2012/03/21 18:12:24 mfred -Made updates requested by GFW team during code review 1. - -Revision 1.4 2012/02/22 18:36:36 mfred -update for PLL lock polling, and check for ddr3 vs ddr4 - -Revision 1.3 2012/02/14 16:34:12 mfred -Fixed code to use halfword(3) instead of halfword(0) - -Revision 1.2 2012/01/31 18:42:07 mfred -Change proc to do a single MBA and DDRPHY. Looping will be handled by the target. - -Revision 1.1 2011/11/18 14:20:10 mfred -Changed name of cen_ddr_phy_reset to mss_ddr_phy_reset. - -Revision 1.1 2011/10/27 22:49:36 mfred -New version of cen_ddr_phy_reset that support the extended scom addresses. - -Revision 1.5 2011/04/29 16:44:06 mfred -Removed a couple of unused address variables. - -Revision 1.4 2011/04/18 20:12:49 mfred -Update scom addresses in comments and fix steps 10 and 13 per info from Gary H. - -Revision 1.3 2011/04/18 18:54:58 mfred -Fixed some output messages. - -Revision 1.2 2011/04/12 13:22:32 mfred -Fixed some output messages. - -Revision 1.1 2011/04/07 16:15:03 mfred -Initial release. - - -*/ - diff --git a/src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset/mss_ddr_phy_reset.H b/src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset/mss_ddr_phy_reset.H deleted file mode 100644 index e03f9e4ab..000000000 --- a/src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset/mss_ddr_phy_reset.H +++ /dev/null @@ -1,73 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset/mss_ddr_phy_reset.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2012,2014 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: mss_ddr_phy_reset.H,v 1.2 2012/03/21 18:12:28 mfred Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_ddr_phy_reset.H,v $ -//------------------------------------------------------------------------------ -// *! (C) Copyright International Business Machines Corp. 2011 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -//------------------------------------------------------------------------------ -// *! TITLE : mss_ddr_phy_reset.H -// *! DESCRIPTION : see additional comments below -// *! OWNER NAME : Mark Fredrickson Email: mfred@us.ibm.com -// *! BACKUP NAME : Mark Bellows Email: bellows@us.ibm.com -// *! ADDITIONAL COMMENTS : -// -// Header file for mss_ddr_phy_reset. -// -//------------------------------------------------------------------------------ -// Don't forget to create CVS comments when you check in your changes! -//------------------------------------------------------------------------------ -// CHANGE HISTORY: -//------------------------------------------------------------------------------ -// Version:| Author: | Date: | Comment: -//---------|----------|---------|----------------------------------------------- -// 1.1 | mfred | 11/19/11| Updated - -#ifndef MSS_DDR_PHY_RESETHWPB_H_ -#define MSS_DDR_PHY_RESETHWPB_H_ - -#include <fapi.H> - -typedef fapi::ReturnCode (*mss_ddr_phy_reset_FP_t)(const fapi::Target& i_target); - -extern "C" -{ - // Target is centaur.mba - -/** - * @brief mss_ddr_phy_reset procedure. The purpose of this procedure is to do a soft reset of the DDR PHY logic and cause the DDR PLLs to lock. - * - * @param[in] i_target Reference to centaur.mba target - * - * @return ReturnCode - */ - - fapi::ReturnCode mss_ddr_phy_reset(const fapi::Target& i_target); - // Target is centaur.mba - -} // extern "C" - -#endif // MSS_DDR_PHY_RESETHWPB_H_ diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_ddr4_funcs.H b/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_ddr4_funcs.H deleted file mode 100644 index 327b8940e..000000000 --- a/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_ddr4_funcs.H +++ /dev/null @@ -1,110 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/dram_training/mss_draminit/mss_ddr4_funcs.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2013,2015 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: mss_ddr4_funcs.H,v 1.5 2015/09/04 18:14:20 thi Exp $ - -//------------------------------------------------------------------------------ -// *! (C) Copyright International Business Machines Corp. 2013 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -//------------------------------------------------------------------------------ -// *! TITLE : mss_ddr4_funcs.H -// *! DESCRIPTION : Tools for DDR4 DIMMs centaur procedures -// *! OWNER NAME : jdsloat@us.ibm.com -// *! BACKUP NAME : sglancy@us.ibm.com -// #! ADDITIONAL COMMENTS : -// - -//------------------------------------------------------------------------------ -// Don't forget to create CVS comments when you check in your changes! -//------------------------------------------------------------------------------ -// CHANGE HISTORY: -//------------------------------------------------------------------------------ -// Version:| Author: | Date: | Comment: -//---------|----------|---------|----------------------------------------------- -// | | | -// 1.5 | 09/04/15 | thi | Fix Doxygen -// 1.4 | 03/14/14 | kcook | Added DDR4 Register function support. -// 1.3 | 10/10/13 | bellows | Added required CVS Id comment -// 1.2 | 10/09/13 | jdsloat | Fixed argument list in function call -// 1.1 | 10/04/13 | jdsloat | First revision - -#ifndef _MSS_DDR4_FUNCS_H -#define _MSS_DDR4_FUNCS_H - - -//---------------------------------------------------------------------- -// DDR4 FUNCS -//---------------------------------------------------------------------- - - -//-------------------------------------------------------------- -// @brief Set MRS1 settings for Rank 0 and Rank 1 -// -// @param[in] i_target Reference to MBA Target. -// @param[in] i_port_number MBA port number -// @param[in/out] io_ccs_inst_cnt CCS instruction count -// -// @return ReturnCode -//-------------------------------------------------------------- -fapi::ReturnCode mss_mrs_load_ddr4( fapi::Target& i_target, - uint32_t i_port_number, - uint32_t& io_ccs_inst_cnt); - -//-------------------------------------------------------------- -// @brief Writes MPR pattern for inverted address location for -// training with DDR4 RDIMMs. -// -// @param[in] i_target_mba Reference to MBA Target. -// -// @return ReturnCode -//-------------------------------------------------------------- -fapi::ReturnCode mss_ddr4_invert_mpr_write( fapi::Target& i_target_mba); - -//-------------------------------------------------------------- -// @brief Writes RCD control words for DDR4 register. -// -// @param[in] i_target Reference to MBA Target. -// @param[in] i_port_number MBA port number -// @param[in/out] io_ccs_inst_cnt CCS instruction count -// -// @return ReturnCode -//-------------------------------------------------------------- -fapi::ReturnCode mss_rcd_load_ddr4( - fapi::Target& i_target, - uint32_t i_port_number, - uint32_t& io_ccs_inst_cnt); - -//-------------------------------------------------------------- -// @brief Creates RCD_CNTRL_WORD attribute for DDR4 register -// -// @param[in] i_target_mba Reference to MBA Target. -// -// @return ReturnCode -//-------------------------------------------------------------- -fapi::ReturnCode mss_create_rcd_ddr4( const fapi::Target& i_target_mba); - -#endif /* _MSS_DDR4_FUNCS_H */ - - diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.C b/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.C deleted file mode 100755 index e95011aee..000000000 --- a/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.C +++ /dev/null @@ -1,2532 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.C $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2012,2015 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: mss_draminit.C,v 1.70 2015/09/04 01:10:11 kmack Exp $ -//------------------------------------------------------------------------------ -// Don't forget to create CVS comments when you check in your changes! -//------------------------------------------------------------------------------ -// CHANGE HISTORY: -//------------------------------------------------------------------------------ -// Version:| Author: | Date: | Comment: -//---------|----------|---------|----------------------------------------------- -// 1.70 | kmack |01-Sep-15| Fixed more RCs and removed extraneous comments -// 1.69 | kmack |28-Aug-15| Fixed an RC -// 1.68 | kmack |10-Aug-15| Moved the mss_lrdimm_ddr4_db_load call to the be included or not included based on def FAPI_LRDIMM -// 1.67 | kmack |05-Aug-15| Commented out FAPI_DDR4 code -// 1.66 | jdsloat |09-MAY-14| Added an explicit 500us delay before execution of MRS cmds. -// 1.65 | jdsloat |09-APL-14| Fixed ifdef around #include mss_lrdimm_ddr4_funcs.H -// 1.64 | jdsloat |01-APL-14| RAS review edits/changes -// 1.63 | jdsloat |01-APL-14| RAS review edits/changes -// 1.62 | jdsloat |28-MAR-14| RAS review edits/changes -// 1.61 | kcook | 03/18/13| Added include mss_lrdimm_ddr4_funcs.H -// 1.60 | kcook | 03/14/13| Added calls to DDR4 ISDIMM functions. -// 1.59 | jdsloat | 11/11/13| Changed EFF attributes to VPD named attributes -// 1.58 | jdsloat | 10/15/13| Added rc checks in ddr4 shadow regs check per review request -// 1.57 | jdsloat | 10/09/13| Added mrs_load_ddr4 with defines for ddr4 usage, added shadow regs, removed complicated flow -// 1.56 | bellows | 09/16/13| Hostboot compile fix -// 1.55 | kcook | 09/13/13| Updated define FAPI_LRDIMM token. -// 1.54 | kcook | 08/27/13| Removed LRDIMM support to mss_lrdimm_funcs.C. -// | | | Added check for valid rank when flagging address mirroring. -// 1.53 | kcook | 08/16/13| Added LRDIMM support. Use with mss_funcs.C v1.32. -// 1.52 | jdsloat | 08/07/13| Added a single rc_num check and edited a debug/error message to make firmware happy. -// 1.51 | jdsloat | 08/01/13| Fixed dimm/rank conversion in address mirroring phy setting for a 4 rank dimm scenario -// 1.50 | mwuu | 07/17/13| Fixed CS when accessing RCD words on 1 rank RDIMMs -// | | | Added checks for invalid RTT_NOM, RTT_WR -// 1.49 | jdsloat | 06/11/13| Added several rc checks -// 1.48 | jdsloat | 05/20/13| Updated Mirror mode for DDR4 and keyed off new mba mirror_mode attribute -// 1.47 | jdsloat | 04/09/13| Added position info to debug messages -// | | | Added setup cycle for 2N mode -// | | | Added CKE high for RCD -// | | | Moved address mirror mode into its own function in mss_funcs -// 1.46 | jdsloat | 02/12/13| Fixed RTT_WR in MR2 -// 1.45 | jdsloat | 01/28/13| is_sim check for address mirror mode -// 1.44 | jdsloat | 01/25/13| Address Mirror Mode added for dual drop CDIMMs -// 1.43 | bellows | 12/06/12| Fixed Review Comment -// 1.42 | jdsloat | 12/02/12| SHADOW REG PRINT OUT FIX -// 1.41 | jdsloat | 11/19/12| RCD Bit order fix. -// 1.40 | jdsloat | 11/17/12| MPR operation bit (MRS3, ADDR2) fix -// 1.39 | gollub | 9/05/12 | Calling mss_unmask_draminit_errors after mss_draminit_cloned -// 1.38 | jdsloat | 8/29/12 | Fixed Shadow Regs with Regression -// 1.37 | jdsloat | 8/28/12 | Revert back to 1.35. -// 1.36 | jdsloat | 7/25/12 | Printing out contents of MRS shadow registers. -// 1.35 | bellows | 7/25/12 | CQ 216395 (move force mclk low deassert to phyreset, resetn toggle) -// 1.34 | bellows | 7/16/12 | added in Id tag -// 1.33 | jdsloat | 6/26/12 | Added rtt_nom rank by rank value. -// 1.32 | jdsloat | 6/11/12 | Fixed Attributes: RTT_NOM, CL, DRAM_WR within the MRS load. -// 1.31 | bellows | 5/24/12 | Removed GP Bit -// 1.30 | bellows | 5/03/12 | MODEQ reg writes (HW191966). Has GP Bit for backwards compatibility -// 1.29 | bellows | 5/03/12 | Workaround removed for (HW199042). Use new hardware or workaround.initfile after phyreset -// 1.28 | bellows | 4/11/12 | fixed missing fapi:: for targets and return codes -// 1.27 | bellows | 4/11/12 | Workaround for fixing up phy config reset (HW199042) -// 1.26 | jdsloat | 3/20/12 | MRS bank fixe to remove reverse in ccs_inst_arry0 -// 1.25 | jdsloat | 3/09/12 | RCD address fix. Cleaned up the RCD section. -// 1.24 | jdsloat | 3/08/12 | Added CDIMM to RCD Check, MRS cycles through only configured ranks -// 1.23 | jdsloat | 3/05/12 | Fixed dram_al enum typo -// 1.22 | jdsloat | 2/27/12 | Fixed hostboot parenthesis error -// 1.21 | jdsloat | 2/27/12 | Cycle through Ports local of MRS/RCD, CL shift fix, Initialization of address/CS, neg end bit bug fix -// 1.20 | jdsloat | 2/23/12 | Fixed CL typo in MRS load -// 1.19 | jdsloat | 2/23/12 | MRS per rank, Interpret MRS ENUM correctly, CSN initialized to 0xFF -// 1.18 | jdsloat | 2/16/12 | Initialize rc_num, add num_ranks ==1 to MRS, Fix BA position in MRS -// 1.17 | jdsloat | 2/14/12 | MBA target translation, if statement clarification, style fixes -// 1.16 | jdsloat | 2/08/12 | Target to Target&, Described target with comment -// 1.15 | jdsloat | 2/02/12 | Fixed attributes array sizes, added debug messagesTarget to Target&, Described target -// 1.14 | jdsloat | 1/19/12 | Tabs to 4 spaces - properly -// 1.13 | jdsloat | 1/16/12 | Tabs to 4 spaces -// 1.12 | jdsloat | 1/13/12 | Curly Brackets, capitalization, "mss_" prefix, argument prefixes, no include C's, RC checks -// 1.11 | jdsloat | 1/5/12 | Changed Attribute grab, cleaned up includes section, Got rid of Globals -// 1.10 | jdsloat | 12/08/11| Changed MRS load RAS, CAS, WEN -// 1.9 | jdsloat | 12/07/11| CSN for 2 rank dimms 0x3 to 0xC -// 1.8 | jdsloat | 11/08/11| Cycling through Ports - fix -// 1.7 | jdsloat | 10/31/11| CCS Update - goto_inst now assumed to be +1, CCS_fail fix, CCS_status fix -// 1.6 | jdsloat | 10/18/11| RCD execution fix, debug messages -// 1.5 | jdsloat | 10/13/11| MRS fix, CCS count fix, get attribute fix, ecmdbuffer lengths within name -// 1.4 | jdsloat | 10/11/11| Fix CS Lines, dataBuffer.insert functions, ASSERT_RESETN_DRIVE_MEM_CLKS fix, attribute names -// 1.3 | jdsloat | 10/05/11| Convert integers to ecmdDataBufferBase in CCS_INST_1, CCS_INST_2, CCS_MODE -// 1.2 | jdsloat |04-OCT-11| Changing cen_funcs.C, cen_funcs.H to mss_funcs.C, mss_funcs.H -// 1.1 | jdsloat |04-OCT-11| First drop -//---------|----------|---------|----------------------------------------------- -// 1.6 | jdsloat |29-Sep-11|Functional Changes: port flow, CCS changes, only configed CS, etc. Compiles. -// 1.5 | jdsloat |22-Sep-11|Converted to FAPI, functional changes to match documentation -// 1.3 | jdsloat |14-Jul-11|Change GP4 register address from 1013 to 0x1013 -// 1.2 | jdsloat |22-Apr-11|Moved CCS operations to Cen_funcs.C, draminit_training to cen_draminit_training.C -// 1.1 | jdsloat |31-Mar-11|First drop for centaur - -//---------------------------------------------------------------------- -// FAPI function Includes -//---------------------------------------------------------------------- - -#include <fapi.H> - -//---------------------------------------------------------------------- -// Centaur function Includes -//---------------------------------------------------------------------- -#include <mss_funcs.H> -#include "cen_scom_addresses.H" -#include <mss_unmask_errors.H> -#include <mss_lrdimm_funcs.H> -#include <mss_ddr4_funcs.H> - -#ifdef FAPI_LRDIMM -#include <mss_lrdimm_ddr4_funcs.H> -#endif - -#ifndef FAPI_LRDIMM -using namespace fapi; -fapi::ReturnCode mss_lrdimm_rcd_load(Target& i_target, uint32_t port_number, uint32_t& ccs_inst_cnt) -{ - ReturnCode rc; - - FAPI_ERR("Invalid exec of mss_lrdimm_rcd_load on %s!", i_target.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); - return rc; - -} -ReturnCode mss_lrdimm_mrs_load(Target& i_target, uint32_t i_port_number, uint32_t dimm_number, uint32_t& io_ccs_inst_cnt) -{ - ReturnCode rc; - - FAPI_ERR("Invalid exec of mss_lrdimm_mrs_load function on %s!", i_target.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); - return rc; - -} -fapi::ReturnCode mss_lrdimm_ddr4_db_load(Target& i_target, uint32_t i_port_number, uint32_t& io_ccs_inst_cnt) -{ - ReturnCode rc; - - FAPI_ERR("Invalid exec of lrdimm_ddr4_db_load %s!", i_target.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); - return rc; - -} -#endif - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -//---------------------------------------------------------------------- -// Constants -//---------------------------------------------------------------------- -const uint8_t MAX_NUM_DIMMS = 2; -const uint8_t MAX_NUM_PORTS = 2; -const uint8_t MAX_NUM_RANK_PAIR = 4; -const uint8_t MAX_NUM_LR_RANKS = 8; -const uint8_t MRS0_BA = 0; -const uint8_t MRS1_BA = 1; -const uint8_t MRS2_BA = 2; -const uint8_t MRS3_BA = 3; -const uint8_t MRS4_BA = 4; -const uint8_t MRS5_BA = 5; -const uint8_t MRS6_BA = 6; -const uint8_t INVALID = 255; - - -extern "C" { - -using namespace fapi; - -ReturnCode mss_rcd_load( Target& i_target, uint32_t i_port_number, uint32_t& io_ccs_inst_cnt); -ReturnCode mss_mrs_load( Target& i_target, uint32_t i_port_number, uint32_t& io_ccs_inst_cnt); -ReturnCode mss_assert_resetn_drive_mem_clks( Target& i_target); -ReturnCode mss_deassert_force_mclk_low( Target& i_target); -ReturnCode mss_assert_resetn ( Target& i_target, uint8_t value); -ReturnCode mss_draminit_cloned(Target& i_target); - -const uint64_t DELAY_100NS = 100; // general purpose 100 ns delay for HW mode (2000 sim cycles if simclk = 20ghz) -const uint64_t DELAY_1US = 1000; // general purpose 1 usec delay for HW mode (20000 sim cycles if simclk = 20ghz) -const uint64_t DELAY_100US = 100000; // general purpose 100 usec delay for HW mode (2000000 sim cycles if simclk = 20ghz) -const uint64_t DELAY_500US = 500000; // general purpose 500 usec delay for HW mode (10000000 sim cycles if simclk = 20ghz) -const uint64_t DELAY_2000SIMCYCLES = 2000; // general purpose 2000 sim cycle delay for sim mode (100 ns if simclk = 20Ghz) -const uint64_t DELAY_20000SIMCYCLES = 20000; // general purpose 20000 sim cycle delay for sim mode (1 usec if simclk = 20Ghz) -const uint64_t DELAY_2000000SIMCYCLES = 2000000; // general purpose 2000000 sim cycle delay for sim mode (100 usec if simclk = 20Ghz) -const uint64_t DELAY_10000000SIMCYCLES = 10000000; // general purpose 10000000 sim cycle delay for sim mode (500 usec if simclk = 20Ghz) - -ReturnCode mss_draminit(Target& i_target) -{ - // Target is centaur.mba - - ReturnCode rc; - - rc = mss_draminit_cloned(i_target); - - // If mss_unmask_draminit_errors gets it's own bad rc, - // it will commit the passed in rc (if non-zero), and return it's own bad rc. - // Else if mss_unmask_draminit_errors runs clean, - // it will just return the passed in rc. - rc = mss_unmask_draminit_errors(i_target, rc); - - return rc; -} - -ReturnCode mss_draminit_cloned(Target& i_target) -{ - // Target is centaur.mba - // - - ReturnCode rc; - ReturnCode rc_buff; - uint32_t rc_num = 0; - uint32_t port_number; - uint32_t ccs_inst_cnt = 0; - uint8_t dram_gen; - uint8_t dimm_type; - uint8_t rank_pair_group = 0; - uint8_t bit_position = 0; - ecmdDataBufferBase data_buffer_64(64); - ecmdDataBufferBase mrs0(16); - ecmdDataBufferBase mrs1(16); - ecmdDataBufferBase mrs2(16); - ecmdDataBufferBase mrs3(16); - ecmdDataBufferBase mrs4(16); - ecmdDataBufferBase mrs5(16); - ecmdDataBufferBase mrs6(16); - uint16_t MRS0 = 0; - uint16_t MRS1 = 0; - uint16_t MRS2 = 0; - uint16_t MRS3 = 0; - uint16_t MRS4 = 0; - uint16_t MRS5 = 0; - uint16_t MRS6 = 0; - uint8_t num_drops_per_port; - uint8_t primary_ranks_array[4][2]; //primary_ranks_array[group][port] - uint8_t secondary_ranks_array[4][2]; //secondary_ranks_array[group][port] - uint8_t tertiary_ranks_array[4][2]; //tertiary_ranks_array[group][port] - uint8_t quaternary_ranks_array[4][2]; //quaternary_ranks_array[group][port] - uint8_t is_sim = 0; - uint8_t pri_dimm = 0; - uint8_t pri_dimm_rank = 0; - uint8_t sec_dimm = 0; - uint8_t sec_dimm_rank = 0; - uint8_t ter_dimm = 0; - uint8_t ter_dimm_rank = 0; - uint8_t qua_dimm = 0; - uint8_t qua_dimm_rank = 0; - - - //populate primary_ranks_arrays_array - rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP0, &i_target, primary_ranks_array[0]); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP1, &i_target, primary_ranks_array[1]); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP2, &i_target, primary_ranks_array[2]); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP3, &i_target, primary_ranks_array[3]); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_SECONDARY_RANK_GROUP0, &i_target, secondary_ranks_array[0]); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_SECONDARY_RANK_GROUP1, &i_target, secondary_ranks_array[1]); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_SECONDARY_RANK_GROUP2, &i_target, secondary_ranks_array[2]); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_SECONDARY_RANK_GROUP3, &i_target, secondary_ranks_array[3]); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_TERTIARY_RANK_GROUP0, &i_target, tertiary_ranks_array[0]); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_TERTIARY_RANK_GROUP1, &i_target, tertiary_ranks_array[1]); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_TERTIARY_RANK_GROUP2, &i_target, tertiary_ranks_array[2]); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_TERTIARY_RANK_GROUP3, &i_target, tertiary_ranks_array[3]); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_QUATERNARY_RANK_GROUP0, &i_target, quaternary_ranks_array[0]); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_QUATERNARY_RANK_GROUP1, &i_target, quaternary_ranks_array[1]); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_QUATERNARY_RANK_GROUP2, &i_target, quaternary_ranks_array[2]); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_QUATERNARY_RANK_GROUP3, &i_target, quaternary_ranks_array[3]); - if(rc) return rc; - - - - rc = FAPI_ATTR_GET(ATTR_EFF_NUM_DROPS_PER_PORT, &i_target, num_drops_per_port); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_GEN, &i_target, dram_gen); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target, dimm_type); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_IS_SIMULATION, NULL, is_sim); - if(rc) return rc; - uint8_t address_mirror_map[2][2]; //address_mirror_map[port][dimm] - rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_ADDRESS_MIRRORING, &i_target, address_mirror_map); - if(rc) return rc; - - - // Check to see if any dimm needs address mirror mode. Set the approriate flag. - if ( ( address_mirror_map[0][0] || - address_mirror_map[0][1] || - address_mirror_map[1][0] || - address_mirror_map[1][1] ) - && (is_sim == 0) ) - { - - FAPI_INF( "Setting Address Mirroring in the PHY on %s ", i_target.toEcmdString()); - - //Set the Address and BA bits affected by mirroring - if (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR3) - { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P0_0x8000C0110301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.setBit(58); - rc_num = rc_num | data_buffer_64.setBit(59); - rc_num = rc_num | data_buffer_64.setBit(60); - rc_num = rc_num | data_buffer_64.setBit(62); - if (rc_num) - { - FAPI_ERR( "mss_draminit_cloned: Error setting up buffers for DPHY01_DDRPHY_PC_RANK_GROUP_P0"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P0_0x8000C0110301143F, data_buffer_64); - if(rc) return rc; - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P1_0x8001C0110301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.setBit(58); - rc_num = rc_num | data_buffer_64.setBit(59); - rc_num = rc_num | data_buffer_64.setBit(60); - rc_num = rc_num | data_buffer_64.setBit(62); - if (rc_num) - { - FAPI_ERR( "mss_draminit_cloned: Error setting up buffers for DPHY01_DDRPHY_PC_RANK_GROUP_P1"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P1_0x8001C0110301143F, data_buffer_64); - if(rc) return rc; - } - if (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4) - { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P0_0x8000C0110301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.setBit(58); - rc_num = rc_num | data_buffer_64.setBit(59); - rc_num = rc_num | data_buffer_64.setBit(60); - rc_num = rc_num | data_buffer_64.setBit(61); - rc_num = rc_num | data_buffer_64.setBit(62); - rc_num = rc_num | data_buffer_64.setBit(63); - if (rc_num) - { - FAPI_ERR( "mss_draminit_cloned: Error setting up buffers for DPHY01_DDRPHY_PC_RANK_GROUP_P0"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P0_0x8000C0110301143F, data_buffer_64); - if(rc) return rc; - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P1_0x8001C0110301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.setBit(58); - rc_num = rc_num | data_buffer_64.setBit(59); - rc_num = rc_num | data_buffer_64.setBit(60); - rc_num = rc_num | data_buffer_64.setBit(61); - rc_num = rc_num | data_buffer_64.setBit(62); - rc_num = rc_num | data_buffer_64.setBit(63); - if (rc_num) - { - FAPI_ERR( "mss_draminit_cloned: Error setting up buffers for DPHY01_DDRPHY_PC_RANK_GROUP_P1"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P1_0x8001C0110301143F, data_buffer_64); - if(rc) return rc; - } - - for ( port_number = 0; port_number < MAX_NUM_PORTS; port_number++) - { - for ( rank_pair_group = 0; rank_pair_group < MAX_NUM_RANK_PAIR; rank_pair_group++) - { - - // dimm 0, dimm_rank 0-3 = ranks 0-3; dimm 1, dimm_rank 0-3 = ranks 4-7 - pri_dimm = (primary_ranks_array[rank_pair_group][port_number]) / 4; - pri_dimm_rank = primary_ranks_array[rank_pair_group][port_number] - 4*pri_dimm; - sec_dimm = (secondary_ranks_array[rank_pair_group][port_number]) / 4; - sec_dimm_rank = secondary_ranks_array[rank_pair_group][port_number] - 4*sec_dimm; - ter_dimm = (tertiary_ranks_array[rank_pair_group][port_number]) / 4; - ter_dimm_rank = tertiary_ranks_array[rank_pair_group][port_number] - 4*ter_dimm; - qua_dimm = (quaternary_ranks_array[rank_pair_group][port_number]) / 4; - qua_dimm_rank = quaternary_ranks_array[rank_pair_group][port_number] - 4*qua_dimm; - // Set the rank pairs that will be affected. - if ( port_number == 0 ) - { - if ( ( ( address_mirror_map[port_number][pri_dimm] & (0x08 >> pri_dimm_rank) ) ) && (primary_ranks_array[rank_pair_group][port_number] != 0xff ) ) - { - FAPI_INF( "Address Mirroring on %s PORT%d RANKPAIR%d RANK%d", i_target.toEcmdString(), port_number, rank_pair_group, primary_ranks_array[rank_pair_group][port_number]); - bit_position = 2 * rank_pair_group + 48; - FAPI_INF( "Setting bit %d", bit_position); - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P0_0x8000C0110301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.setBit(bit_position); - if (rc_num) - { - FAPI_ERR( "mss_draminit_cloned: Error setting up buffers for DPHY01_DDRPHY_PC_RANK_GROUP_P0"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P0_0x8000C0110301143F, data_buffer_64); - if(rc) return rc; - } - if ( ( ( address_mirror_map[port_number][sec_dimm] & (0x08 >> sec_dimm_rank) ) ) && (secondary_ranks_array[rank_pair_group][port_number] != 0xff ) ) - { - FAPI_INF( "Address Mirroring on %s PORT%d RANKPAIR%d RANK%d", i_target.toEcmdString(), port_number, rank_pair_group, primary_ranks_array[rank_pair_group][port_number]); - bit_position = 2 * rank_pair_group + 49; - FAPI_INF( "Setting bit %d", bit_position); - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P0_0x8000C0110301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.setBit(bit_position); - if (rc_num) - { - FAPI_ERR( "mss_draminit_cloned: Error setting up buffers for DPHY01_DDRPHY_PC_RANK_GROUP_P0"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P0_0x8000C0110301143F, data_buffer_64); - if(rc) return rc; - } - if ( ( ( address_mirror_map[port_number][ter_dimm] & (0x08 >> ter_dimm_rank) ) ) && (tertiary_ranks_array[rank_pair_group][port_number] != 0xff ) ) - { - FAPI_INF( "Address Mirroring on %s PORT%d RANKPAIR%d RANK%d", i_target.toEcmdString(), port_number, rank_pair_group, primary_ranks_array[rank_pair_group][port_number]); - bit_position = 2 * rank_pair_group + 48; - FAPI_INF( "Setting bit %d", bit_position); - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_EXT_P0_0x8000C0350301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.setBit(bit_position); - if (rc_num) - { - FAPI_ERR( "mss_draminit_cloned: Error setting up buffers for DPHY01_DDRPHY_PC_RANK_GROUP_EXT_P0"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_EXT_P0_0x8000C0350301143F, data_buffer_64); - if(rc) return rc; - } - if ( ( ( address_mirror_map[port_number][qua_dimm] & (0x08 >> qua_dimm_rank) ) ) && (quaternary_ranks_array[rank_pair_group][port_number] != 0xff ) ) - { - FAPI_INF( "Address Mirroring on %s PORT%d RANKPAIR%d RANK%d", i_target.toEcmdString(), port_number, rank_pair_group, primary_ranks_array[rank_pair_group][port_number]); - bit_position = 2 * rank_pair_group + 49; - FAPI_INF( "Setting bit %d", bit_position); - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_EXT_P0_0x8000C0350301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.setBit(bit_position); - if (rc_num) - { - FAPI_ERR( "mss_draminit_cloned: Error setting up buffers for DPHY01_DDRPHY_PC_RANK_GROUP_EXT_P0"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_EXT_P0_0x8000C0350301143F, data_buffer_64); - if(rc) return rc; - } - } - if ( port_number == 1 ) - { - if ( ( ( address_mirror_map[port_number][pri_dimm] & (0x08 >> pri_dimm_rank) ) ) && (primary_ranks_array[rank_pair_group][port_number] != 0xff ) ) - { - FAPI_INF( "Address Mirroring on %s PORT%d RANKPAIR%d RANK%d", i_target.toEcmdString(), port_number, rank_pair_group, primary_ranks_array[rank_pair_group][port_number]); - bit_position = 2 * rank_pair_group + 48; - FAPI_INF( "Setting bit %d", bit_position); - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P1_0x8001C0110301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.setBit(bit_position); - if (rc_num) - { - FAPI_ERR( "mss_draminit_cloned: Error setting up buffers for DPHY01_DDRPHY_PC_RANK_GROUP_P1"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P1_0x8001C0110301143F, data_buffer_64); - if(rc) return rc; - } - if ( ( ( address_mirror_map[port_number][sec_dimm] & (0x08 >> sec_dimm_rank) ) ) && (secondary_ranks_array[rank_pair_group][port_number] != 0xff ) ) - { - FAPI_INF( "Address Mirroring on %s PORT%d RANKPAIR%d RANK%d", i_target.toEcmdString(), port_number, rank_pair_group, primary_ranks_array[rank_pair_group][port_number]); - bit_position = 2 * rank_pair_group + 49; - FAPI_INF( "Setting bit %d", bit_position); - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P1_0x8001C0110301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.setBit(bit_position); - if (rc_num) - { - FAPI_ERR( "mss_draminit_cloned: Error setting up buffers for DPHY01_DDRPHY_PC_RANK_GROUP_P1"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P1_0x8001C0110301143F, data_buffer_64); - if(rc) return rc; - } - if ( ( ( address_mirror_map[port_number][ter_dimm] & (0x08 >> ter_dimm_rank) ) ) && (tertiary_ranks_array[rank_pair_group][port_number] != 0xff ) ) - { - FAPI_INF( "Address Mirroring on %s PORT%d RANKPAIR%d RANK%d", i_target.toEcmdString(), port_number, rank_pair_group, primary_ranks_array[rank_pair_group][port_number]); - bit_position = 2 * rank_pair_group + 48; - FAPI_INF( "Setting bit %d", bit_position); - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_EXT_P1_0x8001C0350301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.setBit(bit_position); - if (rc_num) - { - FAPI_ERR( "mss_draminit_cloned: Error setting up buffers for DPHY01_DDRPHY_PC_RANK_GROUP_EXT_P1"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_EXT_P1_0x8001C0350301143F, data_buffer_64); - if(rc) return rc; - } - if ( ( ( address_mirror_map[port_number][qua_dimm] & (0x08 >> qua_dimm_rank) ) ) && (quaternary_ranks_array[rank_pair_group][port_number] != 0xff ) ) - { - FAPI_INF( "Address Mirroring on PORT%d RANKPAIR%d RANK%d", port_number, rank_pair_group, primary_ranks_array[rank_pair_group][port_number]); - bit_position = 2 * rank_pair_group + 49; - FAPI_INF( "Setting bit %d", bit_position); - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_EXT_P1_0x8001C0350301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.setBit(bit_position); - if (rc_num) - { - FAPI_ERR( "mss_draminit_cloned: Error setting up buffers for DPHY01_DDRPHY_PC_RANK_GROUP_EXT_P1"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_EXT_P1_0x8001C0350301143F, data_buffer_64); - if(rc) return rc; - } - } - - } - } - } - - //Commented because Master Attention Reg Check not written yet. - //Master Attntion Reg Check... Need to add appropriate call below. - //MASTER_ATTENTION_REG_CHECK(); - - // Step one: Deassert Force_mclk_low signal - // this action needs to be done in ddr_phy_reset so that the plls can actually lock - - // Step two: Assert Resetn signal, Begin driving mem clks - rc = mss_assert_resetn_drive_mem_clks(i_target); - if(rc) - { - FAPI_ERR(" assert_resetn_drive_mem_clks Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator()); - return rc; - } - - rc = mss_assert_resetn(i_target, 0 ); // assert a reset - if(rc) - { - FAPI_ERR(" assert_resetn Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator()); - return rc; - } - - rc = fapiDelay(DELAY_100US, DELAY_2000SIMCYCLES); // wait 2000 simcycles (in sim mode) OR 100 uS (in hw mode) - if(rc) return rc; - - rc = mss_assert_resetn(i_target, 1 ); // de-assert a reset - if(rc) - { - FAPI_ERR(" assert_resetn Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator()); - return rc; - } - // Cycle through Ports... - // Ports 0-1 - for ( port_number = 0; port_number < MAX_NUM_PORTS; port_number++) - { - if (!((dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_UDIMM)||(dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_CDIMM))) - { - // Step three: Load RCD Control Words - if (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4) - { - rc = mss_rcd_load_ddr4(i_target, port_number, ccs_inst_cnt); - if(rc) - { - FAPI_ERR(" rcd_load Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator()); - return rc; - } - if ( dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM ) - { - // Set Data Buffer Function words - rc = mss_lrdimm_ddr4_db_load(i_target, port_number, ccs_inst_cnt); - if(rc) - { - FAPI_ERR(" LRDIMM rcd_load Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator()); - return rc; - } - } - - } - else - { - rc = mss_rcd_load(i_target, port_number, ccs_inst_cnt); - if(rc) - { - FAPI_ERR(" rcd_load Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator()); - return rc; - } - - if ( dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM ) - { - // Set Function 1-13 rcd words - rc = mss_lrdimm_rcd_load(i_target, port_number, ccs_inst_cnt); - if(rc) - { - FAPI_ERR(" LRDIMM rcd_load Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator()); - return rc; - } - } - } - } - } - - rc = fapiDelay(DELAY_500US, DELAY_10000000SIMCYCLES); // wait 10000 simcycles (in sim mode) OR 500 uS (in hw mode) - - if(rc) - { - FAPI_ERR(" Delay Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator()); - return rc; - } - - - - - - // Cycle through Ports... - // Ports 0-1 - for ( port_number = 0; port_number < MAX_NUM_PORTS; port_number++) - { - - // Step four: Load MRS Setting - if (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR3) - { - rc = mss_mrs_load(i_target, port_number, ccs_inst_cnt); - if(rc) - { - FAPI_ERR(" mrs_load Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator()); - return rc; - } - } - else - { - rc = mss_mrs_load_ddr4(i_target, port_number, ccs_inst_cnt); - if(rc) - { - FAPI_ERR(" mrs_load_ddr4 Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator()); - return rc; - } - } - - } - - // Execute the contents of CCS array - if (ccs_inst_cnt > 0) - { - // Set the End bit on the last CCS Instruction - rc = mss_ccs_set_end_bit( i_target, ccs_inst_cnt-1); - if(rc) - { - FAPI_ERR("CCS_SET_END_BIT FAILED rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator()); - return rc; - } - - rc = mss_execute_ccs_inst_array(i_target, 10, 10); - if(rc) - { - FAPI_ERR(" EXECUTE_CCS_INST_ARRAY FAILED rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator()); - return rc; - } - - ccs_inst_cnt = 0; - } - else - { - FAPI_INF("No Memory configured."); - } - - // Cycle through Ports... - // Ports 0-1 - for ( port_number = 0; port_number < MAX_NUM_PORTS; port_number++) - { - - for ( rank_pair_group = 0; rank_pair_group < MAX_NUM_RANK_PAIR; rank_pair_group++) - { - //Check if rank group exists - if((primary_ranks_array[rank_pair_group][0] != INVALID) || (primary_ranks_array[rank_pair_group][1] != INVALID)) - { - - if (port_number == 0) - { - // Get contents of MRS Shadow Regs and Print it to output - if (rank_pair_group == 0) - { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_PRI_RP0_P0_0x8000C01C0301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs0.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs0.extractPreserve(&MRS0, 0, 16, 0); - if (rc_num) - { - FAPI_ERR( "mss_draminit: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 0 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS0 ); - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP0_P0_0x8000C01D0301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs1.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs1.extractPreserve(&MRS1, 0, 16, 0); - if (rc_num) - { - FAPI_ERR( "mss_draminit: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 1 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS1); - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP0_P0_0x8000C01E0301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs2.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs2.extractPreserve(&MRS2, 0, 16, 0); - if (rc_num) - { - FAPI_ERR( "mss_draminit: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 2 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS2); - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR3_PRI_RP0_P0_0x8000C01F0301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs3.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0); - if (rc_num) - { - FAPI_ERR( "mss_draminit: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 3 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS3); - - if (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4) - { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_SEC_RP0_P0_0x8000C0200301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs4.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs4.extractPreserve(&MRS4, 0, 16, 0); - if (rc_num) - { - FAPI_ERR( "mss_draminit: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 4 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS4); - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_SEC_RP0_P0_0x8000C0210301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs5.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs5.extractPreserve(&MRS5, 0, 16, 0); - if (rc_num) - { - FAPI_ERR( "mss_draminit: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 5 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS5); - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_SEC_RP0_P0_0x8000C0220301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs6.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs6.extractPreserve(&MRS6, 0, 16, 0); - if (rc_num) - { - FAPI_ERR( "mss_draminit: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 6 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS6); - } - - } - else if (rank_pair_group == 1) - { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_PRI_RP1_P0_0x8000C11C0301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs0.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs0.extractPreserve(&MRS0, 0, 16, 0); - if (rc_num) - { - FAPI_ERR( "mss_draminit: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 0 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS0); - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP1_P0_0x8000C11D0301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs1.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs1.extractPreserve(&MRS1, 0, 16, 0); - if (rc_num) - { - FAPI_ERR( "mss_draminit: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 1 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS1); - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP1_P0_0x8000C11E0301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs2.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs2.extractPreserve(&MRS2, 0, 16, 0); - if (rc_num) - { - FAPI_ERR( "mss_draminit: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 2 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS2); - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR3_PRI_RP1_P0_0x8000C11F0301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs3.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0); - if (rc_num) - { - FAPI_ERR( "mss_draminit: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 3 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS3); - - if (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4) - { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_SEC_RP1_P0_0x8000C1200301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs4.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs4.extractPreserve(&MRS4, 0, 16, 0); - if (rc_num) - { - FAPI_ERR( "mss_draminit: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 4 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS4); - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_SEC_RP1_P0_0x8000C1210301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs5.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs5.extractPreserve(&MRS5, 0, 16, 0); - if (rc_num) - { - FAPI_ERR( "mss_draminit: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 5 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS5); - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_SEC_RP1_P0_0x8000C1220301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs6.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs6.extractPreserve(&MRS6, 0, 16, 0); - if (rc_num) - { - FAPI_ERR( "mss_draminit: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 6 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS6); - } - - } - else if (rank_pair_group == 2) - { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_PRI_RP2_P0_0x8000C21C0301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs0.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs0.extractPreserve(&MRS0, 0, 16, 0); - if (rc_num) - { - FAPI_ERR( "mss_draminit: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 0 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS0); - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP2_P0_0x8000C21D0301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs1.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs1.extractPreserve(&MRS1, 0, 16, 0); - if (rc_num) - { - FAPI_ERR( "mss_draminit: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 1 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS1); - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP2_P0_0x8000C21E0301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs2.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs2.extractPreserve(&MRS2, 0, 16, 0); - if (rc_num) - { - FAPI_ERR( "mss_draminit: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 2 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS2); - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR3_PRI_RP2_P0_0x8000C21F0301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs3.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0); - if (rc_num) - { - FAPI_ERR( "mss_draminit: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 3 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS3); - - if (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4) - { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_SEC_RP2_P0_0x8000C2200301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs4.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs4.extractPreserve(&MRS4, 0, 16, 0); - if (rc_num) - { - FAPI_ERR( "mss_draminit: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 4 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS4); - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_SEC_RP2_P0_0x8000C2210301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs5.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs5.extractPreserve(&MRS5, 0, 16, 0); - if (rc_num) - { - FAPI_ERR( "mss_draminit: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 5 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS5); - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_SEC_RP2_P0_0x8000C2220301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs6.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs6.extractPreserve(&MRS6, 0, 16, 0); - if (rc_num) - { - FAPI_ERR( "mss_draminit: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 6 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS6); - } - - } - else if (rank_pair_group == 3) - { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_PRI_RP3_P0_0x8000C31C0301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs0.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs0.extractPreserve(&MRS0, 0, 16, 0); - if (rc_num) - { - FAPI_ERR( "mss_draminit: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 0 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS0); - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP3_P0_0x8000C31D0301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs1.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs1.extractPreserve(&MRS1, 0, 16, 0); - if (rc_num) - { - FAPI_ERR( "mss_draminit: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 1 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS1); - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP3_P0_0x8000C31E0301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs2.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs2.extractPreserve(&MRS2, 0, 16, 0); - if (rc_num) - { - FAPI_ERR( "mss_draminit: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 2 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS2); - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR3_PRI_RP3_P0_0x8000C31F0301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs3.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0); - if (rc_num) - { - FAPI_ERR( "mss_draminit: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 3 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS3); - - if (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4) - { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_SEC_RP3_P0_0x8000C3200301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs4.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs4.extractPreserve(&MRS4, 0, 16, 0); - if (rc_num) - { - FAPI_ERR( "mss_draminit: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 4 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS4); - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_SEC_RP3_P0_0x8000C3210301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs5.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs5.extractPreserve(&MRS5, 0, 16, 0); - if (rc_num) - { - FAPI_ERR( "mss_draminit: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 5 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS5); - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_SEC_RP3_P0_0x8000C3220301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs6.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs6.extractPreserve(&MRS6, 0, 16, 0); - if (rc_num) - { - FAPI_ERR( "mss_draminit: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 6 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS6); - } - - } - } - else if (port_number == 1) - { - if (rank_pair_group == 0) - { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_PRI_RP0_P1_0x8001C01C0301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs0.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs0.extractPreserve(&MRS0, 0, 16, 0); - if (rc_num) - { - FAPI_ERR( "mss_draminit: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 0 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS0 ); - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP0_P1_0x8001C01D0301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs1.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs1.extractPreserve(&MRS1, 0, 16, 0); - if (rc_num) - { - FAPI_ERR( "mss_draminit: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 1 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS1); - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP0_P1_0x8001C01E0301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs2.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs2.extractPreserve(&MRS2, 0, 16, 0); - if (rc_num) - { - FAPI_ERR( "mss_draminit: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 2 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS2); - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR3_PRI_RP0_P1_0x8001C01F0301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs3.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0); - if (rc_num) - { - FAPI_ERR( "mss_draminit: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 3 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS3); - - if (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4) - { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_SEC_RP0_P1_0x8001C0200301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs4.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs4.extractPreserve(&MRS4, 0, 16, 0); - if (rc_num) - { - FAPI_ERR( "mss_draminit: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 4 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS4); - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_SEC_RP0_P1_0x8001C0210301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs5.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs5.extractPreserve(&MRS5, 0, 16, 0); - if (rc_num) - { - FAPI_ERR( "mss_draminit: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 5 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS5); - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_SEC_RP0_P1_0x8001C0220301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs6.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs6.extractPreserve(&MRS6, 0, 16, 0); - if (rc_num) - { - FAPI_ERR( "mss_draminit: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 6 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS6); - } - - } - else if (rank_pair_group == 1) - { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_PRI_RP1_P1_0x8001C11C0301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs0.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs0.extractPreserve(&MRS0, 0, 16, 0); - if (rc_num) - { - FAPI_ERR( "mss_draminit: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 0 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS0); - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP1_P1_0x8001C11D0301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs1.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs1.extractPreserve(&MRS1, 0, 16, 0); - if (rc_num) - { - FAPI_ERR( "mss_draminit: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 1 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS1); - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP1_P1_0x8001C11E0301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs2.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs2.extractPreserve(&MRS2, 0, 16, 0); - if (rc_num) - { - FAPI_ERR( "mss_draminit: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 2 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS2); - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR3_PRI_RP1_P1_0x8001C11F0301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs3.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0); - if (rc_num) - { - FAPI_ERR( "mss_draminit: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 3 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS3); - - if (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4) - { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_SEC_RP1_P1_0x8001C1200301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs4.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs4.extractPreserve(&MRS4, 0, 16, 0); - if (rc_num) - { - FAPI_ERR( "mss_draminit: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 4 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS4); - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_SEC_RP1_P1_0x8001C1210301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs5.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs5.extractPreserve(&MRS5, 0, 16, 0); - if (rc_num) - { - FAPI_ERR( "mss_draminit: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 5 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS5); - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_SEC_RP1_P1_0x8001C1220301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs6.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs6.extractPreserve(&MRS6, 0, 16, 0); - if (rc_num) - { - FAPI_ERR( "mss_draminit: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 6 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS6); - - } - - } - else if (rank_pair_group == 2) - { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_PRI_RP2_P1_0x8001C21C0301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs0.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs0.extractPreserve(&MRS0, 0, 16, 0); - if (rc_num) - { - FAPI_ERR( "mss_draminit: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 0 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS0); - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP2_P1_0x8001C21D0301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs1.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs1.extractPreserve(&MRS1, 0, 16, 0); - if (rc_num) - { - FAPI_ERR( "mss_draminit: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 1 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS1); - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP2_P1_0x8001C21E0301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs2.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs2.extractPreserve(&MRS2, 0, 16, 0); - if (rc_num) - { - FAPI_ERR( "mss_draminit: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 2 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS2); - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR3_PRI_RP2_P1_0x8001C21F0301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs3.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0); - if (rc_num) - { - FAPI_ERR( "mss_draminit: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 3 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS3); - - if (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4) - { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_SEC_RP2_P1_0x8001C2200301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs4.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs4.extractPreserve(&MRS4, 0, 16, 0); - if (rc_num) - { - FAPI_ERR( "mss_draminit: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 4 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS4); - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_SEC_RP2_P1_0x8001C2210301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs5.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs5.extractPreserve(&MRS5, 0, 16, 0); - if (rc_num) - { - FAPI_ERR( "mss_draminit: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 5 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS5); - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_SEC_RP2_P1_0x8001C2220301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs6.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs6.extractPreserve(&MRS6, 0, 16, 0); - if (rc_num) - { - FAPI_ERR( "mss_draminit: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 6 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS6); - } - - } - else if (rank_pair_group == 3) - { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_PRI_RP3_P1_0x8001C31C0301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs0.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs0.extractPreserve(&MRS0, 0, 16, 0); - if (rc_num) - { - FAPI_ERR( "mss_draminit: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 0 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS0); - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP3_P1_0x8001C31D0301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs1.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs1.extractPreserve(&MRS1, 0, 16, 0); - if (rc_num) - { - FAPI_ERR( "mss_draminit: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 1 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS1); - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP3_P1_0x8001C31E0301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs2.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs2.extractPreserve(&MRS2, 0, 16, 0); - if (rc_num) - { - FAPI_ERR( "mss_draminit: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 2 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS2); - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR3_PRI_RP3_P1_0x8001C31F0301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs3.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0); - if (rc_num) - { - FAPI_ERR( "mss_draminit: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 3 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS3); - - if (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4) - { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_SEC_RP3_P1_0x8001C3200301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs4.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs4.extractPreserve(&MRS4, 0, 16, 0); - if (rc_num) - { - FAPI_ERR( "mss_draminit: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 4 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS4); - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_SEC_RP3_P1_0x8001C3210301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs5.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs5.extractPreserve(&MRS5, 0, 16, 0); - if (rc_num) - { - FAPI_ERR( "mss_draminit: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 5 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS5); - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_SEC_RP3_P1_0x8001C3220301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs6.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs6.extractPreserve(&MRS6, 0, 16, 0); - if (rc_num) - { - FAPI_ERR( "mss_draminit: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 6 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS6); - } - - } - - } - } - } - } - - if ( (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4) && (dimm_type == fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM || dimm_type == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) ) - { - FAPI_INF("Performing B-side address inversion MPR write pattern"); - - rc = mss_ddr4_invert_mpr_write(i_target); - if (rc) return rc; - } - - - - // TODO: - // This is Commented out because RCD Parity Check has not been written yet. - // Check RCD Parity - //rc = RCD_PARITY_CHECK(i_target); - //if(rc){ - //FAPI_ERR(" RCD_PARITY_CHECK FAILED rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator()); - //return rc; - //} - - //Master Attntion Reg Check... Need to add appropriate call below. - //MASTER_ATTENTION_REG_CHECK(); - - return rc; -} - - - -ReturnCode mss_assert_resetn_drive_mem_clks( - Target& i_target - ) -{ - // mcbist_ddr_resetn = 1 -- to deassert DDR RESET# - //mcbist_ddr_dphy_nclk = 01, mcbist_ddr_dphy_pclk = 10 -- to drive the memory clks - - ReturnCode rc; - ReturnCode rc_buff; - uint32_t rc_num = 0; - ecmdDataBufferBase stop_on_err_1(1); - ecmdDataBufferBase ue_disable_1(1); - ecmdDataBufferBase data_sel_2(2); - ecmdDataBufferBase pclk_2(2); - rc_num = rc_num | pclk_2.insertFromRight((uint32_t) 2, 0, 2); - ecmdDataBufferBase nclk_2(2); - rc_num = rc_num | nclk_2.insertFromRight((uint32_t) 1, 0, 2); - ecmdDataBufferBase cal_time_cnt_16(16); - ecmdDataBufferBase resetn_1(1); - rc_num = rc_num | resetn_1.setBit(0); - ecmdDataBufferBase reset_recover_1(1); - ecmdDataBufferBase copy_spare_cke_1(1); - rc_num = rc_num | copy_spare_cke_1.setBit(0); // mdb : clk enable on for spare - - FAPI_INF( "+++++++++++++++++++++ ASSERTING RESETN, DRIVING MEM CLKS +++++++++++++++++++++"); - - if (rc_num) - { - FAPI_ERR( "mss_assert_resetn_drive_mem_clks: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - - // Setting CCS Mode - rc = mss_ccs_mode(i_target, - stop_on_err_1, - ue_disable_1, - data_sel_2, - pclk_2, - nclk_2, - cal_time_cnt_16, - resetn_1, - reset_recover_1, - copy_spare_cke_1); - - return rc; -} - -ReturnCode mss_rcd_load( - Target& i_target, - uint32_t i_port_number, - uint32_t& io_ccs_inst_cnt - ) { - - ReturnCode rc; - ReturnCode rc_buff; - uint32_t rc_num = 0; - uint32_t dimm_number; - uint32_t rcd_number; - - ecmdDataBufferBase rcd_cntl_wrd_4(8); - ecmdDataBufferBase rcd_cntl_wrd_64(64); - uint16_t num_ranks; - - ecmdDataBufferBase address_16(16); - ecmdDataBufferBase bank_3(3); - ecmdDataBufferBase activate_1(1); - ecmdDataBufferBase rasn_1(1); - rc_num = rc_num | rasn_1.setBit(0); - ecmdDataBufferBase casn_1(1); - rc_num = rc_num | casn_1.setBit(0); - ecmdDataBufferBase wen_1(1); - rc_num = rc_num | wen_1.setBit(0); - ecmdDataBufferBase cke_4(4); - rc_num = rc_num | cke_4.setBit(0,4); - ecmdDataBufferBase csn_8(8); - rc_num = rc_num | csn_8.setBit(0,8); - ecmdDataBufferBase odt_4(4); - rc_num = rc_num | odt_4.clearBit(0,4); - ecmdDataBufferBase ddr_cal_type_4(4); - - ecmdDataBufferBase num_idles_16(16); - ecmdDataBufferBase num_repeat_16(16); - ecmdDataBufferBase data_20(20); - ecmdDataBufferBase read_compare_1(1); - ecmdDataBufferBase rank_cal_4(4); - ecmdDataBufferBase ddr_cal_enable_1(1); - ecmdDataBufferBase ccs_end_1(1); - - uint8_t num_ranks_array[2][2]; //[port][dimm] - uint64_t rcd_array[2][2]; //[port][dimm] - uint8_t dimm_type; - - rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target, dimm_type); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target, num_ranks_array); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_RCD_CNTL_WORD_0_15, &i_target, rcd_array); - if(rc) return rc; - - // Raise CKE high with NOPS, waiting min Reset CKE exit time (tXPR) - 400 cycles - rc_num = rc_num | address_16.clearBit(0, 16); - rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 400, 0, 16); - rc = mss_ccs_inst_arry_0( i_target, - io_ccs_inst_cnt, - address_16, - bank_3, - activate_1, - rasn_1, - casn_1, - wen_1, - cke_4, - csn_8, - odt_4, - ddr_cal_type_4, - i_port_number); - if(rc) return rc; - rc = mss_ccs_inst_arry_1( i_target, - io_ccs_inst_cnt, - num_idles_16, - num_repeat_16, - data_20, - read_compare_1, - rank_cal_4, - ddr_cal_enable_1, - ccs_end_1); - if(rc) return rc; - io_ccs_inst_cnt ++; - - FAPI_INF( "+++++++++++++++++++++ LOADING RCD CONTROL WORDS FOR %s PORT %d +++++++++++++++++++++", i_target.toEcmdString(), i_port_number); - - for ( dimm_number = 0; dimm_number < MAX_NUM_DIMMS; dimm_number++) - { - num_ranks = num_ranks_array[i_port_number][dimm_number]; - - if (num_ranks == 0) - { - FAPI_INF( "PORT%d DIMM%d not configured. Num_ranks: %d", i_port_number, dimm_number, num_ranks); - } - else - { - FAPI_INF( "RCD SETTINGS FOR %s PORT%d DIMM%d ", i_target.toEcmdString(), i_port_number, dimm_number); - FAPI_INF( "RCD Control Word: 0x%016llX", rcd_array[i_port_number][dimm_number]); - - if (rc_num) - { - FAPI_ERR( "mss_rcd_load: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - - // ALL active CS lines at a time. - rc_num = rc_num | csn_8.setBit(0,8); - if (dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) - { - // for dimm0 use CS0,1 (active low); for dimm1 use CS4,5 (active low) - rc_num = rc_num | csn_8.clearBit((4*dimm_number), 2 ); - } - else if ((num_ranks == 1) || (num_ranks == 2)) - { - rc_num = rc_num | csn_8.clearBit(0+4*dimm_number); - rc_num = rc_num | csn_8.clearBit(1+4*dimm_number); - } - else if (num_ranks == 4) - { - rc_num = rc_num | csn_8.clearBit(0+4*dimm_number); - rc_num = rc_num | csn_8.clearBit(1+4*dimm_number); - rc_num = rc_num | csn_8.clearBit(2+4*dimm_number); - rc_num = rc_num | csn_8.clearBit(3+4*dimm_number); - } - - // Propogate through the 16, 4-bit control words - for ( rcd_number = 0; rcd_number<= 15; rcd_number++) - { - rc_num = rc_num | bank_3.clearBit(0, 3); - rc_num = rc_num | address_16.clearBit(0, 16); - - rc_num = rc_num | rcd_cntl_wrd_64.setDoubleWord(0, rcd_array[i_port_number][dimm_number]); - rc_num = rc_num | rcd_cntl_wrd_64.extract(rcd_cntl_wrd_4, 4*rcd_number, 4); - - //control word number code bits A0, A1, A2, BA2 - rc_num = rc_num | address_16.insert(rcd_number, 2, 1, 29); - rc_num = rc_num | address_16.insert(rcd_number, 1, 1, 30); - rc_num = rc_num | address_16.insert(rcd_number, 0, 1, 31); - rc_num = rc_num | bank_3.insert(rcd_number, 2, 1, 28); - - //control word values RCD0 = A3, RCD1 = A4, RCD2 = BA0, RCD3 = BA1 - rc_num = rc_num | address_16.insert(rcd_cntl_wrd_4, 3, 1, 3); - rc_num = rc_num | address_16.insert(rcd_cntl_wrd_4, 4, 1, 2); - rc_num = rc_num | bank_3.insert(rcd_cntl_wrd_4, 0, 1, 1); - rc_num = rc_num | bank_3.insert(rcd_cntl_wrd_4, 1, 1, 0); - - // Send out to the CCS array - if ( dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM && (rcd_number == 2 || rcd_number == 10) ) - { - rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 4000, 0 , 16 ); // wait tStab for clock timing rcd words - } - else - { - rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 12, 0, 16); - } - - - if (rc_num) - { - FAPI_ERR( "mss_rcd_load: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - - rc = mss_ccs_inst_arry_0( i_target, - io_ccs_inst_cnt, - address_16, - bank_3, - activate_1, - rasn_1, - casn_1, - wen_1, - cke_4, - csn_8, - odt_4, - ddr_cal_type_4, - i_port_number); - if(rc) return rc; - rc = mss_ccs_inst_arry_1( i_target, - io_ccs_inst_cnt, - num_idles_16, - num_repeat_16, - data_20, - read_compare_1, - rank_cal_4, - ddr_cal_enable_1, - ccs_end_1); - if(rc) return rc; - io_ccs_inst_cnt ++; - - } - } - } - return rc; -} - -ReturnCode mss_mrs_load( - Target& i_target, - uint32_t i_port_number, - uint32_t& io_ccs_inst_cnt - ) -{ - - uint32_t dimm_number; - uint32_t rank_number; - uint32_t mrs_number; - ReturnCode rc; - ReturnCode rc_buff; - uint32_t rc_num = 0; - - ecmdDataBufferBase data_buffer_64(64); - ecmdDataBufferBase address_16(16); - ecmdDataBufferBase bank_3(3); - ecmdDataBufferBase activate_1(1); - ecmdDataBufferBase rasn_1(1); - rc_num = rc_num | rasn_1.clearBit(0); - ecmdDataBufferBase casn_1(1); - rc_num = rc_num | casn_1.clearBit(0); - ecmdDataBufferBase wen_1(1); - rc_num = rc_num | wen_1.clearBit(0); - ecmdDataBufferBase cke_4(4); - rc_num = rc_num | cke_4.setBit(0,4); - ecmdDataBufferBase csn_8(8); - rc_num = rc_num | csn_8.setBit(0,8); - ecmdDataBufferBase odt_4(4); - rc_num = rc_num | odt_4.clearBit(0,4); - ecmdDataBufferBase ddr_cal_type_4(4); - - ecmdDataBufferBase csn_setup_8(8); - rc_num = rc_num | csn_setup_8.setBit(0,8); - - ecmdDataBufferBase num_idles_16(16); - ecmdDataBufferBase num_idles_setup_16(16); - rc_num = rc_num | num_idles_setup_16.insertFromRight((uint32_t) 400, 0, 16); - - ecmdDataBufferBase num_repeat_16(16); - ecmdDataBufferBase data_20(20); - ecmdDataBufferBase read_compare_1(1); - ecmdDataBufferBase rank_cal_4(4); - ecmdDataBufferBase ddr_cal_enable_1(1); - ecmdDataBufferBase ccs_end_1(1); - - ecmdDataBufferBase mrs0(16); - ecmdDataBufferBase mrs1(16); - ecmdDataBufferBase mrs2(16); - ecmdDataBufferBase mrs3(16); - uint16_t MRS0 = 0; - uint16_t MRS1 = 0; - uint16_t MRS2 = 0; - uint16_t MRS3 = 0; - - uint16_t num_ranks = 0; - uint8_t lrdimm_rank_mult_mode = 0; - - - FAPI_INF( "+++++++++++++++++++++ LOADING MRS SETTINGS FOR %s PORT %d +++++++++++++++++++++", i_target.toEcmdString(), i_port_number); - - uint8_t num_ranks_array[2][2]; //[port][dimm] - rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target, num_ranks_array); - if(rc) return rc; - - uint8_t dimm_type; - rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target, dimm_type); - if(rc) return rc; - - uint8_t is_sim = 0; - rc = FAPI_ATTR_GET(ATTR_IS_SIMULATION, NULL, is_sim); - if(rc) return rc; - - uint8_t dram_2n_mode = 0; - rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_2N_MODE_ENABLED, &i_target, dram_2n_mode); - if(rc) return rc; - - uint8_t address_mirror_map[2][2]; //address_mirror_map[port][dimm] - rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_ADDRESS_MIRRORING, &i_target, address_mirror_map); - if(rc) return rc; - - - //Lines commented out in the following section are waiting for xml attribute adds - //MRS0 - uint8_t dram_bl; - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_BL, &i_target, dram_bl); - if(rc) return rc; - uint8_t read_bt; //Read Burst Type - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_RBT, &i_target, read_bt); - if(rc) return rc; - uint8_t dram_cl; - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_CL, &i_target, dram_cl); - if(rc) return rc; - uint8_t test_mode; //TEST MODE - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_TM, &i_target, test_mode); - if(rc) return rc; - uint8_t dll_reset; //DLL Reset - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_DLL_RESET, &i_target, dll_reset); - if(rc) return rc; - uint8_t dram_wr; - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WR, &i_target, dram_wr); - if(rc) return rc; - uint8_t dll_precharge; //DLL Control For Precharge - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_DLL_PPD, &i_target, dll_precharge); - if(rc) return rc; - - if (dram_bl == ENUM_ATTR_EFF_DRAM_BL_BL8) - { - dram_bl = 0x00; - } - else if (dram_bl == ENUM_ATTR_EFF_DRAM_BL_OTF) - { - dram_bl = 0x80; - } - else if (dram_bl == ENUM_ATTR_EFF_DRAM_BL_BC4) - { - dram_bl = 0x40; - } - - if (dram_wr == 16) - { - dram_wr = 0x00; - } - else if (dram_wr == 5) - { - dram_wr = 0x80; - } - else if (dram_wr == 6) - { - dram_wr = 0x40; - } - else if (dram_wr == 7) - { - dram_wr = 0xC0; - } - else if (dram_wr == 8) - { - dram_wr = 0x20; - } - else if (dram_wr == 10) - { - dram_wr = 0xA0; - } - else if (dram_wr == 12) - { - dram_wr = 0x60; - } - else if (dram_wr == 14) - { - dram_wr = 0xE0; - } - - - if (read_bt == ENUM_ATTR_EFF_DRAM_RBT_SEQUENTIAL) - { - read_bt = 0x00; - } - else if (read_bt == ENUM_ATTR_EFF_DRAM_RBT_INTERLEAVE) - { - read_bt = 0xFF; - } - - if ((dram_cl > 4)&&(dram_cl < 12)) - { - dram_cl = (dram_cl - 4) << 1; - } - else if ((dram_cl > 11)&&(dram_cl < 17)) - { - dram_cl = ((dram_cl - 12) << 1) + 1; - } - dram_cl = mss_reverse_8bits(dram_cl); - - if (test_mode == ENUM_ATTR_EFF_DRAM_TM_NORMAL) - { - test_mode = 0x00; - } - else if (test_mode == ENUM_ATTR_EFF_DRAM_TM_TEST) - { - test_mode = 0xFF; - } - - if (dll_reset == ENUM_ATTR_EFF_DRAM_DLL_RESET_YES) - { - dll_reset = 0xFF; - } - else if (dll_reset == ENUM_ATTR_EFF_DRAM_DLL_RESET_NO) - { - dll_reset = 0x00; - } - - if (dll_precharge == ENUM_ATTR_EFF_DRAM_DLL_PPD_SLOWEXIT) - { - dll_precharge = 0x00; - } - else if (dll_precharge == ENUM_ATTR_EFF_DRAM_DLL_PPD_FASTEXIT) - { - dll_precharge = 0xFF; - } - - //MRS1 - uint8_t dll_enable; //DLL Enable - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_DLL_ENABLE, &i_target, dll_enable); - if(rc) return rc; - uint8_t out_drv_imp_cntl[2][2]; - rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_RON, &i_target, out_drv_imp_cntl); - if(rc) return rc; - uint8_t dram_rtt_nom[2][2][4]; - rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_RTT_NOM, &i_target, dram_rtt_nom); - if(rc) return rc; - uint8_t dram_al; - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_AL, &i_target, dram_al); - if(rc) return rc; - uint8_t wr_lvl; //write leveling enable - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WR_LVL_ENABLE, &i_target, wr_lvl); - if(rc) return rc; - uint8_t tdqs_enable; //TDQS Enable - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_TDQS, &i_target, tdqs_enable); - if(rc) return rc; - uint8_t q_off; //Qoff - Output buffer Enable - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_OUTPUT_BUFFER, &i_target, q_off); - if(rc) return rc; - - if (dll_enable == ENUM_ATTR_EFF_DRAM_DLL_ENABLE_ENABLE) - { - dll_enable = 0x00; - } - else if (dll_enable == ENUM_ATTR_EFF_DRAM_DLL_ENABLE_DISABLE) - { - dll_enable = 0xFF; - } - - if (dram_al == ENUM_ATTR_EFF_DRAM_AL_DISABLE) - { - dram_al = 0x00; - } - else if (dram_al == ENUM_ATTR_EFF_DRAM_AL_CL_MINUS_1) - { - dram_al = 0x80; - } - else if (dram_al == ENUM_ATTR_EFF_DRAM_AL_CL_MINUS_2) - { - dram_al = 0x40; - } - - if (wr_lvl == ENUM_ATTR_EFF_DRAM_WR_LVL_ENABLE_DISABLE) - { - wr_lvl = 0x00; - } - else if (wr_lvl == ENUM_ATTR_EFF_DRAM_WR_LVL_ENABLE_ENABLE) - { - wr_lvl = 0xFF; - } - - if (tdqs_enable == ENUM_ATTR_EFF_DRAM_TDQS_DISABLE) - { - tdqs_enable = 0x00; - } - else if (tdqs_enable == ENUM_ATTR_EFF_DRAM_TDQS_ENABLE) - { - tdqs_enable = 0xFF; - } - - if (q_off == ENUM_ATTR_EFF_DRAM_OUTPUT_BUFFER_DISABLE) - { - q_off = 0xFF; - } - else if (q_off == ENUM_ATTR_EFF_DRAM_OUTPUT_BUFFER_ENABLE) - { - q_off = 0x00; - } - - //MRS2 - uint8_t pt_arr_sr; //Partial Array Self Refresh - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_PASR, &i_target, pt_arr_sr); - if(rc) return rc; - uint8_t cwl; // CAS Write Latency - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_CWL, &i_target, cwl); - if(rc) return rc; - uint8_t auto_sr; // Auto Self-Refresh - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_ASR, &i_target, auto_sr); - if(rc) return rc; - uint8_t sr_temp; // Self-Refresh Temp Range - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_SRT, &i_target, sr_temp); - if(rc) return rc; - uint8_t dram_rtt_wr[2][2][4]; - rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_RTT_WR, &i_target, dram_rtt_wr); - if(rc) return rc; - - if (pt_arr_sr == ENUM_ATTR_EFF_DRAM_PASR_FULL) - { - pt_arr_sr = 0x00; - } - else if (pt_arr_sr == ENUM_ATTR_EFF_DRAM_PASR_FIRST_HALF) - { - pt_arr_sr = 0x80; - } - else if (pt_arr_sr == ENUM_ATTR_EFF_DRAM_PASR_FIRST_QUARTER) - { - pt_arr_sr = 0x40; - } - else if (pt_arr_sr == ENUM_ATTR_EFF_DRAM_PASR_FIRST_EIGHTH) - { - pt_arr_sr = 0xC0; - } - else if (pt_arr_sr == ENUM_ATTR_EFF_DRAM_PASR_LAST_THREE_FOURTH) - { - pt_arr_sr = 0x20; - } - else if (pt_arr_sr == ENUM_ATTR_EFF_DRAM_PASR_LAST_HALF) - { - pt_arr_sr = 0xA0; - } - else if (pt_arr_sr == ENUM_ATTR_EFF_DRAM_PASR_LAST_QUARTER) - { - pt_arr_sr = 0x60; - } - else if (pt_arr_sr == ENUM_ATTR_EFF_DRAM_PASR_LAST_EIGHTH) - { - pt_arr_sr = 0xE0; - } - - cwl = mss_reverse_8bits(cwl - 5); - - if (auto_sr == ENUM_ATTR_EFF_DRAM_ASR_SRT) - { - auto_sr = 0x00; - } - else if (auto_sr == ENUM_ATTR_EFF_DRAM_ASR_ASR) - { - auto_sr = 0xFF; - } - - if (sr_temp == ENUM_ATTR_EFF_DRAM_SRT_NORMAL) - { - sr_temp = 0x00; - } - else if (sr_temp == ENUM_ATTR_EFF_DRAM_SRT_EXTEND) - { - sr_temp = 0xFF; - } - - //MRS3 - uint8_t mpr_loc; // MPR Location - rc = FAPI_ATTR_GET(ATTR_EFF_MPR_LOC, &i_target, mpr_loc); - if(rc) return rc; - uint8_t mpr_op; // MPR Operation Mode - rc = FAPI_ATTR_GET(ATTR_EFF_MPR_MODE, &i_target, mpr_op); - if(rc) return rc; - - mpr_loc = mss_reverse_8bits(mpr_loc); - - if (mpr_op == ENUM_ATTR_EFF_MPR_MODE_ENABLE) - { - mpr_op = 0xFF; - } - else if (mpr_op == ENUM_ATTR_EFF_MPR_MODE_DISABLE) - { - mpr_op = 0x00; - } - - // Raise CKE high with NOPS, waiting min Reset CKE exit time (tXPR) - 400 cycles - rc_num = rc_num | csn_8.setBit(0,8); - rc_num = rc_num | address_16.clearBit(0, 16); - rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 400, 0, 16); - rc = mss_ccs_inst_arry_0( i_target, - io_ccs_inst_cnt, - address_16, - bank_3, - activate_1, - rasn_1, - casn_1, - wen_1, - cke_4, - csn_8, - odt_4, - ddr_cal_type_4, - i_port_number); - if(rc) return rc; - rc = mss_ccs_inst_arry_1( i_target, - io_ccs_inst_cnt, - num_idles_16, - num_repeat_16, - data_20, - read_compare_1, - rank_cal_4, - ddr_cal_enable_1, - ccs_end_1); - if(rc) return rc; - io_ccs_inst_cnt ++; - - // Dimm 0-1 - for ( dimm_number = 0; dimm_number < MAX_NUM_DIMMS; dimm_number++) - { - num_ranks = num_ranks_array[i_port_number][dimm_number]; - - if (num_ranks == 0) - { - FAPI_INF( " %s PORT%d DIMM%d not configured. Num_ranks: %d ", i_target.toEcmdString(), i_port_number, dimm_number, num_ranks); - } - else - { - - if (dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) - { - rc = FAPI_ATTR_GET(ATTR_LRDIMM_RANK_MULT_MODE, &i_target, lrdimm_rank_mult_mode); - if(rc) return rc; - - if ( (lrdimm_rank_mult_mode == 4) && (num_ranks == 8) ) - { - num_ranks = 2; - } - } - - // Rank 0-3 - for ( rank_number = 0; rank_number < num_ranks; rank_number++) - { - FAPI_INF( "MRS SETTINGS FOR %s PORT%d DIMM%d RANK%d", i_target.toEcmdString(), i_port_number, dimm_number, rank_number); - - rc_num = rc_num | csn_8.setBit(0,8); - rc_num = rc_num | address_16.clearBit(0, 16); - - rc_num = rc_num | mrs0.insert((uint8_t) dram_bl, 0, 2, 0); - rc_num = rc_num | mrs0.insert((uint8_t) dram_cl, 2, 1, 0); - rc_num = rc_num | mrs0.insert((uint8_t) read_bt, 3, 1, 0); - rc_num = rc_num | mrs0.insert((uint8_t) dram_cl, 4, 3, 1); - rc_num = rc_num | mrs0.insert((uint8_t) test_mode, 7, 1); - rc_num = rc_num | mrs0.insert((uint8_t) dll_reset, 8, 1); - rc_num = rc_num | mrs0.insert((uint8_t) dram_wr, 9, 3); - rc_num = rc_num | mrs0.insert((uint8_t) dll_precharge, 12, 1); - rc_num = rc_num | mrs0.insert((uint8_t) 0x00, 13, 3); - - rc_num = rc_num | mrs0.extractPreserve(&MRS0, 0, 16, 0); - - if ( lrdimm_rank_mult_mode != 0 ) - { - dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0x00; - } - else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE) - { - dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0x00; - } - else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM20) - { - dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0x20; - } - else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30) - { - dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0xA0; - } - else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40) - { - dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0xC0; - } - else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM60) - { - dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0x80; - } - else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM120) - { - dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0x40; - } - else - { - //DECONFIG and FFDC INFO - const fapi::Target & TARGET_MBA_ERROR = i_target; - const uint8_t & IMP = dram_rtt_nom[i_port_number][dimm_number][rank_number]; - const uint32_t & PORT = i_port_number; - const uint32_t & DIMM = dimm_number; - const uint32_t & RANK = rank_number; - - FAPI_ERR( "mss_mrs_load: Error determining ATTR_VPD_DRAM_RTT_NOM value: %d from attribute", dram_rtt_nom[i_port_number][dimm_number][rank_number]); - FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_RTT_NOM_IMP_INPUT_ERROR); - return rc; - } - - if (out_drv_imp_cntl[i_port_number][dimm_number] == ENUM_ATTR_VPD_DRAM_RON_OHM40) - { - out_drv_imp_cntl[i_port_number][dimm_number] = 0x00; - } - else if (out_drv_imp_cntl[i_port_number][dimm_number] == ENUM_ATTR_VPD_DRAM_RON_OHM34) - { - out_drv_imp_cntl[i_port_number][dimm_number] = 0x80; - } - - rc_num = rc_num | mrs1.insert((uint8_t) dll_enable, 0, 1, 0); - rc_num = rc_num | mrs1.insert((uint8_t) out_drv_imp_cntl[i_port_number][dimm_number], 1, 1, 0); - rc_num = rc_num | mrs1.insert((uint8_t) dram_rtt_nom[i_port_number][dimm_number][rank_number], 2, 1, 0); - rc_num = rc_num | mrs1.insert((uint8_t) dram_al, 3, 2, 0); - rc_num = rc_num | mrs1.insert((uint8_t) out_drv_imp_cntl[i_port_number][dimm_number], 5, 1, 1); - rc_num = rc_num | mrs1.insert((uint8_t) dram_rtt_nom[i_port_number][dimm_number][rank_number], 6, 1, 1); - rc_num = rc_num | mrs1.insert((uint8_t) wr_lvl, 7, 1, 0); - rc_num = rc_num | mrs1.insert((uint8_t) 0x00, 8, 1); - rc_num = rc_num | mrs1.insert((uint8_t) dram_rtt_nom[i_port_number][dimm_number][rank_number], 9, 1, 2); - rc_num = rc_num | mrs1.insert((uint8_t) 0x00, 10, 1); - rc_num = rc_num | mrs1.insert((uint8_t) tdqs_enable, 11, 1, 0); - rc_num = rc_num | mrs1.insert((uint8_t) q_off, 12, 1, 0); - rc_num = rc_num | mrs1.insert((uint8_t) 0x00, 13, 3); - - rc_num = rc_num | mrs1.extractPreserve(&MRS1, 0, 16, 0); - - - if ( (lrdimm_rank_mult_mode != 0) && (rank_number > 1) ) - { - dram_rtt_wr[i_port_number][dimm_number][rank_number] = dram_rtt_wr[i_port_number][dimm_number][0]; - } - else if (dram_rtt_wr[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE) - { - dram_rtt_wr[i_port_number][dimm_number][rank_number] = 0x00; - } - else if (dram_rtt_wr[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60) - { - dram_rtt_wr[i_port_number][dimm_number][rank_number] = 0x80; - } - else if (dram_rtt_wr[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120) - { - dram_rtt_wr[i_port_number][dimm_number][rank_number] = 0x40; - } - else - { - - //DECONFIG and FFDC INFO - const fapi::Target & TARGET_MBA_ERROR = i_target; - const uint8_t & IMP = dram_rtt_nom[i_port_number][dimm_number][rank_number]; - const uint32_t & PORT = i_port_number; - const uint32_t & DIMM = dimm_number; - const uint32_t & RANK = rank_number; - - FAPI_ERR( "mss_mrs_load: Error determining ATTR_VPD_DRAM_RTT_WR value: %d from attribute", dram_rtt_wr[i_port_number][dimm_number][rank_number]); - FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_RTT_WR_IMP_INPUT_ERROR); - return rc; - } - - rc_num = rc_num | mrs2.insert((uint8_t) pt_arr_sr, 0, 3); - rc_num = rc_num | mrs2.insert((uint8_t) cwl, 3, 3); - rc_num = rc_num | mrs2.insert((uint8_t) auto_sr, 6, 1); - rc_num = rc_num | mrs2.insert((uint8_t) sr_temp, 7, 1); - rc_num = rc_num | mrs2.insert((uint8_t) 0x00, 8, 1); - rc_num = rc_num | mrs2.insert((uint8_t) dram_rtt_wr[i_port_number][dimm_number][rank_number], 9, 2); - rc_num = rc_num | mrs2.insert((uint8_t) 0x00, 11, 5); - - rc_num = rc_num | mrs2.extractPreserve(&MRS2, 0, 16, 0); - - rc_num = rc_num | mrs3.insert((uint8_t) mpr_loc, 0, 2); - rc_num = rc_num | mrs3.insert((uint8_t) mpr_op, 2, 1); - rc_num = rc_num | mrs3.insert((uint16_t) 0x0000, 3, 13); - - rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0); - FAPI_INF( "MRS 0: 0x%04X", MRS0); - FAPI_INF( "MRS 1: 0x%04X", MRS1); - FAPI_INF( "MRS 2: 0x%04X", MRS2); - FAPI_INF( "MRS 3: 0x%04X", MRS3); - - if (rc_num) - { - FAPI_ERR( "mss_mrs_load: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - - // Only corresponding CS to rank - rc_num = rc_num | csn_8.setBit(0,8); - rc_num = rc_num | csn_8.clearBit(rank_number+4*dimm_number); - - // Propogate through the 4 MRS cmds - for ( mrs_number = 0; mrs_number < 4; mrs_number++) - { - - // Copying the current MRS into address buffer matching the MRS_array order - // Setting the bank address - if (mrs_number == 0) - { - rc_num = rc_num | address_16.insert(mrs2, 0, 16, 0); - rc_num = rc_num | bank_3.insert((uint8_t) MRS2_BA, 0, 1, 7); - rc_num = rc_num | bank_3.insert((uint8_t) MRS2_BA, 1, 1, 6); - rc_num = rc_num | bank_3.insert((uint8_t) MRS2_BA, 2, 1, 5); - } - else if ( mrs_number == 1) - { - rc_num = rc_num | address_16.insert(mrs3, 0, 16, 0); - rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 0, 1, 7); - rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 1, 1, 6); - rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 2, 1, 5); - } - else if ( mrs_number == 2) - { - rc_num = rc_num | address_16.insert(mrs1, 0, 16, 0); - rc_num = rc_num | bank_3.insert((uint8_t) MRS1_BA, 0, 1, 7); - rc_num = rc_num | bank_3.insert((uint8_t) MRS1_BA, 1, 1, 6); - rc_num = rc_num | bank_3.insert((uint8_t) MRS1_BA, 2, 1, 5); - } - else if ( mrs_number == 3) - { - rc_num = rc_num | address_16.insert(mrs0, 0, 16, 0); - rc_num = rc_num | bank_3.insert((uint8_t) MRS0_BA, 0, 1, 7); - rc_num = rc_num | bank_3.insert((uint8_t) MRS0_BA, 1, 1, 6); - rc_num = rc_num | bank_3.insert((uint8_t) MRS0_BA, 2, 1, 5); - } - - if (rc_num) - { - FAPI_ERR( "mss_mrs_load: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - - if (( address_mirror_map[i_port_number][dimm_number] & (0x08 >> rank_number) ) && (is_sim == 0)) - { - rc = mss_address_mirror_swizzle(i_target, i_port_number, dimm_number, rank_number, address_16, bank_3); - if(rc) return rc; - } - - - if (dram_2n_mode == ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_TRUE) - { - - // Send out to the CCS array a "setup" cycle - rc = mss_ccs_inst_arry_0( i_target, - io_ccs_inst_cnt, - address_16, - bank_3, - activate_1, - rasn_1, - casn_1, - wen_1, - cke_4, - csn_setup_8, - odt_4, - ddr_cal_type_4, - i_port_number); - if(rc) return rc; - rc = mss_ccs_inst_arry_1( i_target, - io_ccs_inst_cnt, - num_idles_setup_16, - num_repeat_16, - data_20, - read_compare_1, - rank_cal_4, - ddr_cal_enable_1, - ccs_end_1); - if(rc) return rc; - - io_ccs_inst_cnt ++; - - } - - // Send out to the CCS array - rc = mss_ccs_inst_arry_0( i_target, - io_ccs_inst_cnt, - address_16, - bank_3, - activate_1, - rasn_1, - casn_1, - wen_1, - cke_4, - csn_8, - odt_4, - ddr_cal_type_4, - i_port_number); - if(rc) return rc; - rc = mss_ccs_inst_arry_1( i_target, - io_ccs_inst_cnt, - num_idles_16, - num_repeat_16, - data_20, - read_compare_1, - rank_cal_4, - ddr_cal_enable_1, - ccs_end_1); - if(rc) return rc; - io_ccs_inst_cnt ++; - } // end mrs loop - } // end rank loop - - // For LRDIMM Set Rtt_nom, rtt_wr, driver impedance for R0 and R1 - if ( (dimm_type == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) && lrdimm_rank_mult_mode != 0 ) - { - rc = mss_lrdimm_mrs_load(i_target, i_port_number, dimm_number, io_ccs_inst_cnt); - if(rc) return rc; - } // end LRDIMM 8R dir MRS 1 - - } // end if has ranks - } // end dimm loop - - return rc; -} - -ReturnCode mss_assert_resetn ( - Target& i_target, - uint8_t value - ) -{ -// value of 1 deasserts reset - - ReturnCode rc; - ReturnCode rc_buff; - uint32_t rc_num = 0; - ecmdDataBufferBase data_buffer(64); - - FAPI_INF( "+++++++++++++++++++++ ASSERTING RESETN to the value of %d +++++++++++++++++++++", value); - - rc = fapiGetScom(i_target, CCS_MODEQ_AB_REG_0x030106A7, data_buffer); - if(rc) return rc; - - //Setting up CCS mode - rc_num = rc_num | data_buffer.insert( value, 24, 1, 7); // use bit 7 - - if (rc_num) - { - FAPI_ERR( "mss_assert_resetn: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - - rc = fapiPutScom(i_target, CCS_MODEQ_AB_REG_0x030106A7, data_buffer); - if(rc) return rc; - - return rc; -} - - -} //end extern C - diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.H b/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.H deleted file mode 100644 index b11db8a7a..000000000 --- a/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.H +++ /dev/null @@ -1,74 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2012,2014 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: mss_draminit.H,v 1.5 2012/02/10 21:59:20 jdsloat Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_draminit.H,v $ -//------------------------------------------------------------------------------ -// *! (C) Copyright International Business Machines Corp. 2011 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -//------------------------------------------------------------------------------ -// *! TITLE : mss_draminit.H -// *! DESCRIPTION : see additional comments below -// *! OWNER NAME : Jacob Sloat Email: jdsloat@us.ibm.com -// *! BACKUP NAME : Mark Bellows Email: bellows@us.ibm.com -// *! ADDITIONAL COMMENTS : -// -// Header file for mss_draminit. -// -//------------------------------------------------------------------------------ -// Don't forget to create CVS comments when you check in your changes! -//------------------------------------------------------------------------------ -// CHANGE HISTORY: -//------------------------------------------------------------------------------ -// Version:| Author: | Date: | Comment: -//---------|----------|---------|----------------------------------------------- -// 1.4 | jdsloat | 2/10/12| & fix -// 1.3 | jdsloat | 2/08/12| added description to target -// 1.2 | jdsloat | 1/13/12| added "fapi::" and "const" in typedef to match the call in the extern -// 1.1 | jdsloat | 11/18/11| Updated - -#ifndef MSS_DRAMINITHWPB_H_ -#define MSS_DRAMINITHWPB_H_ - -#include <fapi.H> - -typedef fapi::ReturnCode (*mss_draminit_FP_t)(const fapi::Target& i_target); - -extern "C" -{ - -/** - * @brief Draminit procedure. Loading RCD and MRS into the drams. - * - * @param[in] i_target Reference to centaur.mba target - * - * @return ReturnCode - */ - -fapi::ReturnCode mss_draminit(const fapi::Target& i_target); - -} // extern "C" - -#endif // MSS_DRAMINITHWPB_H_ diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C deleted file mode 100644 index 23b656401..000000000 --- a/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C +++ /dev/null @@ -1,1281 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2012,2015 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: mss_draminit_mc.C,v 1.51 2015/03/19 16:48:09 dcadiga Exp $ -//------------------------------------------------------------------------------ -// *! (C) Copyright International Business Machines Corp. 2011 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -//------------------------------------------------------------------------------ -// *! TITLE : cen_draminit_mc.C -// *! DESCRIPTION : Procedure for handing over control to the MC -// *! OWNER NAME : David Cadigan Email: dcadiga@us.ibm.com -// *! BACKUP NAME : Jacob Sloat Email: jdsloat@us.ibm.com -// #! ADDITIONAL COMMENTS : -// -// -//Run cen_draminit_mc.C to complete the initialization sequence. This performs the steps of -//***Set the IML Complete bit MBSSQ(2) (SCOM Addr: 0x02011417) to indicate that IML has completed -//***Start the refresh engines -//***Enabling periodic calibration and power management. -//------------------------------------------------------------------------------ -// Don't forget to create CVS comments when you check in your changes! -//------------------------------------------------------------------------------ -// CHANGE HISTORY: -//------------------------------------------------------------------------------ -// Version:| Author: | Date: | Comment: -//---------|----------|---------|----------------------------------------------- -// 1.51 | dcadiga |18-MAR-15| Added function to enable address inversion on port 1 -// 1.50 | gollub |12-FEB-15| Changed maint cmd delay from 100mSec to 1mSec -// 1.49 | gollub |12-FEB-15| Add check for RCD protect time on RDIMM and LRDIMM -// 1.48 | dcadiga |05-DEC-14| Powerdown control at initfile -// 1.47 | dcadiga |09-SEP-14| Removed SPARE cke disable step -// 1.46 | gollub |07-APR-14| Removed call to mss_unmask_inband_errors (moved it to proc_cen_framelock) -// 1.45 | dcadiga |14-FEB-14| Periodic Cal Fix for DD2 -// 1.44 | bellows |12-FEB-14| Workaround for ENABLE_RCE_WITH_OTHER_ERRORS_HW246685 -// 1.43 | dcadiga |28-OCT-13| Fixed code review comments for parent chip and typos -// 1.42 | dcadiga |16-OCT-13| Fixed Code Review Comments, added DD2.X EC check for parity on 32GB -// 1.41 | dcadiga |16-OCT-13| repeating Brent's test -// 1.40 | bwieman |21-JUN-13| just testing a commit -// 1.39 | dcadiga |21-JUN-13| Fixed Code Review Comments -// 1.38 | dcadiga |10-JUN-13| Removed Local Edit Info, added version comment -// 1.37 | dcadiga |10-JUN-13| Added Periodic Cal for 1.1 -// 1.36 | dcadiga |03-APR-13| Fixed compile warning -// 1.35 | dcadiga |01-APR-13| Temp Fix For Parity Error on 32GB -// 1.34 | dcadiga |12-MAR-13| Added spare cke disable as step 0 -// 1.33 | dcadiga |04-FEB-13| For some reason the main procedure call was commented out in the last commit... commenting it back in -// 1.32 | gollub |31-JAN-13| Uncommenting mss_unmask_maint_errors and mss_unmask_inband_errors -// 1.31 | dcadiga |21-JAN-13| Fixed variable name for memcal_interval (coded as memcal_iterval...) -// 1.30 | dcadiga |21-JAN-13| Hardcoded memcal interval to 0 (disabled) until attribute for EC is available -// 1.29 | jdsloat |14-JAN-13| Owner changed to Dave Cadigan. -// 1.28 | bellows |01-JAN-13| Added ECC Enable 64-byte data/checkbit inversion (from jdsloat) -// 1.27 | gollub |21-DEC-12| Calling mss_unmask_maint_errors and mss_unmask_inband_errors after mss_draminit_mc_cloned -// 1.26 | jdsloat |21-NOV-12| Changed Periodic Cal to Execute via MBA regs depending upon the ZQ Cal and MEM Cal timer values; 0 = disabled -// 1.25 | jdsloat |11-SEP-12| Calling mss_unmask_maint_errors and mss_unmask_inband_errors after mss_draminit_mc_cloned -// 1.24 | bellows |16-JUL-12| added in Id tag -// 1.22 | bellows |13-JUL-12| Fixed periodic cal bit 61 being set. HW214829 -// 1.20 | jdsloat |21-MAY-12| Typo fix, addresses moved to cen_scom_addresses.H, moved per cal settings to initfile -// 1.19 | jdsloat |08-MAY-12| All Refresh controls moved to initfile, changed to just enable refresh -// 1.18 | jdsloat |07-MAY-12| Fixed refresh interval, trfc, ref check interval bit ordering -// 1.16 | bellows |04-MAY-12| Temporary remove of attr read of freq until method defined -// 1.15 | jdsloat |16-APR-12| TRFC fixed to insert the right aligned 8 bits -// 1.15 | jdsloat |12-Mar-12| Attribute upgrade for cronusflex 12.4 ... trfc to uint32 -// 1.14 | jdsloat |07-Mar-12| Fixed iml_complete to match target -// 1.13 | jdsloat |07-Mar-12| Changed to target centaur with getChildchip, fixed buffer insert -// 1.12 | jdsloat |20-Feb-12| Built control_bit_ecc and power_management, added ccs_mode_reset -// 1.11 | jdsloat |20-Feb-12| removing #include <fapiClientCapi.H> -// 1.10 | jdsloat |20-Feb-12| Made Constants, Fixed RC_buff checking, Num_ranks check -// 1.10 | jdsloat |10-Feb-12| updated formatting/style, fixed some addresses, removed mba23 calls -// 1.9 | M Bellows|19-Jan-12| temporarily added includes and getconfig functions -// 1.8 | M Bellows|12-Jan-12| fixed refresh address, temporarly disabled periodic cal, -// | | | fixed unsigned long constants, fixed variable declaration -// | | | for calibration registers" -// 1.7 | D Cadigan| 011012 | Changed periodic cal routine to reflect changes in registers for Centaur1 -// 1.6 | D Cadigan| 12222011| Fixed insert again -// 1.5 | D Cadigan| 12212011| Fixed insert for buffers, modified dram_freq to temporarily calculate a value based on the method in mss_freq -// 1.4 | D Cadigan| 12092011| Added header file -// 1.3 | D Cadigan| 09302011| Moved to FAPI VBU directory -// 1.2 | D Cadigan| 09282011| Converted to fapi, enhanced procedures to take in some variables. Still need to debug those functions -// 1.1 | D Cadigan| 04072011| Initial Copy - -//---------------------------------------------------------------------- -// FAPI Includes -//---------------------------------------------------------------------- -#include <fapi.H> - -//---------------------------------------------------------------------- -// Centaur function Includes -//---------------------------------------------------------------------- -#include <mss_funcs.H> -#include <mss_unmask_errors.H> - -//---------------------------------------------------------------------- -// Address Includes -//---------------------------------------------------------------------- -#include <cen_scom_addresses.H> - - -extern "C" { - -using namespace fapi; - - -//---------------------------------------------------------------------- -// Subroutine declarations -//---------------------------------------------------------------------- -ReturnCode mss_draminit_mc_cloned(Target& i_target); -ReturnCode mss_start_refresh (Target& i_mbatarget, Target& i_centarget); -ReturnCode mss_enable_periodic_cal(Target& i_target); -ReturnCode mss_set_iml_complete(Target& i_target); -ReturnCode mss_enable_power_management(Target& i_target); -ReturnCode mss_enable_control_bit_ecc(Target& i_target); -ReturnCode mss_ccs_mode_reset(Target& i_target); -ReturnCode mss_check_RCD_protect_time(Target& i_target); -ReturnCode mss_spare_cke_disable(Target& i_target); -ReturnCode mss_enable_addr_inversion(Target& i_target); - - -ReturnCode mss_draminit_mc(Target& i_target) -{ - // Target is centaur.mba - fapi::ReturnCode l_rc; - //Commented back in by dcadiga - l_rc = mss_draminit_mc_cloned(i_target); - //FAPI_INF("DID NOT RUN DRAMINIT MC\n"); - // If mss_unmask_maint_errors gets it's own bad rc, - // it will commit the passed in rc (if non-zero), and return it's own bad rc. - // Else if mss_unmask_maint_errors runs clean, - // it will just return the passed in rc. - l_rc = mss_unmask_maint_errors(i_target, l_rc); - - return l_rc; -} - - - -ReturnCode mss_draminit_mc_cloned(Target& i_target) -{ -// Target is centaur -// - ReturnCode rc; - std::vector<fapi::Target> l_mbaChiplets; - uint32_t rc_num = 0; - uint8_t scom_parity_fixed_dd2 = 0; - rc = FAPI_ATTR_GET(ATTR_CENTAUR_EC_SCOM_PARITY_ERROR_HW244827_FIXED, &i_target, scom_parity_fixed_dd2); - if (rc) return rc; - // Get associated MBA's on this centaur - rc=fapiGetChildChiplets(i_target, fapi::TARGET_TYPE_MBA_CHIPLET, l_mbaChiplets); - if (rc) return rc; - - - - - - // Step Zero: Turn Off Spare CKE - This needs to be off before IML complete - // STEP COMMENTED FOR SW275629 - FAPI_INF("+++ Disabling Spare CKE FIX DISABLED +++"); - //for (uint32_t i=0; i < l_mbaChiplets.size(); i++) - //{ - // rc = mss_spare_cke_disable(l_mbaChiplets[i]); - // if(rc) - // { - // FAPI_ERR("---Error During Spare CKE Disable rc = 0x%08X (creator = %d)---", uint32_t(rc), rc.getCreator()); - // return rc; - // } - - //} - - - // Step One: Set IML COMPLETE - FAPI_INF( "+++ Setting IML Complete +++"); - rc = mss_set_iml_complete(i_target); - if(rc) - { - FAPI_ERR("---Error During IML Complete Enable rc = 0x%08X (creator = %d)---", uint32_t(rc), rc.getCreator()); - return rc; - } - //DD1.X Scom Parity Fix HW244827 - if(!scom_parity_fixed_dd2) - { - FAPI_INF("+++DD1.X Centaur, clearing MBS Parity FIR +++"); - ecmdDataBufferBase parity_tmp_data_buffer_64(64); - rc = fapiGetScom(i_target, MBS_FIR_REG_0x02011400, parity_tmp_data_buffer_64); - if(rc) return rc; - rc_num = rc_num | parity_tmp_data_buffer_64.clearBit(8); - if(rc_num) - { - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target, MBS_FIR_REG_0x02011400, parity_tmp_data_buffer_64); - if(rc) - { - FAPI_ERR("---Error During Clear Parity Bit rc = 0x%08X (creator = %d)---", uint32_t(rc), rc.getCreator()); - return rc; - } - - } - // Loop through the 2 MBA's - for (uint32_t i=0; i < l_mbaChiplets.size(); i++) - { - - - // Step Two: Disable CCS address lines - FAPI_INF( "+++ Disabling CCS Address Lines +++"); - rc = mss_ccs_mode_reset(l_mbaChiplets[i]); - if(rc) - { - FAPI_ERR("---Error During CCS Mode Reset rc = 0x%08X (creator = %d)---", uint32_t(rc), rc.getCreator()); - return rc; - } - - - // Step Two.1: Check RCD protect time on RDIMM and LRDIMM - FAPI_INF( "+++ Check RCD protect time on RDIMM and LRDIMM +++"); - rc = mss_check_RCD_protect_time(l_mbaChiplets[i]); - if(rc) - { - FAPI_ERR("---Error During Check RCD protect time rc = 0x%08X (creator = %d)---", uint32_t(rc), rc.getCreator()); - return rc; - } - - //Step Two.2: Enable address inversion on each MBA for ALL CARDS - FAPI_INF("+++ Setting up adr inversion for port 1 +++"); - rc = mss_enable_addr_inversion(l_mbaChiplets[i]); - if(rc) - { - FAPI_ERR("---Error During ADR Inversion rc = 0x%08X (creator = %d)---", uint32_t(rc), rc.getCreator()); - return rc; - } - - - // Step Three: Enable Refresh - FAPI_INF( "+++ Enabling Refresh +++"); - ecmdDataBufferBase mba01_ref0q_data_buffer_64(64); - rc = fapiGetScom(l_mbaChiplets[i], MBA01_REF0Q_0x03010432, mba01_ref0q_data_buffer_64); - if(rc) return rc; - //Bit 0 is enable - rc_num = rc_num | mba01_ref0q_data_buffer_64.setBit(0); - if(rc_num) - { - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(l_mbaChiplets[i], MBA01_REF0Q_0x03010432, mba01_ref0q_data_buffer_64); - if(rc) - { - FAPI_ERR("---Error During Refresh Enable rc = 0x%08X (creator = %d)---", uint32_t(rc), rc.getCreator()); - return rc; - } - - // Step Four: Setup Periodic Cals - FAPI_INF( "+++ Setting Up Periodic Cals +++"); - rc = mss_enable_periodic_cal(l_mbaChiplets[i]); - if(rc) - { - FAPI_ERR("---Error During Periodic Cal Setup and Enable rc = 0x%08X (creator = %d)---", uint32_t(rc), rc.getCreator()); - return rc; - } - - // Step Five: Setup Power Management - FAPI_INF( "+++ Setting Up Power Management +++"); - FAPI_INF( "+++ POWER MANAGEMENT HANDLED AT INITFILE +++"); - //Procedure commented out because domain reduction enablement now handled at the initfile - //rc = mss_enable_power_management(l_mbaChiplets[i]); - //if(rc) - //{ - // FAPI_ERR("---Error During Power Management Setup and Enable rc = 0x%08X (creator = %d)---", uint32_t(rc), rc.getCreator()); - // return rc; - //} - - } - - // Step Six: Setup Control Bit ECC - FAPI_INF( "+++ Setting Up Control Bit ECC +++"); - rc = mss_enable_control_bit_ecc(i_target); - if(rc) - { - FAPI_ERR("---Error During Control Bit ECC Setup rc = 0x%08X (creator = %d)---", uint32_t(rc), rc.getCreator()); - return rc; - } - - return rc; -} - -ReturnCode mss_enable_periodic_cal (Target& i_target) -{ - //Target MBA - - //Procedure to setup and enable periodic cals - //Variables - ReturnCode rc; - uint32_t rc_num = 0; - uint8_t bluewaterfall_broken = 0; - uint8_t nwell_misplacement = 0; - - //Find Parent chip for EC check - fapi::Target l_target_centaur; - rc = fapiGetParentChip(i_target, l_target_centaur); - if(rc) return rc; - - - - - ecmdDataBufferBase data_buffer_64(64); - - uint32_t memcal_iterval; // 00 = Disable - rc = FAPI_ATTR_GET(ATTR_EFF_MEMCAL_INTERVAL, &i_target, memcal_iterval); - if(rc) return rc; - //Determine what type of Centaur this is - rc = FAPI_ATTR_GET(ATTR_MSS_BLUEWATERFALL_BROKEN, &l_target_centaur, bluewaterfall_broken); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_MSS_NWELL_MISPLACEMENT, &l_target_centaur, nwell_misplacement); - if(rc) return rc; - - - - if((bluewaterfall_broken == 0) && (nwell_misplacement == 0)){ - FAPI_INF("+++ Centaur is DD1.1 or later, enabling MEMCAL +++"); - } - else{ - FAPI_INF("+++ RD Phase Select Workaround, DISABLING MEMCAL VIA HARDCODE +++"); - memcal_iterval = 0; - } - - uint32_t zq_cal_iterval; // 00 = Disable - rc = FAPI_ATTR_GET(ATTR_EFF_ZQCAL_INTERVAL, &i_target, zq_cal_iterval); - if(rc) return rc; - - - rc = fapiGetScom(i_target, MBA01_MBA_CAL0Q_0x0301040F, data_buffer_64); - if(rc) return rc; - - FAPI_INF("+++ Enabling Periodic Calibration +++"); - - if (zq_cal_iterval != 0) - { - //ZQ Cal Enabled - rc_num = rc_num | data_buffer_64.setBit(0); - if(rc_num) - { - rc.setEcmdError(rc_num); - return rc; - } - FAPI_INF("+++ Periodic Calibration: ZQ Cal Enabled +++"); - } - else - { - //ZQ Cal Disabled - rc_num = rc_num | data_buffer_64.clearBit(0); - if(rc_num) - { - rc.setEcmdError(rc_num); - return rc; - } - FAPI_INF("+++ Periodic Calibration: ZQ Cal Disabled +++"); - } - - rc = fapiPutScom(i_target, MBA01_MBA_CAL0Q_0x0301040F, data_buffer_64); - if(rc) return rc; - - - if (memcal_iterval != 0) - { - - - - uint8_t attr_centaur_ec_rdclk_pr_update_hw236658_fixed; - rc = FAPI_ATTR_GET(ATTR_CENTAUR_EC_RDCLK_PR_UPDATE_HW236658_FIXED, &i_target, attr_centaur_ec_rdclk_pr_update_hw236658_fixed); - if(rc) return rc; - - if(!attr_centaur_ec_rdclk_pr_update_hw236658_fixed){ - - //Check EC, Disable Phase Select Update for DD2 HW - //Phase Select Fix for DD1.1 - rc_num = rc_num | data_buffer_64.flushTo0(); - rc_num = rc_num | data_buffer_64.setBit(52); - if(rc_num) - { - rc.setEcmdError(rc_num); - return rc; - } - - - rc = fapiPutScom(i_target,DPHY01_DDRPHY_DP18_RD_DIA_CONFIG5_P0_0_0x800000120301143F,data_buffer_64); - if(rc) return rc; - rc = fapiPutScom(i_target,DPHY01_DDRPHY_DP18_RD_DIA_CONFIG5_P0_1_0x800004120301143F,data_buffer_64); - if(rc) return rc; - rc = fapiPutScom(i_target,DPHY01_DDRPHY_DP18_RD_DIA_CONFIG5_P0_2_0x800008120301143F,data_buffer_64); - if(rc) return rc; - rc = fapiPutScom(i_target,DPHY01_DDRPHY_DP18_RD_DIA_CONFIG5_P0_3_0x80000C120301143F,data_buffer_64); - if(rc) return rc; - rc = fapiPutScom(i_target,DPHY01_DDRPHY_DP18_RD_DIA_CONFIG5_P0_4_0x800010120301143F,data_buffer_64); - if(rc) return rc; - - rc = fapiPutScom(i_target,DPHY01_DDRPHY_DP18_RD_DIA_CONFIG5_P1_0_0x800100120301143F,data_buffer_64); - if(rc) return rc; - rc = fapiPutScom(i_target,DPHY01_DDRPHY_DP18_RD_DIA_CONFIG5_P1_1_0x800104120301143F,data_buffer_64); - if(rc) return rc; - rc = fapiPutScom(i_target,DPHY01_DDRPHY_DP18_RD_DIA_CONFIG5_P1_2_0x800108120301143F,data_buffer_64); - if(rc) return rc; - rc = fapiPutScom(i_target,DPHY01_DDRPHY_DP18_RD_DIA_CONFIG5_P1_3_0x80010C120301143F,data_buffer_64); - if(rc) return rc; - rc = fapiPutScom(i_target,DPHY01_DDRPHY_DP18_RD_DIA_CONFIG5_P1_4_0x800110120301143F,data_buffer_64); - - - } - - //Disable Periodic Read Centering for ALL HW - rc_num = rc_num | data_buffer_64.flushTo0(); - if(rc_num) - { - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiGetScom(i_target,DPHY01_DDRPHY_PC_PER_CAL_CONFIG_P0_0x8000C00B0301143F,data_buffer_64); - rc_num = rc_num | data_buffer_64.clearBit(54); - rc = fapiPutScom(i_target,DPHY01_DDRPHY_PC_PER_CAL_CONFIG_P0_0x8000C00B0301143F,data_buffer_64); - - - - rc_num = rc_num | data_buffer_64.flushTo0(); - if(rc_num) - { - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiGetScom(i_target,DPHY01_DDRPHY_PC_PER_CAL_CONFIG_P1_0x8001C00B0301143F,data_buffer_64); - rc_num = rc_num | data_buffer_64.clearBit(54); - rc = fapiPutScom(i_target,DPHY01_DDRPHY_PC_PER_CAL_CONFIG_P1_0x8001C00B0301143F,data_buffer_64); - - if(rc) return rc; - - - //Mem Cal Enabled - rc_num = rc_num | data_buffer_64.flushTo0(); - if(rc_num) - { - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiGetScom(i_target, MBA01_MBA_CAL1Q_0x03010410, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.setBit(0); - if(rc_num) - { - rc.setEcmdError(rc_num); - return rc; - } - FAPI_INF("+++ Periodic Calibration: Mem Cal Enabled +++"); - } - else - { - //Mem Cal Disabled - rc_num = rc_num | data_buffer_64.flushTo0(); - if(rc_num) - { - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiGetScom(i_target, MBA01_MBA_CAL1Q_0x03010410, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.clearBit(0); - if(rc_num) - { - rc.setEcmdError(rc_num); - return rc; - } - FAPI_INF("+++ Periodic Calibration: Mem Cal Disabled +++"); - } - rc = fapiPutScom(i_target, MBA01_MBA_CAL1Q_0x03010410, data_buffer_64); - if(rc) return rc; - return rc; - -} - -ReturnCode mss_set_iml_complete (Target& i_target) -{ - //Target centaur - - //Set IML Complete - //Variables - ReturnCode rc; - uint32_t rc_num = 0; - ecmdDataBufferBase data_buffer_64(64); - - rc = fapiGetScom(i_target, MBSSQ_0x02011417, data_buffer_64); - if(rc) return rc; - - rc_num = rc_num | data_buffer_64.setBit(2); - if (rc_num) - { - FAPI_ERR( "mss_set_iml_complete: Error setting up buffers"); - rc.setEcmdError(rc_num); - return rc; - } - - rc = fapiPutScom(i_target, MBSSQ_0x02011417, data_buffer_64); - if(rc) return rc; - - FAPI_INF("+++ IML Complete Enabled +++"); - return rc; -} - -ReturnCode mss_enable_control_bit_ecc (Target& i_target) -{ - //Target centaur - - //Enable Control Bit ECC - //Variables - ReturnCode rc; - uint32_t rc_num = 0; - ecmdDataBufferBase ecc0_data_buffer_64(64); - ecmdDataBufferBase ecc1_data_buffer_64(64); - - rc = fapiGetScom(i_target, MBS_ECC0_MBSECCQ_0x0201144A, ecc0_data_buffer_64); - if(rc) return rc; - - rc = fapiGetScom(i_target, MBS_ECC1_MBSECCQ_0x0201148A, ecc1_data_buffer_64); - if(rc) return rc; - - // Enable Memory ECC Check/Correct for MBA01 - // This assumes that all other settings of this register - // are set in previous precedures or initfile. - rc_num = rc_num | ecc0_data_buffer_64.clearBit(0); - rc_num = rc_num | ecc0_data_buffer_64.clearBit(1); - rc_num = rc_num | ecc0_data_buffer_64.setBit(3); - - // Enable Memory ECC Check/Correct for MBA23 - // This assumes that all other settings of this register - // are set in previous precedures or initfile. - rc_num = rc_num | ecc1_data_buffer_64.clearBit(0); - rc_num = rc_num | ecc1_data_buffer_64.clearBit(1); - rc_num = rc_num | ecc1_data_buffer_64.setBit(3); - - uint8_t attr_centaur_ec_enable_rce_with_other_errors_hw246685; - rc = FAPI_ATTR_GET(ATTR_CENTAUR_EC_ENABLE_RCE_WITH_OTHER_ERRORS_HW246685, &i_target, attr_centaur_ec_enable_rce_with_other_errors_hw246685); - if(rc) return rc; - - if(attr_centaur_ec_enable_rce_with_other_errors_hw246685) { - rc_num = rc_num | ecc0_data_buffer_64.setBit(16); - rc_num = rc_num | ecc1_data_buffer_64.setBit(16); - } - - if (rc_num) - { - FAPI_ERR( "mss_enable_control_bit_ecc: Error setting up buffers"); - rc.setEcmdError(rc_num); - return rc; - } - - rc = fapiPutScom(i_target, MBS_ECC0_MBSECCQ_0x0201144A, ecc0_data_buffer_64); - if(rc) return rc; - - rc = fapiPutScom(i_target, MBS_ECC1_MBSECCQ_0x0201148A, ecc1_data_buffer_64); - if(rc) return rc; - - FAPI_INF("+++ mss_enable_control_bit_ecc complete +++"); - return rc; -} - -ReturnCode mss_enable_power_management (Target& i_target) -{ - // Target MBA - //Enable Power Management - //Variables - ReturnCode rc; - uint32_t rc_num = 0; - ecmdDataBufferBase pm_data_buffer_64(64); - - rc = fapiGetScom(i_target, MBA01_PM0Q_0x03010434, pm_data_buffer_64); - if(rc) return rc; - - // Enable power domain control - // This assumes that all other settings of this register - // are set in previous precedures or initfile. - rc_num = rc_num | pm_data_buffer_64.setBit(2); - - - if (rc_num) - { - FAPI_ERR( "mss_enable_power_management: Error setting up buffers"); - rc.setEcmdError(rc_num); - return rc; - } - - rc = fapiPutScom(i_target, MBA01_PM0Q_0x03010434, pm_data_buffer_64); - if(rc) return rc; - - FAPI_INF("+++ mss_enable_power_management complete +++"); - return rc; -} - -ReturnCode mss_ccs_mode_reset (Target& i_target) -{ - - //Target MBA - //Selects address data from the mainline - //Variables - ReturnCode rc; - uint32_t rc_num = 0; - ecmdDataBufferBase ccs_mode_data_buffer_64(64); - - rc = fapiGetScom(i_target, CCS_MODEQ_AB_REG_0x030106A7, ccs_mode_data_buffer_64); - if(rc) return rc; - - rc_num = rc_num | ccs_mode_data_buffer_64.clearBit(29); - - if (rc_num) - { - FAPI_ERR( "mss_ccs_mode_reset: Error setting up buffers"); - rc.setEcmdError(rc_num); - return rc; - } - - rc = fapiPutScom(i_target, CCS_MODEQ_AB_REG_0x030106A7, ccs_mode_data_buffer_64); - if(rc) return rc; - - FAPI_INF("+++ mss_ccs_mode_reset complete +++"); - return rc; -} - - -ReturnCode mss_check_RCD_protect_time (Target& i_target) -{ - - // Target MBA - - uint32_t l_ecmd_rc = 0; - fapi::ReturnCode l_rc; - fapi::Target l_targetCentaur; - uint8_t l_mbaPosition = 0; - uint8_t l_dimm_type = 0; - uint8_t l_cfg_wrdone_dly = 0; - uint8_t l_cfg_rdtag_dly = 0; - uint8_t l_cfg_rcd_protection_time = 0; - uint8_t l_highest_cfg_rcd_protection_time = 0; - uint8_t l_max_cfg_rcd_protection_time = 0; - uint8_t l_cmdType = 0x10; // DISPLAY, bit 0:5 = 10000b - uint8_t l_valid_dimms = 0; - uint8_t l_valid_dimm[2][2]; - uint8_t l_port=0; - uint8_t l_dimm=0; - uint8_t l_dimm_index = 0; - - std::vector<fapi::Target> l_target_dimm_array; - uint8_t l_target_port = 0; - uint8_t l_target_dimm = 0; - - // 1 ms delay for HW mode - const uint64_t HW_MODE_DELAY = 1000000; - - // 200000 sim cycle delay for SIM mode - const uint64_t SIM_MODE_DELAY = 200000; - - uint32_t l_mbeccfir_mask_or_address[2]={ - // port0/1 port2/3 - MBS_ECC0_MBECCFIR_MASK_OR_0x02011445, MBS_ECC1_MBECCFIR_MASK_OR_0x02011485}; - - uint32_t l_mbeccfir_and_address[2]={ - // port0/1 port2/3 - MBS_ECC0_MBECCFIR_AND_0x02011441, MBS_ECC0_MBECCFIR_AND_0x02011481}; - - uint32_t l_mbeccfir_address[2]={ - // port0/1 port2/3 - MBS_ECC0_MBECCFIR_0x02011440, MBS_ECC1_MBECCFIR_0x02011480}; - - ecmdDataBufferBase l_mbeccfir_mask_or(64); - ecmdDataBufferBase l_mbeccfir_and(64); - ecmdDataBufferBase l_mbeccfir(64); - ecmdDataBufferBase l_mbacalfir_mask_or(64); - ecmdDataBufferBase l_mbacalfir_mask_and(64); - ecmdDataBufferBase l_mbacalfir_and(64); - ecmdDataBufferBase l_mbacalfir(64); - ecmdDataBufferBase l_mba_dsm0(64); - ecmdDataBufferBase l_mba_farb0(64); - ecmdDataBufferBase l_mbmct(64); - ecmdDataBufferBase l_mbmaca(64); - ecmdDataBufferBase l_mbasctl(64); - ecmdDataBufferBase l_mbmcc(64); - ecmdDataBufferBase l_mbafir(64); - ecmdDataBufferBase l_mbmsr(64); - - //------------------------------------------------------ - // Get DIMM type - //------------------------------------------------------ - l_rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target, l_dimm_type); - if(l_rc) - { - FAPI_ERR("Error getting ATTR_EFF_DIMM_TYPE on %s.",i_target.toEcmdString()); - return l_rc; - } - - //------------------------------------------------------ - // Only run on RDIMM or LRDIMM - //------------------------------------------------------ - if ((l_dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_RDIMM)||(l_dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM)) - { - //------------------------------------------------------ - // Exit if parity error reporting disabled - //------------------------------------------------------ - // NOTE: This is just to be safe, so we don't create errors in case the initfile is out of sync. - // Read FARB0 - l_rc = fapiGetScom(i_target, MBA01_MBA_FARB0Q_0x03010413, l_mba_farb0); - if(l_rc) return l_rc; - - if(l_mba_farb0.isBitSet(60)) - { - FAPI_ERR("Exit mss_check_RCD_protect_time, since parity error reporting disabled on %s.",i_target.toEcmdString()); - return l_rc; - } - - //------------------------------------------------------ - // Get Centaur target for the given MBA - //------------------------------------------------------ - l_rc = fapiGetParentChip(i_target, l_targetCentaur); - if(l_rc) - { - FAPI_ERR("Error getting Centaur parent target for the given MBA on %s.",i_target.toEcmdString()); - return l_rc; - } - - //------------------------------------------------------ - // Get MBA position: 0 = mba01, 1 = mba23 - //------------------------------------------------------ - l_rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target, l_mbaPosition); - if(l_rc) - { - FAPI_ERR("Error getting MBA position on %s.",i_target.toEcmdString()); - return l_rc; - } - - //------------------------------------------------------ - // Find out which DIMMs are functional - //------------------------------------------------------ - l_rc = FAPI_ATTR_GET(ATTR_MSS_EFF_DIMM_FUNCTIONAL_VECTOR, &i_target, l_valid_dimms); - if (l_rc) - { - FAPI_ERR("Failed to get attribute: ATTR_MSS_EFF_DIMM_FUNCTIONAL_VECTOR on %s.",i_target.toEcmdString()); - return l_rc; - } - l_valid_dimm[0][0] = (l_valid_dimms & 0x80); // port0, dimm0 - l_valid_dimm[0][1] = (l_valid_dimms & 0x40); // port0, dimm1 - l_valid_dimm[1][0] = (l_valid_dimms & 0x08); // port1, dimm0 - l_valid_dimm[1][1] = (l_valid_dimms & 0x04); // port1, dimm1 - - - //------------------------------------------------------ - // Mask MBECCFIR bit 45: maint RCD parity error - //------------------------------------------------------ - l_ecmd_rc |= l_mbeccfir_mask_or.flushTo0(); - // Set bit 45 in the OR mask - l_ecmd_rc |= l_mbeccfir_mask_or.setBit(45); - if(l_ecmd_rc) - { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - // Write OR mask - l_rc = fapiPutScom(l_targetCentaur, l_mbeccfir_mask_or_address[l_mbaPosition], l_mbeccfir_mask_or); - if(l_rc) return l_rc; - - - //------------------------------------------------------ - // Mask MBACALFIR bits 4,7: port0,1 RCD parity error - //------------------------------------------------------ - l_ecmd_rc |= l_mbacalfir_mask_or.flushTo0(); - // Set bit 4,7 in the OR mask - l_ecmd_rc |= l_mbacalfir_mask_or.setBit(4); - l_ecmd_rc |= l_mbacalfir_mask_or.setBit(7); - if(l_ecmd_rc) - { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - // Write OR mask - l_rc = fapiPutScom(i_target, MBA01_MBACALFIR_MASK_OR_0x03010405, l_mbacalfir_mask_or); - if(l_rc) return l_rc; - - - //------------------------------------------------------ - // Find l_max_cfg_rcd_protection_time - //------------------------------------------------------ - l_rc = fapiGetScom(i_target, MBA01_MBA_DSM0_0x0301040a, l_mba_dsm0); - if(l_rc) return l_rc; - // Get 24:29 cfg_wrdone_dly - l_ecmd_rc |= l_mba_dsm0.extractPreserve(&l_cfg_wrdone_dly, 24, 6, 8-6); - // Get 36:41 cfg_rdtag_dly - l_ecmd_rc |= l_mba_dsm0.extractPreserve(&l_cfg_rdtag_dly, 36, 6, 8-6); - if(l_ecmd_rc) - { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - // Pick lower of the two: cfg_wrdone_dly and cfg_rdtag_dly, and use that for l_max_cfg_rcd_protection_time - if (l_cfg_wrdone_dly <= l_cfg_rdtag_dly) - { - l_max_cfg_rcd_protection_time = l_cfg_wrdone_dly; - } - else - { - l_max_cfg_rcd_protection_time = l_cfg_rdtag_dly; - } - - //------------------------------------------------------ - // Maint cmd setup steps we can do once per MBA - //------------------------------------------------------ - - // Load display cmd type: MBMCT, 0:5 = 10000b - l_rc = fapiGetScom(i_target, MBA01_MBMCTQ_0x0301060A, l_mbmct); - if(l_rc) return l_rc; - l_ecmd_rc |= l_mbmct.insert(l_cmdType, 0, 5, 8-5 ); - if(l_ecmd_rc) - { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - l_rc = fapiPutScom(i_target, MBA01_MBMCTQ_0x0301060A, l_mbmct); - if(l_rc) return l_rc; - - // Clear all stop conditions in MBASCTL - l_rc = fapiGetScom(i_target, MBA01_MBASCTLQ_0x0301060F, l_mbasctl); - if(l_rc) return l_rc; - l_ecmd_rc |= l_mbasctl.clearBit(0,13); - l_ecmd_rc |= l_mbasctl.clearBit(16); - if(l_ecmd_rc) - { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - l_rc = fapiPutScom(i_target, MBA01_MBASCTLQ_0x0301060F, l_mbasctl); - if(l_rc) return l_rc; - - - //------------------------------------------------------ - // For each port in the given MBA:0,1 - //------------------------------------------------------ - for(l_port=0; l_port<2; l_port++ ) - { - //------------------------------------------------------ - // For each DIMM select on the given port:0,1 - //------------------------------------------------------ - for(l_dimm=0; l_dimm<2; l_dimm++ ) - { - //------------------------------------------------------ - // If DIMM valid - //------------------------------------------------------ - if (l_valid_dimm[l_port][l_dimm]) - { - //------------------------------------------------------ - // Start with cfg_rcd_protection_time of 8 - //------------------------------------------------------ - l_cfg_rcd_protection_time = 8; - - //------------------------------------------------------ - // Clear MBECCFIR bit 45: maint RCD parity error - //------------------------------------------------------ - l_ecmd_rc |= l_mbeccfir_and.flushTo1(); - // Clear bit 45 in the AND mask - l_ecmd_rc |= l_mbeccfir_and.clearBit(45); - if(l_ecmd_rc) - { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - // Write AND mask - l_rc = fapiPutScom(l_targetCentaur, l_mbeccfir_and_address[l_mbaPosition], l_mbeccfir_and); - if(l_rc) return l_rc; - - //------------------------------------------------------ - // Loop until we find a passing cfg_rcd_protection_time - //------------------------------------------------------ - do - { - //------------------------------------------------------ - // Clear MBACALFIR bits 4,7: port0,1 RCD parity error - //------------------------------------------------------ - // NOTE: Clearing these each time so they will be accrate for FFDC - l_ecmd_rc |= l_mbacalfir_and.flushTo1(); - // Clear bit 4,7 in the AND mask - l_ecmd_rc |= l_mbacalfir_and.clearBit(4); - l_ecmd_rc |= l_mbacalfir_and.clearBit(7); - if(l_ecmd_rc) - { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - // Write AND mask - l_rc = fapiPutScom(i_target, MBA01_MBACALFIR_AND_0x03010401, l_mbacalfir_and); - if(l_rc) return l_rc; - - - //------------------------------------------------------ - // Set l_cfg_rcd_protection_time - //------------------------------------------------------ - // Read FARB0 - l_rc = fapiGetScom(i_target, MBA01_MBA_FARB0Q_0x03010413, l_mba_farb0); - if(l_rc) return l_rc; - - // Set cfg_rcd_protection_time - l_ecmd_rc |= l_mba_farb0.insert( l_cfg_rcd_protection_time, 48, 6, 8-6 ); - - - //------------------------------------------------------ - // Arm single shot RCD parity error for the given port - //------------------------------------------------------ - // Select single shot - l_ecmd_rc |= l_mba_farb0.clearBit(59); - if(l_port == 0) - { - // Select port0 CAS - l_ecmd_rc |= l_mba_farb0.setBit(40); - } - else - { - // Select port1 CAS - l_ecmd_rc |= l_mba_farb0.setBit(42); - } - if(l_ecmd_rc) - { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - // Write FARB0 - l_rc = fapiPutScom(i_target, MBA01_MBA_FARB0Q_0x03010413, l_mba_farb0); - if(l_rc) return l_rc; - - - //------------------------------------------------------ - // Do single address display cmd - //------------------------------------------------------ - - // Load start address in MBMACA for the given DIMM - l_ecmd_rc |= l_mbmaca.flushTo0(); - if(l_dimm == 1) - { - l_ecmd_rc |= l_mbmaca.setBit(1); - } - - if(l_ecmd_rc) - { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - l_rc = fapiPutScom(i_target, MBA01_MBMACAQ_0x0301060D, l_mbmaca); - if(l_rc) return l_rc; - - // Start the command: MBMCCQ - l_ecmd_rc |= l_mbmcc.flushTo0(); - l_ecmd_rc |= l_mbmcc.setBit(0); - if(l_ecmd_rc) - { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - l_rc = fapiPutScom(i_target, MBA01_MBMCCQ_0x0301060B, l_mbmcc); - if(l_rc) return l_rc; - - // Check for MBAFIR[1], invalid maint address. - l_rc = fapiGetScom(i_target, MBA01_MBAFIRQ_0x03010600, l_mbafir); - if(l_rc) return l_rc; - - if (l_mbafir.isBitSet(1)) - { - FAPI_ERR("Display invalid address = 0x%.8X 0x%.8X, on port%d, dimm%d, %s.", - l_mbmaca.getWord(0), l_mbmaca.getWord(1), l_port, l_dimm, i_target.toEcmdString()); - - // Calling out FW high - // FFDC: MBA target - const fapi::Target & MBA = i_target; - // FFDC: Capture invalid address - ecmdDataBufferBase & MBMACA = l_mbmaca; - // FFDC: Capture FIR - ecmdDataBufferBase & MBAFIR = l_mbafir; - // Create new log - FAPI_SET_HWP_ERROR(l_rc, RC_MSS_DRAMINIT_MC_DISPLAY_INVALID_ADDR); - - return l_rc; - } - - // Delay 1 mSec - fapiDelay(HW_MODE_DELAY, SIM_MODE_DELAY); - - // See if MBMSRQ[0] maint cmd in progress bit if off - l_rc = fapiGetScom(i_target, MBA01_MBMSRQ_0x0301060C, l_mbmsr); - if(l_rc) return l_rc; - - // If cmd still in progress - if (l_mbmsr.isBitSet(1)) - { - FAPI_ERR("Display timeout on %s.",i_target.toEcmdString()); - - // Calling out FW high - // Calling out MBA target low, deconfig, gard - const fapi::Target & MBA = i_target; - // FFDC: Capture cmd type - ecmdDataBufferBase & MBMCT = l_mbmct; - // FFDC: Capture address - ecmdDataBufferBase & MBMACA = l_mbmaca; - // FFDC: Capture stop conditions - ecmdDataBufferBase & MBASCTL = l_mbasctl; - // FFDC: Capture stop/start control reg - ecmdDataBufferBase & MBMCC = l_mbmcc; - // FFDC: Capture Capture cmd in progress reg - ecmdDataBufferBase & MBMSR = l_mbmsr; - // FFDC: Capture FIR - ecmdDataBufferBase & MBAFIR = l_mbafir; - // Create new log - FAPI_SET_HWP_ERROR(l_rc, RC_MSS_DRAMINIT_MC_DISPLAY_TIMEOUT); - - return l_rc; - } - - - //------------------------------------------------------ - // Check for MBECCFIR bit 45: maint RCD parity error - //------------------------------------------------------ - - l_rc = fapiGetScom(l_targetCentaur, l_mbeccfir_address[l_mbaPosition], l_mbeccfir); - if(l_rc) return l_rc; - - // If FIR bit set - if (l_mbeccfir.isBitSet(45)) - { - // Save highest value seen on this MBA - if (l_cfg_rcd_protection_time > l_highest_cfg_rcd_protection_time) - { - l_highest_cfg_rcd_protection_time = l_cfg_rcd_protection_time; - } - - break; // Exit do-while loop and move on to another DIMM - } - - // Else FIR not set - else - { - // Reached max_cfg_rcd_protection_time - if (l_cfg_rcd_protection_time == l_max_cfg_rcd_protection_time) - { - FAPI_ERR("Injected RCD parity error detected too late for RCD retry to be effective, max_cfg_rcd_protection_time=%d, port%d, dimm%d, %s", - l_max_cfg_rcd_protection_time, l_port, l_dimm, i_target.toEcmdString()); - - - //Read mbacalfir for FFDC - l_rc = fapiGetScom(i_target, MBA01_MBACALFIR_0x03010400, l_mbacalfir); - if(l_rc) return l_rc; - - // Get DIMM targets for this MBA - l_rc = fapiGetAssociatedDimms(i_target, l_target_dimm_array); - if (l_rc) - { - FAPI_ERR("Failed to get associated DIMMs on %s.",i_target.toEcmdString()); - return l_rc; - } - - // Find DIMM target for this l_port and l_dimm - for (l_dimm_index = 0; l_dimm_index < l_target_dimm_array.size(); l_dimm_index ++) - { - l_rc = FAPI_ATTR_GET(ATTR_MBA_PORT, &l_target_dimm_array[l_dimm_index], l_target_port); - if (l_rc) - { - FAPI_ERR("Failed to get ATTR_MBA_PORT on %s.",i_target.toEcmdString()); - return l_rc; - } - - l_rc = FAPI_ATTR_GET(ATTR_MBA_DIMM, &l_target_dimm_array[l_dimm_index], l_target_dimm); - if (l_rc) - { - FAPI_ERR("Failed to get ATTR_MBA_DIMM on %s.",i_target.toEcmdString()); - return l_rc; - } - - if ((l_target_port == l_port) && (l_target_dimm == l_dimm)) - { - break; // Break out of for loop since we found the DIMM target for this l_port and l_dimm - } - } - - - // Calling out DIMM high, deconfig, gard - const fapi::Target & DIMM = l_target_dimm_array[l_dimm_index]; - // Calling out MBA target low, deconfig, gard - const fapi::Target & MBA = i_target; - // FFDC: PORT select: 0,1 - uint8_t PORT_SELECT = l_port; - // FFDC: DIMM select: 0,1 - uint8_t DIMM_SELECT = l_dimm; - // FFDC: MBS has to be told about RCD parity error before cfg_wrdone_dly so it knows to retry writes - uint8_t CFG_WRDONE_DLY = l_cfg_wrdone_dly; - // FFDC: MBS has to be told about RCD parity error before cfg_rdtag_dly so it knows to retry reads - uint8_t CFG_RDTAG_DLY = l_cfg_rdtag_dly; - // FFDC: Injected RCD parity error not detected within detected max_cfg_rcd_protection_time, so RCD retry not effective - uint8_t MAX_CFG_RCD_PROTECTION_TIME = l_max_cfg_rcd_protection_time; - // FFDC: Capture register with the RCD retry settings - ecmdDataBufferBase & MBA_FARB0 = l_mba_farb0; - // FFDC: Capture MBACALFIR to see if at least the MBA detected the injected RCD parity error - ecmdDataBufferBase & MBACALFIR = l_mbacalfir; - // Create new log - FAPI_SET_HWP_ERROR(l_rc, RC_MSS_DRAMINIT_MC_INSUF_RCD_PROTECT_TIME); - // 'Commit' the log so we can keep running - fapiLogError(l_rc); - - break; // Exit do-while loop and move on to another DIMM - } - - // Else increment cfg_rcd_protection_time and try again - else - { - l_cfg_rcd_protection_time++; - } - } - } - while (1); - - }// End if valid DIMM - }// End for each DIMM select - }// End for each port - - - //------------------------------------------------------ - // Clear MBECCFIR bit 45 - //------------------------------------------------------ - l_ecmd_rc |= l_mbeccfir_and.flushTo1(); - // Clear bit 45 in the AND mask - l_ecmd_rc |= l_mbeccfir_and.clearBit(45); - if(l_ecmd_rc) - { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - // Write AND mask - l_rc = fapiPutScom(l_targetCentaur, l_mbeccfir_and_address[l_mbaPosition], l_mbeccfir_and); - if(l_rc) return l_rc; - - - //------------------------------------------------------ - // Clear MBACALFIR bits 4,7: port0,1 RCD parity error - //------------------------------------------------------ - l_ecmd_rc |= l_mbacalfir_and.flushTo1(); - // Clear bit 4,7 in the AND mask - l_ecmd_rc |= l_mbacalfir_and.clearBit(4); - l_ecmd_rc |= l_mbacalfir_and.clearBit(7); - if(l_ecmd_rc) - { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - // Write AND mask - l_rc = fapiPutScom(i_target, MBA01_MBACALFIR_AND_0x03010401, l_mbacalfir_and); - if(l_rc) return l_rc; - - - //------------------------------------------------------ - // Unmask MBACALFIR bits 4,7: port0,1 RCD parity error - //------------------------------------------------------ - l_ecmd_rc |= l_mbacalfir_mask_and.flushTo1(); - // Set bit 4,7 in the AND mask - l_ecmd_rc |= l_mbacalfir_mask_and.clearBit(4); - l_ecmd_rc |= l_mbacalfir_mask_and.clearBit(7); - if(l_ecmd_rc) - { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - // Write AND mask - l_rc = fapiPutScom(i_target, MBA01_MBACALFIR_MASK_AND_0x03010404, l_mbacalfir_mask_and); - if(l_rc) return l_rc; - - - //------------------------------------------------------ - // Load l_highest_cfg_rcd_protection_time - //------------------------------------------------------ - // NOTE: We are loading highest_cfg_rcd_protection_time here just so we can stop after mss_draminit_mc and read out the values from the hw as a way to debug - // NOTE: The final value we want to load is max_cfg_rcd_protection_time, which we will do in mss_thermal_init, before we enable RCD recovery. - // NOTE: If no DIMM on this MBA passed, highest_cfg_rcd_protection_time will be 0 - - // Read FARB0 - l_rc = fapiGetScom(i_target, MBA01_MBA_FARB0Q_0x03010413, l_mba_farb0); - if(l_rc) return l_rc; - // Set highest_cfg_rcd_protection_time - l_ecmd_rc |= l_mba_farb0.insert( l_highest_cfg_rcd_protection_time, 48, 6, 8-6 ); - if(l_ecmd_rc) - { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - // Write FARB0 - l_rc = fapiPutScom(i_target, MBA01_MBA_FARB0Q_0x03010413, l_mba_farb0); - if(l_rc) return l_rc; - - - } // End if RDIMM or LRDIMM - - - - FAPI_INF("+++ mss_check_RCD_protect_time complete +++"); - return l_rc; -} - - -ReturnCode mss_spare_cke_disable (Target& i_target) -{ - - //Target MBA - //Selects address data from the mainline - //Variables - ReturnCode rc; - uint32_t rc_num = 0; - ecmdDataBufferBase spare_cke_data_buffer_64(64); - - //Setup SPARE CKE enable bit - rc = fapiGetScom(i_target, MBA01_MBARPC0Q_0x03010434, spare_cke_data_buffer_64); - if(rc) return rc; - rc_num = rc_num | spare_cke_data_buffer_64.clearBit(42); - if(rc_num) - { - rc.setEcmdError(rc_num); - return rc; - } - - rc = fapiPutScom(i_target, MBA01_MBARPC0Q_0x03010434, spare_cke_data_buffer_64); - if(rc) return rc; - - - FAPI_INF("+++ mss_spare_cke_disable complete +++"); - return rc; -} - -ReturnCode mss_enable_addr_inversion (Target& i_target) -{ - - //Target MBA - //Sets address inversion on port 1 of an MBA - //Variables - ReturnCode rc; - uint32_t rc_num = 0; - ecmdDataBufferBase MBA_FARB0_DB_64(64); - - //Set bit 56 for adr inversion on port 1 - rc = fapiGetScom(i_target, MBA01_MBA_FARB0Q_0x03010413, MBA_FARB0_DB_64); - if(rc) return rc; - rc_num = rc_num | MBA_FARB0_DB_64.setBit(56); - if(rc_num) - { - rc.setEcmdError(rc_num); - return rc; - } - - rc = fapiPutScom(i_target, MBA01_MBA_FARB0Q_0x03010413, MBA_FARB0_DB_64); - if(rc) return rc; - - - FAPI_INF("+++ mss_enable_addr_inversion complete +++"); - return rc; -} - - - -} //end extern C - diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.H b/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.H deleted file mode 100644 index f772beb7d..000000000 --- a/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.H +++ /dev/null @@ -1,58 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* COPYRIGHT International Business Machines Corp. 2012,2014 */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: mss_draminit_mc.H,v 1.5 2012/07/17 13:22:39 bellows Exp $ -//------------------------------------------------------------------------------ -// Don't forget to create CVS comments when you check in your changes! -//------------------------------------------------------------------------------ -// CHANGE HISTORY: -//------------------------------------------------------------------------------ -// Version:| Date: | Author: | Comment: -//---------|----------|----------|----------------------------------------------- -// 1.5 | 07/16/12 | bellows | added in Id tag -// 1.4 | 03/07/12 | jdsloat | changed target to centaur -// 1.3 | 02/17/12 | jdsloat | Added the other & -// 1.1 | 02/02/12 | jdsloat | Added & and description of target type -// 1.0 | 12/08/11 | dcadiga | First draft. - -#ifndef mss_draminit_mc_H_ -#define mss_draminit_mc_H_ -#include <fapi.H> - -typedef fapi::ReturnCode (*mss_draminit_mc_FP_t)(const fapi::Target& target); - -extern "C" -{ - -/** - * @brief Draminit MC procedure. Enable MC functions and set IML complete within centaur - * - * @param[in] i_target Reference to centaur target - * - * @return ReturnCode - */ - -fapi::ReturnCode mss_draminit_mc(const fapi::Target& target); - -} // extern "C" - -#endif // mss_draminit_mc_H_ diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_access_delay_reg.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_access_delay_reg.C deleted file mode 100644 index d5c18550e..000000000 --- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_access_delay_reg.C +++ /dev/null @@ -1,4430 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_access_delay_reg.C $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2012,2014 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: mss_access_delay_reg.C,v 1.25 2014/04/18 19:23:36 jdsloat Exp $ -//------------------------------------------------------------------------------ -// *! (C) Copyright International Business Machines Corp. 2011 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -//------------------------------------------------------------------------------ -// *! TITLE : mss_access_delay_reg -// *! OWNER NAME : Saurabh Chadha Email: sauchadh@in.ibm.com -// *! ADDITIONAL COMMENTS : -// -// The purpose of this procedure is to give different phase rototor values like RD_DQ, RD_DQS, WR_DQ, WR_DQS -//------------------------------------------------------------------------------ -// CHANGE HISTORY: -//------------------------------------------------------------------------------ -// Version:| Author: | Date: | Comment: -//---------|----------|---------|----------------------------------------------- -// 1.1 | sauchadh |15-Oct-12| First Draft. -// 1.2 | sauchadh |29-Oct-12| Fixed Firmware comments -// 1.3 | sauchadh |29-Oct-12| Fixed error due to rc_num -// 1.4 | sauchadh |29-Oct-12| Fixed error due to rc -// 1.5 | sauchadh |6-Nov-12 | Added RAW modes -// 1.6 | sauchadh |20-Nov-12| Made index to follow ISDIMM net for DQS and added glacier 2 suppport -// 1.7 | sauchadh |30-Nov-12| Glacier 1 and 2 selected based on init file settings -// 1.8 | sauchadh |5-Dec-12 | Fixed firmware comments and added DQS align DQS gate -// 1.9 | sauchadh |14-Dec-12| Fixed Firmware comments -// 1.10 | sauchadh |14-Dec-12| Fixed Firmware comments -// 1.11 | sauchadh |18-Dec-12| Fixed Frimware comments and removed print statements in between -// 1.12 | sauchadh |18-Dec-12| Added support for unused DQS in x8 mode -// 1.13 | sauchadh |7-Jan-12 | Added DQSCLK and RDCLK in phase select register -// 1.14 | sauchadh |8-Jan-12 | Fixed Firmware comments -// 1.15 | sauchadh |20-may-13| Fixed swizzle issue in DQSCLK phase rotators -// 1.16 | sauchadh |12-jun-13| ADDED CAC registers for read dqs -// 1.17 | sauchadh |18-Jul-13| Added data bit disable registers -// 1.19 | abhijsau |9-Oct-13 | Added mss_c4_phy() function -// 1.21 | abhijsau |16-Dec-13| Added function for fw -// 1.22 |sauchadh |10-Jan-14| changed dimmtype attribute to ATTR_EFF_CUSTOM_DIMM -// 1.23 | mjjones |17-Jan-14| Fixed layout and error handling for RAS Review -// 1.24 |sauchadh |24-Jan-14| Added check for unused DQS -// 1.25 |sauchadh |18-Apr-14| SW257010: mss_c4_phy: initialized dqs_lane array and verbose flag, used array indexes rather than counter - -//---------------------------------------------------------------------- -// My Includes -//---------------------------------------------------------------------- -#include <mss_access_delay_reg.H> - -//---------------------------------------------------------------------- -// Includes -//---------------------------------------------------------------------- -#include <fapi.H> - -extern "C" { - -//****************************************************************************** -//Function name: mss_access_delay_reg() -//Description:This function Read and Write delay values for RD_DQ, WR_DQ, RD_DQS, WR_DQS -//RD_DQ - Read Delay (DQ) registers -//WR_DQ - Write delay (DQ) registers -//RD_DQS - DQS_CLK_ALIGN -//WR_DQS - Write delay (DQS)registers -//Input : Target MBA=i_target_mba, i_access_type_e = READ or WRITE, i_port_u8=0 or 1, i_rank_u8=valid ranks,i_input_type_e=RD_DQ or RD_DQS or WR_DQ or WR_DQS or RAW_modes, i_input_index_u8=follow ISDIMMnet/C4 for non raw modes and supports raw modes, i_verbose-extra print statements -//Output : delay value=io_value_u32 if i_access_type_e = READ else if i_access_type_e = WRITE no return value -//****************************************************************************** -fapi::ReturnCode mss_access_delay_reg(const fapi::Target & i_target_mba, - access_type_t i_access_type_e, - uint8_t i_port_u8, - uint8_t i_rank_u8, - input_type_t i_input_type_e, - uint8_t i_input_index_u8, - uint8_t i_verbose, - uint32_t &io_value_u32) -{ - // Reference variables for Error FFDC - const fapi::Target & MBA_TARGET = i_target_mba; - const access_type_t & ACCESS_TYPE_PARAM = i_access_type_e; - const uint8_t & PORT_PARAM = i_port_u8; - const uint8_t & RANK_PARAM = i_rank_u8; - const input_type_t & TYPE_PARAM = i_input_type_e; - const uint8_t & INDEX_PARAM = i_input_index_u8; - - fapi::ReturnCode rc; - - const uint8_t max_rp=8; - uint8_t l_val=0; - uint8_t l_dram_width=0; - scom_location l_out; - uint64_t l_scom_add=0x0ull; - uint32_t l_sbit=0; - uint32_t l_len=0; - uint32_t rc_num=0; - ecmdDataBufferBase data_buffer_64(64); - ecmdDataBufferBase out(16); - uint32_t l_output=0; - uint32_t l_start=0; - uint8_t l_rank_pair=9; - uint8_t l_rankpair_table[max_rp]={255}; - uint8_t l_dimmtype=0; - uint8_t l_block=0; - uint8_t l_lane=0; - uint8_t l_start_bit=0; - uint8_t l_len8=0; - input_type l_type; - uint8_t l_mbapos=0; - const uint8_t l_ISDIMM_dqmax=71; - const uint8_t l_CDIMM_dqmax=79; - uint8_t l_adr=0; - const uint8_t addr_max=19; - const uint8_t cmd_max=3; - const uint8_t cnt_max=20; - const uint8_t clk_max=8; - const uint8_t addr_lanep0[addr_max]={1,5,3,7,10,6,4,10,13,12,9,9,0,0,6,4,1,4,8}; - const uint8_t addr_adrp0[addr_max]={2,1,1,3,1,3,1,3,3,3,2,3,2,3,1,0,3,3,3}; - const uint8_t addr_lanep1[addr_max]={7,10,3,6,8,12,6,1,5,8,2,0,13,4,5,9,6,11,9}; - const uint8_t addr_adrp1[addr_max]={2,1,2,2,1,3,1,1,1,3,1,3,2,3,3,0,0,1,3}; - const uint8_t addr_lanep2[addr_max]={8,0,7,1,12,10,1,5,9,5,13,5,4,2,4,9,10,9,0}; - const uint8_t addr_adrp2[addr_max]={2,2,3,0,3,1,2,0,1,3,2,1,0,2,3,3,3,2,1}; - const uint8_t addr_lanep3[addr_max]={6,2,9,9,2,3,4,10,0,5,1,5,4,1,8,11,5,12,1}; - const uint8_t addr_adrp3[addr_max]={3,0,2,3,2,0,3,3,1,2,2,1,0,1,3,3,0,3,0}; - - const uint8_t cmd_lanep0[cmd_max]={2,11,5}; - const uint8_t cmd_adrp0[cmd_max]={3,1,3}; - const uint8_t cmd_lanep1[cmd_max]={2,10,10}; - const uint8_t cmd_adrp1[cmd_max]={2,3,2}; - const uint8_t cmd_lanep2[cmd_max]={3,11,3}; - const uint8_t cmd_adrp2[cmd_max]={1,3,0}; - const uint8_t cmd_lanep3[cmd_max]={7,10,7}; - const uint8_t cmd_adrp3[cmd_max]={1,1,3}; - - const uint8_t cnt_lanep0[cnt_max]={0,7,3,1,7,8,8,3,8,6,7,2,2,0,9,1,3,6,9,2}; - const uint8_t cnt_adrp0[cnt_max]={1,0,3,0,2,2,1,2,0,0,1,2,0,0,1,1,0,2,0,1}; - const uint8_t cnt_lanep1[cnt_max]={5,4,0,5,11,9,10,7,1,11,0,4,12,3,6,8,1,4,7,7}; - const uint8_t cnt_adrp1[cnt_max]={2,1,2,0,2,1,0,1,3,0,1,0,2,1,3,0,2,2,3,0}; - const uint8_t cnt_lanep2[cnt_max]={0,4,7,13,11,5,12,2,3,6,11,6,7,1,10,8,8,2,4,1}; - const uint8_t cnt_adrp2[cnt_max]={0,1,1,3,1,2,2,0,2,2,0,1,2,1,0,3,1,1,2,3}; - const uint8_t cnt_lanep3[cnt_max]={0,11,9,8,4,7,0,3,8,6,13,8,7,0,6,6,1,2,9,5}; - const uint8_t cnt_adrp3[cnt_max]={2,1,0,2,1,0,3,2,0,1,3,1,2,0,0,2,3,1,1,3}; - - const uint8_t clk_lanep0[clk_max]={10,11,11,10,4,5,13,12}; - const uint8_t clk_adrp0[clk_max]={0,0,2,2,2,2,2,2}; - const uint8_t clk_lanep1[clk_max]={3,2,8,9,1,0,3,2}; - const uint8_t clk_adrp1[clk_max]={3,3,2,2,0,0,0,0}; - const uint8_t clk_lanep2[clk_max]={11,10,6,7,2,3,8,9}; - const uint8_t clk_adrp2[clk_max]={2,2,0,0,3,3,0,0}; - const uint8_t clk_lanep3[clk_max]={3,2,13,12,10,11,11,10}; - const uint8_t clk_adrp3[clk_max]={3,3,2,2,0,0,2,2}; - - - rc = mss_getrankpair(i_target_mba,i_port_u8,i_rank_u8,&l_rank_pair,l_rankpair_table); if(rc) return rc; - - rc = FAPI_ATTR_GET(ATTR_EFF_CUSTOM_DIMM, &i_target_mba, l_dimmtype); if(rc) return rc; - - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target_mba, l_dram_width); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target_mba, l_mbapos); if(rc) return rc; - - if(i_verbose==1) - { - FAPI_INF("dimm type=%d",l_dimmtype); - FAPI_INF("rank pair=%d",l_rank_pair); - } - if(i_port_u8 >1) - { - FAPI_ERR("Wrong port specified (%d)", i_port_u8); - FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_INVALID_INPUT); - return rc; - } - - if (l_mbapos>1) - { - FAPI_ERR("Bad position from ATTR_CHIP_UNIT_POS (%d)", l_mbapos); - const uint8_t & MBA_POS = l_mbapos; - FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_BAD_MBA_POS); - return rc; - } - - if((l_dram_width ==fapi::ENUM_ATTR_EFF_DRAM_WIDTH_X4) || (l_dram_width ==fapi::ENUM_ATTR_EFF_DRAM_WIDTH_X8)) // Checking for dram width here so that checking can be skipped in called function - { - if(i_verbose==1) - { - FAPI_INF("dram width=%d",l_dram_width); - } - } - else - { - FAPI_ERR("Bad dram width from ATTR_EFF_DRAM_WIDTH (%d)", l_dram_width); - const uint8_t & DRAM_WIDTH = l_dram_width; - FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_BAD_DRAM_WIDTH); - return rc; - } - - if(i_input_type_e==RD_DQ || i_input_type_e==WR_DQ) - { - if(l_dimmtype==fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES) - { - l_type=CDIMM_DQ; - - if(i_input_index_u8>l_CDIMM_dqmax) - { - FAPI_ERR("CDIMM_DQ: Wrong input index specified (%d, max %d)" , - i_input_index_u8, l_CDIMM_dqmax); - FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_INVALID_INPUT); - return rc; - } - } - else - { - l_type=ISDIMM_DQ; - if(i_input_index_u8>l_ISDIMM_dqmax) - { - FAPI_ERR("ISDIMM_DQ: Wrong input index specified (%d, max %d)", - i_input_index_u8, l_ISDIMM_dqmax); - FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_INVALID_INPUT); - return rc; - } - } - - rc=rosetta_map(i_target_mba,i_port_u8,l_type,i_input_index_u8,i_verbose,l_val); if(rc) return rc; - - if(i_verbose==1) - { - FAPI_INF("C4 value is=%d",l_val); - } - rc=cross_coupled(i_target_mba,i_port_u8,l_rank_pair,i_input_type_e,l_val,i_verbose,l_out); if(rc) return rc; - if(i_verbose==1) - { - FAPI_INF("scom_address=%llX",l_out.scom_addr); - FAPI_INF("start bit=%d",l_out.start_bit); - FAPI_INF("length=%d",l_out.bit_length); - } - l_scom_add=l_out.scom_addr; - l_sbit=l_out.start_bit; - l_len=l_out.bit_length; - - } - - else if(i_input_type_e==ADDRESS) - { - if(i_input_index_u8<=18) // 19 delay values for Address - { - if((i_port_u8==0) && (l_mbapos==0)) - { - l_lane=addr_lanep0[i_input_index_u8]; - l_adr=addr_adrp0[i_input_index_u8]; - } - else if((i_port_u8==1) && (l_mbapos==0)) - { - l_lane=addr_lanep1[i_input_index_u8]; - l_adr=addr_adrp1[i_input_index_u8]; - } - else if((i_port_u8==0) && (l_mbapos==1)) - { - l_lane=addr_lanep2[i_input_index_u8]; - l_adr=addr_adrp2[i_input_index_u8]; - } - else - { - l_lane=addr_lanep3[i_input_index_u8]; - l_adr=addr_adrp3[i_input_index_u8]; - } - - } - - else - { - FAPI_ERR("Wrong input index specified (%d)", i_input_index_u8); - FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_INVALID_INPUT); - return rc; - } - - ip_type_t l_input=ADDRESS_t; - if(i_verbose==1) - { - FAPI_INF("ADR=%d",l_adr); - FAPI_INF("lane=%d",l_lane); - } - l_block=l_adr; - rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc; - l_sbit=l_start_bit; - l_len=l_len8; - if(i_verbose==1) - { - FAPI_INF("scom_address=%llX",l_scom_add); - FAPI_INF("start bit=%d",l_start_bit); - FAPI_INF("length=%d",l_len8); - } - } - - else if(i_input_type_e==DATA_DISABLE) - { - if(i_input_index_u8<=4) // 5 delay values for data bits disable register - { - l_block=i_input_index_u8; - } - else - { - FAPI_ERR("Wrong input index specified (%d)", i_input_index_u8); - FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_INVALID_INPUT); - return rc; - } - - ip_type_t l_input=DATA_DISABLE_t; - if(i_verbose==1) - { - FAPI_INF("block=%d",l_block); - } - l_lane=0; - rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc; - l_sbit=l_start_bit; - l_len=l_len8; - if(i_verbose==1) - { - FAPI_INF("scom_address=%llX",l_scom_add); - FAPI_INF("start bit=%d",l_start_bit); - FAPI_INF("length=%d",l_len8); - } - } - - - else if(i_input_type_e==COMMAND) - { - if(i_input_index_u8<=2) // 3 delay values for Command - { - if((i_port_u8==0) && (l_mbapos==0)) - { - l_lane=cmd_lanep0[i_input_index_u8]; - l_adr=cmd_adrp0[i_input_index_u8]; - } - else if((i_port_u8==1) && (l_mbapos==0)) - { - l_lane=cmd_lanep1[i_input_index_u8]; - l_adr=cmd_adrp1[i_input_index_u8]; - } - else if((i_port_u8==0) && (l_mbapos==1)) - { - l_lane=cmd_lanep2[i_input_index_u8]; - l_adr=cmd_adrp2[i_input_index_u8]; - } - else - { - l_lane=cmd_lanep3[i_input_index_u8]; - l_adr=cmd_adrp3[i_input_index_u8]; - } - - } - - else - { - FAPI_ERR("Wrong input index specified (%d)", i_input_index_u8); - FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_INVALID_INPUT); - return rc; - } - - ip_type_t l_input=COMMAND_t; - if(i_verbose==1) - { - FAPI_INF("ADR=%d",l_adr); - FAPI_INF("lane=%d",l_lane); - } - l_block=l_adr; - rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc; - l_sbit=l_start_bit; - l_len=l_len8; - if(i_verbose==1) - { - FAPI_INF("scom_address=%llX",l_scom_add); - FAPI_INF("start bit=%d",l_start_bit); - FAPI_INF("length=%d",l_len8); - } - } - - else if(i_input_type_e==CONTROL) - { - if(i_input_index_u8<=19) // 20 delay values for Control - { - if((i_port_u8==0) && (l_mbapos==0)) - { - l_lane=cnt_lanep0[i_input_index_u8]; - l_adr=cnt_adrp0[i_input_index_u8]; - } - else if((i_port_u8==1) && (l_mbapos==0)) - { - l_lane=cnt_lanep1[i_input_index_u8]; - l_adr=cnt_adrp1[i_input_index_u8]; - } - else if((i_port_u8==0) && (l_mbapos==1)) - { - l_lane=cnt_lanep2[i_input_index_u8]; - l_adr=cnt_adrp2[i_input_index_u8]; - } - else - { - l_lane=cnt_lanep3[i_input_index_u8]; - l_adr=cnt_adrp3[i_input_index_u8]; - } - - } - - else - { - FAPI_ERR("Wrong input index specified (%d)", i_input_index_u8); - FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_INVALID_INPUT); - return rc; - } - - ip_type_t l_input=CONTROL_t; - if(i_verbose==1) - { - FAPI_INF("ADR=%d",l_adr); - FAPI_INF("lane=%d",l_lane); - } - l_block=l_adr; - rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc; - l_sbit=l_start_bit; - l_len=l_len8; - if(i_verbose==1) - { - FAPI_INF("scom_address=%llX",l_scom_add); - FAPI_INF("start bit=%d",l_start_bit); - FAPI_INF("length=%d",l_len8); - } - } - - else if(i_input_type_e==CLOCK) - { - if(i_input_index_u8<=7) // 8 delay values for CLK - { - if((i_port_u8==0) && (l_mbapos==0)) - { - l_lane=clk_lanep0[i_input_index_u8]; - l_adr=clk_adrp0[i_input_index_u8]; - } - else if((i_port_u8==1) && (l_mbapos==0)) - { - l_lane=clk_lanep1[i_input_index_u8]; - l_adr=clk_adrp1[i_input_index_u8]; - } - else if((i_port_u8==0) && (l_mbapos==1)) - { - l_lane=clk_lanep2[i_input_index_u8]; - l_adr=clk_adrp2[i_input_index_u8]; - } - else - { - l_lane=clk_lanep3[i_input_index_u8]; - l_adr=clk_adrp3[i_input_index_u8]; - } - - } - - else - { - FAPI_ERR("Wrong input index specified (%d)", i_input_index_u8); - FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_INVALID_INPUT); - return rc; - } - - ip_type_t l_input=CLOCK_t; - if(i_verbose==1) - { - FAPI_INF("ADR=%d",l_adr); - FAPI_INF("lane=%d",l_lane); - } - l_block=l_adr; - rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc; - l_sbit=l_start_bit; - l_len=l_len8; - if(i_verbose==1) - { - FAPI_INF("scom_address=%llX",l_scom_add); - FAPI_INF("start bit=%d",l_start_bit); - FAPI_INF("length=%d",l_len8); - } - } - - - else if (i_input_type_e==RD_DQS || i_input_type_e==WR_DQS || i_input_type_e==DQS_ALIGN || i_input_type_e==DQS_GATE || i_input_type_e==RDCLK || i_input_type_e==DQSCLK) - { - - if(l_dimmtype==fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES) - { - l_type=CDIMM_DQS; - } - else - { - l_type=ISDIMM_DQS; - } - - rc=rosetta_map(i_target_mba,i_port_u8,l_type,i_input_index_u8,i_verbose,l_val); if(rc) return rc; - if(i_verbose==1) - { - FAPI_INF("C4 value is=%d",l_val); - } - rc=cross_coupled(i_target_mba,i_port_u8,l_rank_pair,i_input_type_e,l_val,i_verbose,l_out); if(rc) return rc; - if(i_verbose==1) - { - FAPI_INF("scom_address=%llX",l_out.scom_addr); - FAPI_INF("start bit=%d",l_out.start_bit); - FAPI_INF("length=%d",l_out.bit_length); - } - l_scom_add=l_out.scom_addr; - l_sbit=l_out.start_bit; - l_len=l_out.bit_length; - - } - - - else if(i_input_type_e==RAW_RDCLK_0 || i_input_type_e==RAW_RDCLK_1 || i_input_type_e==RAW_RDCLK_2 || i_input_type_e==RAW_RDCLK_3 || i_input_type_e==RAW_RDCLK_4) - { - if(i_input_type_e==RAW_RDCLK_0) - { - l_block=0; - } - - else if(i_input_type_e==RAW_RDCLK_1) - { - l_block=1; - } - - else if(i_input_type_e==RAW_RDCLK_2) - { - l_block=2; - } - - else if(i_input_type_e==RAW_RDCLK_3) - { - l_block=3; - } - - else - { - l_block=4; - } - if(i_input_index_u8<=3) // 4 delay values for RDCLK - { - l_lane=i_input_index_u8; - } - - else - { - FAPI_ERR("Wrong input index specified (%d)", i_input_index_u8); - FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_INVALID_INPUT); - return rc; - } - - ip_type_t l_input=RAW_RDCLK; - if(i_verbose==1) - { - FAPI_INF("block=%d",l_block); - } - rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc; - l_sbit=l_start_bit; - l_len=l_len8; - if(i_verbose==1) - { - FAPI_INF("scom_address=%llX",l_scom_add); - FAPI_INF("start bit=%d",l_start_bit); - FAPI_INF("length=%d",l_len8); - } - } - - else if(i_input_type_e==RAW_DQSCLK_0 || i_input_type_e==RAW_DQSCLK_1 || i_input_type_e==RAW_DQSCLK_2 || i_input_type_e==RAW_DQSCLK_3 || i_input_type_e==RAW_DQSCLK_4) - { - if(i_input_type_e==RAW_DQSCLK_0) - { - l_block=0; - } - - else if(i_input_type_e==RAW_DQSCLK_1) - { - l_block=1; - } - - else if(i_input_type_e==RAW_DQSCLK_2) - { - l_block=2; - } - - else if(i_input_type_e==RAW_DQSCLK_3) - { - l_block=3; - } - - else - { - l_block=4; - } - if(i_input_index_u8<=3) // 4 delay values for DQSCLK - { - l_lane=i_input_index_u8; - } - - else - { - FAPI_ERR("Wrong input index specified (%d)", i_input_index_u8); - FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_INVALID_INPUT); - return rc; - } - ip_type_t l_input=RAW_DQSCLK; - if(i_verbose==1) - { - FAPI_INF("block=%d",l_block); - } - rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc; - l_sbit=l_start_bit; - l_len=l_len8; - if(i_verbose==1) - { - FAPI_INF("scom_address=%llX",l_scom_add); - FAPI_INF("start bit=%d",l_start_bit); - FAPI_INF("length=%d",l_len8); - } - } - - - else if(i_input_type_e==RAW_WR_DQ_0 || i_input_type_e==RAW_WR_DQ_1 || i_input_type_e==RAW_WR_DQ_2 || i_input_type_e==RAW_WR_DQ_3 || i_input_type_e==RAW_WR_DQ_4) - { - if(i_input_type_e==RAW_WR_DQ_0) - { - l_block=0; - } - else if(i_input_type_e==RAW_WR_DQ_1) - { - l_block=1; - } - else if(i_input_type_e==RAW_WR_DQ_2) - { - l_block=2; - } - else if(i_input_type_e==RAW_WR_DQ_3) - { - l_block=3; - } - else - { - l_block=4; - } - if(i_input_index_u8<=15) // 16 Write delay values for DQ bits - { - l_lane=i_input_index_u8; - } - - else - { - FAPI_ERR("Wrong input index specified (%d)", i_input_index_u8); - FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_INVALID_INPUT); - return rc; - } - - ip_type_t l_input=RAW_WR_DQ; - if(i_verbose==1) - { - FAPI_INF("block=%d",l_block); - FAPI_INF("lane=%d",l_lane); - } - rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc; - l_sbit=l_start_bit; - l_len=l_len8; - if(i_verbose==1) - { - FAPI_INF("scom_address=%llX",l_scom_add); - FAPI_INF("start bit=%d",l_start_bit); - FAPI_INF("length=%d",l_len8); - } - } - - else if(i_input_type_e==RAW_RD_DQ_0 || i_input_type_e==RAW_RD_DQ_1 || i_input_type_e==RAW_RD_DQ_2 || i_input_type_e==RAW_RD_DQ_3 || i_input_type_e==RAW_RD_DQ_4) - { - if(i_input_type_e==RAW_RD_DQ_0) - { - l_block=0; - } - else if(i_input_type_e==RAW_RD_DQ_1) - { - l_block=1; - } - else if(i_input_type_e==RAW_RD_DQ_2) - { - l_block=2; - } - else if(i_input_type_e==RAW_RD_DQ_3) - { - l_block=3; - } - else - { - l_block=4; - } - if(i_input_index_u8<=15) // 16 read delay values for DQ bits - { - l_lane=i_input_index_u8; - } - else - { - FAPI_ERR("Wrong input index specified (%d)", i_input_index_u8); - FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_INVALID_INPUT); - return rc; - } - ip_type_t l_input=RAW_RD_DQ; - if(i_verbose==1) - { - FAPI_INF("block=%d",l_block); - FAPI_INF("lane=%d",l_lane); - } - rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc; - l_sbit=l_start_bit; - l_len=l_len8; - if(i_verbose==1) - { - FAPI_INF("scom_address=%llX",l_scom_add); - FAPI_INF("start bit=%d",l_start_bit); - FAPI_INF("length=%d",l_len8); - } - } - - else if(i_input_type_e==RAW_RD_DQS_0 || i_input_type_e==RAW_RD_DQS_1 || i_input_type_e==RAW_RD_DQS_2 || i_input_type_e==RAW_RD_DQS_3 || i_input_type_e==RAW_RD_DQS_4) - { - if(i_input_type_e==RAW_RD_DQS_0) - { - l_block=0; - } - else if(i_input_type_e==RAW_RD_DQS_1) - { - l_block=1; - } - else if(i_input_type_e==RAW_RD_DQS_2) - { - l_block=2; - } - else if(i_input_type_e==RAW_RD_DQS_3) - { - l_block=3; - } - else - { - l_block=4; - } - if(i_input_index_u8<=3) // 4 Read DQS delay values - { - l_lane=i_input_index_u8; - } - else - { - FAPI_ERR("Wrong input index specified (%d)", i_input_index_u8); - FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_INVALID_INPUT); - return rc; - } - - ip_type_t l_input=RAW_RD_DQS; - if(i_verbose==1) - { - FAPI_INF("block=%d",l_block); - FAPI_INF("lane=%d",l_lane); - } - rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc; - l_sbit=l_start_bit; - l_len=l_len8; - if(i_verbose==1) - { - FAPI_INF("scom_address=%llX",l_scom_add); - FAPI_INF("start bit=%d",l_start_bit); - FAPI_INF("length=%d",l_len8); - } - } - - else if(i_input_type_e==RAW_DQS_ALIGN_0 || i_input_type_e==RAW_DQS_ALIGN_1 || i_input_type_e==RAW_DQS_ALIGN_2 || i_input_type_e==RAW_DQS_ALIGN_3 || i_input_type_e==RAW_DQS_ALIGN_4) - { - if(i_input_type_e==RAW_DQS_ALIGN_0) - { - l_block=0; - } - else if(i_input_type_e==RAW_DQS_ALIGN_1) - { - l_block=1; - } - else if(i_input_type_e==RAW_DQS_ALIGN_2) - { - l_block=2; - } - else if(i_input_type_e==RAW_DQS_ALIGN_3) - { - l_block=3; - } - else - { - l_block=4; - } - if(i_input_index_u8<=3) // 4 DQS alignment delay values - { - l_lane=i_input_index_u8; - } - else - { - FAPI_ERR("Wrong input index specified (%d)", i_input_index_u8); - FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_INVALID_INPUT); - return rc; - } - ip_type_t l_input=RAW_DQS_ALIGN; - if(i_verbose==1) - { - FAPI_INF("block=%d",l_block); - FAPI_INF("lane=%d",l_lane); - } - rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc; - l_sbit=l_start_bit; - l_len=l_len8; - if(i_verbose==1) - { - FAPI_INF("scom_address=%llX",l_scom_add); - FAPI_INF("start bit=%d",l_start_bit); - FAPI_INF("length=%d",l_len8); - } - } - - - else if(i_input_type_e==RAW_WR_DQS_0 || i_input_type_e==RAW_WR_DQS_1 || i_input_type_e==RAW_WR_DQS_2 || i_input_type_e==RAW_WR_DQS_3 || i_input_type_e==RAW_WR_DQS_4) - { - if(i_input_type_e==RAW_WR_DQS_0) - { - l_block=0; - } - else if(i_input_type_e==RAW_WR_DQS_1) - { - l_block=1; - } - else if(i_input_type_e==RAW_WR_DQS_2) - { - l_block=2; - } - else if(i_input_type_e==RAW_WR_DQS_3) - { - l_block=3; - } - else - { - l_block=4; - } - if(i_input_index_u8<=3) // 4 Write DQS delay values - { - l_lane=i_input_index_u8; - } - else - { - FAPI_ERR("Wrong input index specified (%d)", i_input_index_u8); - FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_INVALID_INPUT); - return rc; - } - ip_type_t l_input=RAW_WR_DQS; - if(i_verbose==1) - { - FAPI_INF("block=%d",l_block); - FAPI_INF("lane=%d",l_lane); - } - rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc; - l_sbit=l_start_bit; - l_len=l_len8; - if(i_verbose==1) - { - FAPI_INF("scom_address=%llX",l_scom_add); - FAPI_INF("start bit=%d",l_start_bit); - FAPI_INF("length=%d",l_len8); - } - } - else if(i_input_type_e==RAW_SYS_CLK_0 || i_input_type_e==RAW_SYS_CLK_1 || i_input_type_e==RAW_SYS_CLK_2 || i_input_type_e==RAW_SYS_CLK_3 || i_input_type_e==RAW_SYS_CLK_4) - { - if(i_input_type_e==RAW_SYS_CLK_0) - { - l_block=0; - } - else if(i_input_type_e==RAW_SYS_CLK_1) - { - l_block=1; - } - else if(i_input_type_e==RAW_SYS_CLK_2) - { - l_block=2; - } - else if(i_input_type_e==RAW_SYS_CLK_3) - { - l_block=3; - } - else - { - l_block=4; - } - if(i_input_index_u8==0) // 1 system clock delay value - { - l_lane=i_input_index_u8; - } - else - { - FAPI_ERR("Wrong input index specified (%d)", i_input_index_u8); - FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_INVALID_INPUT); - return rc; - } - ip_type_t l_input=RAW_SYS_CLK; - if(i_verbose==1) - { - FAPI_INF("block=%d",l_block); - FAPI_INF("lane=%d",l_lane); - } - rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc; - l_sbit=l_start_bit; - l_len=l_len8; - if(i_verbose==1) - { - FAPI_INF("scom_address=%llX",l_scom_add); - FAPI_INF("start bit=%d",l_start_bit); - FAPI_INF("length=%d",l_len8); - } - } - - else if(i_input_type_e==RAW_SYS_ADDR_CLK) - { - if(i_input_index_u8<=1) // 1 system address clock delay value - { - l_lane=i_input_index_u8; - } - else - { - FAPI_ERR("Wrong input index specified (%d)", i_input_index_u8); - FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_INVALID_INPUT); - return rc; - } - ip_type_t l_input=RAW_SYS_ADDR_CLKS0S1; - if(i_verbose==1) - { - FAPI_INF("lane=%d",l_lane); - } - rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc; - l_sbit=l_start_bit; - l_len=l_len8; - if(i_verbose==1) - { - FAPI_INF("scom_address=%llX",l_scom_add); - FAPI_INF("start bit=%d",l_start_bit); - FAPI_INF("length=%d",l_len8); - } - } - - - else if(i_input_type_e==RAW_WR_CLK_0 || i_input_type_e==RAW_WR_CLK_1 || i_input_type_e==RAW_WR_CLK_2 || i_input_type_e==RAW_WR_CLK_3 || i_input_type_e==RAW_WR_CLK_4) - { - if(i_input_type_e==RAW_WR_CLK_0) - { - l_block=0; - } - else if(i_input_type_e==RAW_WR_CLK_1) - { - l_block=1; - } - else if(i_input_type_e==RAW_WR_CLK_2) - { - l_block=2; - } - else if(i_input_type_e==RAW_WR_CLK_3) - { - l_block=3; - } - else - { - l_block=4; - } - if(i_input_index_u8==0) // 1 Write clock delay value - { - l_lane=i_input_index_u8; - } - else - { - FAPI_ERR("Wrong input index specified (%d)", i_input_index_u8); - FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_INVALID_INPUT); - return rc; - } - ip_type_t l_input=RAW_WR_CLK; - if(i_verbose==1) - { - FAPI_INF("block=%d",l_block); - FAPI_INF("lane=%d",l_lane); - } - rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc; - l_sbit=l_start_bit; - l_len=l_len8; - if(i_verbose==1) - { - FAPI_INF("scom_address=%llX",l_scom_add); - FAPI_INF("start bit=%d",l_start_bit); - FAPI_INF("length=%d",l_len8); - } - } - - else if(i_input_type_e==RAW_ADDR_0 || i_input_type_e==RAW_ADDR_1 || i_input_type_e==RAW_ADDR_2 || i_input_type_e==RAW_ADDR_3) - { - if(i_input_type_e==RAW_ADDR_0) - { - l_block=0; - } - else if(i_input_type_e==RAW_ADDR_1) - { - l_block=1; - } - else if(i_input_type_e==RAW_ADDR_2) - { - l_block=2; - } - else - { - l_block=3; - } - if(i_input_index_u8<=15) // 16 Addr delay values - { - l_lane=i_input_index_u8; - } - else - { - FAPI_ERR("Wrong input index specified (%d)", i_input_index_u8); - FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_INVALID_INPUT); - return rc; - } - ip_type_t l_input=RAW_ADDR; - if(i_verbose==1) - { - FAPI_INF("block=%d",l_block); - FAPI_INF("lane=%d",l_lane); - } - rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc; - l_sbit=l_start_bit; - l_len=l_len8; - if(i_verbose==1) - { - FAPI_INF("scom_address=%llX",l_scom_add); - FAPI_INF("start bit=%d",l_start_bit); - FAPI_INF("length=%d",l_len8); - } - } - - else if(i_input_type_e==RAW_DQS_GATE_0 || i_input_type_e==RAW_DQS_GATE_1 || i_input_type_e==RAW_DQS_GATE_2 || i_input_type_e==RAW_DQS_GATE_3 || i_input_type_e==RAW_DQS_GATE_4) - { - if(i_input_type_e==RAW_DQS_GATE_0) - { - l_block=0; - } - else if(i_input_type_e==RAW_DQS_GATE_1) - { - l_block=1; - } - else if(i_input_type_e==RAW_DQS_GATE_2) - { - l_block=2; - } - else if(i_input_type_e==RAW_DQS_GATE_3) - { - l_block=3; - } - else - { - l_block=4; - } - - if(i_input_index_u8<=3) // 4 Gate Delay values - { - l_lane=i_input_index_u8; - } - else - { - FAPI_ERR("Wrong input index specified (%d)", i_input_index_u8); - FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_INVALID_INPUT); - return rc; - } - ip_type_t l_input=RAW_DQS_GATE; - if(i_verbose==1) - { - FAPI_INF("block=%d",l_block); - FAPI_INF("lane=%d",l_lane); - } - rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc; - l_sbit=l_start_bit; - l_len=l_len8; - if(i_verbose==1) - { - FAPI_INF("scom_address=%llX",l_scom_add); - FAPI_INF("start bit=%d",l_start_bit); - FAPI_INF("length=%d",l_len8); - } - } - - else - { - FAPI_ERR("Wrong input type specified (%d)", i_input_type_e); - FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_INVALID_INPUT); - return rc; - } - - if(i_access_type_e==READ) - { - rc=fapiGetScom(i_target_mba,l_scom_add,data_buffer_64);if(rc) return rc; - rc_num= rc_num | data_buffer_64.extractToRight(&l_output,l_sbit,l_len); - if(rc_num) - { - FAPI_ERR( "ecmd error on l_scom_add extract"); - rc.setEcmdError(rc_num); - return rc; - } - io_value_u32=l_output; - // FAPI_INF("Delay value=%d",io_value_u32); - } - - else if(i_access_type_e==WRITE) - { - - if(i_input_type_e==RD_DQ || i_input_type_e==RD_DQS || i_input_type_e==RAW_RD_DQ_0 || i_input_type_e==RAW_RD_DQ_1 || i_input_type_e==RAW_RD_DQ_2 || i_input_type_e==RAW_RD_DQ_3 || i_input_type_e==RAW_RD_DQ_4 || i_input_type_e==RAW_RD_DQS_0 || i_input_type_e==RAW_RD_DQS_1 || i_input_type_e==RAW_RD_DQS_2 || i_input_type_e==RAW_RD_DQS_3 || i_input_type_e==RAW_RD_DQS_4 - || i_input_type_e==RAW_SYS_ADDR_CLK || i_input_type_e==RAW_SYS_CLK_0 || i_input_type_e==RAW_SYS_CLK_1 || i_input_type_e==RAW_SYS_CLK_2 || i_input_type_e==RAW_SYS_CLK_3 || i_input_type_e==RAW_SYS_CLK_4 || i_input_type_e==RAW_WR_CLK_0 || i_input_type_e==RAW_WR_CLK_1 || i_input_type_e==RAW_WR_CLK_2 || i_input_type_e==RAW_WR_CLK_3 || i_input_type_e==RAW_WR_CLK_4 - || i_input_type_e==RAW_ADDR_0 || i_input_type_e==RAW_ADDR_1 || i_input_type_e==RAW_ADDR_2 || i_input_type_e==RAW_ADDR_3 || i_input_type_e==RAW_DQS_ALIGN_0 || i_input_type_e==RAW_DQS_ALIGN_1 || i_input_type_e==RAW_DQS_ALIGN_2 || i_input_type_e==RAW_DQS_ALIGN_3 || i_input_type_e==RAW_DQS_ALIGN_4 - || i_input_type_e==DQS_ALIGN || i_input_type_e==COMMAND || i_input_type_e==ADDRESS || i_input_type_e==CONTROL || i_input_type_e==CLOCK ) - { - l_start=25; // l_start is starting bit of delay value in the register. There are different registers and each register has a different field for delay - } - else if(i_input_type_e==WR_DQ || i_input_type_e==WR_DQS || i_input_type_e==RAW_WR_DQ_0 || i_input_type_e==RAW_WR_DQ_1 || i_input_type_e==RAW_WR_DQ_2 || i_input_type_e==RAW_WR_DQ_3 || i_input_type_e==RAW_WR_DQ_4 || i_input_type_e==RAW_WR_DQS_0 || i_input_type_e==RAW_WR_DQS_1 || i_input_type_e==RAW_WR_DQS_2 || i_input_type_e==RAW_WR_DQS_3 || i_input_type_e==RAW_WR_DQS_4 ) - { - l_start=22; - } - - else if(i_input_type_e==RAW_DQS_GATE_0 || i_input_type_e==RAW_DQS_GATE_1 || i_input_type_e==RAW_DQS_GATE_2 || i_input_type_e==RAW_DQS_GATE_3 || i_input_type_e==RAW_DQS_GATE_4 || i_input_type_e==DQS_GATE) - { - l_start=29; - } - - else if(i_input_type_e==RAW_RDCLK_0 || i_input_type_e==RAW_RDCLK_1 || i_input_type_e==RAW_RDCLK_2 || i_input_type_e==RAW_RDCLK_3 || i_input_type_e==RAW_RDCLK_4 || i_input_type_e==RDCLK || i_input_type_e==RAW_DQSCLK_0 || i_input_type_e==RAW_DQSCLK_1 || i_input_type_e==RAW_DQSCLK_2 || i_input_type_e==RAW_DQSCLK_3 || i_input_type_e==RAW_DQSCLK_4 || i_input_type_e==DQSCLK) - { - l_start=30; - } - - else if(i_input_type_e==DATA_DISABLE) - { - l_start=16; - } - - else - { - FAPI_ERR("Wrong input type specified (%d)", i_input_type_e); - FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_INVALID_INPUT); - return rc; - } - if(i_verbose==1) - { - FAPI_INF("value given=%d",io_value_u32); - } - - rc=fapiGetScom(i_target_mba,l_scom_add,data_buffer_64);if(rc) return rc; - rc_num=data_buffer_64.insert(io_value_u32,l_sbit,l_len,l_start); - if(rc_num) - { - FAPI_ERR( "ecmd error on l_scom_add extract"); - rc.setEcmdError(rc_num); - return rc; - } - rc=fapiPutScom(i_target_mba,l_scom_add,data_buffer_64); if(rc) return rc; - } - return rc; -} - -//****************************************************************************** -//Function name: cross_coupled() -//Description:This function returns address,start bit and bit length for RD_DQ, WR_DQ, RD_DQS, WR_DQS -//Input : Target MBA=i_target_mba, i_port_u8=0 or 1, i_rank_pair=0 or 1 or 2 or 3, i_input_type_e=RD_DQ or RD_DQS or WR_DQ or WR_DQS,i_input_index_u8=0-79/0-71/0-8/0-19 , i_verbose-extra print statements -//Output : out (address,start bit and bit length) -//****************************************************************************** -fapi::ReturnCode cross_coupled(const fapi::Target & i_target_mba, - uint8_t i_port, - uint8_t i_rank_pair, - input_type_t i_input_type_e, - uint8_t i_input_index, - uint8_t i_verbose, - scom_location& out) -{ - fapi::ReturnCode rc; - const uint8_t l_dqmax=80; - const uint8_t l_dqsmax=20; - const uint8_t l_dqs=4; - const uint8_t lane_dq_p0[l_dqmax]={4,6,5,7,2,1,3,0,13,15,12,14,8,9,11,10,13,15,12,14,9,8,11,10,13,15,12,14,11,9,10,8,11,8,9,10,12,13,14,15,7,6,5,4,1,3,2,0,5,6,4,7,3,1,2,0,7,4,5,6,2,0,3,1,3,0,1,2,6,5,4,7,11,8,9,10,15,13,12,14}; - const uint8_t lane_dq_p1[l_dqmax]={9,11,8,10,13,14,15,12,10,8,11,9,12,13,14,15,1,0,2,3,4,5,6,7,9,11,10,8,15,12,13,14,5,7,6,4,1,0,2,3,0,2,1,3,5,4,6,7,0,2,3,1,4,5,6,7,12,15,13,14,11,8,10,9,5,7,4,6,3,2,0,1,14,12,15,13,9,8,11,10}; - const uint8_t lane_dq_p2[l_dqmax]={13,15,12,14,11,9,10,8,13,12,14,15,10,9,11,8,5,6,7,4,2,3,0,1,10,9,8,11,13,12,15,14,15,12,13,14,11,10,9,8,7,6,4,5,1,0,3,2,0,2,1,3,5,6,4,7,5,7,6,4,1,0,2,3,1,2,3,0,7,6,5,4,9,10,8,11,12,15,14,13}; - const uint8_t lane_dq_p3[l_dqmax]={4,5,6,7,0,1,3,2,12,13,15,14,8,9,10,11,10,8,11,9,12,13,15,14,3,0,1,2,4,6,7,5,9,10,11,8,14,13,15,12,7,5,6,4,3,1,2,0,5,6,7,4,1,2,3,0,14,12,15,13,8,10,9,11,0,3,2,1,6,5,7,4,10,11,9,8,12,13,15,14}; - const uint8_t dqs_dq_lane_p0[l_dqsmax]={4,0,12,8,12,8,12,8,8,12,4,0,4,0,4,0,0,4,8,12}; - const uint8_t dqs_dq_lane_p1[l_dqsmax]={8,12,8,12,0,4,8,12,4,0,0,4,0,4,12,8,4,0,12,8}; - const uint8_t dqs_dq_lane_p2[l_dqsmax]={12,8,12,8,4,0,8,12,12,8,4,0,0,4,4,0,0,4,8,12}; - const uint8_t dqs_dq_lane_p3[l_dqsmax]={4,0,12,8,8,12,0,4,8,12,4,0,4,0,12,8,0,4,8,12}; - const uint8_t block_p1[l_dqmax]={0,0,0,0,0,0,0,0,3,3,3,3,3,3,3,3,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,2,2,2,2,2,2,2,2,3,3,3,3,3,3,3,3,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,1,1,1,1,1,1,1,1,2,2,2,2,2,2,2,2}; - const uint8_t block_p0[l_dqmax]={2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,0,0,0,0,0,0,0,0,3,3,3,3,3,3,3,3,4,4,4,4,4,4,4,4,3,3,3,3,3,3,3,3,4,4,4,4,4,4,4,4,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1}; - const uint8_t block_p2[l_dqmax]={1,1,1,1,1,1,1,1,3,3,3,3,3,3,3,3,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,3,3,3,3,3,3,3,3,4,4,4,4,4,4,4,4,1,1,1,1,1,1,1,1,4,4,4,4,4,4,4,4}; - const uint8_t block_p3[l_dqmax]={2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1}; - const uint8_t block_dqs_p0[l_dqsmax]={2,2,2,2,0,0,3,3,4,4,3,3,4,4,1,1,0,0,1,1}; - const uint8_t block_dqs_p1[l_dqsmax]={0,0,3,3,0,0,1,1,2,2,3,3,4,4,4,4,1,1,2,2}; - const uint8_t block_dqs_p2[l_dqsmax]={1,1,3,3,0,0,0,0,2,2,2,2,3,3,4,4,1,1,4,4}; - const uint8_t block_dqs_p3[l_dqsmax]={2,2,2,2,0,0,0,0,3,3,3,3,4,4,4,4,1,1,1,1}; - const uint8_t dqslane[l_dqs]={16,18,20,22}; - uint8_t l_j=0; - uint8_t l_flag=0; - uint8_t l_mbapos = 0; - uint8_t l_dram_width=0; - uint8_t l_lane=0; - const uint8_t & INVALID_DQS =l_lane; - uint8_t l_block=0; - uint8_t lane_dqs[4]; - uint8_t l_index=0; - uint8_t l_dq=0; - uint64_t l_scom_address_64=0x0ull; - uint8_t l_start_bit=0; - uint8_t l_len=0; - ip_type_t l_input_type; - ecmdDataBufferBase data_buffer_64(64); - uint8_t l_dimmtype=0; - uint8_t l_swizzle=0; - - rc = FAPI_ATTR_GET(ATTR_MSS_DQS_SWIZZLE_TYPE, &i_target_mba, l_swizzle); if(rc) return rc; - - rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target_mba, l_mbapos); if(rc) return rc; - - rc = FAPI_ATTR_GET(ATTR_EFF_CUSTOM_DIMM, &i_target_mba, l_dimmtype); if(rc) return rc; - - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target_mba, l_dram_width); if(rc) return rc; - - - if(i_input_type_e==RD_DQ || i_input_type_e==WR_DQ) - { - if(i_port==0 && l_mbapos==0) - { - l_lane=lane_dq_p0[i_input_index]; - l_block=block_p0[i_input_index]; - } - else if(i_port==1 && l_mbapos==0) - { - l_lane=lane_dq_p1[i_input_index]; - l_block=block_p1[i_input_index]; - } - else if(i_port==0 && l_mbapos==1) - { - l_lane=lane_dq_p2[i_input_index]; - l_block=block_p2[i_input_index]; - } - else - { - l_lane=lane_dq_p3[i_input_index]; - l_block=block_p3[i_input_index]; - } - - if(i_verbose==1) - { - FAPI_INF("block=%d",l_block); - FAPI_INF("lane=%d",l_lane); - } - if(i_input_type_e==RD_DQ) - { - l_input_type=RD_DQ_t; - } - else - { - l_input_type=WR_DQ_t; - } - - - rc=get_address(i_target_mba,i_port,i_rank_pair,l_input_type,l_block,l_lane,l_scom_address_64,l_start_bit,l_len); if(rc) return rc; - out.scom_addr=l_scom_address_64; - out.start_bit=l_start_bit; - out.bit_length=l_len; - } - - else if (i_input_type_e==WR_DQS || i_input_type_e==DQS_ALIGN) - { - if(i_port==0 && l_mbapos==0) - { - l_dq=dqs_dq_lane_p0[i_input_index]; - l_block=block_dqs_p0[i_input_index]; - } - - else if(i_port==1 && l_mbapos==0) - { - l_dq=dqs_dq_lane_p1[i_input_index]; - l_block=block_dqs_p1[i_input_index]; - } - else if(i_port==0 && l_mbapos==1) - { - l_dq=dqs_dq_lane_p2[i_input_index]; - l_block=block_dqs_p2[i_input_index]; - } - else - { - l_dq=dqs_dq_lane_p3[i_input_index]; - l_block=block_dqs_p3[i_input_index]; - } - - if(i_verbose==1) - { - FAPI_INF("block=%d",l_block); - FAPI_INF("dqs_dq_lane=%d",l_dq); - } - l_input_type=RD_CLK_t; - rc=get_address(i_target_mba,i_port,i_rank_pair, l_input_type,l_block,l_lane,l_scom_address_64,l_start_bit,l_len); if(rc) return rc; - if(i_verbose==1) - { - FAPI_INF("read clock address=%llx",l_scom_address_64); - } - rc=fapiGetScom(i_target_mba,l_scom_address_64,data_buffer_64);if(rc) return rc; - - if(l_dram_width==fapi::ENUM_ATTR_EFF_DRAM_WIDTH_X4) - { - - if (data_buffer_64.isBitSet(48)) - { - lane_dqs[l_index]=16; - l_index++; - } - else if(data_buffer_64.isBitSet(52)) - { - lane_dqs[l_index]=18; - l_index++; - } - - if (data_buffer_64.isBitSet(49)) - { - lane_dqs[l_index]=16; - l_index++; - } - - else if (data_buffer_64.isBitSet(53)) - { - lane_dqs[l_index]=18; - l_index++; - } - - if (data_buffer_64.isBitSet(54)) - { - lane_dqs[l_index]=20; - l_index++; - } - else if (data_buffer_64.isBitSet(56)) - { - lane_dqs[l_index]=22; - l_index++; - } - - if (data_buffer_64.isBitSet(55)) - { - lane_dqs[l_index]=20; - l_index++; - } - else if (data_buffer_64.isBitSet(57)) // else is not possible as one of them will definitely get set - { - lane_dqs[l_index]=22; - l_index++; - } - if(i_verbose==1) - { - FAPI_INF("array is=%d and %d and %d and %d",lane_dqs[0],lane_dqs[1],lane_dqs[2],lane_dqs[3]); - } - if(l_dq==0) - { - l_lane=lane_dqs[0]; - } - else if(l_dq==4) - { - l_lane=lane_dqs[1]; - } - else if(l_dq==8) - { - l_lane=lane_dqs[2]; - } - else - { - l_lane=lane_dqs[3]; - } - - if(i_verbose==1) - { - FAPI_INF("lane is=%d",l_lane); - } - } - - - else - { - if (data_buffer_64.isBitSet(48)&& data_buffer_64.isBitSet(49)) - { - lane_dqs[l_index]=16; - l_index++; - } - else if (data_buffer_64.isBitSet(52)&& data_buffer_64.isBitSet(53)) - { - lane_dqs[l_index]=18; - l_index++; - } - if (data_buffer_64.isBitSet(54)&& data_buffer_64.isBitSet(55)) - { - lane_dqs[l_index]=20; - l_index++; - } - else if (data_buffer_64.isBitSet(56)&& data_buffer_64.isBitSet(57)) // else is not possible as one of them will definitely get set - { - lane_dqs[l_index]=22; - l_index++; - } - if(i_verbose==1) - { - FAPI_INF("array is=%d and %d",lane_dqs[0],lane_dqs[1]); - } - if((l_dq==0) || (l_dq==4)) - { - l_lane=lane_dqs[0]; - } - else - { - l_lane=lane_dqs[1]; - } - - if(l_dimmtype==fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES) - { - if((i_input_index==1) || (i_input_index==3) || (i_input_index==5) || (i_input_index==7) || (i_input_index==9) || (i_input_index==11) || (i_input_index==13) || (i_input_index==15) || (i_input_index==17) || (i_input_index==19)) - { - if(l_lane==16) - { - l_lane=18; - } - else if(l_lane==18) - { - l_lane=16; - } - - else if(l_lane==20) - { - l_lane=22; - } - - else - { - l_lane=20; - } - - } - } - - else - { - if((i_port==0) && (l_mbapos==0)) - { - if(l_swizzle==1) - { - if((i_input_index==3) || (i_input_index==1) || (i_input_index==4) || (i_input_index==17)|| (i_input_index==9) || (i_input_index==11) || (i_input_index==13) || (i_input_index==15) || (i_input_index==6)) - { - if(l_lane==16) - { - l_lane=18; - } - else if(l_lane==18) - { - l_lane=16; - } - - else if(l_lane==20) - { - l_lane=22; - } - - else - { - l_lane=20; - } - - } - } - - else - { - if((i_input_index==3) || (i_input_index==1) || (i_input_index==5) || (i_input_index==7)|| (i_input_index==9) || (i_input_index==11) || (i_input_index==13) || (i_input_index==15) || (i_input_index==17)) - { - if(l_lane==16) - { - l_lane=18; - } - else if(l_lane==18) - { - l_lane=16; - } - - else if(l_lane==20) - { - l_lane=22; - } - - else - { - l_lane=20; - } - } - - } - } - - else if((i_port==1) && (l_mbapos==0)) - { - if(l_swizzle==1) - { - if((i_input_index==2) || (i_input_index==0) || (i_input_index==4) || (i_input_index==17)|| (i_input_index==9) || (i_input_index==11) || (i_input_index==13) || (i_input_index==15) || (i_input_index==7)) - { - if(l_lane==16) - { - l_lane=18; - } - else if(l_lane==18) - { - l_lane=16; - } - - else if(l_lane==20) - { - l_lane=22; - } - - else - { - l_lane=20; - } - } - } - - else - { - if((i_input_index==1) || (i_input_index==3) || (i_input_index==5) || (i_input_index==7)|| (i_input_index==9) || (i_input_index==11) || (i_input_index==13) || (i_input_index==15) || (i_input_index==17)) - { - if(l_lane==16) - { - l_lane=18; - } - else if(l_lane==18) - { - l_lane=16; - } - - else if(l_lane==20) - { - l_lane=22; - } - - else - { - l_lane=20; - } - } - } - } - - - else - { - if((i_input_index==1) || (i_input_index==3) || (i_input_index==5) || (i_input_index==7)|| (i_input_index==9) || (i_input_index==11) || (i_input_index==13) || (i_input_index==15) || (i_input_index==17)) - { - if(l_lane==16) - { - l_lane=18; - } - else if(l_lane==18) - { - l_lane=16; - } - - else if(l_lane==20) - { - l_lane=22; - } - - else - { - l_lane=20; - } - - } - } - - - - } - if(i_verbose==1) - { - FAPI_INF("lane is=%d",l_lane); - } - } - - if(i_input_type_e==WR_DQS) - { - l_input_type=WR_DQS_t; - } - else - { - l_input_type=DQS_ALIGN_t; - } - - - for(l_j=0;l_j<4;l_j++) - { - if(l_lane==dqslane[l_j]) - { - l_flag=1; - break; - } - - } - if(l_flag==0) - { - FAPI_ERR("Invalid DQS and DQS lane=%d",l_lane); - FAPI_SET_HWP_ERROR(rc, RC_CROSS_COUPLED_INVALID_DQS); - return rc; - } - - - rc=get_address(i_target_mba,i_port,i_rank_pair,l_input_type,l_block,l_lane,l_scom_address_64,l_start_bit,l_len); if(rc) return rc; - out.scom_addr=l_scom_address_64; - out.start_bit=l_start_bit; - out.bit_length=l_len; - } - - - else if (i_input_type_e==RD_DQS || i_input_type_e==DQS_GATE || i_input_type_e==RDCLK || i_input_type_e==DQSCLK) - { - - - if(i_port==0 && l_mbapos==0) - { - l_dq=dqs_dq_lane_p0[i_input_index]; - l_block=block_dqs_p0[i_input_index]; - } - - else if(i_port==1 && l_mbapos==0) - { - l_dq=dqs_dq_lane_p1[i_input_index]; - l_block=block_dqs_p1[i_input_index]; - } - else if(i_port==0 && l_mbapos==1) - { - l_dq=dqs_dq_lane_p2[i_input_index]; - l_block=block_dqs_p2[i_input_index]; - } - else - { - l_dq=dqs_dq_lane_p3[i_input_index]; - l_block=block_dqs_p3[i_input_index]; - } - - if(i_verbose==1) - { - FAPI_INF("block=%d",l_block); - FAPI_INF("dqs_dq_lane=%d",l_dq); - } - if(l_dq==0) - { - l_lane=16; - } - - else if(l_dq==4) - { - l_lane=18; - } - - else if (l_dq==8) - { - l_lane=20; - } - - else - { - l_lane=22; - } - //FAPI_INF("here"); - - if (i_input_type_e==DQS_GATE) - { - l_input_type=DQS_GATE_t; - } - - else if(i_input_type_e==RDCLK) - { - l_input_type=RDCLK_t; - } - - else if(i_input_type_e==RD_DQS) - { - l_input_type=RD_DQS_t; - } - - else - { - l_input_type=DQSCLK_t; - } - - if(i_verbose==1) - { - FAPI_INF("lane is=%d",l_lane); - } - - rc=get_address(i_target_mba,i_port,i_rank_pair,l_input_type,l_block,l_lane,l_scom_address_64,l_start_bit,l_len); if(rc) return rc; - out.scom_addr=l_scom_address_64; - out.start_bit=l_start_bit; - out.bit_length=l_len; - } - - else - { - FAPI_ERR("Wrong input type specified (%d)", i_input_type_e); - const input_type_t & TYPE_PARAM = i_input_type_e; - FAPI_SET_HWP_ERROR(rc, RC_CROSS_COUPLED_INVALID_INPUT); - return rc; - } - - return rc; -} - - -//****************************************************************************** -//Function name: rosetta_map() -//Description:This function returns C4 bit for the corresponding ISDIMM bit -//Input : Target MBA=i_target_mba, i_port_u8=0 or 1,i_input_type_e=RD_DQ or RD_DQS or WR_DQ or WR_DQS, i_input_index_u8=0-79/0-71/0-8/0-19, i_verbose-extra print statements -//Output : C4 bit=o_value -//****************************************************************************** -fapi::ReturnCode rosetta_map(const fapi::Target & i_target_mba, - uint8_t i_port, - input_type i_input_type_e, - uint8_t i_input_index, - uint8_t i_verbose, - uint8_t &o_value) //This function is used by some other procedures -{ // Boundary check is done again - // Reference variables for Error FFDC - const fapi::Target & MBA_TARGET = i_target_mba; - const uint8_t & PORT_PARAM = i_port; - const input_type & TYPE_PARAM = i_input_type_e; - const uint8_t & INDEX_PARAM = i_input_index; - - fapi::ReturnCode rc; - - const uint8_t l_ISDIMM_dqmax=71; - const uint8_t l_CDIMM_dqmax=79; - uint8_t l_mbapos = 0; - uint8_t l_dimmtype=0; - const uint8_t l_maxdq=72; - const uint8_t l_maxdqs=18; - uint8_t l_swizzle=0; - const uint8_t GL_DQ_p0_g1[l_maxdq]={10,9,11,8,12,13,14,15,3,1,2,0,7,5,4,6,20,21,22,23,16,17,18,19,64,65,66,67,71,70,69,68,32,33,34,35,36,37,38,39,42,40,43,41,44,46,45,47,48,51,50,49,52,53,54,55,58,56,57,59,60,61,62,63,31,28,29,30,25,27,26,24}; - const uint8_t GL_DQ_p0_g2[l_maxdq]={10,9,11,8,12,13,14,15,3,1,2,0,7,5,4,6,16,17,18,19,20,21,22,23,64,65,66,67,71,70,69,68,32,33,34,35,36,37,38,39,42,40,43,41,44,46,45,47,48,51,50,49,52,53,54,55,58,56,57,59,60,61,62,63,25,27,26,24,28,31,29,30}; - const uint8_t GL_DQ_p1_g1[l_maxdq]={15,13,12,14,9,8,10,11,5,7,4,6,3,2,1,0,20,22,21,23,16,17,18,19,70,71,69,68,67,66,65,64,32,35,34,33,38,37,39,36,40,41,42,43,44,45,46,47,49,50,48,51,52,53,54,55,59,57,56,58,60,62,61,63,27,26,25,24,31,30,28,29}; - const uint8_t GL_DQ_p1_g2[l_maxdq]={8,9,10,11,12,13,14,15,3,2,1,0,4,5,6,7,16,17,18,19,20,21,22,23,67,66,64,65,70,71,69,68,32,35,34,33,38,37,39,36,40,41,42,43,44,45,46,47,49,50,48,51,52,53,54,55,59,57,56,58,60,62,61,63,27,26,25,24,31,30,28,29}; - const uint8_t GL_DQ_p2[l_maxdq]={9,11,10,8,12,15,13,14,0,1,3,2,5,4,7,6,19,17,16,18,20,22,21,23,66,67,65,64,71,70,69,68,32,33,34,35,36,37,38,39,41,40,43,42,45,44,47,46,48,49,50,51,52,53,54,55,58,56,57,59,60,61,62,63,25,27,24,26,28,31,29,30}; - const uint8_t GL_DQ_p3[l_maxdq]={3,2,0,1,4,5,6,7,11,10,8,9,15,14,12,13,16,17,18,19,20,21,22,23,64,65,66,67,68,69,70,71,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,24,25,26,27,28,29,30,31}; - - const uint8_t GL_DQS_p0_g1[l_maxdqs]={2,0,5,16,8,10,12,14,7,3,1,4,17,9,11,13,15,6}; - const uint8_t GL_DQS_p0_g2[l_maxdqs]={2,0,4,16,8,10,12,14,6,3,1,5,17,9,11,13,15,7}; - const uint8_t GL_DQS_p1_g1[l_maxdqs]={3,1,5,16,8,10,12,14,6,2,0,4,17,9,11,13,15,7}; - const uint8_t GL_DQS_p1_g2[l_maxdqs]={2,0,4,16,8,10,12,14,6,3,1,5,17,9,11,13,15,7}; - const uint8_t GL_DQS_p2[l_maxdqs]={2,0,4,16,8,10,12,14,6,3,1,5,17,9,11,13,15,7}; - const uint8_t GL_DQS_p3[l_maxdqs]={0,2,4,16,8,10,12,14,6,1,3,5,17,9,11,13,15,7}; - - rc = FAPI_ATTR_GET(ATTR_MSS_DQS_SWIZZLE_TYPE, &i_target_mba, l_swizzle); if(rc) return rc; - - - if(l_swizzle ==0 || l_swizzle ==1) - { - if(i_verbose==1) - { - FAPI_INF("swizzle type=%d",l_swizzle); - } - } - - else - { - FAPI_ERR("Wrong swizzle value (%d)", l_swizzle); - const uint8_t & SWIZZLE_TYPE = l_swizzle; - FAPI_SET_HWP_ERROR(rc, RC_ROSETTA_MAP_BAD_SWIZZLE_VALUE); - return rc; - } - - rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target_mba, l_mbapos); if(rc) return rc; - - if(i_port >1) - { - FAPI_ERR("Wrong port specified (%d)", i_port); - FAPI_SET_HWP_ERROR(rc, RC_ROSETTA_MAP_INVALID_INPUT); - return rc; - } - - if (l_mbapos>1) - { - FAPI_ERR("Bad position from ATTR_CHIP_UNIT_POS (%d)", l_mbapos); - const uint8_t & MBA_POS = l_mbapos; - FAPI_SET_HWP_ERROR(rc, RC_ROSETTA_MAP_BAD_MBA_POS); - return rc; - } - - rc = FAPI_ATTR_GET(ATTR_EFF_CUSTOM_DIMM, &i_target_mba, l_dimmtype); if(rc) return rc; - - if(l_dimmtype==fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES) - { - if(i_input_index>l_CDIMM_dqmax) - { - FAPI_SET_HWP_ERROR(rc, RC_ROSETTA_MAP_INVALID_INPUT); - FAPI_ERR("Wrong input index specified rc = 0x%08X" ,uint32_t(rc)); - return rc; - } - } - else - { - if(i_input_index>l_ISDIMM_dqmax) - { - FAPI_ERR("Wrong input index specified (%d)", i_input_index); - FAPI_SET_HWP_ERROR(rc, RC_ROSETTA_MAP_INVALID_INPUT); - return rc; - } - } - - if(i_input_type_e ==ISDIMM_DQ) - { - if(i_port==0 && l_mbapos==0) - { - if(l_swizzle==1) - { - o_value=GL_DQ_p0_g1[i_input_index]; - } - else - { - o_value=GL_DQ_p0_g2[i_input_index]; - } - - } - - else if(i_port==1 && l_mbapos==0) - { - if(l_swizzle==1) - { - o_value=GL_DQ_p1_g1[i_input_index]; - } - else - { - o_value=GL_DQ_p1_g2[i_input_index]; - } - } - - else if(i_port==0 && l_mbapos==1) - { - o_value=GL_DQ_p2[i_input_index]; - } - else - { - o_value=GL_DQ_p3[i_input_index]; - } - - } - - - else if(i_input_type_e ==ISDIMM_DQS) - { - - if(i_port==0 && l_mbapos==0) - { - if(l_swizzle==1) - { - o_value=GL_DQS_p0_g1[i_input_index]; - } - else - { - o_value=GL_DQS_p0_g2[i_input_index]; - } - - } - else if(i_port==1 && l_mbapos==0) - { - if(l_swizzle==1) - { - o_value=GL_DQS_p1_g1[i_input_index]; - } - else - { - o_value=GL_DQS_p1_g2[i_input_index]; - } - - } - else if(i_port==0 && l_mbapos==1) - { - o_value=GL_DQS_p2[i_input_index]; - } - else - { - o_value=GL_DQS_p3[i_input_index]; - } - - } - else if(i_input_type_e==CDIMM_DQS) - { - o_value=i_input_index; - } - - else if(i_input_type_e==CDIMM_DQ) - { - o_value=i_input_index; - } - - else - { - FAPI_ERR("Wrong input type specified (%d)", i_input_type_e); - FAPI_SET_HWP_ERROR(rc, RC_ROSETTA_MAP_INVALID_INPUT); - return rc; - } - - return rc; -} - -//****************************************************************************** -//Function name: get address() -//Description:This function returns address,start bit and bit length for RD_DQ, WR_DQ, RD_DQS, WR_DQS -//Input : Target MBA=i_target_mba, i_port_u8=0 or 1, i_rank_pair=0 or 1 or 2 or 3, i_input_type_e=RD_DQ or RD_DQS or WR_DQ or WR_DQS, i_block=0 or 1 or 2 or 3 or 4, i_lane=0-15 -//Output : scom address=o_scom_address_64, start bit=o_start_bit, bit length=o_len -//****************************************************************************** -fapi::ReturnCode get_address(const fapi::Target & i_target_mba, - uint8_t i_port, - uint8_t i_rank_pair, - ip_type_t i_input_type_e, - uint8_t i_block, - uint8_t i_lane, - uint64_t &o_scom_address_64, - uint8_t &o_start_bit, - uint8_t &o_len) -{ - fapi::ReturnCode rc; - - uint64_t l_scom_address_64 = 0x0ull; - uint64_t l_temp=0x0ull; - uint8_t l_mbapos; - uint8_t l_lane=0; - const uint64_t l_port01_st=0x8000000000000000ull; - const uint64_t l_port23_st=0x8001000000000000ull; - const uint64_t l_port01_adr_st=0x8000400000000000ull; - const uint64_t l_port23_adr_st=0x8001400000000000ull; - const uint32_t l_port01_en=0x0301143f; - const uint64_t l_rd_port01_en=0x040301143full; - const uint64_t l_sys_clk_en=0x730301143full; - const uint64_t l_wr_clk_en =0x740301143full; - const uint64_t l_adr02_st=0x8000400000000000ull; - const uint64_t l_adr13_st=0x8001400000000000ull; - const uint64_t l_dqs_gate_en=0x000000130301143full; - const uint64_t l_dqsclk_en=0x090301143full; - const uint64_t l_data_ds_en=0x7c0301143full; - uint8_t l_tmp=0; - rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target_mba, l_mbapos); if(rc) return rc; - - if(i_input_type_e==WR_DQ_t || i_input_type_e==RAW_WR_DQ) - { - if(i_lane > 7) - { - l_scom_address_64 = 0x00000040; - l_scom_address_64=l_scom_address_64<<32; - l_temp|=(i_lane-8); - } - - else - { - l_scom_address_64|=0x00000038; - l_scom_address_64=l_scom_address_64<<32; - l_temp|=i_lane; - } - l_temp|=(i_block*4)<<8; - l_temp|=i_rank_pair<<8; - l_temp=l_temp<<32; - if((i_port==0 && l_mbapos==0) || (i_port==0 && l_mbapos==1)) - { - l_scom_address_64|= l_port01_st | l_temp | l_port01_en; - } - else - { - l_scom_address_64|= l_port23_st | l_temp | l_port01_en; - } - - o_scom_address_64=l_scom_address_64; - o_start_bit=48; - o_len=10; - - } - - else if(i_input_type_e==RD_DQ_t || i_input_type_e==RAW_RD_DQ) - { - l_scom_address_64|=0x00000050; - l_scom_address_64=l_scom_address_64<<32; - l_lane=i_lane/2; - l_temp|=l_lane; - l_temp|=(i_block*4)<<8; - l_temp|=i_rank_pair<<8; - l_temp=l_temp<<32; - if((i_port==0 && l_mbapos==0) || (i_port==0 && l_mbapos==1)) - { - l_scom_address_64|= l_port01_st | l_temp | l_port01_en; - } - else - { - l_scom_address_64|= l_port23_st | l_temp | l_port01_en; - } - - if((i_lane % 2) == 0) - { - o_start_bit=48; - o_len=7; - } - else - { - o_start_bit=56; - o_len=7; - } - - - o_scom_address_64=l_scom_address_64; - - } - - else if(i_input_type_e==COMMAND_t || i_input_type_e==CLOCK_t || i_input_type_e==CONTROL_t || i_input_type_e==ADDRESS_t ) - { - l_tmp|=4; - l_lane=i_lane/2; - l_temp=l_lane+l_tmp; - l_temp|=(i_block*4)<<8; - l_temp=l_temp<<32; - if((i_port==0 && l_mbapos==0) || (i_port==0 && l_mbapos==1)) - { - l_scom_address_64|= l_port01_adr_st | l_temp | l_port01_en; - } - else - { - l_scom_address_64|= l_port23_adr_st | l_temp | l_port01_en; - } - - if((i_lane % 2) == 0) - { - o_start_bit=49; - o_len=7; - } - else - { - o_start_bit=57; - o_len=7; - } - - - o_scom_address_64=l_scom_address_64; - - } - - - else if(i_input_type_e==WR_DQS_t || i_input_type_e==RAW_WR_DQS) - { - - if(i_input_type_e==RAW_WR_DQS) - { - if(i_lane==0) - { - i_lane=16; - } - else if(i_lane==1) - { - i_lane=18; - } - else if(i_lane==2) - { - i_lane=20; - } - else - { - i_lane=22; - } - } - if(i_lane==16) - { - l_scom_address_64|=0x00000048; - } - else if(i_lane==18) - { - l_scom_address_64|=0x0000004a; - } - else if(i_lane==20) - { - l_scom_address_64|=0x0000004c; - } - else - { - l_scom_address_64|=0x0000004e; - } - - l_scom_address_64=l_scom_address_64<<32; - l_temp|=(i_block*4)<<8; - l_temp|=i_rank_pair<<8; - l_temp=l_temp<<32; - if((i_port==0 && l_mbapos==0) || (i_port==0 && l_mbapos==1)) - { - l_scom_address_64|= l_port01_st | l_temp | l_port01_en; - } - else - { - l_scom_address_64|= l_port23_st | l_temp | l_port01_en; - } - - o_start_bit=48; - o_len=10; - o_scom_address_64=l_scom_address_64; - - } - - else if(i_input_type_e==DATA_DISABLE_t) - { - l_temp|=(i_block*4)<<8; - l_temp|=i_rank_pair<<8; - l_temp=l_temp<<32; - if((i_port==0 && l_mbapos==0) || (i_port==0 && l_mbapos==1)) - { - l_scom_address_64|= l_port01_st | l_temp | l_data_ds_en; - } - else - { - l_scom_address_64|= l_port23_st | l_temp | l_data_ds_en; - } - - o_start_bit=48; - o_len=16; - o_scom_address_64=l_scom_address_64; - } - - else if(i_input_type_e==RD_CLK_t) - { - l_temp|=(i_block*4)<<8; - l_temp|=i_rank_pair<<8; - l_temp=l_temp<<32; - if((i_port==0 && l_mbapos==0) || (i_port==0 && l_mbapos==1)) - { - l_scom_address_64|= l_port01_st | l_temp| l_rd_port01_en; - } - else - { - l_scom_address_64|= l_port23_st | l_temp| l_rd_port01_en; - } - - - o_start_bit=0; - o_len=0; - o_scom_address_64=l_scom_address_64; - - } - - else if(i_input_type_e==RD_DQS_t || i_input_type_e==RAW_RD_DQS) - { - - if(i_input_type_e==RAW_RD_DQS) - { - if(i_lane==0) - { - i_lane=16; - } - else if(i_lane==1) - { - i_lane=18; - } - else if(i_lane==2) - { - i_lane=20; - } - else - { - i_lane=22; - } - } - if(i_lane==16) - { - l_scom_address_64|=0x00000030; - o_start_bit=49; - } - else if(i_lane==18) - { - l_scom_address_64|=0x00000030; - o_start_bit=57; - } - else if(i_lane==20) - { - l_scom_address_64|=0x00000031; - o_start_bit=49; - } - else - { - l_scom_address_64|=0x00000031; - o_start_bit=57; - } - - l_scom_address_64=l_scom_address_64<<32; - l_temp|=(i_block*4)<<8; - l_temp|=i_rank_pair<<8; - l_temp=l_temp<<32; - - if((i_port==0 && l_mbapos==0) || (i_port==0 && l_mbapos==1)) - { - l_scom_address_64|= l_port01_st | l_temp | l_port01_en; - } - else - { - l_scom_address_64|= l_port23_st | l_temp | l_port01_en; - } - - - o_len=7; - o_scom_address_64=l_scom_address_64; - - } - - else if(i_input_type_e==RDCLK_t || i_input_type_e==RAW_RDCLK) - { - if(i_input_type_e==RAW_RDCLK) - { - if(i_lane==0) - { - i_lane=16; - } - else if(i_lane==1) - { - i_lane=18; - } - else if(i_lane==2) - { - i_lane=20; - } - else - { - i_lane=22; - } - } - if(i_lane==16) - { - o_start_bit=50; - } - else if(i_lane==18) - { - o_start_bit=54; - } - else if(i_lane==20) - { - o_start_bit=58; - } - else - { - o_start_bit=62; - } - - l_temp|=(i_block*4)<<8; - l_temp|=i_rank_pair<<8; - l_temp=l_temp<<32; - - if((i_port==0 && l_mbapos==0) || (i_port==0 && l_mbapos==1)) - { - l_scom_address_64|= l_port01_st | l_temp | l_dqsclk_en; - } - else - { - l_scom_address_64|= l_port23_st | l_temp | l_dqsclk_en; - } - - o_len=2; - o_scom_address_64=l_scom_address_64; - - } - - else if(i_input_type_e==DQSCLK_t || i_input_type_e==RAW_DQSCLK) - { - if(i_input_type_e==RAW_DQSCLK) - { - if(i_lane==0) - { - i_lane=16; - } - else if(i_lane==1) - { - i_lane=18; - } - else if(i_lane==2) - { - i_lane=20; - } - else - { - i_lane=22; - } - } - - if(i_lane==16) - { - o_start_bit=48; - } - else if(i_lane==18) - { - o_start_bit=52; - } - else if(i_lane==20) - { - o_start_bit=56; - } - else - { - o_start_bit=60; - } - - l_temp|=(i_block*4)<<8; - l_temp|=i_rank_pair<<8; - l_temp=l_temp<<32; - - if((i_port==0 && l_mbapos==0) || (i_port==0 && l_mbapos==1)) - { - l_scom_address_64|= l_port01_st | l_temp | l_dqsclk_en; - } - else - { - l_scom_address_64|= l_port23_st | l_temp | l_dqsclk_en; - } - - o_len=2; - o_scom_address_64=l_scom_address_64; - - } - - - else if(i_input_type_e==DQS_ALIGN_t || i_input_type_e==RAW_DQS_ALIGN) - { - - if(i_input_type_e==RAW_DQS_ALIGN) - { - if(i_lane==0) - { - i_lane=16; - } - else if(i_lane==1) - { - i_lane=18; - } - else if(i_lane==2) - { - i_lane=20; - } - else - { - i_lane=22; - } - } - if(i_lane==16) - { - l_scom_address_64|=0x0000005c; - o_start_bit=49; - } - else if(i_lane==18) - { - l_scom_address_64|=0x0000005c; - o_start_bit=57; - } - else if(i_lane==20) - { - l_scom_address_64|=0x0000005d; - o_start_bit=49; - } - else - { - l_scom_address_64|=0x0000005d; - o_start_bit=57; - } - - l_scom_address_64=l_scom_address_64<<32; - l_temp|=(i_block*4)<<8; - l_temp|=i_rank_pair<<8; - l_temp=l_temp<<32; - if((i_port==0 && l_mbapos==0) || (i_port==0 && l_mbapos==1)) - { - l_scom_address_64|= l_port01_st | l_temp | l_port01_en; - } - else - { - l_scom_address_64|= l_port23_st | l_temp | l_port01_en; - } - - - o_len=7; - o_scom_address_64=l_scom_address_64; - - } - - - - else if(i_input_type_e==RAW_SYS_ADDR_CLKS0S1) - { - - if((i_port==0 && l_mbapos==0) || (i_port==0 && l_mbapos==1)) - { - if(i_lane==0) - { - l_scom_address_64=0x800080340301143full; - } - else - { - l_scom_address_64=0x800084340301143full; - } - } - - else - { - if(i_lane==0) - { - l_scom_address_64=0x800180340301143full; - } - else - { - l_scom_address_64=0x800184340301143full; - } - } - - o_start_bit=49; - o_len=7; - o_scom_address_64=l_scom_address_64; - - } - - else if(i_input_type_e==RAW_SYS_CLK) - { - l_temp|=(i_block*4)<<8; - l_temp=l_temp<<32; - if((i_port==0 && l_mbapos==0) || (i_port==0 && l_mbapos==1)) - { - l_scom_address_64|= l_port01_st | l_temp| l_sys_clk_en; - } - else - { - l_scom_address_64|= l_port23_st | l_temp| l_sys_clk_en; - } - - o_start_bit=49; - o_len=7; - o_scom_address_64=l_scom_address_64; - - } - - else if(i_input_type_e==RAW_WR_CLK) - { - l_temp|=(i_block*4)<<8; - l_temp=l_temp<<32; - if((i_port==0 && l_mbapos==0) || (i_port==0 && l_mbapos==1)) - { - l_scom_address_64|= l_port01_st | l_temp| l_wr_clk_en; - } - else - { - l_scom_address_64|= l_port23_st | l_temp| l_wr_clk_en; - } - - o_start_bit=49; - o_len=7; - o_scom_address_64=l_scom_address_64; - - } - - else if(i_input_type_e==RAW_ADDR) - { - l_scom_address_64|=0x00000004; - l_lane=i_lane; - if(i_lane<=7) - { - i_lane=i_lane/2; - } - else if(i_lane==8 || i_lane==9) - { - l_scom_address_64=0x00000008; - i_lane=0; - } - else if(i_lane==10 || i_lane==11) - { - l_scom_address_64=0x00000009; - i_lane=0; - } - else if(i_lane==12 || i_lane==13) - { - l_scom_address_64=0x0000000a; - i_lane=0; - } - else - { - l_scom_address_64=0x0000000b; - i_lane=0; - } - l_scom_address_64=l_scom_address_64<<32; - l_temp|=i_lane; - l_temp|=(i_block*4)<<8; - l_temp=l_temp<<32; - if((i_port==0 && l_mbapos==0) || (i_port==0 && l_mbapos==1)) - { - l_scom_address_64|= l_adr02_st | l_temp | l_port01_en; - } - else - { - l_scom_address_64|= l_adr13_st | l_temp | l_port01_en; - } - - if((l_lane % 2) == 0) - { - o_start_bit=49; - o_len=7; - } - else - { - o_start_bit=57; - o_len=7; - } - - - o_scom_address_64=l_scom_address_64; - - } - - else if(i_input_type_e==RAW_DQS_GATE || i_input_type_e==DQS_GATE_t) - { - if(i_input_type_e==RAW_DQS_GATE) - { - l_lane=i_lane/4; - l_temp|=l_lane; - } - if(i_input_type_e==DQS_GATE_t) - { - l_lane=i_lane; - } - - l_temp|=(i_block*4)<<8; - l_temp|=i_rank_pair<<8; - l_temp=l_temp<<32; - - if(i_input_type_e==RAW_DQS_GATE) - { - if((i_lane % 4) == 0) - { - o_start_bit=49; - o_len=3; - } - else if((i_lane % 4) == 1) - { - o_start_bit=53; - o_len=3; - } - - else if((i_lane % 4) == 2) - { - o_start_bit=57; - o_len=3; - } - - else - { - o_start_bit=61; - o_len=3; - } - } - - else - { - if(l_lane == 16) - { - o_start_bit=49; - o_len=3; - } - else if(l_lane ==18) - { - o_start_bit=53; - o_len=3; - } - - else if(l_lane ==20) - { - o_start_bit=57; - o_len=3; - } - - else - { - o_start_bit=61; - o_len=3; - } - - } - - if((i_port==0 && l_mbapos==0) || (i_port==0 && l_mbapos==1)) - { - l_scom_address_64|= l_port01_st | l_temp | l_dqs_gate_en; - } - else - { - l_scom_address_64|= l_port23_st | l_temp | l_dqs_gate_en; - } - - o_scom_address_64=l_scom_address_64; - - } - - return rc; -} - -//****************************************************************************** -//Function name: mss_getrankpair() -//Description:This function returns rank pair and valid ranks from a given rank -//Input : Target MBA=i_target_mba, i_port_u8=0 or 1, i_rank=valid ranks -//Output : rank pair=o_rank_pair, valid ranks=o_rankpair_table[] -//****************************************************************************** -fapi::ReturnCode mss_getrankpair(const fapi::Target & i_target_mba, - uint8_t i_port, - uint8_t i_rank, - uint8_t *o_rank_pair, - uint8_t o_rankpair_table[]) -{ - fapi::ReturnCode rc; - uint8_t l_temp_rank[2]={0}; - uint8_t l_temp_rankpair_table[16]={0}; - uint8_t l_i= 0; - uint8_t l_rank_pair = 0; - uint8_t l_j= 0; - uint8_t l_temp_swap = 0; - - - for(l_i=0; l_i<8; l_i++) //populate Rank Pair Table as FF - invalid - { - //l_temp_rankpair_table[l_i]=255; - o_rankpair_table[l_i]=255; - } - - if(i_port==0 || i_port ==1) - { - - rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP0, &i_target_mba, l_temp_rank);if(rc) return rc; - l_temp_rankpair_table[0]=l_temp_rank[i_port]; - - rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP1, &i_target_mba, l_temp_rank);if(rc) return rc; - l_temp_rankpair_table[1]=l_temp_rank[i_port]; - - rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP2, &i_target_mba, l_temp_rank);if(rc) return rc; - l_temp_rankpair_table[2]=l_temp_rank[i_port]; - rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP3, &i_target_mba, l_temp_rank);if(rc) return rc; - l_temp_rankpair_table[3]=l_temp_rank[i_port]; - - rc = FAPI_ATTR_GET(ATTR_EFF_SECONDARY_RANK_GROUP0, &i_target_mba, l_temp_rank);if(rc) return rc; - l_temp_rankpair_table[4]=l_temp_rank[i_port]; - - rc = FAPI_ATTR_GET(ATTR_EFF_SECONDARY_RANK_GROUP1, &i_target_mba, l_temp_rank);if(rc) return rc; - l_temp_rankpair_table[5]=l_temp_rank[i_port]; - rc = FAPI_ATTR_GET(ATTR_EFF_SECONDARY_RANK_GROUP2, &i_target_mba, l_temp_rank);if(rc) return rc; - l_temp_rankpair_table[6]=l_temp_rank[i_port]; - - rc = FAPI_ATTR_GET(ATTR_EFF_SECONDARY_RANK_GROUP3, &i_target_mba, l_temp_rank);if(rc) return rc; - l_temp_rankpair_table[7]=l_temp_rank[i_port]; - - rc = FAPI_ATTR_GET(ATTR_EFF_TERTIARY_RANK_GROUP0, &i_target_mba, l_temp_rank);if(rc) return rc; - l_temp_rankpair_table[8]=l_temp_rank[i_port]; - - rc = FAPI_ATTR_GET(ATTR_EFF_TERTIARY_RANK_GROUP1, &i_target_mba, l_temp_rank);if(rc) return rc; - l_temp_rankpair_table[9]=l_temp_rank[i_port]; - - rc = FAPI_ATTR_GET(ATTR_EFF_TERTIARY_RANK_GROUP2, &i_target_mba, l_temp_rank);if(rc) return rc; - l_temp_rankpair_table[10]=l_temp_rank[i_port]; - - rc = FAPI_ATTR_GET(ATTR_EFF_TERTIARY_RANK_GROUP3, &i_target_mba, l_temp_rank);if(rc) return rc; - l_temp_rankpair_table[11]=l_temp_rank[i_port]; - - rc = FAPI_ATTR_GET(ATTR_EFF_QUATERNARY_RANK_GROUP0, &i_target_mba, l_temp_rank);if(rc) return rc; - l_temp_rankpair_table[12]=l_temp_rank[i_port]; - - rc = FAPI_ATTR_GET(ATTR_EFF_QUATERNARY_RANK_GROUP1, &i_target_mba, l_temp_rank);if(rc) return rc; - l_temp_rankpair_table[13]=l_temp_rank[i_port]; - - rc = FAPI_ATTR_GET(ATTR_EFF_QUATERNARY_RANK_GROUP2, &i_target_mba, l_temp_rank);if(rc) return rc; - l_temp_rankpair_table[14]=l_temp_rank[i_port]; - - rc = FAPI_ATTR_GET(ATTR_EFF_QUATERNARY_RANK_GROUP3, &i_target_mba, l_temp_rank);if(rc) return rc; - l_temp_rankpair_table[15]=l_temp_rank[i_port]; - - - } - - for(l_i=0; l_i<16; l_i++) - { - if(l_temp_rankpair_table[l_i]==i_rank) - { - l_rank_pair=l_i;break; - } - } - - l_rank_pair = l_rank_pair%4; // if index l_i is greater than 4,8,12 Secondary, Tertiary, Quaternary. - - - for(l_i=0; l_i<15; l_i++) - { - for(l_j=l_i+1;l_j<16;l_j++) - { - if(l_temp_rankpair_table[l_i]>l_temp_rankpair_table[l_j]) - { - l_temp_swap = l_temp_rankpair_table[l_j]; - l_temp_rankpair_table[l_j]=l_temp_rankpair_table[l_i]; - l_temp_rankpair_table[l_i]=l_temp_swap; - } - } - } - - for(l_i=0; l_i<8; l_i++) - { - if(l_temp_rankpair_table[l_i]!=255) - o_rankpair_table[l_i]=l_temp_rankpair_table[l_i]; - } - *o_rank_pair = l_rank_pair; - - - return rc; -} //end of mss_getrankpair - -//****************************************************************************** -//Function name: mss_c4_phy() -//Description:This function returns address,start bit and bit length for RD_DQ, WR_DQ, RD_DQS, WR_DQS -//Input : Target MBA=i_target_mba, i_port_u8=0 or 1, i_rank_pair=0 or 1 or 2 or 3, i_input_type_e=RD_DQ or RD_DQS or WR_DQ or WR_DQS,i_input_index_u8=0-79/0-71/0-8/0-19 , i_verbose-extra print statements -//Output : out (address,start bit and bit length) -//****************************************************************************** -fapi::ReturnCode mss_c4_phy(const fapi::Target & i_target_mba, - uint8_t i_port, - uint8_t i_rank_pair, - input_type_t i_input_type_e, - uint8_t &i_input_index, - uint8_t i_verbose, - uint8_t &phy_lane, - uint8_t &phy_block, - uint8_t flag) -{ - fapi::ReturnCode rc; - const uint8_t l_dqmax=80; - const uint8_t l_dqsmax=20; - //const uint8_t l_blkmax=5; - const uint8_t lane_dq_p0[l_dqmax]={4,6,5,7,2,1,3,0,13,15,12,14,8,9,11,10,13,15,12,14,9,8,11,10,13,15,12,14,11,9,10,8,11,8,9,10,12,13,14,15,7,6,5,4,1,3,2,0,5,6,4,7,3,1,2,0,7,4,5,6,2,0,3,1,3,0,1,2,6,5,4,7,11,8,9,10,15,13,12,14}; - const uint8_t lane_dq_p1[l_dqmax]={9,11,8,10,13,14,15,12,10,8,11,9,12,13,14,15,1,0,2,3,4,5,6,7,9,11,10,8,15,12,13,14,5,7,6,4,1,0,2,3,0,2,1,3,5,4,6,7,0,2,3,1,4,5,6,7,12,15,13,14,11,8,10,9,5,7,4,6,3,2,0,1,14,12,15,13,9,8,11,10}; - const uint8_t lane_dq_p2[l_dqmax]={13,15,12,14,11,9,10,8,13,12,14,15,10,9,11,8,5,6,7,4,2,3,0,1,10,9,8,11,13,12,15,14,15,12,13,14,11,10,9,8,7,6,4,5,1,0,3,2,0,2,1,3,5,6,4,7,5,7,6,4,1,0,2,3,1,2,3,0,7,6,5,4,9,10,8,11,12,15,14,13}; - const uint8_t lane_dq_p3[l_dqmax]={4,5,6,7,0,1,3,2,12,13,15,14,8,9,10,11,10,8,11,9,12,13,15,14,3,0,1,2,4,6,7,5,9,10,11,8,14,13,15,12,7,5,6,4,3,1,2,0,5,6,7,4,1,2,3,0,14,12,15,13,8,10,9,11,0,3,2,1,6,5,7,4,10,11,9,8,12,13,15,14}; - const uint8_t dqs_dq_lane_p0[l_dqsmax]={4,0,12,8,12,8,12,8,8,12,4,0,4,0,4,0,0,4,8,12}; - const uint8_t dqs_dq_lane_p1[l_dqsmax]={8,12,8,12,0,4,8,12,4,0,0,4,0,4,12,8,4,0,12,8}; - const uint8_t dqs_dq_lane_p2[l_dqsmax]={12,8,12,8,4,0,8,12,12,8,4,0,0,4,4,0,0,4,8,12}; - const uint8_t dqs_dq_lane_p3[l_dqsmax]={4,0,12,8,8,12,0,4,8,12,4,0,4,0,12,8,0,4,8,12}; - const uint8_t block_p1[l_dqmax]={0,0,0,0,0,0,0,0,3,3,3,3,3,3,3,3,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,2,2,2,2,2,2,2,2,3,3,3,3,3,3,3,3,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,1,1,1,1,1,1,1,1,2,2,2,2,2,2,2,2}; - const uint8_t block_p0[l_dqmax]={2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,0,0,0,0,0,0,0,0,3,3,3,3,3,3,3,3,4,4,4,4,4,4,4,4,3,3,3,3,3,3,3,3,4,4,4,4,4,4,4,4,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1}; - const uint8_t block_p2[l_dqmax]={1,1,1,1,1,1,1,1,3,3,3,3,3,3,3,3,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,3,3,3,3,3,3,3,3,4,4,4,4,4,4,4,4,1,1,1,1,1,1,1,1,4,4,4,4,4,4,4,4}; - const uint8_t block_p3[l_dqmax]={2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1}; - const uint8_t block_dqs_p0[l_dqsmax]={2,2,2,2,0,0,3,3,4,4,3,3,4,4,1,1,0,0,1,1}; - const uint8_t block_dqs_p1[l_dqsmax]={0,0,3,3,0,0,1,1,2,2,3,3,4,4,4,4,1,1,2,2}; - const uint8_t block_dqs_p2[l_dqsmax]={1,1,3,3,0,0,0,0,2,2,2,2,3,3,4,4,1,1,4,4}; - const uint8_t block_dqs_p3[l_dqsmax]={2,2,2,2,0,0,0,0,3,3,3,3,4,4,4,4,1,1,1,1}; - uint8_t l_mbapos = 0; - uint8_t l_dram_width=0; - uint8_t l_lane=0; - uint8_t l_block=0; - uint8_t lane_dqs[4]={0}; //Initialize to 0. This is a numerical ID of a false lane. Another function catches this in mss_draminit_training. - uint8_t l_index=0; - uint8_t l_dq=0; - uint8_t l_phy_dq=0; - //uint8_t l_phy_block=0; - uint64_t l_scom_address_64=0x0ull; - uint8_t l_start_bit=0; - uint8_t l_len=0; - ip_type_t l_input_type; - ecmdDataBufferBase data_buffer_64(64); - uint8_t l_dimmtype=0; - uint8_t l_swizzle=0; - i_verbose=1; //Default the verbose flag high - - rc = FAPI_ATTR_GET(ATTR_MSS_DQS_SWIZZLE_TYPE, &i_target_mba, l_swizzle); if(rc) return rc; - - rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target_mba, l_mbapos); if(rc) return rc; - - rc = FAPI_ATTR_GET(ATTR_EFF_CUSTOM_DIMM, &i_target_mba, l_dimmtype); if(rc) return rc; - - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target_mba, l_dram_width); if(rc) return rc; - - - if(i_input_type_e==RD_DQ || i_input_type_e==WR_DQ) - { - - if(i_port==0 && l_mbapos==0) - { - - if(flag==1){ - for(l_phy_dq=0;l_phy_dq<l_dqmax;l_phy_dq++){ - if(phy_block==block_p0[l_phy_dq]){ - if(phy_lane==lane_dq_p0[l_phy_dq]){ - i_input_index=l_phy_dq; - } - } - } - }else{ - - l_lane=lane_dq_p0[i_input_index]; - l_block=block_p0[i_input_index]; - } - } - else if(i_port==1 && l_mbapos==0) - { - - if(flag==1){ - for(l_phy_dq=0;l_phy_dq<l_dqmax;l_phy_dq++){ - if(phy_block==block_p1[l_phy_dq]){ - if(phy_lane==lane_dq_p1[l_phy_dq]){ - i_input_index=l_phy_dq; - } - } - } - }else{ - l_lane=lane_dq_p1[i_input_index]; - l_block=block_p1[i_input_index]; - } - } - else if(i_port==0 && l_mbapos==1) - { - if(flag==1){ - for(l_phy_dq=0;l_phy_dq<l_dqmax;l_phy_dq++){ - if(phy_block==block_p2[l_phy_dq]){ - if(phy_lane==lane_dq_p2[l_phy_dq]){ - i_input_index=l_phy_dq; - } - } - } - }else{ - - l_lane=lane_dq_p2[i_input_index]; - l_block=block_p2[i_input_index]; - } - } - else - { - if(flag==1){ - for(l_phy_dq=0;l_phy_dq<l_dqmax;l_phy_dq++){ - if(phy_block==block_p3[l_phy_dq]){ - if(phy_lane==lane_dq_p3[l_phy_dq]){ - i_input_index=l_phy_dq; - } - } - } - }else{ - l_lane=lane_dq_p3[i_input_index]; - l_block=block_p3[i_input_index]; - } - } - - if(i_verbose==1) - { - FAPI_INF("block=%d",l_block); - FAPI_INF("lane=%d",l_lane); - } - // if(i_input_type_e==RD_DQ) - // { - // l_input_type=RD_DQ_t; - // } - // else - // { - // l_input_type=WR_DQ_t; - // } - - - // rc=get_address(i_target_mba,i_port,i_rank_pair,l_input_type,l_block,l_lane,l_scom_address_64,l_start_bit,l_len); if(rc) return rc; - if(flag==0){ - phy_lane=l_lane; - phy_block=l_block; - } - // out.scom_addr=l_scom_address_64; - // out.start_bit=l_start_bit; - // out.bit_length=l_len; - } - - else if (i_input_type_e==WR_DQS || i_input_type_e==DQS_ALIGN) - { - if(i_port==0 && l_mbapos==0) - { - l_dq=dqs_dq_lane_p0[i_input_index]; - l_block=block_dqs_p0[i_input_index]; - } - - else if(i_port==1 && l_mbapos==0) - { - l_dq=dqs_dq_lane_p1[i_input_index]; - l_block=block_dqs_p1[i_input_index]; - } - else if(i_port==0 && l_mbapos==1) - { - l_dq=dqs_dq_lane_p2[i_input_index]; - l_block=block_dqs_p2[i_input_index]; - } - else - { - l_dq=dqs_dq_lane_p3[i_input_index]; - l_block=block_dqs_p3[i_input_index]; - } - - if(i_verbose==1) - { - FAPI_INF("block=%d",l_block); - FAPI_INF("dqs_dq_lane=%d",l_dq); - } - l_input_type=RD_CLK_t; - rc=get_address(i_target_mba,i_port,i_rank_pair, l_input_type,l_block,l_lane,l_scom_address_64,l_start_bit,l_len); if(rc) return rc; - if(i_verbose==1) - { - FAPI_INF("read clock address=%llx",l_scom_address_64); - } - rc=fapiGetScom(i_target_mba,l_scom_address_64,data_buffer_64);if(rc) return rc; - - if(l_dram_width==fapi::ENUM_ATTR_EFF_DRAM_WIDTH_X4) - { - - if (data_buffer_64.isBitSet(48)) - { - lane_dqs[0]=16; - - } - else if(data_buffer_64.isBitSet(52)) - { - lane_dqs[0]=18; - - } - - if (data_buffer_64.isBitSet(49)) - { - lane_dqs[1]=16; - - } - - else if (data_buffer_64.isBitSet(53)) - { - lane_dqs[1]=18; - - } - - if (data_buffer_64.isBitSet(54)) - { - lane_dqs[2]=20; - - } - else if (data_buffer_64.isBitSet(56)) - { - lane_dqs[2]=22; - - } - - if (data_buffer_64.isBitSet(55)) - { - lane_dqs[3]=20; - } - else if (data_buffer_64.isBitSet(57)) // else is not possible as one of them will definitely get set - { - lane_dqs[3]=22; - - } - if(i_verbose==1) - { - FAPI_INF("array is=%d and %d and %d and %d",lane_dqs[0],lane_dqs[1],lane_dqs[2],lane_dqs[3]); - } - if(l_dq==0) - { - l_lane=lane_dqs[0]; - } - else if(l_dq==4) - { - l_lane=lane_dqs[1]; - } - else if(l_dq==8) - { - l_lane=lane_dqs[2]; - } - else - { - l_lane=lane_dqs[3]; - } - - if(i_verbose==1) - { - FAPI_INF("lane is=%d",l_lane); - } - } - - - else - { - if (data_buffer_64.isBitSet(48)&& data_buffer_64.isBitSet(49)) - { - lane_dqs[l_index]=16; - l_index++; - } - else if (data_buffer_64.isBitSet(52)&& data_buffer_64.isBitSet(53)) - { - lane_dqs[l_index]=18; - l_index++; - } - if (data_buffer_64.isBitSet(54)&& data_buffer_64.isBitSet(55)) - { - lane_dqs[l_index]=20; - l_index++; - } - else if (data_buffer_64.isBitSet(56)&& data_buffer_64.isBitSet(57)) // else is not possible as one of them will definitely get set - { - lane_dqs[l_index]=22; - l_index++; - } - if(i_verbose==1) - { - FAPI_INF("array is=%d and %d",lane_dqs[0],lane_dqs[1]); - } - if((l_dq==0) || (l_dq==4)) - { - l_lane=lane_dqs[0]; - } - else - { - l_lane=lane_dqs[1]; - } - - if(l_dimmtype==fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES) - { - if((i_input_index==1) || (i_input_index==3) || (i_input_index==5) || (i_input_index==7) || (i_input_index==9) || (i_input_index==11) || (i_input_index==13) || (i_input_index==15) || (i_input_index==17) || (i_input_index==19)) - { - if(l_lane==16) - { - l_lane=18; - } - else if(l_lane==18) - { - l_lane=16; - } - - else if(l_lane==20) - { - l_lane=22; - } - - else - { - l_lane=20; - } - - } - } - - else - { - if((i_port==0) && (l_mbapos==0)) - { - if(l_swizzle==1) - { - if((i_input_index==3) || (i_input_index==1) || (i_input_index==4) || (i_input_index==17)|| (i_input_index==9) || (i_input_index==11) || (i_input_index==13) || (i_input_index==15) || (i_input_index==6)) - { - if(l_lane==16) - { - l_lane=18; - } - else if(l_lane==18) - { - l_lane=16; - } - - else if(l_lane==20) - { - l_lane=22; - } - - else - { - l_lane=20; - } - - } - } - - else - { - if((i_input_index==3) || (i_input_index==1) || (i_input_index==5) || (i_input_index==7)|| (i_input_index==9) || (i_input_index==11) || (i_input_index==13) || (i_input_index==15) || (i_input_index==17)) - { - if(l_lane==16) - { - l_lane=18; - } - else if(l_lane==18) - { - l_lane=16; - } - - else if(l_lane==20) - { - l_lane=22; - } - - else - { - l_lane=20; - } - } - - } - } - - else if((i_port==1) && (l_mbapos==0)) - { - if(l_swizzle==1) - { - if((i_input_index==2) || (i_input_index==0) || (i_input_index==4) || (i_input_index==17)|| (i_input_index==9) || (i_input_index==11) || (i_input_index==13) || (i_input_index==15) || (i_input_index==7)) - { - if(l_lane==16) - { - l_lane=18; - } - else if(l_lane==18) - { - l_lane=16; - } - - else if(l_lane==20) - { - l_lane=22; - } - - else - { - l_lane=20; - } - } - } - - else - { - if((i_input_index==1) || (i_input_index==3) || (i_input_index==5) || (i_input_index==7)|| (i_input_index==9) || (i_input_index==11) || (i_input_index==13) || (i_input_index==15) || (i_input_index==17)) - { - if(l_lane==16) - { - l_lane=18; - } - else if(l_lane==18) - { - l_lane=16; - } - - else if(l_lane==20) - { - l_lane=22; - } - - else - { - l_lane=20; - } - } - } - } - - - else - { - if((i_input_index==1) || (i_input_index==3) || (i_input_index==5) || (i_input_index==7)|| (i_input_index==9) || (i_input_index==11) || (i_input_index==13) || (i_input_index==15) || (i_input_index==17)) - { - if(l_lane==16) - { - l_lane=18; - } - else if(l_lane==18) - { - l_lane=16; - } - - else if(l_lane==20) - { - l_lane=22; - } - - else - { - l_lane=20; - } - - } - } - - - - } - if(i_verbose==1) - { - FAPI_INF("lane is=%d",l_lane); - } - } - - // if(i_input_type_e==WR_DQS) - // { - // l_input_type=WR_DQS_t; - // } - // else - // { - // l_input_type=DQS_ALIGN_t; - // } - - // rc=get_address(i_target_mba,i_port,i_rank_pair,l_input_type,l_block,l_lane,l_scom_address_64,l_start_bit,l_len); if(rc) return rc; - if(flag==0){ - phy_lane=l_lane; - phy_block=l_block; - } - // out.scom_addr=l_scom_address_64; - // out.start_bit=l_start_bit; - // out.bit_length=l_len; - } else if (i_input_type_e==RD_DQS || i_input_type_e==DQS_GATE || i_input_type_e==RDCLK || i_input_type_e==DQSCLK) - { - - - if(i_port==0 && l_mbapos==0) - { - l_dq=dqs_dq_lane_p0[i_input_index]; - l_block=block_dqs_p0[i_input_index]; - } - - else if(i_port==1 && l_mbapos==0) - { - l_dq=dqs_dq_lane_p1[i_input_index]; - l_block=block_dqs_p1[i_input_index]; - } - else if(i_port==0 && l_mbapos==1) - { - l_dq=dqs_dq_lane_p2[i_input_index]; - l_block=block_dqs_p2[i_input_index]; - } - else - { - l_dq=dqs_dq_lane_p3[i_input_index]; - l_block=block_dqs_p3[i_input_index]; - } - - if(i_verbose==1) - { - FAPI_INF("block=%d",l_block); - FAPI_INF("dqs_dq_lane=%d",l_dq); - } - if(l_dq==0) - { - l_lane=16; - } - - else if(l_dq==4) - { - l_lane=18; - } - - else if (l_dq==8) - { - l_lane=20; - } - - else - { - l_lane=22; - } - //FAPI_INF("here"); - - if (i_input_type_e==DQS_GATE) - { - l_input_type=DQS_GATE_t; - } - - else if(i_input_type_e==RDCLK) - { - l_input_type=RDCLK_t; - } - - else if(i_input_type_e==RD_DQS) - { - l_input_type=RD_DQS_t; - } - - else - { - l_input_type=DQSCLK_t; - } - - if(i_verbose==1) - { - FAPI_INF("lane is=%d",l_lane); - } - - if(flag==0){ - phy_lane=l_lane; - phy_block=l_block; - } - - // rc=get_address(i_target_mba,i_port,i_rank_pair,l_input_type,l_block,l_lane,l_scom_address_64,l_start_bit,l_len); if(rc) return rc; - // out.scom_addr=l_scom_address_64; - // out.start_bit=l_start_bit; - // out.bit_length=l_len; - } - - else - { - FAPI_ERR("Wrong input type specified (%d)", i_input_type_e); - const input_type_t & TYPE_PARAM = i_input_type_e; - FAPI_SET_HWP_ERROR(rc, RC_MSS_C4_PHY_INVALID_INPUT); - return rc; - } - - return rc; -} - -fapi::ReturnCode mss_access_delay_reg_schmoo(const fapi::Target & i_target_mba, - access_type_t i_access_type_e, - uint8_t i_port_u8, - uint8_t i_rank_u8, - input_type_t i_input_type_e, - uint8_t i_input_index_u8, - uint8_t i_verbose, - uint16_t &io_value_u16) -{ - // Reference variables for Error FFDC - const fapi::Target & MBA_TARGET = i_target_mba; - const access_type_t & ACCESS_TYPE_PARAM = i_access_type_e; - const uint8_t & PORT_PARAM = i_port_u8; - const uint8_t & RANK_PARAM = i_rank_u8; - const input_type_t & TYPE_PARAM = i_input_type_e; - const uint8_t & INDEX_PARAM = i_input_index_u8; - - fapi::ReturnCode rc; - - const uint8_t max_rp=8; - uint8_t l_val=0; - uint8_t l_dram_width=0; - scom_location l_out; - uint64_t l_scom_add=0x0ull; - uint32_t l_sbit=0; - uint32_t l_len=0; - uint32_t l_value_u32=0; - uint32_t rc_num=0; - ecmdDataBufferBase data_buffer_64(64); - ecmdDataBufferBase data_buffer_32(32); - ecmdDataBufferBase out(16); - uint32_t l_output=0; - uint32_t l_start=0; - uint8_t l_rank_pair=9; - uint8_t l_rankpair_table[max_rp]={255}; - uint8_t l_dimmtype=0; - uint8_t l_block=0; - uint8_t l_lane=0; - uint8_t l_start_bit=0; - uint8_t l_len8=0; - input_type l_type; - uint8_t l_mbapos=0; - const uint8_t l_ISDIMM_dqmax=71; - const uint8_t l_CDIMM_dqmax=79; - uint8_t l_adr=0; - const uint8_t addr_max=19; - const uint8_t cmd_max=3; - const uint8_t cnt_max=20; - const uint8_t clk_max=8; - const uint8_t addr_lanep0[addr_max]={1,5,3,7,10,6,4,10,13,12,9,9,0,0,6,4,1,4,8}; - const uint8_t addr_adrp0[addr_max]={2,1,1,3,1,3,1,3,3,3,2,3,2,3,1,0,3,3,3}; - const uint8_t addr_lanep1[addr_max]={7,10,3,6,8,12,6,1,5,8,2,0,13,4,5,9,6,11,9}; - const uint8_t addr_adrp1[addr_max]={2,1,2,2,1,3,1,1,1,3,1,3,2,3,3,0,0,1,3}; - const uint8_t addr_lanep2[addr_max]={8,0,7,1,12,10,1,5,9,5,13,5,4,2,4,9,10,9,0}; - const uint8_t addr_adrp2[addr_max]={2,2,3,0,3,1,2,0,1,3,2,1,0,2,3,3,3,2,1}; - const uint8_t addr_lanep3[addr_max]={6,2,9,9,2,3,4,10,0,5,1,5,4,1,8,11,5,12,1}; - const uint8_t addr_adrp3[addr_max]={3,0,2,3,2,0,3,3,1,2,2,1,0,1,3,3,0,3,0}; - - const uint8_t cmd_lanep0[cmd_max]={2,11,5}; - const uint8_t cmd_adrp0[cmd_max]={3,1,3}; - const uint8_t cmd_lanep1[cmd_max]={2,10,10}; - const uint8_t cmd_adrp1[cmd_max]={2,3,2}; - const uint8_t cmd_lanep2[cmd_max]={3,11,3}; - const uint8_t cmd_adrp2[cmd_max]={1,3,0}; - const uint8_t cmd_lanep3[cmd_max]={7,10,7}; - const uint8_t cmd_adrp3[cmd_max]={1,1,3}; - - const uint8_t cnt_lanep0[cnt_max]={0,7,3,1,7,8,8,3,8,6,7,2,2,0,9,1,3,6,9,2}; - const uint8_t cnt_adrp0[cnt_max]={1,0,3,0,2,2,1,2,0,0,1,2,0,0,1,1,0,2,0,1}; - const uint8_t cnt_lanep1[cnt_max]={5,4,0,5,11,9,10,7,1,11,0,4,12,3,6,8,1,4,7,7}; - const uint8_t cnt_adrp1[cnt_max]={2,1,2,0,2,1,0,1,3,0,1,0,2,1,3,0,2,2,3,0}; - const uint8_t cnt_lanep2[cnt_max]={0,4,7,13,11,5,12,2,3,6,11,6,7,1,10,8,8,2,4,1}; - const uint8_t cnt_adrp2[cnt_max]={0,1,1,3,1,2,2,0,2,2,0,1,2,1,0,3,1,1,2,3}; - const uint8_t cnt_lanep3[cnt_max]={0,11,9,8,4,7,0,3,8,6,13,8,7,0,6,6,1,2,9,5}; - const uint8_t cnt_adrp3[cnt_max]={2,1,0,2,1,0,3,2,0,1,3,1,2,0,0,2,3,1,1,3}; - - const uint8_t clk_lanep0[clk_max]={10,11,11,10,4,5,13,12}; - const uint8_t clk_adrp0[clk_max]={0,0,2,2,2,2,2,2}; - const uint8_t clk_lanep1[clk_max]={3,2,8,9,1,0,3,2}; - const uint8_t clk_adrp1[clk_max]={3,3,2,2,0,0,0,0}; - const uint8_t clk_lanep2[clk_max]={11,10,6,7,2,3,8,9}; - const uint8_t clk_adrp2[clk_max]={2,2,0,0,3,3,0,0}; - const uint8_t clk_lanep3[clk_max]={3,2,13,12,10,11,11,10}; - const uint8_t clk_adrp3[clk_max]={3,3,2,2,0,0,2,2}; - - - rc = mss_getrankpair(i_target_mba,i_port_u8,i_rank_u8,&l_rank_pair,l_rankpair_table); if(rc) return rc; - - rc = FAPI_ATTR_GET(ATTR_EFF_CUSTOM_DIMM, &i_target_mba, l_dimmtype); if(rc) return rc; - - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target_mba, l_dram_width); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target_mba, l_mbapos); if(rc) return rc; - - if(i_verbose==1) - { - FAPI_INF("dimm type=%d",l_dimmtype); - FAPI_INF("rank pair=%d",l_rank_pair); - } - if(i_port_u8 >1) - { - FAPI_ERR("Wrong port specified (%d)", i_port_u8); - FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_SCHMOO_INVALID_INPUT); - return rc; - } - - if (l_mbapos>1) - { - FAPI_ERR("Bad position from ATTR_CHIP_UNIT_POS (%d)", l_mbapos); - const uint8_t & MBA_POS = l_mbapos; - FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_SCHMOO_BAD_MBA_POS); - } - - if((l_dram_width ==fapi::ENUM_ATTR_EFF_DRAM_WIDTH_X4) || (l_dram_width ==fapi::ENUM_ATTR_EFF_DRAM_WIDTH_X8)) // Checking for dram width here so that checking can be skipped in called function - { - if(i_verbose==1) - { - FAPI_INF("dram width=%d",l_dram_width); - } - } - - else - { - FAPI_ERR("Bad dram width from ATTR_EFF_DRAM_WIDTH (%d)", l_dram_width); - const uint8_t & DRAM_WIDTH = l_dram_width; - FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_SCHMOO_BAD_DRAM_WIDTH); - return rc; - } - - if(i_input_type_e==RD_DQ || i_input_type_e==WR_DQ) - { - - if(l_dimmtype==fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES) - { - l_type=CDIMM_DQ; - - if(i_input_index_u8>l_CDIMM_dqmax) - { - FAPI_ERR("CDIMM_DQ: Wrong input index specified (%d, max %d)" , - i_input_index_u8, l_CDIMM_dqmax); - FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_SCHMOO_INVALID_INPUT); - return rc; - } - - } - else - { - l_type=ISDIMM_DQ; - if(i_input_index_u8>l_ISDIMM_dqmax) - { - FAPI_ERR("ISDIMM_DQ: Wrong input index specified (%d, max %d)", - i_input_index_u8, l_ISDIMM_dqmax); - FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_SCHMOO_INVALID_INPUT); - return rc; - } - } - - rc=rosetta_map(i_target_mba,i_port_u8,l_type,i_input_index_u8,i_verbose,l_val); if(rc) return rc; - - if(i_verbose==1) - { - FAPI_INF("C4 value is=%d",l_val); - } - rc=cross_coupled(i_target_mba,i_port_u8,l_rank_pair,i_input_type_e,l_val,i_verbose,l_out); if(rc) return rc; - if(i_verbose==1) - { - FAPI_INF("scom_address=%llX",l_out.scom_addr); - FAPI_INF("start bit=%d",l_out.start_bit); - FAPI_INF("length=%d",l_out.bit_length); - } - l_scom_add=l_out.scom_addr; - l_sbit=l_out.start_bit; - l_len=l_out.bit_length; - - } - - else if(i_input_type_e==ADDRESS) - { - if(i_input_index_u8<=18) // 19 delay values for Address - { - if((i_port_u8==0) && (l_mbapos==0)) - { - l_lane=addr_lanep0[i_input_index_u8]; - l_adr=addr_adrp0[i_input_index_u8]; - } - else if((i_port_u8==1) && (l_mbapos==0)) - { - l_lane=addr_lanep1[i_input_index_u8]; - l_adr=addr_adrp1[i_input_index_u8]; - } - else if((i_port_u8==0) && (l_mbapos==1)) - { - l_lane=addr_lanep2[i_input_index_u8]; - l_adr=addr_adrp2[i_input_index_u8]; - } - else - { - l_lane=addr_lanep3[i_input_index_u8]; - l_adr=addr_adrp3[i_input_index_u8]; - } - - } - - else - { - FAPI_ERR("Wrong input index specified (%d)", i_input_index_u8); - FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_SCHMOO_INVALID_INPUT); - return rc; - } - - ip_type_t l_input=ADDRESS_t; - if(i_verbose==1) - { - FAPI_INF("ADR=%d",l_adr); - FAPI_INF("lane=%d",l_lane); - } - l_block=l_adr; - rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc; - l_sbit=l_start_bit; - l_len=l_len8; - if(i_verbose==1) - { - FAPI_INF("scom_address=%llX",l_scom_add); - FAPI_INF("start bit=%d",l_start_bit); - FAPI_INF("length=%d",l_len8); - } - } - - else if(i_input_type_e==DATA_DISABLE) - { - if(i_input_index_u8<=4) // 5 delay values for data bits disable register - { - l_block=i_input_index_u8; - } - else - { - FAPI_ERR("Wrong input index specified (%d)", i_input_index_u8); - FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_SCHMOO_INVALID_INPUT); - return rc; - } - - ip_type_t l_input=DATA_DISABLE_t; - if(i_verbose==1) - { - FAPI_INF("block=%d",l_block); - } - l_lane=0; - rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc; - l_sbit=l_start_bit; - l_len=l_len8; - if(i_verbose==1) - { - FAPI_INF("scom_address=%llX",l_scom_add); - FAPI_INF("start bit=%d",l_start_bit); - FAPI_INF("length=%d",l_len8); - } - } - - - else if(i_input_type_e==COMMAND) - { - if(i_input_index_u8<=2) // 3 delay values for Command - { - if((i_port_u8==0) && (l_mbapos==0)) - { - l_lane=cmd_lanep0[i_input_index_u8]; - l_adr=cmd_adrp0[i_input_index_u8]; - } - else if((i_port_u8==1) && (l_mbapos==0)) - { - l_lane=cmd_lanep1[i_input_index_u8]; - l_adr=cmd_adrp1[i_input_index_u8]; - } - else if((i_port_u8==0) && (l_mbapos==1)) - { - l_lane=cmd_lanep2[i_input_index_u8]; - l_adr=cmd_adrp2[i_input_index_u8]; - } - else - { - l_lane=cmd_lanep3[i_input_index_u8]; - l_adr=cmd_adrp3[i_input_index_u8]; - } - - } - - else - { - FAPI_ERR("Wrong input index specified (%d)", i_input_index_u8); - FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_SCHMOO_INVALID_INPUT); - return rc; - } - - ip_type_t l_input=COMMAND_t; - if(i_verbose==1) - { - FAPI_INF("ADR=%d",l_adr); - FAPI_INF("lane=%d",l_lane); - } - l_block=l_adr; - rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc; - l_sbit=l_start_bit; - l_len=l_len8; - if(i_verbose==1) - { - FAPI_INF("scom_address=%llX",l_scom_add); - FAPI_INF("start bit=%d",l_start_bit); - FAPI_INF("length=%d",l_len8); - } - } - - else if(i_input_type_e==CONTROL) - { - if(i_input_index_u8<=19) // 20 delay values for Control - { - if((i_port_u8==0) && (l_mbapos==0)) - { - l_lane=cnt_lanep0[i_input_index_u8]; - l_adr=cnt_adrp0[i_input_index_u8]; - } - else if((i_port_u8==1) && (l_mbapos==0)) - { - l_lane=cnt_lanep1[i_input_index_u8]; - l_adr=cnt_adrp1[i_input_index_u8]; - } - else if((i_port_u8==0) && (l_mbapos==1)) - { - l_lane=cnt_lanep2[i_input_index_u8]; - l_adr=cnt_adrp2[i_input_index_u8]; - } - else - { - l_lane=cnt_lanep3[i_input_index_u8]; - l_adr=cnt_adrp3[i_input_index_u8]; - } - - } - - else - { - FAPI_ERR("Wrong input index specified (%d)", i_input_index_u8); - FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_SCHMOO_INVALID_INPUT); - return rc; - } - - ip_type_t l_input=CONTROL_t; - if(i_verbose==1) - { - FAPI_INF("ADR=%d",l_adr); - FAPI_INF("lane=%d",l_lane); - } - l_block=l_adr; - rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc; - l_sbit=l_start_bit; - l_len=l_len8; - if(i_verbose==1) - { - FAPI_INF("scom_address=%llX",l_scom_add); - FAPI_INF("start bit=%d",l_start_bit); - FAPI_INF("length=%d",l_len8); - } - } - - else if(i_input_type_e==CLOCK) - { - if(i_input_index_u8<=7) // 8 delay values for CLK - { - if((i_port_u8==0) && (l_mbapos==0)) - { - l_lane=clk_lanep0[i_input_index_u8]; - l_adr=clk_adrp0[i_input_index_u8]; - } - else if((i_port_u8==1) && (l_mbapos==0)) - { - l_lane=clk_lanep1[i_input_index_u8]; - l_adr=clk_adrp1[i_input_index_u8]; - } - else if((i_port_u8==0) && (l_mbapos==1)) - { - l_lane=clk_lanep2[i_input_index_u8]; - l_adr=clk_adrp2[i_input_index_u8]; - } - else - { - l_lane=clk_lanep3[i_input_index_u8]; - l_adr=clk_adrp3[i_input_index_u8]; - } - - } - - else - { - FAPI_ERR("Wrong input index specified (%d)", i_input_index_u8); - FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_SCHMOO_INVALID_INPUT); - return rc; - } - - ip_type_t l_input=CLOCK_t; - if(i_verbose==1) - { - FAPI_INF("ADR=%d",l_adr); - FAPI_INF("lane=%d",l_lane); - } - l_block=l_adr; - rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc; - l_sbit=l_start_bit; - l_len=l_len8; - if(i_verbose==1) - { - FAPI_INF("scom_address=%llX",l_scom_add); - FAPI_INF("start bit=%d",l_start_bit); - FAPI_INF("length=%d",l_len8); - } - } - - - else if (i_input_type_e==RD_DQS || i_input_type_e==WR_DQS || i_input_type_e==DQS_ALIGN || i_input_type_e==DQS_GATE || i_input_type_e==RDCLK || i_input_type_e==DQSCLK) - { - - if(l_dimmtype==fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES) - { - l_type=CDIMM_DQS; - } - else - { - l_type=ISDIMM_DQS; - } - - rc=rosetta_map(i_target_mba,i_port_u8,l_type,i_input_index_u8,i_verbose,l_val); if(rc) return rc; - if(i_verbose==1) - { - FAPI_INF("C4 value is=%d",l_val); - } - rc=cross_coupled(i_target_mba,i_port_u8,l_rank_pair,i_input_type_e,l_val,i_verbose,l_out); if(rc) return rc; - if(i_verbose==1) - { - FAPI_INF("scom_address=%llX",l_out.scom_addr); - FAPI_INF("start bit=%d",l_out.start_bit); - FAPI_INF("length=%d",l_out.bit_length); - } - l_scom_add=l_out.scom_addr; - l_sbit=l_out.start_bit; - l_len=l_out.bit_length; - - } - - - else if(i_input_type_e==RAW_RDCLK_0 || i_input_type_e==RAW_RDCLK_1 || i_input_type_e==RAW_RDCLK_2 || i_input_type_e==RAW_RDCLK_3 || i_input_type_e==RAW_RDCLK_4) - { - if(i_input_type_e==RAW_RDCLK_0) - { - l_block=0; - } - - else if(i_input_type_e==RAW_RDCLK_1) - { - l_block=1; - } - - else if(i_input_type_e==RAW_RDCLK_2) - { - l_block=2; - } - - else if(i_input_type_e==RAW_RDCLK_3) - { - l_block=3; - } - - else - { - l_block=4; - } - if(i_input_index_u8<=3) // 4 delay values for RDCLK - { - l_lane=i_input_index_u8; - } - - else - { - FAPI_ERR("Wrong input index specified (%d)", i_input_index_u8); - FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_SCHMOO_INVALID_INPUT); - return rc; - } - - ip_type_t l_input=RAW_RDCLK; - if(i_verbose==1) - { - FAPI_INF("block=%d",l_block); - } - rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc; - l_sbit=l_start_bit; - l_len=l_len8; - if(i_verbose==1) - { - FAPI_INF("scom_address=%llX",l_scom_add); - FAPI_INF("start bit=%d",l_start_bit); - FAPI_INF("length=%d",l_len8); - } - } - - else if(i_input_type_e==RAW_DQSCLK_0 || i_input_type_e==RAW_DQSCLK_1 || i_input_type_e==RAW_DQSCLK_2 || i_input_type_e==RAW_DQSCLK_3 || i_input_type_e==RAW_DQSCLK_4) - { - if(i_input_type_e==RAW_DQSCLK_0) - { - l_block=0; - } - - else if(i_input_type_e==RAW_DQSCLK_1) - { - l_block=1; - } - - else if(i_input_type_e==RAW_DQSCLK_2) - { - l_block=2; - } - - else if(i_input_type_e==RAW_DQSCLK_3) - { - l_block=3; - } - - else - { - l_block=4; - } - if(i_input_index_u8<=3) // 4 delay values for DQSCLK - { - l_lane=i_input_index_u8; - } - - else - { - FAPI_ERR("Wrong input index specified (%d)", i_input_index_u8); - FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_SCHMOO_INVALID_INPUT); - return rc; - } - ip_type_t l_input=RAW_DQSCLK; - if(i_verbose==1) - { - FAPI_INF("block=%d",l_block); - } - rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc; - l_sbit=l_start_bit; - l_len=l_len8; - if(i_verbose==1) - { - FAPI_INF("scom_address=%llX",l_scom_add); - FAPI_INF("start bit=%d",l_start_bit); - FAPI_INF("length=%d",l_len8); - } - } - - - else if(i_input_type_e==RAW_WR_DQ_0 || i_input_type_e==RAW_WR_DQ_1 || i_input_type_e==RAW_WR_DQ_2 || i_input_type_e==RAW_WR_DQ_3 || i_input_type_e==RAW_WR_DQ_4) - { - if(i_input_type_e==RAW_WR_DQ_0) - { - l_block=0; - } - else if(i_input_type_e==RAW_WR_DQ_1) - { - l_block=1; - } - else if(i_input_type_e==RAW_WR_DQ_2) - { - l_block=2; - } - else if(i_input_type_e==RAW_WR_DQ_3) - { - l_block=3; - } - else - { - l_block=4; - } - if(i_input_index_u8<=15) // 16 Write delay values for DQ bits - { - l_lane=i_input_index_u8; - } - - else - { - FAPI_ERR("Wrong input index specified (%d)", i_input_index_u8); - FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_SCHMOO_INVALID_INPUT); - return rc; - } - - ip_type_t l_input=RAW_WR_DQ; - if(i_verbose==1) - { - FAPI_INF("block=%d",l_block); - FAPI_INF("lane=%d",l_lane); - } - rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc; - l_sbit=l_start_bit; - l_len=l_len8; - if(i_verbose==1) - { - FAPI_INF("scom_address=%llX",l_scom_add); - FAPI_INF("start bit=%d",l_start_bit); - FAPI_INF("length=%d",l_len8); - } - } - - else if(i_input_type_e==RAW_RD_DQ_0 || i_input_type_e==RAW_RD_DQ_1 || i_input_type_e==RAW_RD_DQ_2 || i_input_type_e==RAW_RD_DQ_3 || i_input_type_e==RAW_RD_DQ_4) - { - if(i_input_type_e==RAW_RD_DQ_0) - { - l_block=0; - } - else if(i_input_type_e==RAW_RD_DQ_1) - { - l_block=1; - } - else if(i_input_type_e==RAW_RD_DQ_2) - { - l_block=2; - } - else if(i_input_type_e==RAW_RD_DQ_3) - { - l_block=3; - } - else - { - l_block=4; - } - if(i_input_index_u8<=15) // 16 read delay values for DQ bits - { - l_lane=i_input_index_u8; - } - else - { - FAPI_ERR("Wrong input index specified (%d)", i_input_index_u8); - FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_SCHMOO_INVALID_INPUT); - return rc; - } - ip_type_t l_input=RAW_RD_DQ; - if(i_verbose==1) - { - FAPI_INF("block=%d",l_block); - FAPI_INF("lane=%d",l_lane); - } - rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc; - l_sbit=l_start_bit; - l_len=l_len8; - if(i_verbose==1) - { - FAPI_INF("scom_address=%llX",l_scom_add); - FAPI_INF("start bit=%d",l_start_bit); - FAPI_INF("length=%d",l_len8); - } - } - - else if(i_input_type_e==RAW_RD_DQS_0 || i_input_type_e==RAW_RD_DQS_1 || i_input_type_e==RAW_RD_DQS_2 || i_input_type_e==RAW_RD_DQS_3 || i_input_type_e==RAW_RD_DQS_4) - { - if(i_input_type_e==RAW_RD_DQS_0) - { - l_block=0; - } - else if(i_input_type_e==RAW_RD_DQS_1) - { - l_block=1; - } - else if(i_input_type_e==RAW_RD_DQS_2) - { - l_block=2; - } - else if(i_input_type_e==RAW_RD_DQS_3) - { - l_block=3; - } - else - { - l_block=4; - } - if(i_input_index_u8<=3) // 4 Read DQS delay values - { - l_lane=i_input_index_u8; - } - else - { - FAPI_ERR("Wrong input index specified (%d)", i_input_index_u8); - FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_SCHMOO_INVALID_INPUT); - return rc; - } - - ip_type_t l_input=RAW_RD_DQS; - if(i_verbose==1) - { - FAPI_INF("block=%d",l_block); - FAPI_INF("lane=%d",l_lane); - } - rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc; - l_sbit=l_start_bit; - l_len=l_len8; - if(i_verbose==1) - { - FAPI_INF("scom_address=%llX",l_scom_add); - FAPI_INF("start bit=%d",l_start_bit); - FAPI_INF("length=%d",l_len8); - } - } - - else if(i_input_type_e==RAW_DQS_ALIGN_0 || i_input_type_e==RAW_DQS_ALIGN_1 || i_input_type_e==RAW_DQS_ALIGN_2 || i_input_type_e==RAW_DQS_ALIGN_3 || i_input_type_e==RAW_DQS_ALIGN_4) - { - if(i_input_type_e==RAW_DQS_ALIGN_0) - { - l_block=0; - } - else if(i_input_type_e==RAW_DQS_ALIGN_1) - { - l_block=1; - } - else if(i_input_type_e==RAW_DQS_ALIGN_2) - { - l_block=2; - } - else if(i_input_type_e==RAW_DQS_ALIGN_3) - { - l_block=3; - } - else - { - l_block=4; - } - if(i_input_index_u8<=3) // 4 DQS alignment delay values - { - l_lane=i_input_index_u8; - } - else - { - FAPI_ERR("Wrong input index specified (%d)", i_input_index_u8); - FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_SCHMOO_INVALID_INPUT); - return rc; - } - ip_type_t l_input=RAW_DQS_ALIGN; - if(i_verbose==1) - { - FAPI_INF("block=%d",l_block); - FAPI_INF("lane=%d",l_lane); - } - rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc; - l_sbit=l_start_bit; - l_len=l_len8; - if(i_verbose==1) - { - FAPI_INF("scom_address=%llX",l_scom_add); - FAPI_INF("start bit=%d",l_start_bit); - FAPI_INF("length=%d",l_len8); - } - } - - - else if(i_input_type_e==RAW_WR_DQS_0 || i_input_type_e==RAW_WR_DQS_1 || i_input_type_e==RAW_WR_DQS_2 || i_input_type_e==RAW_WR_DQS_3 || i_input_type_e==RAW_WR_DQS_4) - { - if(i_input_type_e==RAW_WR_DQS_0) - { - l_block=0; - } - else if(i_input_type_e==RAW_WR_DQS_1) - { - l_block=1; - } - else if(i_input_type_e==RAW_WR_DQS_2) - { - l_block=2; - } - else if(i_input_type_e==RAW_WR_DQS_3) - { - l_block=3; - } - else - { - l_block=4; - } - if(i_input_index_u8<=3) // 4 Write DQS delay values - { - l_lane=i_input_index_u8; - } - else - { - FAPI_ERR("Wrong input index specified (%d)", i_input_index_u8); - FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_SCHMOO_INVALID_INPUT); - return rc; - } - ip_type_t l_input=RAW_WR_DQS; - if(i_verbose==1) - { - FAPI_INF("block=%d",l_block); - FAPI_INF("lane=%d",l_lane); - } - rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc; - l_sbit=l_start_bit; - l_len=l_len8; - if(i_verbose==1) - { - FAPI_INF("scom_address=%llX",l_scom_add); - FAPI_INF("start bit=%d",l_start_bit); - FAPI_INF("length=%d",l_len8); - } - } - else if(i_input_type_e==RAW_SYS_CLK_0 || i_input_type_e==RAW_SYS_CLK_1 || i_input_type_e==RAW_SYS_CLK_2 || i_input_type_e==RAW_SYS_CLK_3 || i_input_type_e==RAW_SYS_CLK_4) - { - if(i_input_type_e==RAW_SYS_CLK_0) - { - l_block=0; - } - else if(i_input_type_e==RAW_SYS_CLK_1) - { - l_block=1; - } - else if(i_input_type_e==RAW_SYS_CLK_2) - { - l_block=2; - } - else if(i_input_type_e==RAW_SYS_CLK_3) - { - l_block=3; - } - else - { - l_block=4; - } - if(i_input_index_u8==0) // 1 system clock delay value - { - l_lane=i_input_index_u8; - } - else - { - FAPI_ERR("Wrong input index specified (%d)", i_input_index_u8); - FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_SCHMOO_INVALID_INPUT); - return rc; - } - ip_type_t l_input=RAW_SYS_CLK; - if(i_verbose==1) - { - FAPI_INF("block=%d",l_block); - FAPI_INF("lane=%d",l_lane); - } - rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc; - l_sbit=l_start_bit; - l_len=l_len8; - if(i_verbose==1) - { - FAPI_INF("scom_address=%llX",l_scom_add); - FAPI_INF("start bit=%d",l_start_bit); - FAPI_INF("length=%d",l_len8); - } - } - - else if(i_input_type_e==RAW_SYS_ADDR_CLK) - { - if(i_input_index_u8<=1) // 1 system address clock delay value - { - l_lane=i_input_index_u8; - } - else - { - FAPI_ERR("Wrong input index specified (%d)", i_input_index_u8); - FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_SCHMOO_INVALID_INPUT); - return rc; - } - ip_type_t l_input=RAW_SYS_ADDR_CLKS0S1; - if(i_verbose==1) - { - FAPI_INF("lane=%d",l_lane); - } - rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc; - l_sbit=l_start_bit; - l_len=l_len8; - if(i_verbose==1) - { - FAPI_INF("scom_address=%llX",l_scom_add); - FAPI_INF("start bit=%d",l_start_bit); - FAPI_INF("length=%d",l_len8); - } - } - - - else if(i_input_type_e==RAW_WR_CLK_0 || i_input_type_e==RAW_WR_CLK_1 || i_input_type_e==RAW_WR_CLK_2 || i_input_type_e==RAW_WR_CLK_3 || i_input_type_e==RAW_WR_CLK_4) - { - if(i_input_type_e==RAW_WR_CLK_0) - { - l_block=0; - } - else if(i_input_type_e==RAW_WR_CLK_1) - { - l_block=1; - } - else if(i_input_type_e==RAW_WR_CLK_2) - { - l_block=2; - } - else if(i_input_type_e==RAW_WR_CLK_3) - { - l_block=3; - } - else - { - l_block=4; - } - if(i_input_index_u8==0) // 1 Write clock delay value - { - l_lane=i_input_index_u8; - } - else - { - FAPI_ERR("Wrong input index specified (%d)", i_input_index_u8); - FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_SCHMOO_INVALID_INPUT); - return rc; - } - ip_type_t l_input=RAW_WR_CLK; - if(i_verbose==1) - { - FAPI_INF("block=%d",l_block); - FAPI_INF("lane=%d",l_lane); - } - rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc; - l_sbit=l_start_bit; - l_len=l_len8; - if(i_verbose==1) - { - FAPI_INF("scom_address=%llX",l_scom_add); - FAPI_INF("start bit=%d",l_start_bit); - FAPI_INF("length=%d",l_len8); - } - } - - else if(i_input_type_e==RAW_ADDR_0 || i_input_type_e==RAW_ADDR_1 || i_input_type_e==RAW_ADDR_2 || i_input_type_e==RAW_ADDR_3) - { - if(i_input_type_e==RAW_ADDR_0) - { - l_block=0; - } - else if(i_input_type_e==RAW_ADDR_1) - { - l_block=1; - } - else if(i_input_type_e==RAW_ADDR_2) - { - l_block=2; - } - else - { - l_block=3; - } - if(i_input_index_u8<=15) // 16 Addr delay values - { - l_lane=i_input_index_u8; - } - else - { - FAPI_ERR("Wrong input index specified (%d)", i_input_index_u8); - FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_SCHMOO_INVALID_INPUT); - return rc; - } - ip_type_t l_input=RAW_ADDR; - if(i_verbose==1) - { - FAPI_INF("block=%d",l_block); - FAPI_INF("lane=%d",l_lane); - } - rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc; - l_sbit=l_start_bit; - l_len=l_len8; - if(i_verbose==1) - { - FAPI_INF("scom_address=%llX",l_scom_add); - FAPI_INF("start bit=%d",l_start_bit); - FAPI_INF("length=%d",l_len8); - } - } - - else if(i_input_type_e==RAW_DQS_GATE_0 || i_input_type_e==RAW_DQS_GATE_1 || i_input_type_e==RAW_DQS_GATE_2 || i_input_type_e==RAW_DQS_GATE_3 || i_input_type_e==RAW_DQS_GATE_4) - { - if(i_input_type_e==RAW_DQS_GATE_0) - { - l_block=0; - } - else if(i_input_type_e==RAW_DQS_GATE_1) - { - l_block=1; - } - else if(i_input_type_e==RAW_DQS_GATE_2) - { - l_block=2; - } - else if(i_input_type_e==RAW_DQS_GATE_3) - { - l_block=3; - } - else - { - l_block=4; - } - - if(i_input_index_u8<=3) // 4 Gate Delay values - { - l_lane=i_input_index_u8; - } - else - { - FAPI_ERR("Wrong input index specified (%d)", i_input_index_u8); - FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_SCHMOO_INVALID_INPUT); - return rc; - } - ip_type_t l_input=RAW_DQS_GATE; - if(i_verbose==1) - { - FAPI_INF("block=%d",l_block); - FAPI_INF("lane=%d",l_lane); - } - rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc; - l_sbit=l_start_bit; - l_len=l_len8; - if(i_verbose==1) - { - FAPI_INF("scom_address=%llX",l_scom_add); - FAPI_INF("start bit=%d",l_start_bit); - FAPI_INF("length=%d",l_len8); - } - } - - else - { - FAPI_ERR("Wrong input index specified (%d)", i_input_index_u8); - FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_SCHMOO_INVALID_INPUT); - return rc; - } - - if(i_access_type_e==READ) - { - rc=fapiGetScom(i_target_mba,l_scom_add,data_buffer_64);if(rc) return rc; - rc_num= rc_num | data_buffer_64.extractToRight(&l_output,l_sbit,l_len); - if(rc_num) - { - FAPI_ERR( "ecmd error on l_scom_add extract"); - rc.setEcmdError(rc_num); - return rc; - } - rc_num = data_buffer_32.setWord(0,l_output);if(rc_num) return rc; -io_value_u16=data_buffer_32.getHalfWord(1); - //io_value_u32=l_output; - - //FAPI_INF(" Abhijit Delay value=%d and original=%d",io_value_u16,l_output); - } - - else if(i_access_type_e==WRITE) - { - - if(i_input_type_e==RD_DQ || i_input_type_e==RD_DQS || i_input_type_e==RAW_RD_DQ_0 || i_input_type_e==RAW_RD_DQ_1 || i_input_type_e==RAW_RD_DQ_2 || i_input_type_e==RAW_RD_DQ_3 || i_input_type_e==RAW_RD_DQ_4 || i_input_type_e==RAW_RD_DQS_0 || i_input_type_e==RAW_RD_DQS_1 || i_input_type_e==RAW_RD_DQS_2 || i_input_type_e==RAW_RD_DQS_3 || i_input_type_e==RAW_RD_DQS_4 - || i_input_type_e==RAW_SYS_ADDR_CLK || i_input_type_e==RAW_SYS_CLK_0 || i_input_type_e==RAW_SYS_CLK_1 || i_input_type_e==RAW_SYS_CLK_2 || i_input_type_e==RAW_SYS_CLK_3 || i_input_type_e==RAW_SYS_CLK_4 || i_input_type_e==RAW_WR_CLK_0 || i_input_type_e==RAW_WR_CLK_1 || i_input_type_e==RAW_WR_CLK_2 || i_input_type_e==RAW_WR_CLK_3 || i_input_type_e==RAW_WR_CLK_4 - || i_input_type_e==RAW_ADDR_0 || i_input_type_e==RAW_ADDR_1 || i_input_type_e==RAW_ADDR_2 || i_input_type_e==RAW_ADDR_3 || i_input_type_e==RAW_DQS_ALIGN_0 || i_input_type_e==RAW_DQS_ALIGN_1 || i_input_type_e==RAW_DQS_ALIGN_2 || i_input_type_e==RAW_DQS_ALIGN_3 || i_input_type_e==RAW_DQS_ALIGN_4 - || i_input_type_e==DQS_ALIGN || i_input_type_e==COMMAND || i_input_type_e==ADDRESS || i_input_type_e==CONTROL || i_input_type_e==CLOCK ) - { - l_start=25; // l_start is starting bit of delay value in the register. There are different registers and each register has a different field for delay - } - else if(i_input_type_e==WR_DQ || i_input_type_e==WR_DQS || i_input_type_e==RAW_WR_DQ_0 || i_input_type_e==RAW_WR_DQ_1 || i_input_type_e==RAW_WR_DQ_2 || i_input_type_e==RAW_WR_DQ_3 || i_input_type_e==RAW_WR_DQ_4 || i_input_type_e==RAW_WR_DQS_0 || i_input_type_e==RAW_WR_DQS_1 || i_input_type_e==RAW_WR_DQS_2 || i_input_type_e==RAW_WR_DQS_3 || i_input_type_e==RAW_WR_DQS_4 ) - { - l_start=22; - } - - else if(i_input_type_e==RAW_DQS_GATE_0 || i_input_type_e==RAW_DQS_GATE_1 || i_input_type_e==RAW_DQS_GATE_2 || i_input_type_e==RAW_DQS_GATE_3 || i_input_type_e==RAW_DQS_GATE_4 || i_input_type_e==DQS_GATE) - { - l_start=29; - } - - else if(i_input_type_e==RAW_RDCLK_0 || i_input_type_e==RAW_RDCLK_1 || i_input_type_e==RAW_RDCLK_2 || i_input_type_e==RAW_RDCLK_3 || i_input_type_e==RAW_RDCLK_4 || i_input_type_e==RDCLK || i_input_type_e==RAW_DQSCLK_0 || i_input_type_e==RAW_DQSCLK_1 || i_input_type_e==RAW_DQSCLK_2 || i_input_type_e==RAW_DQSCLK_3 || i_input_type_e==RAW_DQSCLK_4 || i_input_type_e==DQSCLK) - { - l_start=30; - } - - else if(i_input_type_e==DATA_DISABLE) - { - l_start=16; - } - - else - { - FAPI_ERR("Wrong input type specified (%d)", i_input_type_e); - FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_SCHMOO_INVALID_INPUT); - return rc; - } - if(i_verbose==1) - { - FAPI_INF("value given=%d",io_value_u16); - } - rc_num = data_buffer_32.setHalfWord(1,io_value_u16);if(rc_num) return rc; - l_value_u32 = data_buffer_32.getWord(0); - - // FAPI_INF("\n Abhijit the original passed=%d and the changed=%d ",io_value_u16,l_value_u32); - rc=fapiGetScom(i_target_mba,l_scom_add,data_buffer_64);if(rc) return rc; - rc_num=data_buffer_64.insert(l_value_u32,l_sbit,l_len,l_start); - if(rc_num) - { - FAPI_ERR( "ecmd error on l_scom_add extract"); - rc.setEcmdError(rc_num); - return rc; - } - rc=fapiPutScom(i_target_mba,l_scom_add,data_buffer_64); if(rc) return rc; - } - return rc; -} - -} // extern "C" diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_access_delay_reg.H b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_access_delay_reg.H deleted file mode 100644 index 6cb8156fe..000000000 --- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_access_delay_reg.H +++ /dev/null @@ -1,355 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_access_delay_reg.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2012,2014 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -//$Id: mss_access_delay_reg.H,v 1.12 2014/01/24 17:22:16 sasethur Exp $ -//------------------------------------------------------------------------------ -// *! (C) Copyright International Business Machines Corp. 2011 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -//------------------------------------------------------------------------------ -// *! TITLE : mss_demo_access_delay_reg.H -// *! DESCRIPTION : Header file for mss_access_delay_reg. -// *! OWNER NAME : Saurabh Chadha Email: sauchadh@in.ibm.com -// *! ADDITIONAL COMMENTS : -// -// -// -//------------------------------------------------------------------------------ -// Don't forget to create CVS comments when you check in your changes! -//------------------------------------------------------------------------------ -// CHANGE HISTORY: -//------------------------------------------------------------------------------ -// Version:| Author: | Date: | Comment: -//---------|----------|---------|----------------------------------------------- -// 1.12 | mjjones |20-Jan-14| RAS Review Updates -// 1.1 | sauchadh |15-Oct-12| First Draft. -//------------------------------------------------------------------------------ - - -#ifndef MSS_ACCESS_DELAY_REG_H_ -#define MSS_ACCESS_DELAY_REG_H_ - -//------------------------------------------------------------------------------ -// My Includes -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Includes -//------------------------------------------------------------------------------ -#include <fapi.H> - - -//---------------------------------------------------------------------- -// ENUMs -//---------------------------------------------------------------------- -enum access_type_t { - READ = 0, - WRITE = 1 -}; - -enum input_type_t { - WR_DQ, - RAW_WR_DQ_0, - RAW_WR_DQ_1, - RAW_WR_DQ_2, - RAW_WR_DQ_3, - RAW_WR_DQ_4, - RD_DQ, - RAW_RD_DQ_0, - RAW_RD_DQ_1, - RAW_RD_DQ_2, - RAW_RD_DQ_3, - RAW_RD_DQ_4, - WR_DQS, - RAW_WR_DQS_0, - RAW_WR_DQS_1, - RAW_WR_DQS_2, - RAW_WR_DQS_3, - RAW_WR_DQS_4, - RD_DQS, - RAW_RD_DQS_0, - RAW_RD_DQS_1, - RAW_RD_DQS_2, - RAW_RD_DQS_3, - RAW_RD_DQS_4, - RAW_SYS_ADDR_CLK, - RAW_SYS_CLK_0, - RAW_SYS_CLK_1, - RAW_SYS_CLK_2, - RAW_SYS_CLK_3, - RAW_SYS_CLK_4, - RAW_WR_CLK_0, - RAW_WR_CLK_1, - RAW_WR_CLK_2, - RAW_WR_CLK_3, - RAW_WR_CLK_4, - RAW_ADDR_0, - RAW_ADDR_1, - RAW_ADDR_2, - RAW_ADDR_3, - DQS_GATE, - RAW_DQS_GATE_0, - RAW_DQS_GATE_1, - RAW_DQS_GATE_2, - RAW_DQS_GATE_3, - RAW_DQS_GATE_4, - DQS_ALIGN, - RAW_DQS_ALIGN_0, - RAW_DQS_ALIGN_1, - RAW_DQS_ALIGN_2, - RAW_DQS_ALIGN_3, - RAW_DQS_ALIGN_4, - RAW_RDCLK_0, - RAW_RDCLK_1, - RAW_RDCLK_2, - RAW_RDCLK_3, - RAW_RDCLK_4, - RDCLK, - RAW_DQSCLK_0, - RAW_DQSCLK_1, - RAW_DQSCLK_2, - RAW_DQSCLK_3, - RAW_DQSCLK_4, - DQSCLK, - COMMAND, - CONTROL, - CLOCK, - ADDRESS, - DATA_DISABLE - }; - -enum ip_type_t { - WR_DQ_t, - RAW_WR_DQ, - RD_DQ_t, - RAW_RD_DQ, - WR_DQS_t, - RAW_WR_DQS, - RD_DQS_t, - RAW_RD_DQS, - RD_CLK_t, - RAW_SYS_ADDR_CLKS0S1, - RAW_SYS_CLK, - RAW_WR_CLK, - RAW_ADDR, - DQS_GATE_t, - RAW_DQS_GATE, - DQS_ALIGN_t, - RAW_DQS_ALIGN, - RDCLK_t, - RAW_RDCLK, - DQSCLK_t, - RAW_DQSCLK, - COMMAND_t, - CONTROL_t, - CLOCK_t, - ADDRESS_t, - DATA_DISABLE_t -}; - - -enum input_type { - ISDIMM_DQ, - ISDIMM_DQS, - CDIMM_DQS, - CDIMM_DQ, - GL_NET_DQ, - GL_NET_DQS -}; - -struct scom_location { - uint64_t scom_addr; - uint8_t start_bit; - uint8_t bit_length; -}; - - -typedef fapi::ReturnCode (*mss_access_delay_reg_FP_t)(const fapi::Target &, - access_type_t, - uint8_t, - uint8_t, - input_type_t, - uint8_t, - uint8_t, - uint32_t &); - -extern "C" { - -/** - * @brief Reads or Writes delay values - * - * @param[in] i_target_mba Reference to centaur.mba target - * @param[in] i_access_type_e Access type (READ or WRITE) - * @param[in] i_port_u8 Port number - * @param[in] i_rank_u8 Rank number - * @param[in] i_input_type_e Input type (from input_type_t) - * @param[in] i_input_index_u8 Input index - * @param[in] i_verbose 1 = Verbose tracing - * @param[io] io_value_u32 READ=input, WRITE=output - * - * @return ReturnCode - */ -fapi::ReturnCode mss_access_delay_reg_schmoo(const fapi::Target & i_target_mba, - access_type_t i_access_type_e, - uint8_t i_port_u8, - uint8_t i_rank_u8, - input_type_t i_input_type_e, - uint8_t i_input_index_u8, - uint8_t i_verbose, - uint16_t &io_value_u32); - -/** - * @brief Reads or Writes delay values - * - * @param[in] i_target_mba Reference to centaur.mba target - * @param[in] i_access_type_e Access type (READ or WRITE) - * @param[in] i_port_u8 Port number - * @param[in] i_rank_u8 Rank number - * @param[in] i_input_type_e Input type (from input_type_t) - * @param[in] i_input_index_u8 Input index - * @param[in] i_verbose 1 = Verbose tracing - * @param[io] io_value_u32 READ=input, WRITE=output - * - * @return ReturnCode - */ -fapi::ReturnCode mss_access_delay_reg(const fapi::Target & i_target_mba, - access_type_t i_access_type_e, - uint8_t i_port_u8, - uint8_t i_rank_u8, - input_type_t i_input_type_e, - uint8_t i_input_index_u8, - uint8_t i_verbose, - uint32_t &io_value_u32); - -/** - * @brief cross_coupled - * - * @param[in] i_target_mba Reference to centaur.mba target - * @param[in] i_port Port number - * @param[in] i_rank_pair Rank pair - * @param[in] i_input_type_e Input type (from input_type_t) - * @param[in] i_input_index Input index - * @param[in] i_verbose 1 = Verbose tracing - * @param[out] out Output - * - * @return ReturnCode - */ -fapi::ReturnCode cross_coupled(const fapi::Target & i_target_mba, - uint8_t i_port, - uint8_t i_rank_pair, - input_type_t i_input_type_e, - uint8_t i_input_index, - uint8_t i_verbose, - scom_location& out); - -/** - * @brief mss_c4_phy - * - * @param[in] i_target_mba Reference to centaur.mba target - * @param[in] i_port Port number - * @param[in] i_rank_pair Rank pair - * @param[in] i_input_type_e Input type (from input_type_t) - * @param[in] i_input_index Input index - * @param[in] i_verbose 1 = Verbose tracing - * @param[io] phy_lane PHY Lane - * @param[io] phy_block PHY Block - * @param[in] flag Flag - * - * @return ReturnCode - */ -fapi::ReturnCode mss_c4_phy(const fapi::Target & i_target_mba, - uint8_t i_port, - uint8_t i_rank_pair, - input_type_t i_input_type_e, - uint8_t &i_input_index, - uint8_t i_verbose, - uint8_t &phy_lane, - uint8_t &phy_block, - uint8_t flag); - -/** - * @brief get_address - * - * @param[in] i_target_mba Reference to centaur.mba target - * @param[in] i_port Port number - * @param[in] i_rank_pair Rank pair - * @param[in] i_input_type_e Input type (from input_type_t) - * @param[in] i_block Block - * @param[in] i_lane Lane - * @param[out] o_scom_address_64 Output scom address - * @param[out] o_start_bit Output Start bit - * @param[out] o_len Output length - * - * @return ReturnCode - */ -fapi::ReturnCode get_address(const fapi::Target & i_target_mba, - uint8_t i_port, - uint8_t i_rank_pair, - ip_type_t i_input_type_e, - uint8_t i_block, - uint8_t i_lane, - uint64_t &o_scom_address_64, - uint8_t &o_start_bit, - uint8_t &o_len); - -/** - * @brief Returns C4 bit for the corresponding ISDIMM bit - * - * @param[in] i_target_mba Reference to centaur.mba target - * @param[in] i_port Port number - * @param[in] i_input_type_e Input type (from input_type_t) - * @param[in] i_input_index Input index - * @param[in] i_verbose 1 = Verbose tracing - * @param[out] o_value Output C4 bit - * - * @return ReturnCode - */ -fapi::ReturnCode rosetta_map(const fapi::Target & i_target_mba, - uint8_t i_port, - input_type i_input_type_e, - uint8_t i_input_index, - uint8_t i_verbose, - uint8_t &o_value); - -/** - * @brief Gets the rank pair - * - * @param[in] i_target_mba Reference to centaur.mba target - * @param[in] i_port Port - * @param[in] i_rank Rank - * @param[out] o_rank_pair Output rank pair - * @param[out] o_rankpair_table Output rank pair table - * - * @return ReturnCode - */ -fapi::ReturnCode mss_getrankpair(const fapi::Target & i_target_mba, - uint8_t i_port, - uint8_t i_rank, - uint8_t *o_rank_pair, - uint8_t o_rankpair_table[]); - -} // extern "C" - -#endif // MSS_ACCESS_DELAY_REG_H - diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_ddr4_funcs.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_ddr4_funcs.C deleted file mode 100644 index 9454c344d..000000000 --- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_ddr4_funcs.C +++ /dev/null @@ -1,2447 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_ddr4_funcs.C $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2015 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: mss_ddr4_funcs.C,v 1.15 2015/08/28 18:15:08 sglancy Exp $ -//------------------------------------------------------------------------------ -// *! (C) Copyright International Business Machines Corp. 2013 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -//------------------------------------------------------------------------------ -// *! TITLE : mss_ddr4_funcs.C -// *! DESCRIPTION : Tools for DDR4 DIMMs centaur procedures -// *! OWNER NAME : jdsloat@us.ibm.com -// *! BACKUP NAME : sglancy@us.ibm.com -// #! ADDITIONAL COMMENTS : -// - -//------------------------------------------------------------------------------ -// Don't forget to create CVS comments when you check in your changes! -//------------------------------------------------------------------------------ -// CHANGE HISTORY: -//------------------------------------------------------------------------------ -// Version:| Author: | Date: | Comment: -//---------|----------|---------|----------------------------------------------- -// | | | -// 1.15 | 08/28/15 | sglancy | Added RCs - addressed FW comments -// 1.14 | 08/21/15 | sglancy | Fixed ODT initialization bug - ODT must be held low through ZQ cal -// 1.13 | 08/05/15 | kmack | Commented out FAPI_DDR4 code -// 1.12 | 07/31/15 | kmack | Mostly removed and changed comments. Reviewed some questions about the code. No real functional changes -// | | | Need new ATTRIBUTE, see comments with FIXME -// 1.11 | 07/15/15 | sglancy | Addeded DDR4 Register functions and changes for DDR4 LRDIMM -// 1.10 | 05/14/15 | sglancy | Addeded DDR4 Register functions and changes for DDR4 3DS -// 1.7 | 03/14/14 | kcook | Addeded DDR4 Register functions -// 1.6 | 01/10/14 | kcook | Updated Address mirroring swizzle (removed DIMM_TYPE_CDIMM) and -// | | | added DDR4 RDIMM support -// 1.5 | 12/03/13 | kcook | Updated VPD attributes. -// 1.4 | 11/27/13 | bellows | Added using namespace fapi -// 1.3 | 10/10/13 | bellows | Added required cvs id tag -// 1.2 | 10/09/13 | jdsloat | Added CONSTs -// 1.1 | 10/04/13 | jdsloat | First revision - - -//---------------------------------------------------------------------- -// Includes -//---------------------------------------------------------------------- -#include <fapi.H> -#include <mss_funcs.H> -#include <cen_scom_addresses.H> -#include <mss_ddr4_funcs.H> - -using namespace fapi; - -//#ifdef FAPI_DDR4 - -const uint8_t MAX_NUM_DIMMS = 2; -const uint8_t MRS0_BA = 0; -const uint8_t MRS1_BA = 1; -const uint8_t MRS2_BA = 2; -const uint8_t MRS3_BA = 3; -const uint8_t MRS4_BA = 4; -const uint8_t MRS5_BA = 5; -const uint8_t MRS6_BA = 6; - -const uint8_t PORT_SIZE = 2; - -ReturnCode mss_ddr4_invert_mpr_write( Target& i_target_mba) { - ReturnCode rc; - uint32_t rank_number; - - ReturnCode rc_buff; - uint32_t rc_num = 0; - - ecmdDataBufferBase address_16(16); - ecmdDataBufferBase bank_3(3); - ecmdDataBufferBase activate_1(1); - rc_num = rc_num | activate_1.setBit(0); - ecmdDataBufferBase rasn_1(1); - rc_num = rc_num | rasn_1.clearBit(0); - ecmdDataBufferBase casn_1(1); - rc_num = rc_num | casn_1.clearBit(0); - ecmdDataBufferBase wen_1(1); - rc_num = rc_num | wen_1.clearBit(0); - ecmdDataBufferBase cke_4(4); - rc_num = rc_num | cke_4.setBit(0,4); - ecmdDataBufferBase csn_8(8); - rc_num = rc_num | csn_8.setBit(0,8); - ecmdDataBufferBase odt_4(4); - rc_num = rc_num | odt_4.clearBit(0,4); - ecmdDataBufferBase ddr_cal_type_4(4); - - ecmdDataBufferBase num_idles_16(16); - ecmdDataBufferBase num_repeat_16(16); - ecmdDataBufferBase data_20(20); - ecmdDataBufferBase read_compare_1(1); - ecmdDataBufferBase rank_cal_4(4); - ecmdDataBufferBase ddr_cal_enable_1(1); - ecmdDataBufferBase ccs_end_1(1); - - ecmdDataBufferBase mrs3(16); - uint16_t MRS3 = 0; - uint8_t mpr_op; // MPR Op - - ecmdDataBufferBase data_buffer(64); - - uint32_t io_ccs_inst_cnt = 0; - - uint16_t num_ranks = 0; - uint8_t mpr_pattern = 0xAA; - - if(rc_num) - { - rc.setEcmdError(rc_num); - return rc; - } - - uint8_t num_ranks_array[2][2]; //[port][dimm] - rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target_mba, num_ranks_array); - if(rc) return rc; - - uint8_t num_master_ranks_array[2][2]; //[port][dimm] - rc = FAPI_ATTR_GET(ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM, &i_target_mba, num_master_ranks_array); - if(rc) return rc; - - uint8_t is_sim = 0; - rc = FAPI_ATTR_GET(ATTR_IS_SIMULATION, NULL, is_sim); - if(rc) return rc; - - uint8_t address_mirror_map[2][2]; //address_mirror_map[port][dimm] - rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_ADDRESS_MIRRORING, &i_target_mba, address_mirror_map); - if(rc) return rc; - - uint8_t dram_stack[2][2]; - rc = FAPI_ATTR_GET(ATTR_EFF_STACK_TYPE, &i_target_mba, dram_stack); - if(rc) return rc; - - for (uint8_t l_port = 0; l_port < PORT_SIZE; l_port++) { - // Raise CKE high with NOPS, waiting min Reset CKE exit time (tXPR) - 400 cycles - rc_num = rc_num | csn_8.setBit(0,8); - rc_num = rc_num | address_16.clearBit(0, 16); - rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 400, 0, 16); - - FAPI_INF( "Stack Type in mss_ddr4_invert_mpr_write : %d\n", dram_stack[0][0]); - if (dram_stack[0][0] == ENUM_ATTR_EFF_STACK_TYPE_STACK_3DS) - { - FAPI_INF( "============= Got in the 3DS stack loop =====================\n"); - rc_num = rc_num | csn_8.clearBit(2,2); - rc_num = rc_num | csn_8.clearBit(6,2); - // COMMENT IN LATER!!!!!! rc_num = rc_num | cke_4.clearBit(1); - } - - if(rc_num) - { - rc.setEcmdError(rc_num); - return rc; - } - rc = mss_ccs_inst_arry_0( i_target_mba, - io_ccs_inst_cnt, - address_16, - bank_3, - activate_1, - rasn_1, - casn_1, - wen_1, - cke_4, - csn_8, - odt_4, - ddr_cal_type_4, - l_port); - if(rc) return rc; - rc = mss_ccs_inst_arry_1( i_target_mba, - io_ccs_inst_cnt, - num_idles_16, - num_repeat_16, - data_20, - read_compare_1, - rank_cal_4, - ddr_cal_enable_1, - ccs_end_1); - if(rc) return rc; - io_ccs_inst_cnt ++; - - for (uint8_t l_dimm = 0; l_dimm < MAX_NUM_DIMMS; l_dimm++) { - if (dram_stack[0][0] == ENUM_ATTR_EFF_STACK_TYPE_STACK_3DS) - { - num_ranks = num_master_ranks_array[l_port][l_dimm]; - } - else { - num_ranks = num_ranks_array[l_port][l_dimm]; - } - - if (num_ranks == 0) - { - FAPI_INF( "PORT%d DIMM%d not configured. Num_ranks: %d ", l_port, l_dimm, num_ranks); - } - else - { - // Rank 0-3 - for ( rank_number = 0; rank_number < num_ranks; rank_number++) - { - - rc_num = rc_num | csn_8.setBit(0,8); - rc_num = rc_num | csn_8.clearBit(rank_number+4*l_dimm); - rc_num = rc_num | address_16.clearBit(0, 16); - - // MRS CMD to CMD spacing = 12 cycles - rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 24, 0, 16); - if(rc_num) - { - rc.setEcmdError(rc_num); - return rc; - } - - if (l_port == 0) { - rc = fapiGetScom(i_target_mba, DPHY01_DDRPHY_PC_MR3_PRI_RP0_P0_0x8000C01F0301143F, data_buffer); // Need to look up Rank Group??? - if(rc) return rc; - } - else if ( l_port == 1 ) { - rc = fapiGetScom(i_target_mba, DPHY01_DDRPHY_PC_MR3_PRI_RP0_P1_0x8001C01F0301143F, data_buffer); // Need to look up Rank Group??? - if(rc) return rc; - } - - rc_num = rc_num | data_buffer.reverse(); - rc_num = rc_num | mrs3.insert(data_buffer, 0, 16, 0); - rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0); - - if(rc_num) - { - rc.setEcmdError(rc_num); - return rc; - } - - FAPI_INF( "CURRENT MRS 3: 0x%04X", MRS3); - - mpr_op = 0xff; - - rc_num = rc_num | mrs3.insert((uint8_t) mpr_op, 2, 1); - - rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0); - FAPI_INF( "Set data flow from MPR, New MRS 3: 0x%04X", MRS3); - - if (rc_num) - { - FAPI_ERR( " Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - - - rc_num = rc_num | address_16.insert(mrs3, 0, 16, 0); - rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 0, 1, 7); - rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 1, 1, 6); - rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 2, 1, 5); - - // Indicate B-Side DRAMS BG1=1 - rc_num = rc_num | address_16.setBit(15); // Set BG1 = 1 - - rc_num = rc_num | address_16.flipBit(3,7); // Invert A3:A9 - rc_num = rc_num | address_16.flipBit(11); // Invert A11 - rc_num = rc_num | address_16.flipBit(13); // Invert A13 - rc_num = rc_num | address_16.flipBit(14); // Invert A17 - rc_num = rc_num | bank_3.flipBit(0,3); // Invert BA0,BA1,BG0 - - if (rc_num) - { - FAPI_ERR( " Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - - - if (( address_mirror_map[l_port][l_dimm] & (0x08 >> rank_number) ) && (is_sim == 0)) - { - rc = mss_address_mirror_swizzle(i_target_mba, l_port, l_dimm, rank_number, address_16, bank_3); - if(rc) return rc; - } - - // Send out to the CCS array - rc = mss_ccs_inst_arry_0( i_target_mba, - io_ccs_inst_cnt, - address_16, - bank_3, - activate_1, - rasn_1, - casn_1, - wen_1, - cke_4, - csn_8, - odt_4, - ddr_cal_type_4, - l_port); - if(rc) return rc; - rc = mss_ccs_inst_arry_1( i_target_mba, - io_ccs_inst_cnt, - num_idles_16, - num_repeat_16, - data_20, - read_compare_1, - rank_cal_4, - ddr_cal_enable_1, - ccs_end_1); - if(rc) return rc; - io_ccs_inst_cnt ++; - - - // Write pattern to MPR register - //Command structure setup - rc_num = rc_num | cke_4.flushTo1(); - rc_num = rc_num | rasn_1.setBit(0); - rc_num = rc_num | casn_1.clearBit(0); - rc_num = rc_num | wen_1.clearBit(0); - - - //Final setup - rc_num = rc_num | odt_4.flushTo0(); - rc_num = rc_num | ddr_cal_type_4.flushTo0(); - rc_num = rc_num | activate_1.setBit(0); - - - //CCS Array 1 Setup - rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 24, 0, 16); - rc_num = rc_num | num_repeat_16.flushTo0(); - rc_num = rc_num | data_20.flushTo0(); - rc_num = rc_num | read_compare_1.flushTo0(); - rc_num = rc_num | rank_cal_4.flushTo0(); - rc_num = rc_num | ddr_cal_enable_1.flushTo0(); - rc_num = rc_num | ccs_end_1.flushTo0(); - - rc_num = rc_num | address_16.clearBit(0, 16); - rc_num = rc_num | address_16.insertFromRight(mpr_pattern,0, 8); - - rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 0, 1, 7); - rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 1, 1, 6); - rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 2, 1, 5); - - // Indicate B-Side DRAMS BG1=1 - rc_num = rc_num | address_16.setBit(15); // Set BG1 = 1 - - rc_num = rc_num | address_16.flipBit(3,7); // Invert A3:A9 - rc_num = rc_num | address_16.flipBit(11); // Invert A11 - rc_num = rc_num | address_16.flipBit(13); // Invert A13 - rc_num = rc_num | address_16.flipBit(14); // Invert A17 - rc_num = rc_num | bank_3.flipBit(0,3); // Invert BA0,BA1,BG0 - - if (rc_num) - { - FAPI_ERR( " Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - - - if (( address_mirror_map[l_port][l_dimm] & (0x08 >> rank_number) ) && (is_sim == 0)) - { - rc = mss_address_mirror_swizzle(i_target_mba, l_port, l_dimm, rank_number, address_16, bank_3); - if(rc) return rc; - } - - FAPI_INF( "Writing MPR register with 0101 pattern"); - // Send out to the CCS array - rc = mss_ccs_inst_arry_0( i_target_mba, - io_ccs_inst_cnt, - address_16, - bank_3, - activate_1, - rasn_1, - casn_1, - wen_1, - cke_4, - csn_8, - odt_4, - ddr_cal_type_4, - l_port); - if(rc) return rc; - rc = mss_ccs_inst_arry_1( i_target_mba, - io_ccs_inst_cnt, - num_idles_16, - num_repeat_16, - data_20, - read_compare_1, - rank_cal_4, - ddr_cal_enable_1, - ccs_end_1); - if(rc) return rc; - io_ccs_inst_cnt ++; - - // Restore MR3 to normal MPR operation - //Command structure setup - rc_num = rc_num | cke_4.flushTo1(); - rc_num = rc_num | rasn_1.clearBit(0); - rc_num = rc_num | casn_1.clearBit(0); - rc_num = rc_num | wen_1.clearBit(0); - - rc_num = rc_num | read_compare_1.clearBit(0); - - rc_num = rc_num | odt_4.flushTo0(); - rc_num = rc_num | ddr_cal_type_4.flushTo0(); - rc_num = rc_num | activate_1.setBit(0); - - rc_num = rc_num | num_repeat_16.flushTo0(); - rc_num = rc_num | data_20.flushTo0(); - rc_num = rc_num | read_compare_1.flushTo0(); - rc_num = rc_num | rank_cal_4.flushTo0(); - rc_num = rc_num | ddr_cal_enable_1.flushTo0(); - rc_num = rc_num | ccs_end_1.flushTo0(); - - rc_num = rc_num | address_16.clearBit(0, 16); - - // MRS CMD to CMD spacing = 12 cycles - rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 24, 0, 16); - if(rc_num) - { - rc.setEcmdError(rc_num); - return rc; - } - - if (l_port == 0) { - rc = fapiGetScom(i_target_mba, DPHY01_DDRPHY_PC_MR3_PRI_RP0_P0_0x8000C01F0301143F, data_buffer); // Need to look up Rank Group??? - if(rc) return rc; - } - else if ( l_port == 1 ) { - rc = fapiGetScom(i_target_mba, DPHY01_DDRPHY_PC_MR3_PRI_RP0_P1_0x8001C01F0301143F, data_buffer); // Need to look up Rank Group??? - if(rc) return rc; - } - - rc_num = rc_num | data_buffer.reverse(); - rc_num = rc_num | mrs3.insert(data_buffer, 0, 16, 0); - rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0); - - if(rc_num) - { - rc.setEcmdError(rc_num); - return rc; - } - - FAPI_INF( "CURRENT MRS 3: 0x%04X", MRS3); - - mpr_op = 0x00; - - rc_num = rc_num | mrs3.insert((uint8_t) mpr_op, 2, 1); - - rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0); - FAPI_INF( "Set data flow from MPR, New MRS 3: 0x%04X", MRS3); - - if (rc_num) - { - FAPI_ERR( " Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - - - rc_num = rc_num | address_16.insert(mrs3, 0, 16, 0); - rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 0, 1, 7); - rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 1, 1, 6); - rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 2, 1, 5); - - // Indicate B-Side DRAMS BG1=1 - rc_num = rc_num | address_16.setBit(15); // Set BG1 = 1 - - rc_num = rc_num | address_16.flipBit(3,7); // Invert A3:A9 - rc_num = rc_num | address_16.flipBit(11); // Invert A11 - rc_num = rc_num | address_16.flipBit(13); // Invert A13 - rc_num = rc_num | address_16.flipBit(14); // Invert A17 - rc_num = rc_num | bank_3.flipBit(0,3); // Invert BA0,BA1,BG0 - - - if (( address_mirror_map[l_port][l_dimm] & (0x08 >> rank_number) ) && (is_sim == 0)) - { - rc = mss_address_mirror_swizzle(i_target_mba, l_port, l_dimm, rank_number, address_16, bank_3); - if(rc) return rc; - } - - - if (rc_num) - { - FAPI_ERR( " Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - - // Send out to the CCS array - rc = mss_ccs_inst_arry_0( i_target_mba, - io_ccs_inst_cnt, - address_16, - bank_3, - activate_1, - rasn_1, - casn_1, - wen_1, - cke_4, - csn_8, - odt_4, - ddr_cal_type_4, - l_port); - if(rc) return rc; - rc = mss_ccs_inst_arry_1( i_target_mba, - io_ccs_inst_cnt, - num_idles_16, - num_repeat_16, - data_20, - read_compare_1, - rank_cal_4, - ddr_cal_enable_1, - ccs_end_1); - if(rc) return rc; - io_ccs_inst_cnt ++; - - } - } - } - } - - uint32_t NUM_POLL = 100; - rc = mss_execute_ccs_inst_array( i_target_mba, NUM_POLL, 60); - - return rc; -} - -ReturnCode mss_create_rcd_ddr4(const Target& i_target_mba) { - ReturnCode rc; - uint32_t rc_num = 0; - - uint8_t l_rcd_cntl_word_0_1; - uint8_t l_rcd_cntl_word_2; - uint8_t l_rcd_cntl_word_3; - uint8_t l_rcd_cntl_word_4; - uint8_t l_rcd_cntl_word_5; - uint8_t l_rcd_cntl_word_6_7; - uint8_t l_rcd_cntl_word_8_9; - uint8_t l_rcd_cntl_word_10; - uint8_t l_rcd_cntl_word_11; - uint8_t l_rcd_cntl_word_12; - uint8_t l_rcd_cntl_word_13; - uint8_t l_rcd_cntl_word_14; - uint8_t l_rcd_cntl_word_15; - uint64_t l_rcd_cntl_word_0_15; - uint8_t stack_type[PORT_SIZE][MAX_NUM_DIMMS]; - uint64_t l_attr_eff_dimm_rcd_cntl_word_0_15[PORT_SIZE][MAX_NUM_DIMMS]; - uint8_t l_num_ranks_per_dimm_u8array[PORT_SIZE][MAX_NUM_DIMMS]; - uint8_t l_num_master_ranks_per_dimm_u8array[PORT_SIZE][MAX_NUM_DIMMS]; - uint8_t l_dimm_type_u8; - uint8_t l_dram_width_u8; - ecmdDataBufferBase data_buffer_8(8); - ecmdDataBufferBase data_buffer_64(64); - - - rc = FAPI_ATTR_GET(ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM,&i_target_mba, l_num_master_ranks_per_dimm_u8array); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_STACK_TYPE, &i_target_mba, stack_type); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target_mba, l_dimm_type_u8); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_RCD_CNTL_WORD_0_15, &i_target_mba, l_attr_eff_dimm_rcd_cntl_word_0_15); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target_mba, l_num_ranks_per_dimm_u8array); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target_mba, l_dram_width_u8); if(rc) return rc; - - uint64_t l_attr_eff_dimm_cntl_word_x; - - uint8_t l_rcd_cntl_word_1x; - uint8_t l_rcd_cntl_word_2x; - uint8_t l_rcd_cntl_word_3x; - uint8_t l_rcd_cntl_word_7x; - uint8_t l_rcd_cntl_word_8x; - uint8_t l_rcd_cntl_word_9x; - uint8_t l_rcd_cntl_word_Ax; - uint8_t l_rcd_cntl_word_Bx; - - //FIXME: ATTR_MCBIST_MAX_TIMEOUT is being used until firmware is ready with a new attribute, ATTR_EFF_LRDIMM_WORD_X (subject to change) - rc = FAPI_ATTR_GET(ATTR_MCBIST_MAX_TIMEOUT, &i_target_mba, l_attr_eff_dimm_cntl_word_x); if(rc) return rc; - - fapi::Target l_target_centaur; - uint32_t l_mss_freq = 0; - uint32_t l_mss_volt = 0; - rc = fapiGetParentChip(i_target_mba, l_target_centaur); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_MSS_FREQ, &l_target_centaur, l_mss_freq); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_MSS_VOLT, &l_target_centaur, l_mss_volt); if(rc) return rc; - - for (uint8_t l_port = 0; l_port < PORT_SIZE; l_port++) { - for (uint8_t l_dimm = 0; l_dimm < MAX_NUM_DIMMS; l_dimm++) { - - // Global Features, Clock Driver Enable Control Words - l_rcd_cntl_word_0_1 = 0x00; - - // Timing and IBT Control Word - l_rcd_cntl_word_2 = 0; - - // CA and CS Signals Driver Characteristics Control Word - if (l_num_ranks_per_dimm_u8array[l_port][l_dimm] > 1) { - l_rcd_cntl_word_3 = 6; // QxCS0_n...QxCS3_n Outputs strong drive, Address/Command moderate drive - } else { - l_rcd_cntl_word_3 = 5; // QxCS0_n...QxCS3_n Outputs moderate drive, Address/Command moderate drive - } - - l_rcd_cntl_word_4 = 5; // QxODT0...QxODT1 and QxCKE0...QxCKE1 Output Drivers moderate drive - l_rcd_cntl_word_5 = 5; // Clock Y1_t, Y1_c, Y3_t, Y3_c and Y0_t, Y0_c, Y2_t, Y2_c Output Drivers moderate drive - - // Command Space Control Word - l_rcd_cntl_word_6_7 = 0xf0; // No op - // Input/Output Configuration, Power Saving Settings Control Words - if(stack_type[l_port][l_dimm] == ENUM_ATTR_EFF_STACK_TYPE_STACK_3DS) { - //no master ranks found, then program to disable all CIDs - //master ranks should always be found so this is a bit weird - might want to throw an error here - if(l_num_master_ranks_per_dimm_u8array[l_port][l_dimm] == 0) { - l_rcd_cntl_word_8_9 = 0x30; - } - //determine stack density - 2H, 4H, or 8H - else { - uint8_t stack_height = l_num_ranks_per_dimm_u8array[l_port][l_dimm] / l_num_master_ranks_per_dimm_u8array[l_port][l_dimm]; - FAPI_INF("3DS RCD set stack_height: %d",stack_height); - if(stack_height == 8) { - l_rcd_cntl_word_8_9 = 0x00; - } - else if(stack_height == 4) { - l_rcd_cntl_word_8_9 = 0x10; - } - else if(stack_height == 2) { - l_rcd_cntl_word_8_9 = 0x20; - } - //weird, we shouldn't have 1H stacks - else { - l_rcd_cntl_word_8_9 = 0x30; - } - } - } - - //LR DIMM and 4 ranks - else if(l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM && l_num_ranks_per_dimm_u8array[l_port][l_dimm] == 4) { - FAPI_INF("Creating RCD value for F0rC08 - LRDDIMM and 4 ranks -> 0x10"); - l_rcd_cntl_word_8_9 = 0x10; - } - else { - l_rcd_cntl_word_8_9 = 0x30; - } - - // RDIMM Operating Speed Control Word - if ( l_mss_freq <= 1733 ) { // 1600 - l_rcd_cntl_word_10 = 0; - } else if ( l_mss_freq <= 2000 ) { // 1866 - l_rcd_cntl_word_10 = 1; - } else if ( l_mss_freq <= 2266 ) { // 2133 - l_rcd_cntl_word_10 = 2; - } else if ( l_mss_freq <= 2533 ) { // 2400 - l_rcd_cntl_word_10 = 3; - } else if ( l_mss_freq <= 2800 ) { // 2666 - l_rcd_cntl_word_10 = 4; - } else if ( l_mss_freq <= 3333 ) { // 3200 - l_rcd_cntl_word_10 = 5; - } else { - FAPI_ERR("Invalid LRDIMM ATTR_MSS_FREQ = %d on %s!", l_mss_freq, i_target_mba.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; - } - - // Operating Voltage VDD and VREFCA Source Control Word - if ( l_mss_volt >= 1120 ) { // 1.2V - l_rcd_cntl_word_11 = 14; - } else if ( l_mss_volt >= 1020 ) { // 1.0xV - l_rcd_cntl_word_11 = 15; - } else { - FAPI_ERR("Invalid LRDIMM ATTR_MSS_VOLT = %d on %s!", l_mss_volt, i_target_mba.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; - } - - // Training Control Word - l_rcd_cntl_word_12 = 0; - - // DIMM Configuration Control words - data_buffer_8.clearBit(0,8); - if ( l_num_ranks_per_dimm_u8array[l_port][l_dimm] == 4 ) { - rc_num |= data_buffer_8.setBit(3); // Direct QuadCS mode - } - if ( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM ) { - rc_num |= data_buffer_8.setBit(1); - } - if ( l_num_ranks_per_dimm_u8array[l_port][l_dimm] > 1 ) { - rc_num |= data_buffer_8.setBit(0); // Address mirroring for MRS commands - } - - rc_num |= data_buffer_8.extractToRight( &l_rcd_cntl_word_13, 0, 4); - - // Parity Control Word - l_rcd_cntl_word_14 = 0; - - // Command Latency Adder Control Word - if ( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM ) { - l_rcd_cntl_word_15 = 4; // 0nCk latency adder - } - else { - l_rcd_cntl_word_15 = 0; // 1nCk latency adder with DB control bus - } - - rc_num |= data_buffer_64.insertFromRight(&l_rcd_cntl_word_0_1, 0 , 8); - rc_num |= data_buffer_64.insertFromRight(&l_rcd_cntl_word_2, 8 , 4); - rc_num |= data_buffer_64.insertFromRight(&l_rcd_cntl_word_3, 12, 4); - rc_num |= data_buffer_64.insertFromRight(&l_rcd_cntl_word_4, 16, 4); - rc_num |= data_buffer_64.insertFromRight(&l_rcd_cntl_word_5, 20, 4); - rc_num |= data_buffer_64.insertFromRight(&l_rcd_cntl_word_6_7, 24, 8); - rc_num |= data_buffer_64.insertFromRight(&l_rcd_cntl_word_8_9, 32, 8); - rc_num |= data_buffer_64.insertFromRight(&l_rcd_cntl_word_10, 40, 4); - rc_num |= data_buffer_64.insertFromRight(&l_rcd_cntl_word_11, 44, 4); - rc_num |= data_buffer_64.insertFromRight(&l_rcd_cntl_word_12, 48, 4); - rc_num |= data_buffer_64.insertFromRight(&l_rcd_cntl_word_13, 52, 4); - rc_num |= data_buffer_64.insertFromRight(&l_rcd_cntl_word_14, 56, 4); - rc_num |= data_buffer_64.insertFromRight(&l_rcd_cntl_word_15, 60, 4); - - if(rc_num) - { - rc.setEcmdError(rc_num); - return rc; - } - - l_rcd_cntl_word_0_15 = data_buffer_64.getDoubleWord(0); if(rc) return rc; - l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = l_rcd_cntl_word_0_15; - - // Set RCD control word x - - // RC1x Internal VREF CW - l_rcd_cntl_word_1x = 0; - - // RC2x I2C Bus Control Word - l_rcd_cntl_word_2x = 0; - - // RC3x Fine Granularity RDIMM Operating Speed Control Word - if ( l_mss_freq > 1240 && l_mss_freq < 3200 ) { - l_rcd_cntl_word_3x = int ((l_mss_freq - 1250) / 20); - } else { - FAPI_ERR("Invalid DIMM ATTR_MSS_FREQ = %d on %s!", l_mss_freq, i_target_mba.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; - } - - // RC7x IBT Control Word - l_rcd_cntl_word_7x = 0; - - // RC8x ODT Input Buffer/IBT, QxODT Output Buffer and Timing Control Word - l_rcd_cntl_word_8x = 0; - - // RC9x QxODT[1:0] Write Pattern CW - l_rcd_cntl_word_9x = 0; - - // RCAx QxODT[1:0] Read Pattern CW - l_rcd_cntl_word_Ax = 0; - - // RCBx IBT and MRS Snoop CW - if ( l_num_ranks_per_dimm_u8array[l_port][l_dimm] == 4 ) { - l_rcd_cntl_word_Bx = 4; - } else { - l_rcd_cntl_word_Bx = 7; - } - - - rc_num |= data_buffer_64.insertFromRight(&l_rcd_cntl_word_1x, 0 , 8); - rc_num |= data_buffer_64.insertFromRight(&l_rcd_cntl_word_2x, 8 , 8); - rc_num |= data_buffer_64.insertFromRight(&l_rcd_cntl_word_3x, 16, 8); - rc_num |= data_buffer_64.insertFromRight(&l_rcd_cntl_word_7x, 24, 8); - rc_num |= data_buffer_64.insertFromRight(&l_rcd_cntl_word_8x, 32, 8); - rc_num |= data_buffer_64.insertFromRight(&l_rcd_cntl_word_9x, 40, 8); - rc_num |= data_buffer_64.insertFromRight(&l_rcd_cntl_word_Ax, 48, 8); - rc_num |= data_buffer_64.insertFromRight(&l_rcd_cntl_word_Bx, 56, 8); - if(rc_num) - { - rc.setEcmdError(rc_num); - return rc; - } - - l_attr_eff_dimm_cntl_word_x = data_buffer_64.getDoubleWord(0); if(rc) return rc; - FAPI_INF("from data buffer: rcd control word X %llX", l_attr_eff_dimm_cntl_word_x ); - - } // end dimm loop - } // end port loop - - rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_RCD_CNTL_WORD_0_15, &i_target_mba, l_attr_eff_dimm_rcd_cntl_word_0_15); if(rc) return rc; - - //FIXME: ATTR_MCBIST_MAX_TIMEOUT is being used until firmware is ready with a new attribute, ATTR_EFF_LRDIMM_WORD_X (subject to change) - rc = FAPI_ATTR_SET(ATTR_MCBIST_MAX_TIMEOUT, &i_target_mba, l_attr_eff_dimm_cntl_word_x); if(rc) return rc; - - return rc; - -} - -ReturnCode mss_rcd_load_ddr4( - Target& i_target, - uint32_t i_port_number, - uint32_t& io_ccs_inst_cnt - ) { - - ReturnCode rc; - ReturnCode rc_buff; - uint32_t rc_num = 0; - uint32_t dimm_number; - uint32_t rcd_number; - - ecmdDataBufferBase rcd_cntl_wrd_4(8); - ecmdDataBufferBase rcd_cntl_wrd_8(8); - ecmdDataBufferBase rcd_cntl_wrd_64(64); - uint16_t num_ranks; - - ecmdDataBufferBase address_16(16); - ecmdDataBufferBase bank_3(3); - ecmdDataBufferBase activate_1(1); - ecmdDataBufferBase rasn_1(1); - rc_num = rc_num | rasn_1.setBit(0); - ecmdDataBufferBase casn_1(1); - rc_num = rc_num | casn_1.setBit(0); - ecmdDataBufferBase wen_1(1); - rc_num = rc_num | wen_1.setBit(0); - ecmdDataBufferBase cke_4(4); - rc_num = rc_num | cke_4.setBit(0,4); - ecmdDataBufferBase csn_8(8); - rc_num = rc_num | csn_8.setBit(0,8); - ecmdDataBufferBase odt_4(4); - rc_num = rc_num | odt_4.clearBit(0,4); - ecmdDataBufferBase ddr_cal_type_4(4); - - ecmdDataBufferBase num_idles_16(16); - ecmdDataBufferBase num_repeat_16(16); - ecmdDataBufferBase data_20(20); - ecmdDataBufferBase read_compare_1(1); - ecmdDataBufferBase rank_cal_4(4); - ecmdDataBufferBase ddr_cal_enable_1(1); - ecmdDataBufferBase ccs_end_1(1); - - if(rc_num) - { - rc.setEcmdError(rc_num); - return rc; - } - - uint8_t num_ranks_array[2][2]; //[port][dimm] - uint64_t rcd_array[2][2]; //[port][dimm] - uint8_t dimm_type; - - rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target, dimm_type); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target, num_ranks_array); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_RCD_CNTL_WORD_0_15, &i_target, rcd_array); - if(rc) return rc; - - uint32_t cntlx_offset[]= {1,2,3,7,8,9,10,11}; - // Dummy attribute for addtitional cntl words - uint64_t rcdx_array; - // uint64_t rcdx_array[2][2]; - - //FIXME: ATTR_MCBIST_MAX_TIMEOUT is being used until firmware is ready with a new attribute, ATTR_EFF_LRDIMM_WORD_X (subject to change) - rc = FAPI_ATTR_GET(ATTR_MCBIST_MAX_TIMEOUT, &i_target, rcdx_array); - if(rc) return rc; - - // Raise CKE high with NOPS, waiting min Reset CKE exit time (tXPR) - 400 cycles - rc_num = rc_num | address_16.clearBit(0, 16); - rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 400, 0, 16); - rc = mss_ccs_inst_arry_0( i_target, - io_ccs_inst_cnt, - address_16, - bank_3, - activate_1, - rasn_1, - casn_1, - wen_1, - cke_4, - csn_8, - odt_4, - ddr_cal_type_4, - i_port_number); - if(rc) return rc; - rc = mss_ccs_inst_arry_1( i_target, - io_ccs_inst_cnt, - num_idles_16, - num_repeat_16, - data_20, - read_compare_1, - rank_cal_4, - ddr_cal_enable_1, - ccs_end_1); - if(rc) return rc; - io_ccs_inst_cnt ++; - - FAPI_INF( "+++++++++++++++++++++ LOADING RCD CONTROL WORDS FOR %s PORT %d +++++++++++++++++++++", i_target.toEcmdString(), i_port_number); - - for ( dimm_number = 0; dimm_number < MAX_NUM_DIMMS; dimm_number++) - { - num_ranks = num_ranks_array[i_port_number][dimm_number]; - - if (num_ranks == 0) - { - FAPI_INF( "PORT%d DIMM%d not configured. Num_ranks: %d", i_port_number, dimm_number, num_ranks); - } - else - { - FAPI_INF( "RCD SETTINGS FOR %s PORT%d DIMM%d ", i_target.toEcmdString(), i_port_number, dimm_number); - FAPI_INF( "RCD Control Word: 0x%016llX", rcd_array[i_port_number][dimm_number]); - //FAPI_INF( "RCD Control Word X: 0x%016llX", rcdx_array[i_port_number][dimm_number]); - FAPI_INF( "RCD Control Word X: 0x%016llX", rcdx_array); - - if (rc_num) - { - FAPI_ERR( "mss_rcd_load: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - - // ALL active CS lines at a time. - rc_num = rc_num | csn_8.setBit(0,8); - rc_num = rc_num | csn_8.clearBit(0); //DCS0_n is LOW - - // DBG1, DBG0, DBA1, DBA0 = 4`b0111 - rc_num = rc_num | bank_3.setBit(0, 3); - // DACT_n is HIGH - rc_num = rc_num | activate_1.setBit(0); - // RAS_n/CAS_n/WE_n are LOW - rc_num = rc_num | rasn_1.clearBit(0); - rc_num = rc_num | casn_1.clearBit(0); - rc_num = rc_num | wen_1.clearBit(0); - - // Propogate through the 16, 4-bit control words - for ( rcd_number = 0; rcd_number<= 15; rcd_number++) - { - //rc_num = rc_num | bank_3.clearBit(0, 3); - rc_num = rc_num | address_16.clearBit(0, 16); - - rc_num = rc_num | rcd_cntl_wrd_64.setDoubleWord(0, rcd_array[i_port_number][dimm_number]); - rc_num = rc_num | rcd_cntl_wrd_64.extract(rcd_cntl_wrd_4, 4*rcd_number, 4); - - //control word number code bits A[7:4] - rc_num = rc_num | address_16.insert(rcd_number, 7, 1, 28); - rc_num = rc_num | address_16.insert(rcd_number, 6, 1, 29); - rc_num = rc_num | address_16.insert(rcd_number, 5, 1, 30); - rc_num = rc_num | address_16.insert(rcd_number, 4, 1, 31); - - //control word values RCD0 = A0, RCD1 = A1, RCD2 = A2, RCD3 = A3 - rc_num = rc_num | address_16.insert(rcd_cntl_wrd_4, 0, 1, 3); - rc_num = rc_num | address_16.insert(rcd_cntl_wrd_4, 1, 1, 2); - rc_num = rc_num | address_16.insert(rcd_cntl_wrd_4, 2, 1, 1); - rc_num = rc_num | address_16.insert(rcd_cntl_wrd_4, 3, 1, 0); - - // Send out to the CCS array - //if ( dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM && (rcd_number == 2 || rcd_number == 10) ) - if ( rcd_number == 2 || rcd_number == 10 ) - { - rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 4000, 0 , 16 ); // wait tStab for clock timing rcd words - } - else - { - rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 12, 0, 16); - } - - - if (rc_num) - { - FAPI_ERR( "mss_rcd_load: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - - rc = mss_ccs_inst_arry_0( i_target, - io_ccs_inst_cnt, - address_16, - bank_3, - activate_1, - rasn_1, - casn_1, - wen_1, - cke_4, - csn_8, - odt_4, - ddr_cal_type_4, - i_port_number); - if(rc) return rc; - rc = mss_ccs_inst_arry_1( i_target, - io_ccs_inst_cnt, - num_idles_16, - num_repeat_16, - data_20, - read_compare_1, - rank_cal_4, - ddr_cal_enable_1, - ccs_end_1); - if(rc) return rc; - io_ccs_inst_cnt ++; - - if (rc_num) - { - FAPI_ERR( "mss_rcd_load: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - } - - // 8-bit Control words - for ( rcd_number = 0; rcd_number<= 7; rcd_number++) - { - //rc_num = rc_num | bank_3.clearBit(0, 3); - rc_num = rc_num | address_16.clearBit(0, 16); - - //rc_num = rc_num | rcd_cntl_wrd_64.setDoubleWord(0, rcdx_array[i_port_number][dimm_number]); - rc_num = rc_num | rcd_cntl_wrd_64.setDoubleWord(0, rcdx_array); - rc_num = rc_num | rcd_cntl_wrd_64.extract(rcd_cntl_wrd_8, 8*rcd_number, 8); - - //control word number code bits A[11:8] - rc_num = rc_num | address_16.insert(cntlx_offset[rcd_number], 11, 1, 28); - rc_num = rc_num | address_16.insert(cntlx_offset[rcd_number], 10, 1, 29); - rc_num = rc_num | address_16.insert(cntlx_offset[rcd_number], 9, 1, 30); - rc_num = rc_num | address_16.insert(cntlx_offset[rcd_number], 8, 1, 31); - - //control word values RCD0 = A0, RCD1 = A1, RCD2 = A2, RCD3 = A3, RCD4=A4, RCD5=A5, RCD6=A6, RCD7=A7 - rc_num = rc_num | address_16.insert(rcd_cntl_wrd_8, 0, 1, 7); - rc_num = rc_num | address_16.insert(rcd_cntl_wrd_8, 1, 1, 6); - rc_num = rc_num | address_16.insert(rcd_cntl_wrd_8, 2, 1, 5); - rc_num = rc_num | address_16.insert(rcd_cntl_wrd_8, 3, 1, 4); - rc_num = rc_num | address_16.insert(rcd_cntl_wrd_8, 4, 1, 3); - rc_num = rc_num | address_16.insert(rcd_cntl_wrd_8, 5, 1, 2); - rc_num = rc_num | address_16.insert(rcd_cntl_wrd_8, 6, 1, 1); - rc_num = rc_num | address_16.insert(rcd_cntl_wrd_8, 7, 1, 0); - - // Send out to the CCS array - if ( rcd_number == 2 ) // CW RC3x - { - rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 4000, 0 , 16 ); // wait tStab for clock timing rcd words - } - else - { - rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 12, 0, 16); - } - - if (rc_num) - { - FAPI_ERR( "mss_rcd_load: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - - rc = mss_ccs_inst_arry_0( i_target, - io_ccs_inst_cnt, - address_16, - bank_3, - activate_1, - rasn_1, - casn_1, - wen_1, - cke_4, - csn_8, - odt_4, - ddr_cal_type_4, - i_port_number); - if(rc) return rc; - rc = mss_ccs_inst_arry_1( i_target, - io_ccs_inst_cnt, - num_idles_16, - num_repeat_16, - data_20, - read_compare_1, - rank_cal_4, - ddr_cal_enable_1, - ccs_end_1); - if(rc) return rc; - io_ccs_inst_cnt ++; - - if (rc_num) - { - FAPI_ERR( "mss_rcd_load: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - } - } - } - - rc = mss_ccs_set_end_bit( i_target, io_ccs_inst_cnt-1); - if(rc) - { - FAPI_ERR("CCS_SET_END_BIT FAILED rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator()); - return rc; - } - io_ccs_inst_cnt = 0; - - rc = mss_execute_ccs_inst_array(i_target, 10, 10); - if(rc) - { - FAPI_ERR(" EXECUTE_CCS_INST_ARRAY FAILED rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator()); - return rc; - } - - - return rc; -} - -ReturnCode mss_mrs_load_ddr4( - Target& i_target, - uint32_t i_port_number, - uint32_t& io_ccs_inst_cnt - ) -{ - - uint32_t dimm_number; - uint32_t rank_number; - uint32_t mrs_number; - ReturnCode rc; - ReturnCode rc_buff; - uint32_t rc_num = 0; - ecmdDataBufferBase data_buffer_64(64); - ecmdDataBufferBase address_16(16); - ecmdDataBufferBase bank_3(3); - ecmdDataBufferBase activate_1(1); - rc_num = rc_num | activate_1.setBit(0); - ecmdDataBufferBase rasn_1(1); - rc_num = rc_num | rasn_1.clearBit(0); - ecmdDataBufferBase casn_1(1); - rc_num = rc_num | casn_1.clearBit(0); - ecmdDataBufferBase wen_1(1); - rc_num = rc_num | wen_1.clearBit(0); - ecmdDataBufferBase cke_4(4); - rc_num = rc_num | cke_4.clearBit(0,4); - ecmdDataBufferBase csn_8(8); - rc_num = rc_num | csn_8.clearBit(0,8); - ecmdDataBufferBase odt_4(4); - rc_num = rc_num | odt_4.clearBit(0,4); - ecmdDataBufferBase ddr_cal_type_4(4); - - ecmdDataBufferBase num_idles_16(16); - ecmdDataBufferBase num_idles_16_vref_train(16); - rc_num = rc_num | num_idles_16_vref_train.insertFromRight((uint32_t) 160, 0, 16); - - if(rc_num) { - rc.setEcmdError(rc_num); - return rc; - } - - ecmdDataBufferBase num_repeat_16(16); - ecmdDataBufferBase data_20(20); - ecmdDataBufferBase read_compare_1(1); - ecmdDataBufferBase rank_cal_4(4); - ecmdDataBufferBase ddr_cal_enable_1(1); - ecmdDataBufferBase ccs_end_1(1); - - ecmdDataBufferBase mrs0(16); - ecmdDataBufferBase mrs1(16); - ecmdDataBufferBase mrs2(16); - ecmdDataBufferBase mrs3(16); - ecmdDataBufferBase mrs4(16); - ecmdDataBufferBase mrs5(16); - ecmdDataBufferBase mrs6(16); - ecmdDataBufferBase mrs6_train_on(16); - uint16_t MRS0 = 0; - uint16_t MRS1 = 0; - uint16_t MRS2 = 0; - uint16_t MRS3 = 0; - uint16_t MRS4 = 0; - uint16_t MRS5 = 0; - uint16_t MRS6 = 0; - - ecmdDataBufferBase data_buffer(64); - - - uint16_t num_ranks = 0; - - FAPI_INF( "+++++++++++++++++++++ LOADING MRS SETTINGS FOR PORT %d +++++++++++++++++++++", i_port_number); - - uint8_t num_ranks_array[2][2]; //[port][dimm] - rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target, num_ranks_array); - if(rc) return rc; - - uint8_t num_master_ranks_array[2][2]; //[port][dimm] - rc = FAPI_ATTR_GET(ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM, &i_target, num_master_ranks_array); - if(rc) return rc; - - uint8_t dimm_type; - rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target, dimm_type); - if(rc) return rc; - - uint8_t is_sim = 0; - rc = FAPI_ATTR_GET(ATTR_IS_SIMULATION, NULL, is_sim); - if(rc) return rc; - - uint8_t address_mirror_map[2][2]; //address_mirror_map[port][dimm] - rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_ADDRESS_MIRRORING, &i_target, address_mirror_map); - if(rc) return rc; - - - // WORKAROUNDS - rc = fapiGetScom(i_target, CCS_MODEQ_AB_REG_0x030106A7, data_buffer); - if(rc) return rc; - //Setting up CCS mode - rc_num = rc_num | data_buffer.setBit(51); - if(rc_num) { - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target, CCS_MODEQ_AB_REG_0x030106A7, data_buffer); - if(rc) return rc; - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_WC_CONFIG3_P0_0x8000CC050301143F, data_buffer); - if(rc) return rc; - //Setting up CCS mode - rc_num = rc_num | data_buffer.clearBit(48); - if(rc_num) { - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target, DPHY01_DDRPHY_WC_CONFIG3_P0_0x8000CC050301143F, data_buffer); - if(rc) return rc; - - - uint8_t dram_stack[2][2]; - rc = FAPI_ATTR_GET(ATTR_EFF_STACK_TYPE, &i_target, dram_stack); - if(rc) return rc; - - FAPI_INF( "Stack Type: %d\n", dram_stack[0][0]); - if (dram_stack[0][0] == ENUM_ATTR_EFF_STACK_TYPE_STACK_3DS) - { - FAPI_INF( "============= Got in the 3DS stack loop CKE !!!!! =====================\n"); - rc_num = rc_num | csn_8.clearBit(2,2); - rc_num = rc_num | csn_8.clearBit(6,2); - // COMMENT IN LATER!!!! rc_num = rc_num | cke_4.clearBit(1); - if(rc_num) { - rc.setEcmdError(rc_num); - return rc; - } - } - - //Lines commented out in the following section are waiting for xml attribute adds - //MRS0 - uint8_t dram_bl; - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_BL, &i_target, dram_bl); - if(rc) return rc; - uint8_t read_bt; //Read Burst Type - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_RBT, &i_target, read_bt); - if(rc) return rc; - uint8_t dram_cl; - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_CL, &i_target, dram_cl); - if(rc) return rc; - uint8_t test_mode; //TEST MODE - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_TM, &i_target, test_mode); - if(rc) return rc; - uint8_t dll_reset; //DLL Reset - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_DLL_RESET, &i_target, dll_reset); - if(rc) return rc; - uint8_t dram_wr; //DRAM write recovery - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WR, &i_target, dram_wr); - if(rc) return rc; - uint8_t dram_rtp; //DRAM RTP - read to precharge - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WR, &i_target, dram_rtp); - if(rc) return rc; - uint8_t dll_precharge; //DLL Control For Precharge - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_DLL_PPD, &i_target, dll_precharge); - if(rc) return rc; - - if (dram_bl == ENUM_ATTR_EFF_DRAM_BL_BL8) - { - dram_bl = 0x00; - } - else if (dram_bl == ENUM_ATTR_EFF_DRAM_BL_OTF) - { - dram_bl = 0x80; - } - else if (dram_bl == ENUM_ATTR_EFF_DRAM_BL_BC4) - { - dram_bl = 0x40; - } - - uint8_t dram_wr_rtp = 0x00; - if ( (dram_wr == 10) )//&& (dram_rtp == 5) ) - { - dram_wr_rtp = 0x00; - } - else if ( (dram_wr == 12) )//&& (dram_rtp == 6) ) - { - dram_wr_rtp = 0x80; - } - else if ( (dram_wr == 13) )//&& (dram_rtp == 7) ) - { - dram_wr_rtp = 0x40; - } - else if ( (dram_wr == 14) )//&& (dram_rtp == 8) ) - { - dram_wr_rtp = 0xC0; - } - else if ( (dram_wr == 18) )//&& (dram_rtp == 9) ) - { - dram_wr_rtp = 0x20; - } - else if ( (dram_wr == 20) )//&& (dram_rtp == 10) ) - { - dram_wr_rtp = 0xA0; - } - else if ( (dram_wr == 24) )//&& (dram_rtp == 12) ) - { - dram_wr_rtp = 0x60; - } - - if (read_bt == ENUM_ATTR_EFF_DRAM_RBT_SEQUENTIAL) - { - read_bt = 0x00; - } - else if (read_bt == ENUM_ATTR_EFF_DRAM_RBT_INTERLEAVE) - { - read_bt = 0xFF; - } - - if ((dram_cl > 8)&&(dram_cl < 17)) - { - dram_cl = dram_cl - 9; - } - else if ((dram_cl > 17)&&(dram_cl < 25)) - { - dram_cl = (dram_cl >> 1) - 1; - } - dram_cl = mss_reverse_8bits(dram_cl); - - if (test_mode == ENUM_ATTR_EFF_DRAM_TM_NORMAL) - { - test_mode = 0x00; - } - else if (test_mode == ENUM_ATTR_EFF_DRAM_TM_TEST) - { - test_mode = 0xFF; - } - - if (dll_reset == ENUM_ATTR_EFF_DRAM_DLL_RESET_YES) - { - dll_reset = 0xFF; - } - else if (dll_reset == ENUM_ATTR_EFF_DRAM_DLL_RESET_NO) - { - dll_reset = 0x00; - } - - if (dll_precharge == ENUM_ATTR_EFF_DRAM_DLL_PPD_SLOWEXIT) - { - dll_precharge = 0x00; - } - else if (dll_precharge == ENUM_ATTR_EFF_DRAM_DLL_PPD_FASTEXIT) - { - dll_precharge = 0xFF; - } - - //MRS1 - uint8_t dll_enable; //DLL Enable - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_DLL_ENABLE, &i_target, dll_enable); - if(rc) return rc; - uint8_t out_drv_imp_cntl[2][2]; - rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_RON, &i_target, out_drv_imp_cntl); - if(rc) return rc; - uint8_t dram_rtt_nom[2][2][4]; - rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_RTT_NOM, &i_target, dram_rtt_nom); - if(rc) return rc; - uint8_t dram_al; - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_AL, &i_target, dram_al); - if(rc) return rc; - uint8_t wr_lvl; //write leveling enable - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WR_LVL_ENABLE, &i_target, wr_lvl); - if(rc) return rc; - uint8_t tdqs_enable; //TDQS Enable - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_TDQS, &i_target, tdqs_enable); - if(rc) return rc; - uint8_t q_off; //Qoff - Output buffer Enable - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_OUTPUT_BUFFER, &i_target, q_off); - if(rc) return rc; - - if (dll_enable == ENUM_ATTR_EFF_DRAM_DLL_ENABLE_DISABLE) - { - dll_enable = 0x00; - } - else if (dll_enable == ENUM_ATTR_EFF_DRAM_DLL_ENABLE_ENABLE) - { - dll_enable = 0xFF; - } - - if (dram_al == ENUM_ATTR_EFF_DRAM_AL_DISABLE) - { - dram_al = 0x00; - } - else if (dram_al == ENUM_ATTR_EFF_DRAM_AL_CL_MINUS_1) - { - dram_al = 0x80; - } - else if (dram_al == ENUM_ATTR_EFF_DRAM_AL_CL_MINUS_2) - { - dram_al = 0x40; - } - - if (wr_lvl == ENUM_ATTR_EFF_DRAM_WR_LVL_ENABLE_DISABLE) - { - wr_lvl = 0x00; - } - else if (wr_lvl == ENUM_ATTR_EFF_DRAM_WR_LVL_ENABLE_ENABLE) - { - wr_lvl = 0xFF; - } - - if (tdqs_enable == ENUM_ATTR_EFF_DRAM_TDQS_DISABLE) - { - tdqs_enable = 0x00; - } - else if (tdqs_enable == ENUM_ATTR_EFF_DRAM_TDQS_ENABLE) - { - tdqs_enable = 0xFF; - } - - if (q_off == ENUM_ATTR_EFF_DRAM_OUTPUT_BUFFER_DISABLE) - { - q_off = 0xFF; - } - else if (q_off == ENUM_ATTR_EFF_DRAM_OUTPUT_BUFFER_ENABLE) - { - q_off = 0x00; - } - - //MRS2 - - uint8_t lpasr; // Low Power Auto Self-Refresh -- new not yet supported - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_LPASR, &i_target, lpasr); - if(rc) return rc; - uint8_t cwl; // CAS Write Latency - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_CWL, &i_target, cwl); - if(rc) return rc; - uint8_t dram_rtt_wr[2][2][4]; - rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_RTT_WR, &i_target, dram_rtt_wr); - if(rc) return rc; - uint8_t write_crc; // CAS Write Latency - rc = FAPI_ATTR_GET(ATTR_EFF_WRITE_CRC, &i_target, write_crc); - if(rc) return rc; - - if (lpasr == ENUM_ATTR_EFF_DRAM_LPASR_MANUAL_NORMAL) - { - lpasr = 0x00; - } - else if (lpasr == ENUM_ATTR_EFF_DRAM_LPASR_MANUAL_REDUCED) - { - lpasr = 0x80; - } - else if (lpasr == ENUM_ATTR_EFF_DRAM_LPASR_MANUAL_EXTENDED) - { - lpasr = 0x40; - } - else if (lpasr == ENUM_ATTR_EFF_DRAM_LPASR_ASR) - { - lpasr = 0xFF; - } - - if ((cwl > 8)&&(cwl < 13)) - { - cwl = cwl - 9; - } - else if ((cwl > 13)&&(cwl < 19)) - { - cwl = (cwl >> 1) - 3; - } - else - { - //no correcct value for CWL was found - FAPI_INF("ERROR: Improper CWL value found. Setting CWL to 9 and continuing..."); - cwl = 0; - } - cwl = mss_reverse_8bits(cwl); - - if ( write_crc == ENUM_ATTR_EFF_WRITE_CRC_ENABLE) - { - write_crc = 0xFF; - } - else if (write_crc == ENUM_ATTR_EFF_WRITE_CRC_DISABLE) - { - write_crc = 0x00; - } - - //MRS3 - uint8_t mpr_op; // MPR Op - rc = FAPI_ATTR_GET(ATTR_EFF_MPR_MODE, &i_target, mpr_op); - if(rc) return rc; - uint8_t mpr_page; // MPR Page Selection - NEW - rc = FAPI_ATTR_GET(ATTR_EFF_MPR_PAGE, &i_target, mpr_page); - if(rc) return rc; - uint8_t geardown_mode; // Gear Down Mode - NEW - rc = FAPI_ATTR_GET(ATTR_EFF_GEARDOWN_MODE, &i_target, geardown_mode); - if(rc) return rc; - uint8_t dram_access; // per dram accessibility - NEW - rc = FAPI_ATTR_GET(ATTR_EFF_PER_DRAM_ACCESS, &i_target, dram_access); - if(rc) return rc; - uint8_t temp_readout; // Temperature sensor readout - NEW - rc = FAPI_ATTR_GET(ATTR_EFF_TEMP_READOUT, &i_target, temp_readout); - if(rc) return rc; - uint8_t fine_refresh; // fine refresh mode - NEW - rc = FAPI_ATTR_GET(ATTR_EFF_FINE_REFRESH_MODE, &i_target, fine_refresh); - if(rc) return rc; - uint8_t wr_latency; // write latency for CRC and DM - NEW - rc = FAPI_ATTR_GET(ATTR_EFF_CRC_WR_LATENCY, &i_target, wr_latency); - if(rc) return rc; - uint8_t read_format; // MPR READ FORMAT - NEW - rc = FAPI_ATTR_GET(ATTR_EFF_MPR_RD_FORMAT, &i_target, read_format); - if(rc) return rc; - - if (mpr_op == ENUM_ATTR_EFF_MPR_MODE_ENABLE) - { - mpr_op = 0xFF; - } - else if (mpr_op == ENUM_ATTR_EFF_MPR_MODE_DISABLE) - { - mpr_op = 0x00; - } - - mpr_page = mss_reverse_8bits(mpr_page); - - if (dram_access == ENUM_ATTR_EFF_PER_DRAM_ACCESS_ENABLE) - { - dram_access = 0xFF; - } - else if (dram_access == ENUM_ATTR_EFF_PER_DRAM_ACCESS_DISABLE) - { - dram_access = 0x00; - } - - if ( geardown_mode == ENUM_ATTR_EFF_GEARDOWN_MODE_HALF) - { - geardown_mode = 0x00; - } - else if ( geardown_mode == ENUM_ATTR_EFF_GEARDOWN_MODE_QUARTER) - { - geardown_mode = 0xFF; - } - - if (temp_readout == ENUM_ATTR_EFF_TEMP_READOUT_ENABLE) - { - temp_readout = 0xFF; - } - else if (temp_readout == ENUM_ATTR_EFF_TEMP_READOUT_DISABLE) - { - temp_readout = 0x00; - } - - if (fine_refresh == ENUM_ATTR_EFF_FINE_REFRESH_MODE_NORMAL) - { - fine_refresh = 0x00; - } - else if (fine_refresh == ENUM_ATTR_EFF_FINE_REFRESH_MODE_FIXED_2X) - { - fine_refresh = 0x80; - } - else if (fine_refresh == ENUM_ATTR_EFF_FINE_REFRESH_MODE_FIXED_4X) - { - fine_refresh = 0x40; - } - else if (fine_refresh == ENUM_ATTR_EFF_FINE_REFRESH_MODE_FLY_2X) - { - fine_refresh = 0xA0; - } - else if (fine_refresh == ENUM_ATTR_EFF_FINE_REFRESH_MODE_FLY_4X) - { - fine_refresh = 0x60; - } - - if (wr_latency == ENUM_ATTR_EFF_CRC_WR_LATENCY_4NCK) - { - wr_latency = 0x00; - } - else if (wr_latency == ENUM_ATTR_EFF_CRC_WR_LATENCY_5NCK) - { - wr_latency = 0x80; - } - else if (wr_latency == ENUM_ATTR_EFF_CRC_WR_LATENCY_6NCK) - { - wr_latency = 0xC0; - } - - if (read_format == ENUM_ATTR_EFF_MPR_RD_FORMAT_SERIAL) - { - read_format = 0x00; - } - else if (read_format == ENUM_ATTR_EFF_MPR_RD_FORMAT_PARALLEL) - { - read_format = 0x80; - } - else if (read_format == ENUM_ATTR_EFF_MPR_RD_FORMAT_STAGGERED) - { - read_format = 0x40; - } - else if (read_format == ENUM_ATTR_EFF_MPR_RD_FORMAT_RESERVED_TEMP) - { - read_format = 0xC0; - } - - //MRS4 - uint8_t max_pd_mode; // Max Power down mode - NEW - rc = FAPI_ATTR_GET(ATTR_EFF_MAX_POWERDOWN_MODE, &i_target, max_pd_mode); - if(rc) return rc; - uint8_t temp_ref_range; // Temp ref range - NEW - rc = FAPI_ATTR_GET(ATTR_EFF_TEMP_REF_RANGE, &i_target, temp_ref_range); - if(rc) return rc; - uint8_t temp_ref_mode; // Temp controlled ref mode - NEW - rc = FAPI_ATTR_GET(ATTR_EFF_TEMP_REF_MODE, &i_target, temp_ref_mode); - if(rc) return rc; - uint8_t vref_mon; // Internal Vref Monitor - NEW - rc = FAPI_ATTR_GET(ATTR_EFF_INT_VREF_MON, &i_target, vref_mon); - if(rc) return rc; - uint8_t cs_cmd_latency; // CS to CMD/ADDR Latency - NEW - rc = FAPI_ATTR_GET(ATTR_EFF_CS_CMD_LATENCY, &i_target, cs_cmd_latency); - if(rc) return rc; - uint8_t ref_abort; // Self Refresh Abort - NEW - rc = FAPI_ATTR_GET(ATTR_EFF_SELF_REF_ABORT, &i_target, ref_abort); - if(rc) return rc; - uint8_t rd_pre_train_mode; // Read Pre amble Training Mode - NEW - rc = FAPI_ATTR_GET(ATTR_EFF_RD_PREAMBLE_TRAIN, &i_target, rd_pre_train_mode); - if(rc) return rc; - uint8_t rd_preamble; // Read Pre amble - NEW - rc = FAPI_ATTR_GET(ATTR_EFF_RD_PREAMBLE, &i_target, rd_preamble); - if(rc) return rc; - uint8_t wr_preamble; // Write Pre amble - NEW - rc = FAPI_ATTR_GET(ATTR_EFF_WR_PREAMBLE, &i_target, wr_preamble); - if(rc) return rc; - - if ( max_pd_mode == ENUM_ATTR_EFF_MAX_POWERDOWN_MODE_ENABLE) - { - max_pd_mode = 0xF0; - } - else if ( max_pd_mode == ENUM_ATTR_EFF_MAX_POWERDOWN_MODE_DISABLE) - { - max_pd_mode = 0x00; - } - - if (temp_ref_range == ENUM_ATTR_EFF_TEMP_REF_RANGE_NORMAL) - { - temp_ref_range = 0x00; - } - else if ( temp_ref_range== ENUM_ATTR_EFF_TEMP_REF_RANGE_EXTEND) - { - temp_ref_range = 0xFF; - } - - if (temp_ref_mode == ENUM_ATTR_EFF_TEMP_REF_MODE_ENABLE) - { - temp_ref_mode = 0x80; - } - else if (temp_ref_mode == ENUM_ATTR_EFF_TEMP_REF_MODE_DISABLE) - { - temp_ref_mode = 0x00; - } - - if ( vref_mon == ENUM_ATTR_EFF_INT_VREF_MON_ENABLE) - { - vref_mon = 0xFF; - } - else if ( vref_mon == ENUM_ATTR_EFF_INT_VREF_MON_DISABLE) - { - vref_mon = 0x00; - } - - - if ( cs_cmd_latency == 3) - { - cs_cmd_latency = 0x80; - } - else if (cs_cmd_latency == 4) - { - cs_cmd_latency = 0x40; - } - else if (cs_cmd_latency == 5) - { - cs_cmd_latency = 0xC0; - } - else if (cs_cmd_latency == 6) - { - cs_cmd_latency = 0x20; - } - else if (cs_cmd_latency == 8) - { - cs_cmd_latency = 0xA0; - } - - if (ref_abort == ENUM_ATTR_EFF_SELF_REF_ABORT_ENABLE) - { - ref_abort = 0xFF; - } - else if (ref_abort == ENUM_ATTR_EFF_SELF_REF_ABORT_DISABLE) - { - ref_abort = 0x00; - } - - if (rd_pre_train_mode == ENUM_ATTR_EFF_RD_PREAMBLE_TRAIN_ENABLE) - { - rd_pre_train_mode = 0xFF; - } - else if (rd_pre_train_mode == ENUM_ATTR_EFF_RD_PREAMBLE_TRAIN_DISABLE) - { - rd_pre_train_mode = 0x00; - } - - if (rd_preamble == ENUM_ATTR_EFF_RD_PREAMBLE_1NCLK) - { - rd_preamble = 0x00; - } - else if (rd_preamble == ENUM_ATTR_EFF_RD_PREAMBLE_2NCLK) - { - rd_preamble = 0xFF; - } - - if (wr_preamble == ENUM_ATTR_EFF_WR_PREAMBLE_1NCLK) - { - wr_preamble = 0x00; - } - else if (wr_preamble == ENUM_ATTR_EFF_WR_PREAMBLE_2NCLK) - { - wr_preamble = 0xFF; - } - - - //MRS5 - uint8_t ca_parity_latency; //C/A Parity Latency Mode - NEW - rc = FAPI_ATTR_GET(ATTR_EFF_CA_PARITY_LATENCY , &i_target, ca_parity_latency); - if(rc) return rc; - uint8_t crc_error_clear; //CRC Error Clear - NEW - rc = FAPI_ATTR_GET(ATTR_EFF_CRC_ERROR_CLEAR , &i_target, crc_error_clear); - if(rc) return rc; - uint8_t ca_parity_error_status; //C/A Parity Error Status - NEW - rc = FAPI_ATTR_GET(ATTR_EFF_CA_PARITY_ERROR_STATUS , &i_target, ca_parity_error_status); - if(rc) return rc; - uint8_t odt_input_buffer; //ODT Input Buffer during power down - NEW - rc = FAPI_ATTR_GET(ATTR_EFF_ODT_INPUT_BUFF , &i_target, odt_input_buffer); - if(rc) return rc; - uint8_t rtt_park[2][2][4]; //RTT_Park value - NEW - rc = FAPI_ATTR_GET(ATTR_EFF_RTT_PARK , &i_target, rtt_park); - if(rc) return rc; - uint8_t ca_parity; //CA Parity Persistance Error - NEW - rc = FAPI_ATTR_GET(ATTR_EFF_CA_PARITY , &i_target, ca_parity); - if(rc) return rc; - uint8_t data_mask; //Data Mask - NEW - rc = FAPI_ATTR_GET(ATTR_EFF_DATA_MASK , &i_target, data_mask); - if(rc) return rc; - uint8_t write_dbi; //Write DBI - NEW - rc = FAPI_ATTR_GET(ATTR_EFF_WRITE_DBI , &i_target, write_dbi); - if(rc) return rc; - uint8_t read_dbi; //Read DBI - NEW - rc = FAPI_ATTR_GET(ATTR_EFF_READ_DBI , &i_target, read_dbi); - if(rc) return rc; - - - if (ca_parity_latency == 4) - { - ca_parity_latency = 0x80; - } - else if (ca_parity_latency == 5) - { - ca_parity_latency = 0x40; - } - else if (ca_parity_latency == 6) - { - ca_parity_latency = 0xC0; - } - else if (ca_parity_latency == 8) - { - ca_parity_latency = 0x20; - } - else if (ca_parity_latency == ENUM_ATTR_EFF_CA_PARITY_LATENCY_DISABLE) - { - ca_parity_latency = 0x00; - } - - if (crc_error_clear == ENUM_ATTR_EFF_CRC_ERROR_CLEAR_ERROR) - { - crc_error_clear = 0xFF; - } - else if (crc_error_clear == ENUM_ATTR_EFF_CRC_ERROR_CLEAR_CLEAR) - { - crc_error_clear = 0x00; - } - - if (ca_parity_error_status == ENUM_ATTR_EFF_CA_PARITY_ERROR_STATUS_ERROR) - { - ca_parity_error_status = 0xFF; - } - else if (ca_parity_error_status == ENUM_ATTR_EFF_CA_PARITY_ERROR_STATUS_CLEAR) - { - ca_parity_error_status = 0x00; - } - - if (odt_input_buffer == ENUM_ATTR_EFF_ODT_INPUT_BUFF_ACTIVATED) - { - odt_input_buffer = 0x00; - } - else if (odt_input_buffer == ENUM_ATTR_EFF_ODT_INPUT_BUFF_DEACTIVATED) - { - odt_input_buffer = 0xFF; - } - - - if (ca_parity == ENUM_ATTR_EFF_CA_PARITY_ENABLE) - { - ca_parity = 0xFF; - } - else if (ca_parity == ENUM_ATTR_EFF_CA_PARITY_DISABLE) - { - ca_parity = 0x00; - } - - if (data_mask == ENUM_ATTR_EFF_DATA_MASK_DISABLE) - { - data_mask = 0x00; - } - else if (data_mask == ENUM_ATTR_EFF_DATA_MASK_ENABLE) - { - data_mask = 0xFF; - } - - if (write_dbi == ENUM_ATTR_EFF_WRITE_DBI_DISABLE) - { - write_dbi = 0x00; - } - else if (write_dbi == ENUM_ATTR_EFF_WRITE_DBI_ENABLE) - { - write_dbi = 0xFF; - } - - if (read_dbi == ENUM_ATTR_EFF_READ_DBI_DISABLE) - { - read_dbi = 0x00; - } - else if (read_dbi == ENUM_ATTR_EFF_READ_DBI_ENABLE) - { - read_dbi = 0xFF; - } - - //MRS6 - uint8_t vrefdq_train_value[2][2][4]; //vrefdq_train value - NEW - rc = FAPI_ATTR_GET( ATTR_VREF_DQ_TRAIN_VALUE, &i_target, vrefdq_train_value); - if(rc) return rc; - uint8_t vrefdq_train_range[2][2][4]; //vrefdq_train range - NEW - rc = FAPI_ATTR_GET( ATTR_VREF_DQ_TRAIN_RANGE, &i_target, vrefdq_train_range); - if(rc) return rc; - uint8_t vrefdq_train_enable[2][2][4]; //vrefdq_train enable - NEW - rc = FAPI_ATTR_GET( ATTR_VREF_DQ_TRAIN_ENABLE, &i_target, vrefdq_train_enable); - if(rc) return rc; - uint8_t tccd_l; //tccd_l - NEW - rc = FAPI_ATTR_GET( ATTR_TCCD_L, &i_target, tccd_l); - if(rc) return rc; - if (tccd_l == 4) - { - tccd_l = 0x00; - } - else if (tccd_l == 5) - { - tccd_l = 0x80; - } - else if (tccd_l == 6) - { - tccd_l = 0x40; - } - else if (tccd_l == 7) - { - tccd_l = 0xC0; - } - else if (tccd_l == 8) - { - tccd_l = 0x20; - } - - // Raise CKE high with NOPS, waiting min Reset CKE exit time (tXPR) - 400 cycles - rc_num = rc_num | cke_4.setBit(0,4); - rc_num = rc_num | csn_8.setBit(0,8); - rc_num = rc_num | address_16.clearBit(0, 16); - rc_num = rc_num | odt_4.clearBit(0,4); - rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 400, 0, 16); - if(rc_num) { - rc.setEcmdError(rc_num); - return rc; - } - rc = mss_ccs_inst_arry_0( i_target, - io_ccs_inst_cnt, - address_16, - bank_3, - activate_1, - rasn_1, - casn_1, - wen_1, - cke_4, - csn_8, - odt_4, - ddr_cal_type_4, - i_port_number); - if(rc) return rc; - rc = mss_ccs_inst_arry_1( i_target, - io_ccs_inst_cnt, - num_idles_16, - num_repeat_16, - data_20, - read_compare_1, - rank_cal_4, - ddr_cal_enable_1, - ccs_end_1); - if(rc) return rc; - io_ccs_inst_cnt ++; - - // Dimm 0-1 - for ( dimm_number = 0; dimm_number < MAX_NUM_DIMMS; dimm_number++) - { - //if the dram stack type is a 3DS dimm - if(dram_stack[i_port_number][dimm_number] == ENUM_ATTR_EFF_STACK_TYPE_STACK_3DS) { - FAPI_INF("DIMM is a 3DS type, using num_masetr_ranks_array"); - num_ranks = num_master_ranks_array[i_port_number][dimm_number]; - } - else { - num_ranks = num_ranks_array[i_port_number][dimm_number]; - } - - if (num_ranks == 0) - { - FAPI_INF( "PORT%d DIMM%d not configured. Num_ranks: %d ", i_port_number, dimm_number, num_ranks); - } - else - { - // Rank 0-3 - for ( rank_number = 0; rank_number < num_ranks; rank_number++) - { - FAPI_INF( "MRS SETTINGS FOR PORT%d DIMM%d RANK%d", i_port_number, dimm_number, rank_number); - - rc_num = rc_num | csn_8.setBit(0,8); - rc_num = rc_num | address_16.clearBit(0, 16); - - //For DDR4: - //Address 14 = Address 17, Address 15 = BG1 - rc_num = rc_num | mrs0.insert((uint8_t) dram_bl, 0, 2, 0); - rc_num = rc_num | mrs0.insert((uint8_t) dram_cl, 2, 1, 0); - rc_num = rc_num | mrs0.insert((uint8_t) read_bt, 3, 1, 0); - rc_num = rc_num | mrs0.insert((uint8_t) dram_cl, 4, 3, 1); - rc_num = rc_num | mrs0.insert((uint8_t) test_mode, 7, 1); - rc_num = rc_num | mrs0.insert((uint8_t) dll_reset, 8, 1); - rc_num = rc_num | mrs0.insert((uint8_t) dram_wr_rtp, 9, 3); - rc_num = rc_num | mrs0.insert((uint8_t) 0x00, 12, 4); - - rc_num = rc_num | mrs0.extractPreserve(&MRS0, 0, 16, 0); - if(rc_num) { - rc.setEcmdError(rc_num); - return rc; - } - - if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE) - { - dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0x00; - } - else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM240) //not supported - { - dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0x20; - FAPI_INF("DRAM RTT_NOM is configured for 240 OHM which is not supported."); - } - else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM48) //not supported - { - dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0xA0; - FAPI_INF("DRAM RTT_NOM is configured for 48 OHM which is not supported."); - } - else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40) - { - dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0xC0; - } - else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM60) - { - dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0x80; - } - else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM120) - { - dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0x40; - } - else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM80) // not supported - { - dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0x60; - FAPI_INF("DRAM RTT_NOM is configured for 80 OHM which is not supported."); - } - else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM34) // not supported - { - dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0xE0; - FAPI_INF("DRAM RTT_NOM is configured for 34 OHM which is not supported."); - } - - if (out_drv_imp_cntl[i_port_number][dimm_number] == ENUM_ATTR_VPD_DRAM_RON_OHM34) - { - out_drv_imp_cntl[i_port_number][dimm_number] = 0x00; - } - // Not currently supported - else if (out_drv_imp_cntl[i_port_number][dimm_number] == ENUM_ATTR_VPD_DRAM_RON_OHM48) //not supported - { - out_drv_imp_cntl[i_port_number][dimm_number] = 0x80; - FAPI_INF("DRAM RON is configured for 48 OHM which is not supported."); - } - - //For DDR4: - //Address 14 = Address 17, Address 15 = BG1 - rc_num = rc_num | mrs1.insert((uint8_t) dll_enable, 0, 1, 0); - rc_num = rc_num | mrs1.insert((uint8_t) out_drv_imp_cntl[i_port_number][dimm_number], 1, 2, 0); - rc_num = rc_num | mrs1.insert((uint8_t) dram_al, 3, 2, 0); - rc_num = rc_num | mrs1.insert((uint8_t) 0x00, 5, 2); - rc_num = rc_num | mrs1.insert((uint8_t) wr_lvl, 7, 1, 0); - rc_num = rc_num | mrs1.insert((uint8_t) dram_rtt_nom[i_port_number][dimm_number][rank_number], 8, 3, 0); - rc_num = rc_num | mrs1.insert((uint8_t) tdqs_enable, 11, 1, 0); - rc_num = rc_num | mrs1.insert((uint8_t) q_off, 12, 1, 0); - rc_num = rc_num | mrs1.insert((uint8_t) 0x00, 13, 3); - - - rc_num = rc_num | mrs1.extractPreserve(&MRS1, 0, 16, 0); - if(rc_num) { - rc.setEcmdError(rc_num); - return rc; - } - - - if (dram_rtt_wr[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE) - { - dram_rtt_wr[i_port_number][dimm_number][rank_number] = 0x00; - } - else if (dram_rtt_wr[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120) - { - dram_rtt_wr[i_port_number][dimm_number][rank_number] = 0x80; - } - else if (dram_rtt_wr[i_port_number][dimm_number][rank_number] == 240)//ENUM_ATTR_EFF_DRAM_RTT_WR_OHM240) - { - dram_rtt_wr[i_port_number][dimm_number][rank_number] = 0x40; - } - else if (dram_rtt_wr[i_port_number][dimm_number][rank_number] == 0xFF)//ENUM_ATTR_EFF_DRAM_RTT_WR_HIGHZ) - { - dram_rtt_wr[i_port_number][dimm_number][rank_number] = 0xFF; - } - - rc_num = rc_num | mrs2.insert((uint8_t) 0x00, 0, 3); - rc_num = rc_num | mrs2.insert((uint8_t) cwl, 3, 3); - rc_num = rc_num | mrs2.insert((uint8_t) lpasr, 6, 2); - rc_num = rc_num | mrs2.insert((uint8_t) 0x00, 8, 1); - rc_num = rc_num | mrs2.insert((uint8_t) dram_rtt_wr[i_port_number][dimm_number][rank_number], 9, 2); - rc_num = rc_num | mrs2.insert((uint8_t) 0x00, 11, 1); - rc_num = rc_num | mrs2.insert((uint8_t) write_crc, 12, 1); - rc_num = rc_num | mrs2.insert((uint8_t) 0x00, 13, 2); - - rc_num = rc_num | mrs2.extractPreserve(&MRS2, 0, 16, 0); - if(rc_num) { - rc.setEcmdError(rc_num); - return rc; - } - - rc_num = rc_num | mrs3.insert((uint8_t) mpr_page, 0, 2); - rc_num = rc_num | mrs3.insert((uint8_t) mpr_op, 2, 1); - rc_num = rc_num | mrs3.insert((uint8_t) geardown_mode, 3, 1); - rc_num = rc_num | mrs3.insert((uint8_t) dram_access, 4, 1); - rc_num = rc_num | mrs3.insert((uint8_t) temp_readout, 5, 1); - rc_num = rc_num | mrs3.insert((uint8_t) fine_refresh, 6, 3); - rc_num = rc_num | mrs3.insert((uint8_t) wr_latency, 9, 2); - rc_num = rc_num | mrs3.insert((uint8_t) read_format, 11, 2); - rc_num = rc_num | mrs3.insert((uint8_t) 0x00, 13, 2); - - - rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0); - if(rc_num) { - rc.setEcmdError(rc_num); - return rc; - } - - rc_num = rc_num | mrs4.insert((uint8_t) 0x00, 0, 1); - rc_num = rc_num | mrs4.insert((uint8_t) max_pd_mode, 1, 1); - rc_num = rc_num | mrs4.insert((uint8_t) temp_ref_range, 2, 1); - rc_num = rc_num | mrs4.insert((uint8_t) temp_ref_mode, 3, 1); - rc_num = rc_num | mrs4.insert((uint8_t) vref_mon, 4, 1); - rc_num = rc_num | mrs4.insert((uint8_t) 0x00, 5, 1); - rc_num = rc_num | mrs4.insert((uint8_t) cs_cmd_latency, 6, 3); - rc_num = rc_num | mrs4.insert((uint8_t) ref_abort, 9, 1); - rc_num = rc_num | mrs4.insert((uint8_t) rd_pre_train_mode, 10, 1); - rc_num = rc_num | mrs4.insert((uint8_t) rd_preamble, 11, 1); - rc_num = rc_num | mrs4.insert((uint8_t) wr_preamble, 12, 1); - rc_num = rc_num | mrs4.extractPreserve(&MRS4, 0, 16, 0); - if(rc_num) { - rc.setEcmdError(rc_num); - return rc; - } - - - //MRS5 - if (rtt_park[i_port_number][dimm_number][rank_number] == ENUM_ATTR_EFF_RTT_PARK_DISABLE) - { - rtt_park[i_port_number][dimm_number][rank_number] = 0x00; - } - else if (rtt_park[i_port_number][dimm_number][rank_number] == ENUM_ATTR_EFF_RTT_PARK_60OHM) - { - rtt_park[i_port_number][dimm_number][rank_number] = 0x80; - } - else if (rtt_park[i_port_number][dimm_number][rank_number] == ENUM_ATTR_EFF_RTT_PARK_40OHM) - { - rtt_park[i_port_number][dimm_number][rank_number] = 0xC0; - } - else if (rtt_park[i_port_number][dimm_number][rank_number] == ENUM_ATTR_EFF_RTT_PARK_120OHM) - { - rtt_park[i_port_number][dimm_number][rank_number] = 0x40; - } - else if (rtt_park[i_port_number][dimm_number][rank_number] == ENUM_ATTR_EFF_RTT_PARK_240OHM) - { - rtt_park[i_port_number][dimm_number][rank_number] = 0x20; - } - else if (rtt_park[i_port_number][dimm_number][rank_number] == ENUM_ATTR_EFF_RTT_PARK_48OHM) - { - rtt_park[i_port_number][dimm_number][rank_number] = 0xA0; - } - else if (rtt_park[i_port_number][dimm_number][rank_number] == ENUM_ATTR_EFF_RTT_PARK_80OHM) - { - rtt_park[i_port_number][dimm_number][rank_number] = 0x60; - } - else if (rtt_park[i_port_number][dimm_number][rank_number] == ENUM_ATTR_EFF_RTT_PARK_34OHM) - { - rtt_park[i_port_number][dimm_number][rank_number] = 0xE0; - } - - rc_num = rc_num | mrs5.insert((uint8_t) ca_parity_latency, 0, 2); - rc_num = rc_num | mrs5.insert((uint8_t) crc_error_clear, 3, 1); - rc_num = rc_num | mrs5.insert((uint8_t) ca_parity_error_status, 4, 1); - rc_num = rc_num | mrs5.insert((uint8_t) odt_input_buffer, 5, 1); - rc_num = rc_num | mrs5.insert((uint8_t) rtt_park[i_port_number][dimm_number][rank_number], 6, 3); - rc_num = rc_num | mrs5.insert((uint8_t) ca_parity, 9, 1); - rc_num = rc_num | mrs5.insert((uint8_t) data_mask, 10, 1); - rc_num = rc_num | mrs5.insert((uint8_t) write_dbi, 11, 1); - rc_num = rc_num | mrs5.insert((uint8_t) read_dbi, 12, 1); - rc_num = rc_num | mrs5.insert((uint8_t) 0x00, 13, 2); - - - rc_num = rc_num | mrs5.extractPreserve(&MRS5, 0, 16, 0); - if(rc_num) { - rc.setEcmdError(rc_num); - return rc; - } - - //MRS6 - - vrefdq_train_value[i_port_number][dimm_number][rank_number] = mss_reverse_8bits(vrefdq_train_value[i_port_number][dimm_number][rank_number]); - - if (vrefdq_train_range[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VREF_DQ_TRAIN_RANGE_RANGE1) - { - vrefdq_train_range[i_port_number][dimm_number][rank_number] = 0x00; - } - else if (vrefdq_train_range[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VREF_DQ_TRAIN_RANGE_RANGE2) - { - vrefdq_train_range[i_port_number][dimm_number][rank_number] = 0xFF; - } - - if (vrefdq_train_enable[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE) - { - vrefdq_train_enable[i_port_number][dimm_number][rank_number] = 0xFF; - } - else if (vrefdq_train_enable[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_DISABLE) - { - vrefdq_train_enable[i_port_number][dimm_number][rank_number] = 0x00; - } - - rc_num = rc_num | mrs6.insert((uint8_t) vrefdq_train_value[i_port_number][dimm_number][rank_number], 0, 6); - rc_num = rc_num | mrs6.insert((uint8_t) vrefdq_train_range[i_port_number][dimm_number][rank_number], 6, 1); - rc_num = rc_num | mrs6.insert((uint8_t) vrefdq_train_enable[i_port_number][dimm_number][rank_number], 7, 1); - rc_num = rc_num | mrs6.insert((uint8_t) 0x00, 8, 2); - rc_num = rc_num | mrs6.insert((uint8_t) tccd_l, 10, 3); - rc_num = rc_num | mrs6.insert((uint8_t) 0x00, 13, 2); - - rc_num = rc_num | mrs6_train_on.insert((uint8_t) vrefdq_train_value[i_port_number][dimm_number][rank_number], 0, 6); - rc_num = rc_num | mrs6_train_on.insert((uint8_t) vrefdq_train_range[i_port_number][dimm_number][rank_number], 6, 1); - rc_num = rc_num | mrs6_train_on.insert((uint8_t) 0xff, 7, 1); - rc_num = rc_num | mrs6_train_on.insert((uint8_t) 0x00, 8, 2); - rc_num = rc_num | mrs6_train_on.insert((uint8_t) tccd_l, 10, 3); - rc_num = rc_num | mrs6_train_on.insert((uint8_t) 0x00, 13, 2); - - - rc_num = rc_num | mrs6.extractPreserve(&MRS6, 0, 16, 0); - - FAPI_INF( "MRS 0: 0x%04X", MRS0); - FAPI_INF( "MRS 1: 0x%04X", MRS1); - FAPI_INF( "MRS 2: 0x%04X", MRS2); - FAPI_INF( "MRS 3: 0x%04X", MRS3); - FAPI_INF( "MRS 4: 0x%04X", MRS4); - FAPI_INF( "MRS 5: 0x%04X", MRS5); - FAPI_INF( "MRS 6: 0x%04X", MRS6); - - if (rc_num) - { - FAPI_ERR( "mss_mrs_load: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - - // Only corresponding CS to rank - rc_num = rc_num | csn_8.setBit(0,8); - rc_num = rc_num | csn_8.clearBit(rank_number+4*dimm_number); - - if(rc_num) { - rc.setEcmdError(rc_num); - return rc; - } - - uint8_t dram_stack[2][2]; - rc = FAPI_ATTR_GET(ATTR_EFF_STACK_TYPE, &i_target, dram_stack); - if(rc) return rc; - - FAPI_INF( "Stack Type: %d\n", dram_stack[0][0]); - if (dram_stack[0][0] == ENUM_ATTR_EFF_STACK_TYPE_STACK_3DS) - { - FAPI_INF( "============= Got in the 3DS stack loop CKE !!!!=====================\n"); - rc_num = rc_num | csn_8.clearBit(2+4*dimm_number,2); - // COMMENT IN LATER!!!! rc_num = rc_num | cke_4.clearBit(1); - if(rc_num) { - rc.setEcmdError(rc_num); - return rc; - } - } - - // Propogate through the 4 MRS cmds - for ( mrs_number = 0; mrs_number < 7; mrs_number++) - { - //mrs_number = 1; - // Copying the current MRS into address buffer matching the MRS_array order - // Setting the bank address - if (mrs_number == 0) - { - rc_num = rc_num | address_16.insert(mrs3, 0, 16, 0); - rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 0, 1, 7); - rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 1, 1, 6); - rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 2, 1, 5); - } - else if ( mrs_number == 1) - { - - rc_num = rc_num | address_16.insert(mrs6, 0, 16, 0); - rc_num = rc_num | bank_3.insert((uint8_t) MRS6_BA, 0, 1, 7); - rc_num = rc_num | bank_3.insert((uint8_t) MRS6_BA, 1, 1, 6); - rc_num = rc_num | bank_3.insert((uint8_t) MRS6_BA, 2, 1, 5); - } - else if ( mrs_number == 2) - { - rc_num = rc_num | address_16.insert(mrs5, 0, 16, 0); - rc_num = rc_num | bank_3.insert((uint8_t) MRS5_BA, 0, 1, 7); - rc_num = rc_num | bank_3.insert((uint8_t) MRS5_BA, 1, 1, 6); - rc_num = rc_num | bank_3.insert((uint8_t) MRS5_BA, 2, 1, 5); - } - else if ( mrs_number == 3) - { - rc_num = rc_num | address_16.insert(mrs4, 0, 16, 0); - rc_num = rc_num | bank_3.insert((uint8_t) MRS4_BA, 0, 1, 7); - rc_num = rc_num | bank_3.insert((uint8_t) MRS4_BA, 1, 1, 6); - rc_num = rc_num | bank_3.insert((uint8_t) MRS4_BA, 2, 1, 5); - } - else if ( mrs_number == 4) - { - rc_num = rc_num | address_16.insert(mrs2, 0, 16, 0); - rc_num = rc_num | bank_3.insert((uint8_t) MRS2_BA, 0, 1, 7); - rc_num = rc_num | bank_3.insert((uint8_t) MRS2_BA, 1, 1, 6); - rc_num = rc_num | bank_3.insert((uint8_t) MRS2_BA, 2, 1, 5); - } - else if ( mrs_number == 5) - { - rc_num = rc_num | address_16.insert(mrs1, 0, 16, 0); - rc_num = rc_num | bank_3.insert((uint8_t) MRS1_BA, 0, 1, 7); - rc_num = rc_num | bank_3.insert((uint8_t) MRS1_BA, 1, 1, 6); - rc_num = rc_num | bank_3.insert((uint8_t) MRS1_BA, 2, 1, 5); - } - else if ( mrs_number == 6) - { - rc_num = rc_num | address_16.insert(mrs0, 0, 16, 0); - rc_num = rc_num | bank_3.insert((uint8_t) MRS0_BA, 0, 1, 7); - rc_num = rc_num | bank_3.insert((uint8_t) MRS0_BA, 1, 1, 6); - rc_num = rc_num | bank_3.insert((uint8_t) MRS0_BA, 2, 1, 5); - } - //mrs_number = 7; - - if (( address_mirror_map[i_port_number][dimm_number] & (0x08 >> rank_number) ) && (is_sim == 0)) - { - rc = mss_address_mirror_swizzle(i_target, i_port_number, dimm_number, rank_number, address_16, bank_3); - if(rc) return rc; - } - - - if (rc_num) - { - FAPI_ERR( "mss_mrs_load: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - - // Send out to the CCS array - rc = mss_ccs_inst_arry_0( i_target, - io_ccs_inst_cnt, - address_16, - bank_3, - activate_1, - rasn_1, - casn_1, - wen_1, - cke_4, - csn_8, - odt_4, - ddr_cal_type_4, - i_port_number); - if(rc) return rc; - rc = mss_ccs_inst_arry_1( i_target, - io_ccs_inst_cnt, - num_idles_16, - num_repeat_16, - data_20, - read_compare_1, - rank_cal_4, - ddr_cal_enable_1, - ccs_end_1); - if(rc) return rc; - io_ccs_inst_cnt ++; - - - - } - - // Address inversion for RCD - if ( (dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_RDIMM) || (dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) ) - { - FAPI_INF( "Sending out MRS with Address Inversion to B-side DRAMs\n"); - - - // Propogate through the 4 MRS cmds - for ( mrs_number = 0; mrs_number < 7; mrs_number++) - { - //mrs_number = 1; - // Copying the current MRS into address buffer matching the MRS_array order - // Setting the bank address - if (mrs_number == 0) - { - rc_num = rc_num | address_16.insert(mrs3, 0, 16, 0); - rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 0, 1, 7); - rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 1, 1, 6); - rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 2, 1, 5); - } - else if ( mrs_number == 1) - { - - - rc_num = rc_num | address_16.insert(mrs6, 0, 16, 0); - rc_num = rc_num | bank_3.insert((uint8_t) MRS6_BA, 0, 1, 7); - rc_num = rc_num | bank_3.insert((uint8_t) MRS6_BA, 1, 1, 6); - rc_num = rc_num | bank_3.insert((uint8_t) MRS6_BA, 2, 1, 5); - } - else if ( mrs_number == 2) - { - rc_num = rc_num | address_16.insert(mrs5, 0, 16, 0); - rc_num = rc_num | bank_3.insert((uint8_t) MRS5_BA, 0, 1, 7); - rc_num = rc_num | bank_3.insert((uint8_t) MRS5_BA, 1, 1, 6); - rc_num = rc_num | bank_3.insert((uint8_t) MRS5_BA, 2, 1, 5); - } - else if ( mrs_number == 3) - { - rc_num = rc_num | address_16.insert(mrs4, 0, 16, 0); - rc_num = rc_num | bank_3.insert((uint8_t) MRS4_BA, 0, 1, 7); - rc_num = rc_num | bank_3.insert((uint8_t) MRS4_BA, 1, 1, 6); - rc_num = rc_num | bank_3.insert((uint8_t) MRS4_BA, 2, 1, 5); - } - else if ( mrs_number == 4) - { - rc_num = rc_num | address_16.insert(mrs2, 0, 16, 0); - rc_num = rc_num | bank_3.insert((uint8_t) MRS2_BA, 0, 1, 7); - rc_num = rc_num | bank_3.insert((uint8_t) MRS2_BA, 1, 1, 6); - rc_num = rc_num | bank_3.insert((uint8_t) MRS2_BA, 2, 1, 5); - } - else if ( mrs_number == 5) - { - rc_num = rc_num | address_16.insert(mrs1, 0, 16, 0); - rc_num = rc_num | bank_3.insert((uint8_t) MRS1_BA, 0, 1, 7); - rc_num = rc_num | bank_3.insert((uint8_t) MRS1_BA, 1, 1, 6); - rc_num = rc_num | bank_3.insert((uint8_t) MRS1_BA, 2, 1, 5); - } - else if ( mrs_number == 6) - { - rc_num = rc_num | address_16.insert(mrs0, 0, 16, 0); - rc_num = rc_num | bank_3.insert((uint8_t) MRS0_BA, 0, 1, 7); - rc_num = rc_num | bank_3.insert((uint8_t) MRS0_BA, 1, 1, 6); - rc_num = rc_num | bank_3.insert((uint8_t) MRS0_BA, 2, 1, 5); - } - - // Indicate B-Side DRAMS BG1=1 - rc_num = rc_num | address_16.setBit(15); // Set BG1 = 1 - - rc_num = rc_num | address_16.flipBit(3,7); // Invert A3:A9 - rc_num = rc_num | address_16.flipBit(11); // Invert A11 - rc_num = rc_num | address_16.flipBit(13); // Invert A13 - rc_num = rc_num | address_16.flipBit(14); // Invert A17 - rc_num = rc_num | bank_3.flipBit(0,3); // Invert BA0,BA1,BG0 - - - if (( address_mirror_map[i_port_number][dimm_number] & (0x08 >> rank_number) ) && (is_sim == 0)) - { - rc = mss_address_mirror_swizzle(i_target, i_port_number, dimm_number, rank_number, address_16, bank_3); - if(rc) return rc; - } - - - if (rc_num) - { - FAPI_ERR( " Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - - // Send out to the CCS array - rc = mss_ccs_inst_arry_0( i_target, - io_ccs_inst_cnt, - address_16, - bank_3, - activate_1, - rasn_1, - casn_1, - wen_1, - cke_4, - csn_8, - odt_4, - ddr_cal_type_4, - i_port_number); - if(rc) return rc; - rc = mss_ccs_inst_arry_1( i_target, - io_ccs_inst_cnt, - num_idles_16, - num_repeat_16, - data_20, - read_compare_1, - rank_cal_4, - ddr_cal_enable_1, - ccs_end_1); - if(rc) return rc; - io_ccs_inst_cnt ++; - - } - } - - } - } - } - - return rc; -} - -//#endif - - - - - - diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_ddr4_pda.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_ddr4_pda.C deleted file mode 100644 index 9dd69c773..000000000 --- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_ddr4_pda.C +++ /dev/null @@ -1,3503 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_ddr4_pda.C $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2015 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: mss_ddr4_pda.C,v 1.42 2015/07/23 14:18:55 sglancy Exp $ -//------------------------------------------------------------------------------ -// *! (C) Copyright International Business Machines Corp. 2013 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -//------------------------------------------------------------------------------ -// *! TITLE : mss_ddr4_pda.C -// *! DESCRIPTION : Tools for DDR4 DIMMs centaur procedures -// *! OWNER NAME : Stephen Glancy Email: sglancy@us.ibm.com -// *! BACKUP NAME : Andre Marin Email: aamarin@us.ibm.com -// #! ADDITIONAL COMMENTS : -// - -//------------------------------------------------------------------------------ -// Don't forget to create CVS comments when you check in your changes! -//------------------------------------------------------------------------------ -// CHANGE HISTORY: -//------------------------------------------------------------------------------ -// Version:| Author: | Date: | Comment: -//---------|----------|---------|----------------------------------------------- -// 1.11 | 07/23/15 | sglancy | Changed code to address FW comments -// 1.10 | 06/09/15 | sglancy | Fixed bug -// 1.9 | 05/27/15 | sglancy | Fixed bug -// 1.8 | 05/13/15 | sglancy | Added new checks, FFDC, and checked -// 1.7 | 05/11/15 | sglancy | Fixed compile errors -// 1.6 | 05/11/15 | sglancy | Updated for FW comments -// 1.5 | 05/07/15 | sglancy | Updated for FW comments -// 1.4 | 04/22/15 | sglancy | Fixed several code bugs -// 1.3 | 04/21/15 | sglancy | Added support for R and LR DIMMs as well as x8, fixed minor bug in setup and disable code -// 1.2 | 11/27/14 | sglancy | Updated to allow for file inputs and changed print statements -// 1.1 | 10/27/14 | sglancy | First revision - - -//---------------------------------------------------------------------- -// Includes -//---------------------------------------------------------------------- -#include <fapi.H> -#include <mss_ddr4_pda.H> -#include <mss_funcs.H> -#include <cen_scom_addresses.H> -#include <mss_access_delay_reg.H> -#include <vector> -#include <algorithm> -using namespace fapi; -using namespace std; -extern "C" { - -//PDA_Scom_Storage constructor -PDA_Scom_Storage::PDA_Scom_Storage(uint64_t sa, uint32_t sb, uint32_t nb) { - scom_addr = sa; - start_bit = sb; - num_bits = nb; -} -PDA_Scom_Storage::~PDA_Scom_Storage() {} - -//PDA_MRS_Storage class constructor -PDA_MRS_Storage::PDA_MRS_Storage(uint8_t ad,uint32_t an,uint8_t dr,uint8_t di,uint8_t r,uint8_t p) { - attribute_data = ad; - attribute_name = an; - dram = dr; - dimm = di; - rank = r; - port = p; - MRS = 0xFF; - pda_string[0] = '\0'; -} - -const uint8_t MRS0_BA = 0; -const uint8_t MRS1_BA = 1; -const uint8_t MRS2_BA = 2; -const uint8_t MRS3_BA = 3; -const uint8_t MRS4_BA = 4; -const uint8_t MRS5_BA = 5; -const uint8_t MRS6_BA = 6; -const uint8_t MAX_NUM_DP18S = 5; -const uint8_t MAX_NUM_PORTS = 2; -const uint8_t MAX_NUM_DIMMS = 2; -const uint8_t PORT_SIZE = 2; - -//generates the string -void PDA_MRS_Storage::generatePDAString() { - snprintf(pda_string,MAX_ECMD_STRING_LEN,"ATTR_NAME 0x%08x ATTR_DATA 0x%02x MRS %d P %d DI %d R %d DR %d",attribute_name,attribute_data,MRS,port,dimm,rank,dram); -} - -//sends out the string -char * PDA_MRS_Storage::c_str() { - //generate new string - generatePDAString(); //note using a separate function here in case some other function would need to call the generation of the string - return pda_string; -} - -//Checks to make sure that -ReturnCode PDA_MRS_Storage::checkPDAValid(Target& i_target) { - ReturnCode rc; - - //checks constants first - //ports out of range - if(port >= MAX_NUM_PORTS) { - const uint32_t PORT_VALUE = port; - const uint32_t DIMM_VALUE = dimm; - const uint32_t RANK_VALUE = rank; - const uint32_t DRAM_VALUE = dram; - const fapi::Target & MBA_TARGET = i_target; - FAPI_SET_HWP_ERROR(rc, RC_MSS_PDA_DRAM_DNE); - FAPI_ERR("ERROR!! Port out of valid range! Exiting..."); - return rc; - } - - //DIMMs out of range - if(dimm >= MAX_NUM_DIMMS) { - const uint32_t PORT_VALUE = port; - const uint32_t DIMM_VALUE = dimm; - const uint32_t RANK_VALUE = rank; - const uint32_t DRAM_VALUE = dram; - const fapi::Target & MBA_TARGET = i_target; - FAPI_SET_HWP_ERROR(rc, RC_MSS_PDA_DRAM_DNE); - FAPI_ERR("ERROR!! DIMM out of valid range! Exiting..."); - return rc; - } - - //now checks based upon attributes - uint8_t num_ranks[2][2]; - rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM,&i_target,num_ranks); - if(rc) return rc; - - //no ranks on the selected dimm - if(num_ranks[port][dimm] == 0) { - const uint32_t PORT_VALUE = port; - const uint32_t DIMM_VALUE = dimm; - const uint32_t RANK_VALUE = rank; - const uint32_t DRAM_VALUE = dram; - const fapi::Target & MBA_TARGET = i_target; - FAPI_SET_HWP_ERROR(rc, RC_MSS_PDA_DRAM_DNE); - FAPI_ERR("ERROR!! DIMM has no valid ranks! Exiting..."); - return rc; - } - - //rank is out of range - if(num_ranks[port][dimm] <= rank) { - const uint32_t PORT_VALUE = port; - const uint32_t DIMM_VALUE = dimm; - const uint32_t RANK_VALUE = rank; - const uint32_t DRAM_VALUE = dram; - const fapi::Target & MBA_TARGET = i_target; - FAPI_SET_HWP_ERROR(rc, RC_MSS_PDA_DRAM_DNE); - FAPI_ERR("ERROR!! Rank is out of bounds! Exiting..."); - return rc; - } - - uint8_t num_spares[2][2][4]; - rc = FAPI_ATTR_GET(ATTR_VPD_DIMM_SPARE,&i_target,num_spares); - if(rc) return rc; - - uint8_t dram_width; - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH,&i_target,dram_width); - if(rc) return rc; - - uint8_t num_spare = 0; - if(num_spares[port][dimm][rank] == ENUM_ATTR_VPD_DIMM_SPARE_LOW_NIBBLE) { - num_spare = 1; - } - if(num_spares[port][dimm][rank] == ENUM_ATTR_VPD_DIMM_SPARE_HIGH_NIBBLE) { - num_spare = 1; - } - if(num_spares[port][dimm][rank] == ENUM_ATTR_VPD_DIMM_SPARE_FULL_BYTE && dram_width == ENUM_ATTR_EFF_DRAM_WIDTH_X4) { - num_spare = 2; - } - if(num_spares[port][dimm][rank] == ENUM_ATTR_VPD_DIMM_SPARE_FULL_BYTE && dram_width == ENUM_ATTR_EFF_DRAM_WIDTH_X8) { - num_spare = 1; - } - - uint8_t num_dram = 72/dram_width + num_spare; - if(num_dram <= dram) { - const uint32_t PORT_VALUE = port; - const uint32_t DIMM_VALUE = dimm; - const uint32_t RANK_VALUE = rank; - const uint32_t DRAM_VALUE = dram; - const fapi::Target & MBA_TARGET = i_target; - FAPI_SET_HWP_ERROR(rc, RC_MSS_PDA_DRAM_DNE); - FAPI_ERR("ERROR!! DRAM is out of bounds! Exiting..."); - return rc; - } - - return rc; -} - -//sets the MRS variable based upon the inputted attribute name -ReturnCode PDA_MRS_Storage::setMRSbyAttr(Target& i_target) { - fapi::ReturnCode rc; - switch(attribute_name) { - - //MRS0 - case ATTR_EFF_DRAM_BL: MRS = MRS0_BA; break; - case ATTR_EFF_DRAM_RBT: MRS = MRS0_BA; break; - case ATTR_EFF_DRAM_CL: MRS = MRS0_BA; break; - case ATTR_EFF_DRAM_TM: MRS = MRS0_BA; break; - case ATTR_EFF_DRAM_DLL_RESET: MRS = MRS0_BA; break; - case ATTR_EFF_DRAM_WR: MRS = MRS0_BA; break; - case ATTR_EFF_DRAM_TRTP: MRS = MRS0_BA; break; - case ATTR_EFF_DRAM_DLL_PPD: MRS = MRS0_BA; break; - - //MRS1 - case ATTR_EFF_DRAM_DLL_ENABLE: MRS = MRS1_BA; break; - case ATTR_VPD_DRAM_RON: MRS = MRS1_BA; break; - case ATTR_VPD_DRAM_RTT_NOM: MRS = MRS1_BA; break; - case ATTR_EFF_DRAM_AL: MRS = MRS1_BA; break; - case ATTR_EFF_DRAM_WR_LVL_ENABLE: MRS = MRS1_BA; break; - case ATTR_EFF_DRAM_TDQS: MRS = MRS1_BA; break; - case ATTR_EFF_DRAM_OUTPUT_BUFFER: MRS = MRS1_BA; break; - - //MRS2 - case ATTR_EFF_DRAM_LPASR: MRS = MRS2_BA; break; - case ATTR_EFF_DRAM_CWL: MRS = MRS2_BA; break; - case ATTR_VPD_DRAM_RTT_WR: MRS = MRS2_BA; break; - case ATTR_EFF_WRITE_CRC: MRS = MRS2_BA; break; - - //MRS3 - case ATTR_EFF_MPR_MODE: MRS = MRS3_BA; break; - case ATTR_EFF_MPR_PAGE: MRS = MRS3_BA; break; - case ATTR_EFF_GEARDOWN_MODE: MRS = MRS3_BA; break; - case ATTR_EFF_PER_DRAM_ACCESS: MRS = MRS3_BA; break; - case ATTR_EFF_TEMP_READOUT: MRS = MRS3_BA; break; - case ATTR_EFF_FINE_REFRESH_MODE: MRS = MRS3_BA; break; - case ATTR_EFF_CRC_WR_LATENCY: MRS = MRS3_BA; break; - case ATTR_EFF_MPR_RD_FORMAT: MRS = MRS3_BA; break; - - //MRS4 - case ATTR_EFF_MAX_POWERDOWN_MODE: MRS = MRS4_BA; break; - case ATTR_EFF_TEMP_REF_RANGE: MRS = MRS4_BA; break; - case ATTR_EFF_TEMP_REF_MODE: MRS = MRS4_BA; break; - case ATTR_EFF_INT_VREF_MON: MRS = MRS4_BA; break; - case ATTR_EFF_CS_CMD_LATENCY: MRS = MRS4_BA; break; - case ATTR_EFF_SELF_REF_ABORT: MRS = MRS4_BA; break; - case ATTR_EFF_RD_PREAMBLE_TRAIN: MRS = MRS4_BA; break; - case ATTR_EFF_RD_PREAMBLE: MRS = MRS4_BA; break; - case ATTR_EFF_WR_PREAMBLE: MRS = MRS4_BA; break; - - - //MRS5 - case ATTR_EFF_CA_PARITY_LATENCY : MRS = MRS5_BA; break; - case ATTR_EFF_CRC_ERROR_CLEAR : MRS = MRS5_BA; break; - case ATTR_EFF_CA_PARITY_ERROR_STATUS : MRS = MRS5_BA; break; - case ATTR_EFF_ODT_INPUT_BUFF : MRS = MRS5_BA; break; - case ATTR_EFF_RTT_PARK : MRS = MRS5_BA; break; - case ATTR_EFF_CA_PARITY : MRS = MRS5_BA; break; - case ATTR_EFF_DATA_MASK : MRS = MRS5_BA; break; - case ATTR_EFF_WRITE_DBI : MRS = MRS5_BA; break; - case ATTR_EFF_READ_DBI : MRS = MRS5_BA; break; - - //MRS6 - case ATTR_VREF_DQ_TRAIN_VALUE: MRS = MRS6_BA; break; - case ATTR_VREF_DQ_TRAIN_RANGE: MRS = MRS6_BA; break; - case ATTR_VREF_DQ_TRAIN_ENABLE: MRS = MRS6_BA; break; - case ATTR_TCCD_L: MRS = MRS6_BA; break; - - //MRS attribute not found, error out - default: - const uint32_t NONMRS_ATTR_NAME = attribute_name; - const fapi::Target & MBA_TARGET = i_target; - FAPI_SET_HWP_ERROR(rc, RC_MSS_PDA_NONMRS_ATTR_NAME); - FAPI_ERR("ERROR!! Found attribute name not associated with an MRS! Exiting..."); - } - return rc; -}//end setMRSbyAttr - -//PDA_MRS_Storage class destructor -PDA_MRS_Storage::~PDA_MRS_Storage() {} - -bool PDA_MRS_Storage::operator> (const PDA_MRS_Storage &PDA2) const { - //check on the DRAM first - //DRAM for A is greater than B return true - if(dram > PDA2.dram) return true; - //B > A -> false - else if(dram < PDA2.dram) return false; - //B == A, so go to port - //A > B -> true - else if(port > PDA2.port) return true; - //A < B -> false - else if(port < PDA2.port) return false; - //ports are equal, so start comparing dimms - //A > B -> true - else if(dimm > PDA2.dimm) return true; - //A < B -> false - else if(dimm < PDA2.dimm) return false; - //dimms are equal, so start comparing ranks - //A > B -> true - else if(rank > PDA2.rank) return true; - //A < B -> false - else if(rank < PDA2.rank) return false; - //ports are equal, so start comparing the MRS number - //A > B -> true - else if(MRS > PDA2.MRS) return true; - //A < B -> false - else if(MRS < PDA2.MRS) return false; - //ports are equal, so start comparing the attribute_name - //A > B -> true - else if(attribute_name > PDA2.attribute_name) return true; - //A < B -> false - else if(attribute_name < PDA2.attribute_name) return false; - //ports are equal, so start comparing the attribute_data - //A > B -> true - else if(attribute_data > PDA2.attribute_data) return true; - //equal or less than - return false; -}//end operator> - -bool PDA_MRS_Storage::operator< (const PDA_MRS_Storage &PDA2) const { -//check on the DRAM first - //DRAM for A is less than B return true - if(dram < PDA2.dram) return true; - //B < A -> false - else if(dram > PDA2.dram) return false; - //B == A, so go to port - //A < B -> true - else if(port < PDA2.port) return true; - //A > B -> false - else if(port > PDA2.port) return false; - //ports are equal, so start comparing dimms - //A < B -> true - else if(dimm < PDA2.dimm) return true; - //A > B -> false - else if(dimm > PDA2.dimm) return false; - //dimms are equal, so start comparing ranks - //A < B -> true - else if(rank < PDA2.rank) return true; - //A > B -> false - else if(rank > PDA2.rank) return false; - //ports are equal, so start comparing the MRS number - //A < B -> true - else if(MRS < PDA2.MRS) return true; - //A > B -> false - else if(MRS > PDA2.MRS) return false; - //ports are equal, so start comparing the attribute_name - //A < B -> true - else if(attribute_name < PDA2.attribute_name) return true; - //A > B -> false - else if(attribute_name > PDA2.attribute_name) return false; - //ports are equal, so start comparing the attribute_data - //A < B -> true - else if(attribute_data < PDA2.attribute_data) return true; - //equal or greater than - return false; -}//end operator< - - -///////////////////////////////////////////////////////////////////////////////// -/// PDA_MRS_Storage::copy -/// copies one PDA_MRS_Storage to this one -///////////////////////////////////////////////////////////////////////////////// -void PDA_MRS_Storage::copy(PDA_MRS_Storage &temp) { - attribute_data = temp.attribute_data; - attribute_name = temp.attribute_name; - MRS = temp.MRS ; - dram = temp.dram ; - dimm = temp.dimm ; - rank = temp.rank ; - port = temp.port ; -} - -///////////////////////////////////////////////////////////////////////////////// -/// mss_ddr4_checksort_pda -/// sorts the vector of PDA_MRS_Storage, so the commands will be run in a more efficient order -///////////////////////////////////////////////////////////////////////////////// -ReturnCode mss_ddr4_checksort_pda(Target& i_target, vector<PDA_MRS_Storage>& pda) { - ReturnCode rc; - - //does the check to make sure all given attributes are associated with an MRS - for(uint32_t i=0;i<pda.size();i++) { - rc = pda[i].setMRSbyAttr(i_target); - if(rc) return rc; - rc = pda[i].checkPDAValid(i_target); - if(rc) return rc; - } - - //does the sort, sorting by the class comparator (should be DRAM first) - sort(pda.begin(),pda.end()); - - return rc; -} - - -///////////////////////////////////////////////////////////////////////////////// -/// mss_ddr4_setup_pda -/// sets up per-DRAM addressability funcitonality on both ports on the passed MBA -///////////////////////////////////////////////////////////////////////////////// -ReturnCode mss_ddr4_setup_pda( - Target& i_target, - uint32_t& io_ccs_inst_cnt - ) -{ - uint32_t i_port_number=0; - uint32_t dimm_number; - uint32_t rank_number; - const uint32_t NUM_POLL = 10; - const uint32_t WAIT_TIMER = 1500; - ReturnCode rc; - ReturnCode rc_buff; - uint32_t rc_num = 0; - uint64_t reg_address; - ecmdDataBufferBase data_buffer(64); - ecmdDataBufferBase address_16(16); - ecmdDataBufferBase bank_3(3); - ecmdDataBufferBase activate_1(1); - rc_num = rc_num | activate_1.setBit(0); - ecmdDataBufferBase rasn_1(1); - ecmdDataBufferBase casn_1(1); - ecmdDataBufferBase wen_1(1); - ecmdDataBufferBase cke_4(4); - rc_num = rc_num | cke_4.setBit(0,4); - ecmdDataBufferBase csn_8(8); - rc_num = rc_num | csn_8.setBit(0,8); - ecmdDataBufferBase odt_4(4); - ecmdDataBufferBase ddr_cal_type_4(4); - - ecmdDataBufferBase num_idles_16(16); - ecmdDataBufferBase num_repeat_16(16); - ecmdDataBufferBase data_20(20); - ecmdDataBufferBase read_compare_1(1); - ecmdDataBufferBase rank_cal_4(4); - ecmdDataBufferBase ddr_cal_enable_1(1); - ecmdDataBufferBase ccs_end_1(1); - - ecmdDataBufferBase mrs3(16); - uint16_t MRS3 = 0; - - uint8_t num_ranks_array[2][2]; //[port][dimm] - - uint8_t dimm_type; - rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target, dimm_type); - if(rc) return rc; - - uint8_t num_ranks; - rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target, num_ranks_array); - if(rc) return rc; - - uint8_t is_sim = 0; - rc = FAPI_ATTR_GET(ATTR_IS_SIMULATION, NULL, is_sim); - if(rc) return rc; - - uint8_t address_mirror_map[2][2]; //address_mirror_map[port][dimm] - rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_ADDRESS_MIRRORING, &i_target, address_mirror_map); - if(rc) return rc; - - // WORKAROUNDS - rc = fapiGetScom(i_target, CCS_MODEQ_AB_REG_0x030106A7, data_buffer); - if(rc) return rc; - //Setting up CCS mode - rc_num = rc_num | data_buffer.setBit(51); - - if (rc_num) - { - FAPI_ERR( "mss_ddr4_setup_pda: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - - rc = fapiPutScom(i_target, CCS_MODEQ_AB_REG_0x030106A7, data_buffer); - if(rc) return rc; - - //loops through port 0 and port 1 on the given MBA - for(i_port_number=0;i_port_number<MAX_NUM_PORTS;i_port_number++) { - // Raise CKE high with NOPS, waiting min Reset CKE exit time (tXPR) - 400 cycles - rc_num = rc_num | cke_4.setBit(0,4); - rc_num = rc_num | csn_8.setBit(0,8); - rc_num = rc_num | address_16.clearBit(0, 16); - rc_num = rc_num | odt_4.clearBit(0,4); - rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 400, 0, 16); - if (rc_num) - { - FAPI_ERR( "mss_ddr4_setup_pda: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - - rc = mss_ccs_inst_arry_0( i_target, - io_ccs_inst_cnt, - address_16, - bank_3, - activate_1, - rasn_1, - casn_1, - wen_1, - cke_4, - csn_8, - odt_4, - ddr_cal_type_4, - i_port_number); - if(rc) return rc; - rc = mss_ccs_inst_arry_1( i_target, - io_ccs_inst_cnt, - num_idles_16, - num_repeat_16, - data_20, - read_compare_1, - rank_cal_4, - ddr_cal_enable_1, - ccs_end_1); - if(rc) return rc; - io_ccs_inst_cnt ++; - } - - - //Sets up MRS3 -> the MRS that has PDA - uint8_t mpr_op; // MPR Op - rc = FAPI_ATTR_GET(ATTR_EFF_MPR_MODE, &i_target, mpr_op); - if(rc) return rc; - uint8_t mpr_page; // MPR Page Selection - NEW - rc = FAPI_ATTR_GET(ATTR_EFF_MPR_PAGE, &i_target, mpr_page); - if(rc) return rc; - uint8_t geardown_mode; // Gear Down Mode - NEW - rc = FAPI_ATTR_GET(ATTR_EFF_GEARDOWN_MODE, &i_target, geardown_mode); - if(rc) return rc; - uint8_t temp_readout; // Temperature sensor readout - NEW - rc = FAPI_ATTR_GET(ATTR_EFF_TEMP_READOUT, &i_target, temp_readout); - if(rc) return rc; - uint8_t fine_refresh; // fine refresh mode - NEW - rc = FAPI_ATTR_GET(ATTR_EFF_FINE_REFRESH_MODE, &i_target, fine_refresh); - if(rc) return rc; - uint8_t wr_latency; // write latency for CRC and DM - NEW - rc = FAPI_ATTR_GET(ATTR_EFF_CRC_WR_LATENCY, &i_target, wr_latency); - if(rc) return rc; - uint8_t read_format; // MPR READ FORMAT - NEW - rc = FAPI_ATTR_GET(ATTR_EFF_MPR_RD_FORMAT, &i_target, read_format); - if(rc) return rc; - - //enables PDA mode - //loops through all ports - for(i_port_number=0;i_port_number<MAX_NUM_PORTS;i_port_number++) { - // Dimm 0-1 - for ( dimm_number = 0; dimm_number < MAX_NUM_DIMMS; dimm_number++) - { - num_ranks = num_ranks_array[i_port_number][dimm_number]; - - if (num_ranks == 0) - { - FAPI_INF( "PORT%d DIMM%d not configured. Num_ranks: %d ", i_port_number, dimm_number, num_ranks); - } - else - { - // Rank 0-3 - for ( rank_number = 0; rank_number < num_ranks; rank_number++) - { - // Only corresponding CS to rank - rc_num = rc_num | csn_8.setBit(0,8); - rc_num = rc_num | csn_8.clearBit(rank_number+4*dimm_number); - - rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 0, 1, 7); - rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 1, 1, 6); - rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 2, 1, 5); - - //sets up MRS3 ecmd buffer - rc_num = rc_num | mrs3.insert((uint8_t) mpr_page, 0, 2); - rc_num = rc_num | mrs3.insert((uint8_t) mpr_op, 2, 1); - rc_num = rc_num | mrs3.insert((uint8_t) geardown_mode, 3, 1); - rc_num = rc_num | mrs3.insert((uint8_t) 0xff, 4, 1); //enables PDA mode!!!! - rc_num = rc_num | mrs3.insert((uint8_t) temp_readout, 5, 1); - rc_num = rc_num | mrs3.insert((uint8_t) fine_refresh, 6, 3); - rc_num = rc_num | mrs3.insert((uint8_t) wr_latency, 9, 2); - rc_num = rc_num | mrs3.insert((uint8_t) read_format, 11, 2); - rc_num = rc_num | mrs3.insert((uint8_t) 0x00, 13, 2); - rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0); - rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 24, 0, 16); - rc_num = rc_num | address_16.insert(mrs3, 0, 16, 0); - - if (rc_num) - { - FAPI_ERR( "mss_ddr4_setup_pda: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - - - if (( address_mirror_map[i_port_number][dimm_number] & (0x08 >> rank_number) ) && (is_sim == 0)) - { - rc = mss_address_mirror_swizzle(i_target, i_port_number, dimm_number, rank_number, address_16, bank_3); - if(rc) return rc; - } - - - // Send out to the CCS array - rc = mss_ccs_inst_arry_0( i_target, - io_ccs_inst_cnt, - address_16, - bank_3, - activate_1, - rasn_1, - casn_1, - wen_1, - cke_4, - csn_8, - odt_4, - ddr_cal_type_4, - i_port_number); - if(rc) return rc; - rc = mss_ccs_inst_arry_1( i_target, - io_ccs_inst_cnt, - num_idles_16, - num_repeat_16, - data_20, - read_compare_1, - rank_cal_4, - ddr_cal_enable_1, - ccs_end_1); - if(rc) return rc; - io_ccs_inst_cnt ++; - - //if the DIMM is an R or LR DIMM, then run inverted for the B-Side DRAM - if ( (dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_RDIMM) || (dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) ) - { - //reload all MRS values (removes address swizzling) - // Only corresponding CS to rank - rc_num = rc_num | csn_8.setBit(0,8); - rc_num = rc_num | csn_8.clearBit(rank_number+4*dimm_number); - - rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 0, 1, 7); - rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 1, 1, 6); - rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 2, 1, 5); - - //sets up MRS3 ecmd buffer - rc_num = rc_num | address_16.insert(mrs3, 0, 16, 0); - - //FLIPS all necessary bits - // Indicate B-Side DRAMS BG1=1 - rc_num = rc_num | address_16.setBit(15); // Set BG1 = 1 - - rc_num = rc_num | address_16.flipBit(3,7); // Invert A3:A9 - rc_num = rc_num | address_16.flipBit(11); // Invert A11 - rc_num = rc_num | address_16.flipBit(13); // Invert A13 - rc_num = rc_num | address_16.flipBit(14); // Invert A17 - rc_num = rc_num | bank_3.flipBit(0,3); // Invert BA0,BA1,BG0 - - if (rc_num) - { - FAPI_ERR( "mss_ddr4_setup_pda: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - - if (( address_mirror_map[i_port_number][dimm_number] & (0x08 >> rank_number) ) && (is_sim == 0)) - { - rc = mss_address_mirror_swizzle(i_target, i_port_number, dimm_number, rank_number, address_16, bank_3); - if(rc) return rc; - } - - // Send out to the CCS array - rc = mss_ccs_inst_arry_0( i_target, - io_ccs_inst_cnt, - address_16, - bank_3, - activate_1, - rasn_1, - casn_1, - wen_1, - cke_4, - csn_8, - odt_4, - ddr_cal_type_4, - i_port_number); - if(rc) return rc; - rc = mss_ccs_inst_arry_1( i_target, - io_ccs_inst_cnt, - num_idles_16, - num_repeat_16, - data_20, - read_compare_1, - rank_cal_4, - ddr_cal_enable_1, - ccs_end_1); - if(rc) return rc; - io_ccs_inst_cnt ++; - } - } - } - } - } - - //runs a NOP command for 24 cycle - rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 24, 0, 16); - // Raise CKE high with NOPS, waiting min Reset CKE exit time (tXPR) - 400 cycles - rc_num = rc_num | cke_4.setBit(0,4); - rc_num = rc_num | csn_8.setBit(0,8); - rc_num = rc_num | address_16.clearBit(0, 16); - rc_num = rc_num | odt_4.clearBit(0,4); - rc_num = rc_num | num_idles_16.clearBit(0,16); - rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 24, 0, 16); - rc_num = rc_num | rasn_1.setBit(0,1); - rc_num = rc_num | casn_1.setBit(0,1); - rc_num = rc_num | wen_1.setBit(0,1); - - if (rc_num) - { - FAPI_ERR( "mss_ddr4_setup_pda: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - - rc = mss_ccs_inst_arry_0( i_target, - io_ccs_inst_cnt, - address_16, - bank_3, - activate_1, - rasn_1, - casn_1, - wen_1, - cke_4, - csn_8, - odt_4, - ddr_cal_type_4, - i_port_number); - if(rc) return rc; - rc = mss_ccs_inst_arry_1( i_target, - io_ccs_inst_cnt, - num_idles_16, - num_repeat_16, - data_20, - read_compare_1, - rank_cal_4, - ddr_cal_enable_1, - ccs_end_1); - - //Setup end bit for CCS - rc = mss_ccs_set_end_bit (i_target, io_ccs_inst_cnt); - if (rc) return rc; - - //Enable CCS and set RAS/CAS/WE high during idles - FAPI_INF("Enabling CCS\n"); - reg_address = CCS_MODEQ_AB_REG_0x030106A7; - rc = fapiGetScom(i_target, reg_address, data_buffer); - if(rc) return rc; - - rc_num |= data_buffer.setBit(29); //Enable CCS - rc_num |= data_buffer.setBit(52); //RAS high - rc_num |= data_buffer.setBit(53); //CAS high - rc_num |= data_buffer.setBit(54); //WE high - if (rc_num) { - FAPI_ERR( "enable ccs setup: Error setting up buffers"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target, reg_address, data_buffer); - if(rc) return rc; - - - //Execute the CCS array - FAPI_INF("Executing the CCS array\n"); - rc = mss_execute_ccs_inst_array (i_target, NUM_POLL, WAIT_TIMER); - io_ccs_inst_cnt=0; - - //exits PDA - //loops through the DP18's and sets everything to 1's - no PDA - for(i_port_number=0;i_port_number<MAX_NUM_PORTS;i_port_number++) { - for(uint8_t dp18 = 0; dp18<MAX_NUM_DP18S;dp18++) { - reg_address = 0x800000010301143full + 0x0001000000000000ull*i_port_number+ 0x0000040000000000ull*(dp18); - rc = fapiGetScom(i_target, reg_address, data_buffer); - if(rc) return rc; - - rc_num |= data_buffer.setBit(60,4); //Enable CCS - if (rc_num) { - FAPI_ERR( "enable ccs setup: Error setting up buffers"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target, reg_address, data_buffer); - if(rc) return rc; - } - } - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_WC_CONFIG3_P0_0x8000CC050301143F, data_buffer); - if(rc) return rc; - //Setting up CCS mode - rc_num = rc_num | data_buffer.setBit(48); - if (rc_num) - { - FAPI_ERR( "mss_ddr4_setup_pda: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - rc = fapiPutScom(i_target, DPHY01_DDRPHY_WC_CONFIG3_P0_0x8000CC050301143F, data_buffer); - if(rc) return rc; - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_WC_CONFIG3_P1_0x8001CC050301143F, data_buffer); - if(rc) return rc; - //Setting up CCS mode - rc_num = rc_num | data_buffer.setBit(48); - if (rc_num) - { - FAPI_ERR( "mss_ddr4_setup_pda: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - rc = fapiPutScom(i_target, DPHY01_DDRPHY_WC_CONFIG3_P1_0x8001CC050301143F, data_buffer); - if(rc) return rc; - - return rc; -}// end mss_ddr4_setup_pda - - -///////////////////////////////////////////////////////////////////////////////// -/// mss_ddr4_pda -/// configures a vector of PDA accesses to run -///////////////////////////////////////////////////////////////////////////////// -ReturnCode mss_ddr4_pda( - Target& i_target, - vector<PDA_MRS_Storage> pda - ) -{ - ReturnCode rc; - uint8_t dram_loop_end; - uint8_t dram_loop_end_with_spare; - - //gets the rank information - uint8_t num_ranks_array[2][2]; //[port][dimm] - rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target, num_ranks_array); - if(rc) return rc; - - //gets the spare information - uint8_t num_spare[2][2][4]; //[port][dimm] - rc = FAPI_ATTR_GET(ATTR_VPD_DIMM_SPARE, &i_target, num_spare); - if(rc) return rc; - - //gets the WR VREF information - uint8_t wr_vref[2][2][4]; //[port][dimm] - rc = FAPI_ATTR_GET(ATTR_VREF_DQ_TRAIN_VALUE, &i_target, wr_vref); - if(rc) return rc; - - - uint8_t dram_width; - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target, dram_width); - if(rc) return rc; - - //sets the loop_end value, to ensure that the proper number of loops are conducted - if(dram_width == 0x08) { - dram_loop_end = 9; - } - //must be a x4 DRAM - else { - dram_loop_end = 18; - } - - uint8_t array[][2][19] = {{{0x18,0x18,0x1c,0x1c,0x18,0x18,0x1c,0x1c,0x18,0x1c,0x18,0x18,0x1c,0x1c,0x1c,0x18,0x1c,0x18,0x18},{0x18,0x1c,0x20,0x1c,0x20,0x1c,0x20,0x20,0x1c,0x1c,0x20,0x1c,0x18,0x1c,0x1c,0x1c,0x1c,0x18,0x18}},{{0x18,0x1c,0x1c,0x1c,0x20,0x1c,0x20,0x18,0x18,0x18,0x1c,0x1c,0x1c,0x18,0x18,0x1c,0x18,0x18,0x1c},{0x18,0x1c,0x18,0x1c,0x20,0x1c,0x18,0x1c,0x20,0x1c,0x1c,0x1c,0x1c,0x24,0x1c,0x1c,0x1c,0x1c,0x1c}}}; - - - //if pda is empty then, sets up the vector for the MRS storage - if(pda.size() == 0) { - //loops through each port each dimm each rank each dram and sets everything - for(uint8_t port = 0; port < MAX_NUM_PORTS; port++) { - for(uint8_t dimm = 0; dimm < MAX_NUM_DIMMS; dimm++) { - for(uint8_t rank = 0; rank < num_ranks_array[port][dimm]; rank++) { - //DIMM has a spare, add one DRAM to the loop - if(num_spare[port][dimm][rank]) { - dram_loop_end_with_spare = dram_loop_end+1; - } - else { - dram_loop_end_with_spare = dram_loop_end; - } - //loops through all dram - for(uint8_t dram = 0; dram < dram_loop_end_with_spare; dram++) { - //uint8_t ad,uint32_t an,uint8_t d,uint8_t r,uint8_t - if(port == 0) wr_vref[port][dimm][rank] = dram*3; - else wr_vref[port][dimm][rank] = 57-dram*3; - if(wr_vref[port][dimm][rank] > 50) wr_vref[port][dimm][rank] = 50; - pda.push_back(PDA_MRS_Storage(array[port][dimm][dram],ATTR_VREF_DQ_TRAIN_VALUE,dram,dimm,rank,port)); - FAPI_INF("PDA STRING: %d %s",pda.size()-1,pda[pda.size()-1].c_str()); - } - } - } - } - } - rc = mss_ddr4_run_pda(i_target,pda); - return rc; -} - -///////////////////////////////////////////////////////////////////////////////// -/// mss_ddr4_run_pda -/// runs per-DRAM addressability funcitonality on both ports on the passed MBA -///////////////////////////////////////////////////////////////////////////////// -ReturnCode mss_ddr4_run_pda( - Target& i_target, - vector<PDA_MRS_Storage> pda - ) -{ - ReturnCode rc; - //no PDA was entered, just exit - if(pda.size() == 0) return rc; - - uint32_t io_ccs_inst_cnt = 0; - const uint32_t NUM_POLL = 10; - const uint32_t WAIT_TIMER = 1500; - ReturnCode rc_buff; - uint32_t rc_num = 0; - ecmdDataBufferBase data_buffer_64(64); - ecmdDataBufferBase address_16(16); - ecmdDataBufferBase address_16_backup(16); - ecmdDataBufferBase bank_3(3); - ecmdDataBufferBase activate_1(1); - rc_num = rc_num | activate_1.setBit(0); - ecmdDataBufferBase rasn_1(1); - ecmdDataBufferBase casn_1(1); - ecmdDataBufferBase wen_1(1); - ecmdDataBufferBase cke_4(4); - rc_num = rc_num | cke_4.setBit(0,4); - ecmdDataBufferBase csn_8(8); - rc_num = rc_num | csn_8.setBit(0,8); - ecmdDataBufferBase odt_4(4); - - ecmdDataBufferBase ddr_cal_type_4(4); - - ecmdDataBufferBase num_idles_16(16); - ecmdDataBufferBase num_repeat_16(16); - ecmdDataBufferBase data_20(20); - ecmdDataBufferBase read_compare_1(1); - ecmdDataBufferBase rank_cal_4(4); - ecmdDataBufferBase ddr_cal_enable_1(1); - ecmdDataBufferBase ccs_end_1(1); - - //checks each MRS and saves each - rc = mss_ddr4_checksort_pda(i_target,pda); - if(rc) return rc; - - //loads in dram type - uint8_t dimm_type; - rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target, dimm_type); - if(rc) return rc; - - //dram density - uint8_t dram_width; - - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target, dram_width); - if(rc) return rc; - - ecmdDataBufferBase data_buffer(64); - - uint8_t num_ranks_array[2][2]; //[port][dimm] - rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target, num_ranks_array); - if(rc) return rc; - - uint8_t is_sim = 0; - rc = FAPI_ATTR_GET(ATTR_IS_SIMULATION, NULL, is_sim); - if(rc) return rc; - - uint8_t address_mirror_map[2][2]; //address_mirror_map[port][dimm] - rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_ADDRESS_MIRRORING, &i_target, address_mirror_map); - if(rc) return rc; - - rc = mss_ddr4_setup_pda(i_target, io_ccs_inst_cnt ); - if(rc) return rc; - - rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 100, 0, 16); - - - - rc_num = rc_num | cke_4.setBit(0,4); - rc_num = rc_num | csn_8.setBit(0,8); - rc_num = rc_num | address_16.clearBit(0, 16); - rc_num = rc_num | odt_4.clearBit(0,4); - rc_num = rc_num | rasn_1.clearBit(0,1); - rc_num = rc_num | casn_1.clearBit(0,1); - rc_num = rc_num | wen_1.clearBit(0,1); - - //gets the start PDA values - uint8_t prev_dram = pda[0].dram; - uint8_t prev_port = pda[0].port; - uint8_t prev_rank = pda[0].rank; - uint8_t prev_dimm = pda[0].dimm; - uint8_t prev_mrs = pda[0].MRS; - rc = mss_ddr4_load_nominal_mrs_pda(i_target,bank_3,address_16, prev_mrs, prev_port, prev_dimm, prev_rank); - if(rc) return rc; - - vector<PDA_Scom_Storage> scom_storage; - scom_storage.clear(); - rc = mss_ddr4_add_dram_pda(i_target,prev_port,prev_dram,scom_storage); - if(rc) return rc; - - //runs through each PDA command - for(uint32_t i=0;i<pda.size();i++) { - FAPI_INF("Target %s On PDA %d is %s",i_target.toEcmdString(),i,pda[i].c_str()); - //dram, port, rank, dimm, and mrs are the same - if(prev_dram == pda[i].dram && prev_port == pda[i].port && prev_rank == pda[i].rank && prev_dimm == pda[i].dimm && prev_mrs == pda[i].MRS) { - //modifies this attribute - rc = mss_ddr4_modify_mrs_pda(i_target,address_16, pda[i].attribute_name,pda[i].attribute_data); - if(rc) return rc; - } - //another MRS, so set this MRS. do additional checks to later in the code - else { - - //adds values to a backup address_16 before doing the mirroring - address_16_backup.clearBit(0, 16); - rc_num = rc_num | address_16_backup.insert(address_16, 0, 16, 0); - - //loads the previous DRAM - if (( address_mirror_map[prev_port][prev_dimm] & (0x08 >> prev_rank) ) && (is_sim == 0)) - { - rc = mss_address_mirror_swizzle(i_target, prev_port, prev_dimm, prev_rank, address_16, bank_3); - if(rc) return rc; - } - - // Only corresponding CS to rank - rc_num = rc_num | csn_8.setBit(0,8); - rc_num = rc_num | csn_8.clearBit(prev_rank+4*prev_dimm); - - // Send out to the CCS array - rc = mss_ccs_inst_arry_0( i_target, - io_ccs_inst_cnt, - address_16, - bank_3, - activate_1, - rasn_1, - casn_1, - wen_1, - cke_4, - csn_8, - odt_4, - ddr_cal_type_4, - prev_port); - if(rc) return rc; - rc = mss_ccs_inst_arry_1( i_target, - io_ccs_inst_cnt, - num_idles_16, - num_repeat_16, - data_20, - read_compare_1, - rank_cal_4, - ddr_cal_enable_1, - ccs_end_1); - if(rc) return rc; - io_ccs_inst_cnt ++; - - //is an R or LR DIMM -> do a B side MRS write - if ( (dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_RDIMM) || (dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) ) { - //takes values from the backup - address_16.clearBit(0, 16); - rc_num = rc_num | address_16.insert(address_16_backup, 0, 16, 0); - - //FLIPS all necessary bits - // Indicate B-Side DRAMS BG1=1 - rc_num = rc_num | address_16.setBit(15); // Set BG1 = 1 - - rc_num = rc_num | address_16.flipBit(3,7); // Invert A3:A9 - rc_num = rc_num | address_16.flipBit(11); // Invert A11 - rc_num = rc_num | address_16.flipBit(13); // Invert A13 - rc_num = rc_num | address_16.flipBit(14); // Invert A17 - rc_num = rc_num | bank_3.flipBit(0,3); // Invert BA0,BA1,BG0 - - //loads the previous DRAM - if (( address_mirror_map[prev_port][prev_dimm] & (0x08 >> prev_rank) ) && (is_sim == 0)) - { - rc = mss_address_mirror_swizzle(i_target, prev_port, prev_dimm, prev_rank, address_16, bank_3); - if(rc) return rc; - } - - // Only corresponding CS to rank - rc_num = rc_num | csn_8.setBit(0,8); - rc_num = rc_num | csn_8.clearBit(prev_rank+4*prev_dimm); - - // Send out to the CCS array - rc = mss_ccs_inst_arry_0( i_target, - io_ccs_inst_cnt, - address_16, - bank_3, - activate_1, - rasn_1, - casn_1, - wen_1, - cke_4, - csn_8, - odt_4, - ddr_cal_type_4, - prev_port); - if(rc) return rc; - rc = mss_ccs_inst_arry_1( i_target, - io_ccs_inst_cnt, - num_idles_16, - num_repeat_16, - data_20, - read_compare_1, - rank_cal_4, - ddr_cal_enable_1, - ccs_end_1); - if(rc) return rc; - io_ccs_inst_cnt ++; - } - - //the DRAM are different, so kick off CCS, and clear out the MRS DRAMs and set up a new DRAM - if(prev_dram != pda[i].dram) { - //sets a NOP as the last command - rc_num = rc_num | cke_4.setBit(0,4); - rc_num = rc_num | csn_8.setBit(0,8); - rc_num = rc_num | address_16.clearBit(0, 16); - rc_num = rc_num | rasn_1.setBit(0,1); - rc_num = rc_num | casn_1.setBit(0,1); - rc_num = rc_num | wen_1.setBit(0,1); - - // Send out to the CCS array - rc = mss_ccs_inst_arry_0( i_target, - io_ccs_inst_cnt, - address_16, - bank_3, - activate_1, - rasn_1, - casn_1, - wen_1, - cke_4, - csn_8, - odt_4, - ddr_cal_type_4, - prev_port); - if(rc) return rc; - rc = mss_ccs_inst_arry_1( i_target, - io_ccs_inst_cnt, - num_idles_16, - num_repeat_16, - data_20, - read_compare_1, - rank_cal_4, - ddr_cal_enable_1, - ccs_end_1); - if(rc) return rc; - io_ccs_inst_cnt ++; - - //Setup end bit for CCS - rc = mss_ccs_set_end_bit (i_target, io_ccs_inst_cnt-1); - if (rc) return rc; - - //Execute the CCS array - FAPI_INF("Executing the CCS array\n"); - rc = mss_execute_ccs_inst_array (i_target, NUM_POLL, WAIT_TIMER); - if(rc) return rc; - io_ccs_inst_cnt = 0; - - // Sets NOP as the first command - rc = mss_ccs_inst_arry_0( i_target, - io_ccs_inst_cnt, - address_16, - bank_3, - activate_1, - rasn_1, - casn_1, - wen_1, - cke_4, - csn_8, - odt_4, - ddr_cal_type_4, - prev_port); - if(rc) return rc; - rc = mss_ccs_inst_arry_1( i_target, - io_ccs_inst_cnt, - num_idles_16, - num_repeat_16, - data_20, - read_compare_1, - rank_cal_4, - ddr_cal_enable_1, - ccs_end_1); - if(rc) return rc; - io_ccs_inst_cnt ++; - - rc_num = rc_num | cke_4.setBit(0,4); - rc_num = rc_num | csn_8.setBit(0,8); - rc_num = rc_num | address_16.clearBit(0, 16); - rc_num = rc_num | rasn_1.clearBit(0,1); - rc_num = rc_num | casn_1.clearBit(0,1); - rc_num = rc_num | wen_1.clearBit(0,1); - - //loops through and clears out the storage class - for(uint32_t scoms = 0; scoms < scom_storage.size(); scoms++) { - rc = fapiGetScom(i_target, scom_storage[scoms].scom_addr, data_buffer); - if(rc) return rc; - - rc_num |= data_buffer.setBit(scom_storage[scoms].start_bit,scom_storage[scoms].num_bits); //Enable CCS - if (rc_num) { - FAPI_ERR( "enable ccs setup: Error setting up buffers"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target, scom_storage[scoms].scom_addr, data_buffer); - if(rc) return rc; - } - scom_storage.clear(); - //enables the next dram scom - rc = mss_ddr4_add_dram_pda(i_target,pda[i].port,pda[i].dram,scom_storage); - if(rc) return rc; - } - //different port but same DRAM, enable the next scom - else if(prev_port != pda[i].port) { - //enables the next dram scom - rc = mss_ddr4_add_dram_pda(i_target,pda[i].port,pda[i].dram,scom_storage); - if(rc) return rc; - } - - //loads in the nominal MRS for this target - prev_dram = pda[i].dram; - prev_port = pda[i].port; - prev_rank = pda[i].rank; - prev_dimm = pda[i].dimm; - prev_mrs = pda[i].MRS; - - rc = mss_ddr4_load_nominal_mrs_pda(i_target,bank_3,address_16, prev_mrs, prev_port, prev_dimm, prev_rank); - //modifies the MRS - rc = mss_ddr4_modify_mrs_pda(i_target,address_16, pda[i].attribute_name,pda[i].attribute_data); - if(rc) return rc; - } - } - - //runs the last PDA command - //adds values to a backup address_16 before doing the mirroring - address_16_backup.clearBit(0, 16); - rc_num = rc_num | address_16_backup.insert(address_16, 0, 16, 0); - - //loads the previous DRAM - if (( address_mirror_map[prev_port][prev_dimm] & (0x08 >> prev_rank) ) && (is_sim == 0)) - { - rc = mss_address_mirror_swizzle(i_target, prev_port, prev_dimm, prev_rank, address_16, bank_3); - if(rc) return rc; - } - - // Only corresponding CS to rank - rc_num = rc_num | csn_8.setBit(0,8); - rc_num = rc_num | csn_8.clearBit(prev_rank+4*prev_dimm); - - // Send out to the CCS array - rc = mss_ccs_inst_arry_0( i_target, - io_ccs_inst_cnt, - address_16, - bank_3, - activate_1, - rasn_1, - casn_1, - wen_1, - cke_4, - csn_8, - odt_4, - ddr_cal_type_4, - prev_port); - if(rc) return rc; - rc = mss_ccs_inst_arry_1( i_target, - io_ccs_inst_cnt, - num_idles_16, - num_repeat_16, - data_20, - read_compare_1, - rank_cal_4, - ddr_cal_enable_1, - ccs_end_1); - if(rc) return rc; - io_ccs_inst_cnt ++; - - //is an R or LR DIMM -> do a B side MRS write - if ( (dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_RDIMM) || (dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) ) { - //takes values from the backup - address_16.clearBit(0, 16); - rc_num = rc_num | address_16.insert(address_16_backup, 0, 16, 0); - - //FLIPS all necessary bits - // Indicate B-Side DRAMS BG1=1 - rc_num = rc_num | address_16.setBit(15); // Set BG1 = 1 - - rc_num = rc_num | address_16.flipBit(3,7); // Invert A3:A9 - rc_num = rc_num | address_16.flipBit(11); // Invert A11 - rc_num = rc_num | address_16.flipBit(13); // Invert A13 - rc_num = rc_num | address_16.flipBit(14); // Invert A17 - rc_num = rc_num | bank_3.flipBit(0,3); // Invert BA0,BA1,BG0 - - //loads the previous DRAM - if (( address_mirror_map[prev_port][prev_dimm] & (0x08 >> prev_rank) ) && (is_sim == 0)) - { - rc = mss_address_mirror_swizzle(i_target, prev_port, prev_dimm, prev_rank, address_16, bank_3); - if(rc) return rc; - } - - // Only corresponding CS to rank - rc_num = rc_num | csn_8.setBit(0,8); - rc_num = rc_num | csn_8.clearBit(prev_rank+4*prev_dimm); - - // Send out to the CCS array - rc = mss_ccs_inst_arry_0( i_target, - io_ccs_inst_cnt, - address_16, - bank_3, - activate_1, - rasn_1, - casn_1, - wen_1, - cke_4, - csn_8, - odt_4, - ddr_cal_type_4, - prev_port); - if(rc) return rc; - rc = mss_ccs_inst_arry_1( i_target, - io_ccs_inst_cnt, - num_idles_16, - num_repeat_16, - data_20, - read_compare_1, - rank_cal_4, - ddr_cal_enable_1, - ccs_end_1); - if(rc) return rc; - io_ccs_inst_cnt ++; - } - - - //sets a NOP as the last command - rc_num = rc_num | cke_4.setBit(0,4); - rc_num = rc_num | csn_8.setBit(0,8); - rc_num = rc_num | address_16.clearBit(0, 16); - rc_num = rc_num | rasn_1.setBit(0,1); - rc_num = rc_num | casn_1.setBit(0,1); - rc_num = rc_num | wen_1.setBit(0,1); - - // Send out to the CCS array - rc = mss_ccs_inst_arry_0( i_target, - io_ccs_inst_cnt, - address_16, - bank_3, - activate_1, - rasn_1, - casn_1, - wen_1, - cke_4, - csn_8, - odt_4, - ddr_cal_type_4, - prev_port); - if(rc) return rc; - rc = mss_ccs_inst_arry_1( i_target, - io_ccs_inst_cnt, - num_idles_16, - num_repeat_16, - data_20, - read_compare_1, - rank_cal_4, - ddr_cal_enable_1, - ccs_end_1); - if(rc) return rc; - io_ccs_inst_cnt ++; - - //Setup end bit for CCS - rc = mss_ccs_set_end_bit (i_target, io_ccs_inst_cnt-1); - if (rc) return rc; - - //Execute the CCS array - FAPI_INF("Executing the CCS array\n"); - rc = mss_execute_ccs_inst_array (i_target, NUM_POLL, WAIT_TIMER); - if(rc) return rc; - - //loops through and clears out the storage class - for(uint32_t scoms = 0; scoms < scom_storage.size(); scoms++) { - rc = fapiGetScom(i_target, scom_storage[scoms].scom_addr, data_buffer); - if(rc) return rc; - - rc_num |= data_buffer.setBit(scom_storage[scoms].start_bit,scom_storage[scoms].num_bits); //Enable CCS - if (rc_num) { - FAPI_ERR( "enable ccs setup: Error setting up buffers"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target, scom_storage[scoms].scom_addr, data_buffer); - if(rc) return rc; - } - //} - - io_ccs_inst_cnt = 0; - rc = mss_ddr4_disable_pda(i_target,io_ccs_inst_cnt); - return rc; -} - - -////////////////////////////////////////////////////////////////////////////////// -/// mss_ddr4_add_dram_pda -/// adds a specific DRAM on a specific port to receive the current MRS command in PDA mode -////////////////////////////////////////////////////////////////////////////////// -ReturnCode mss_ddr4_add_dram_pda(Target& i_target,uint8_t port,uint8_t dram,vector<PDA_Scom_Storage> & scom_storage) { - ReturnCode rc; - ecmdDataBufferBase data_buffer(64); - //access delay regs function - uint8_t i_rank_pair = 0; - input_type_t i_input_type_e = WR_DQ; - uint8_t i_input_index = 75; - uint8_t i_verbose = 1; - uint8_t phy_lane = 6; - uint8_t phy_block = 6; - uint8_t flag = 0; - uint32_t scom_len = 0; - uint32_t scom_start = 0; - uint32_t rc_num = 0; - - - uint8_t dram_width; - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target, dram_width); - if(rc) return rc; - - // C4 DQ to lane/block (flag = 0) in PHY or lane/block to C4 DQ (flag = 1) - // In this case moving from lane/block to C4 DQ to use access_delay_reg - i_input_index = 4*dram; - rc = mss_c4_phy(i_target,port,i_rank_pair,i_input_type_e,i_input_index,i_verbose,phy_lane,phy_block,flag); - - uint64_t reg_address = 0x800000010301143full + 0x0001000000000000ull*port+ 0x0000040000000000ull*(phy_block); - //gets the lane and number of bits to set to 0's - if(dram_width == 0x04) { - scom_start = 60 + (uint32_t)(phy_lane/4); - scom_len = 1; - } - //x8 DIMM - else { - scom_start = 60 + (uint32_t)((phy_lane/8)*2); - scom_len = 2; - } - FAPI_INF("Enabling %016llx start at %d for %d bits",reg_address,scom_start,scom_len); - - rc = fapiGetScom(i_target, reg_address, data_buffer); - if(rc) return rc; - - rc_num |= data_buffer.clearBit(scom_start,scom_len); //Enable CCS - if (rc_num) { - FAPI_ERR( "enable ccs setup: Error setting up buffers"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target, reg_address, data_buffer); - if(rc) return rc; - - scom_storage.push_back(PDA_Scom_Storage(reg_address,scom_start,scom_len)); - - return rc; -} - -////////////////////////////////////////////////////////////////////////////////// -/// mss_ddr4_disable_pda -/// disables per-DRAM addressability funcitonality on both ports on the passed MBA -////////////////////////////////////////////////////////////////////////////////// -ReturnCode mss_ddr4_disable_pda(Target& i_target,uint32_t& io_ccs_inst_cnt) { - uint32_t i_port_number=0; - uint32_t dimm_number; - uint32_t rank_number; - const uint32_t NUM_POLL = 10; - const uint32_t WAIT_TIMER = 1500; - ReturnCode rc; - ReturnCode rc_buff; - uint32_t rc_num = 0; - uint64_t reg_address; - ecmdDataBufferBase data_buffer(64); - ecmdDataBufferBase data_buffer_64(64); - ecmdDataBufferBase address_16(16); - ecmdDataBufferBase bank_3(3); - ecmdDataBufferBase activate_1(1); - rc_num = rc_num | activate_1.setBit(0); - ecmdDataBufferBase rasn_1(1); - ecmdDataBufferBase casn_1(1); - ecmdDataBufferBase wen_1(1); - ecmdDataBufferBase cke_4(4); - rc_num = rc_num | cke_4.setBit(0,4); - ecmdDataBufferBase csn_8(8); - rc_num = rc_num | csn_8.setBit(0,8); - ecmdDataBufferBase odt_4(4); - ecmdDataBufferBase ddr_cal_type_4(4); - - ecmdDataBufferBase num_idles_16(16); - ecmdDataBufferBase num_repeat_16(16); - ecmdDataBufferBase data_20(20); - ecmdDataBufferBase read_compare_1(1); - ecmdDataBufferBase rank_cal_4(4); - ecmdDataBufferBase ddr_cal_enable_1(1); - ecmdDataBufferBase ccs_end_1(1); - - ecmdDataBufferBase mrs3(16); - uint16_t MRS3 = 0; - - uint8_t num_ranks_array[2][2]; //[port][dimm] - - uint8_t num_ranks; - rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target, num_ranks_array); - if(rc) return rc; - - uint8_t dimm_type; - rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target, dimm_type); - if(rc) return rc; - - uint8_t is_sim = 0; - rc = FAPI_ATTR_GET(ATTR_IS_SIMULATION, NULL, is_sim); - if(rc) return rc; - - uint8_t address_mirror_map[2][2]; //address_mirror_map[port][dimm] - rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_ADDRESS_MIRRORING, &i_target, address_mirror_map); - if(rc) return rc; - - // WORKAROUNDS - rc = fapiGetScom(i_target, CCS_MODEQ_AB_REG_0x030106A7, data_buffer); - if(rc) return rc; - //Setting up CCS mode - rc_num = rc_num | data_buffer.setBit(51); - if (rc_num) { - FAPI_ERR( "disable ccs setup: Error disabling up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - rc = fapiPutScom(i_target, CCS_MODEQ_AB_REG_0x030106A7, data_buffer); - if(rc) return rc; - - //loops through port 0 and port 1 on the given MBA - for(i_port_number=0;i_port_number<MAX_NUM_PORTS;i_port_number++) { - // Raise CKE high with NOPS, waiting min Reset CKE exit time (tXPR) - 400 cycles - rc_num = rc_num | cke_4.setBit(0,4); - rc_num = rc_num | csn_8.setBit(0,8); - rc_num = rc_num | address_16.clearBit(0, 16); - rc_num = rc_num | odt_4.clearBit(0,4); - rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 400, 0, 16); - if (rc_num) { - FAPI_ERR( "disable ccs setup: Error disabling up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - rc = mss_ccs_inst_arry_0( i_target, - io_ccs_inst_cnt, - address_16, - bank_3, - activate_1, - rasn_1, - casn_1, - wen_1, - cke_4, - csn_8, - odt_4, - ddr_cal_type_4, - i_port_number); - if(rc) return rc; - rc = mss_ccs_inst_arry_1( i_target, - io_ccs_inst_cnt, - num_idles_16, - num_repeat_16, - data_20, - read_compare_1, - rank_cal_4, - ddr_cal_enable_1, - ccs_end_1); - if(rc) return rc; - io_ccs_inst_cnt ++; - } - - - //Sets up MRS3 -> the MRS that has PDA - uint8_t mpr_op; // MPR Op - rc = FAPI_ATTR_GET(ATTR_EFF_MPR_MODE, &i_target, mpr_op); - if(rc) return rc; - uint8_t mpr_page; // MPR Page Selection - rc = FAPI_ATTR_GET(ATTR_EFF_MPR_PAGE, &i_target, mpr_page); - if(rc) return rc; - uint8_t geardown_mode; // Gear Down Mode - rc = FAPI_ATTR_GET(ATTR_EFF_GEARDOWN_MODE, &i_target, geardown_mode); - if(rc) return rc; - uint8_t temp_readout; // Temperature sensor readout - rc = FAPI_ATTR_GET(ATTR_EFF_TEMP_READOUT, &i_target, temp_readout); - if(rc) return rc; - uint8_t fine_refresh; // fine refresh mode - rc = FAPI_ATTR_GET(ATTR_EFF_FINE_REFRESH_MODE, &i_target, fine_refresh); - if(rc) return rc; - uint8_t wr_latency; // write latency for CRC and DM - rc = FAPI_ATTR_GET(ATTR_EFF_CRC_WR_LATENCY, &i_target, wr_latency); - if(rc) return rc; - uint8_t read_format; // MPR READ FORMAT - rc = FAPI_ATTR_GET(ATTR_EFF_MPR_RD_FORMAT, &i_target, read_format); - if(rc) return rc; - - //exits PDA - for(i_port_number=0;i_port_number<2;i_port_number++) { - //loops through the DP18's and sets everything to 0's - for(uint8_t dp18 = 0; dp18<MAX_NUM_DP18S;dp18++) { - reg_address = 0x800000010301143full + 0x0001000000000000ull*i_port_number+ 0x0000040000000000ull*(dp18); - rc = fapiGetScom(i_target, reg_address, data_buffer); - if(rc) return rc; - - rc_num |= data_buffer.clearBit(60,4); //Enable CCS - if (rc_num) { - FAPI_ERR( "enable ccs setup: Error setting up buffers"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target, reg_address, data_buffer); - if(rc) return rc; - } - } - - //exits PDA - for(i_port_number=0;i_port_number<2;i_port_number++) { - for ( dimm_number = 0; dimm_number < MAX_NUM_DIMMS; dimm_number++) - { - num_ranks = num_ranks_array[i_port_number][dimm_number]; - - if (num_ranks == 0) - { - FAPI_INF( "PORT%d DIMM%d not configured. Num_ranks: %d ", i_port_number, dimm_number, num_ranks); - } - else - { - // Rank 0-3 - for ( rank_number = 0; rank_number < num_ranks; rank_number++) - { - // Only corresponding CS to rank - rc_num = rc_num | csn_8.setBit(0,8); - rc_num = rc_num | csn_8.clearBit(rank_number+4*dimm_number); - - rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 0, 1, 7); - rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 1, 1, 6); - rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 2, 1, 5); - - //enables PDA - rc_num = rc_num | mrs3.insert((uint8_t) mpr_page, 0, 2); - rc_num = rc_num | mrs3.insert((uint8_t) mpr_op, 2, 1); - rc_num = rc_num | mrs3.insert((uint8_t) geardown_mode, 3, 1); - rc_num = rc_num | mrs3.insert((uint8_t) 0x00, 4, 1); - rc_num = rc_num | mrs3.insert((uint8_t) temp_readout, 5, 1); - rc_num = rc_num | mrs3.insert((uint8_t) fine_refresh, 6, 3); - rc_num = rc_num | mrs3.insert((uint8_t) wr_latency, 9, 2); - rc_num = rc_num | mrs3.insert((uint8_t) read_format, 11, 2); - rc_num = rc_num | mrs3.insert((uint8_t) 0x00, 13, 2); - rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0); - rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 100, 0, 16); - - //copies over values - rc_num = rc_num | address_16.insert(mrs3, 0, 16, 0); - if (rc_num) - { - FAPI_ERR( "mss_mrs_load: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - - if (( address_mirror_map[i_port_number][dimm_number] & (0x08 >> rank_number) ) && (is_sim == 0)) - { - rc = mss_address_mirror_swizzle(i_target, i_port_number, dimm_number, rank_number, address_16, bank_3); - if(rc) return rc; - } - - // Send out to the CCS array - rc = mss_ccs_inst_arry_0( i_target, - io_ccs_inst_cnt, - address_16, - bank_3, - activate_1, - rasn_1, - casn_1, - wen_1, - cke_4, - csn_8, - odt_4, - ddr_cal_type_4, - i_port_number); - if(rc) return rc; - rc = mss_ccs_inst_arry_1( i_target, - io_ccs_inst_cnt, - num_idles_16, - num_repeat_16, - data_20, - read_compare_1, - rank_cal_4, - ddr_cal_enable_1, - ccs_end_1); - if(rc) return rc; - io_ccs_inst_cnt ++; - - //if the DIMM is an R or LR DIMM, then run inverted for the B-Side DRAM - if ( (dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_RDIMM) || (dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) ) - { - - //reload all MRS values (removes address swizzling) - // Only corresponding CS to rank - rc_num = rc_num | csn_8.setBit(0,8); - rc_num = rc_num | csn_8.clearBit(rank_number+4*dimm_number); - - rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 0, 1, 7); - rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 1, 1, 6); - rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 2, 1, 5); - - //enables PDA - rc_num = rc_num | mrs3.insert((uint8_t) mpr_page, 0, 2); - rc_num = rc_num | mrs3.insert((uint8_t) mpr_op, 2, 1); - rc_num = rc_num | mrs3.insert((uint8_t) geardown_mode, 3, 1); - rc_num = rc_num | mrs3.insert((uint8_t) 0x00, 4, 1); - rc_num = rc_num | mrs3.insert((uint8_t) temp_readout, 5, 1); - rc_num = rc_num | mrs3.insert((uint8_t) fine_refresh, 6, 3); - rc_num = rc_num | mrs3.insert((uint8_t) wr_latency, 9, 2); - rc_num = rc_num | mrs3.insert((uint8_t) read_format, 11, 2); - rc_num = rc_num | mrs3.insert((uint8_t) 0x00, 13, 2); - rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0); - rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 100, 0, 16); - //copies over values - rc_num = rc_num | address_16.insert(mrs3, 0, 16, 0); - - //FLIPS all necessary bits - // Indicate B-Side DRAMS BG1=1 - rc_num = rc_num | address_16.setBit(15); // Set BG1 = 1 - - rc_num = rc_num | address_16.flipBit(3,7); // Invert A3:A9 - rc_num = rc_num | address_16.flipBit(11); // Invert A11 - rc_num = rc_num | address_16.flipBit(13); // Invert A13 - rc_num = rc_num | address_16.flipBit(14); // Invert A17 - rc_num = rc_num | bank_3.flipBit(0,3); // Invert BA0,BA1,BG0 - - if (rc_num) - { - FAPI_ERR( "mss_ddr4_setup_pda: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - - if (( address_mirror_map[i_port_number][dimm_number] & (0x08 >> rank_number) ) && (is_sim == 0)) - { - rc = mss_address_mirror_swizzle(i_target, i_port_number, dimm_number, rank_number, address_16, bank_3); - if(rc) return rc; - } - - // Send out to the CCS array - rc = mss_ccs_inst_arry_0( i_target, - io_ccs_inst_cnt, - address_16, - bank_3, - activate_1, - rasn_1, - casn_1, - wen_1, - cke_4, - csn_8, - odt_4, - ddr_cal_type_4, - i_port_number); - if(rc) return rc; - rc = mss_ccs_inst_arry_1( i_target, - io_ccs_inst_cnt, - num_idles_16, - num_repeat_16, - data_20, - read_compare_1, - rank_cal_4, - ddr_cal_enable_1, - ccs_end_1); - if(rc) return rc; - io_ccs_inst_cnt ++; - } - } - } - } - } - - //Setup end bit for CCS - rc = mss_ccs_set_end_bit (i_target, io_ccs_inst_cnt-1); - if (rc) return rc; - - //Execute the CCS array - FAPI_INF("Executing the CCS array\n"); - rc = mss_execute_ccs_inst_array (i_target, NUM_POLL, WAIT_TIMER); - - //Disable CCS - FAPI_INF("Disabling CCS\n"); - reg_address = CCS_MODEQ_AB_REG_0x030106A7; - rc = fapiGetScom(i_target, reg_address, data_buffer); - if(rc) return rc; - - - rc_num |= data_buffer.clearBit(29); - if (rc_num) { - FAPI_ERR( "disable ccs setup: Error disabling up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - rc = fapiPutScom(i_target, reg_address, data_buffer); - if(rc) return rc; - - //disables the DDR4 PDA mode writes - rc = fapiGetScom(i_target, DPHY01_DDRPHY_WC_CONFIG3_P0_0x8000CC050301143F, data_buffer); - if(rc) return rc; - //Setting up CCS mode - rc_num = rc_num | data_buffer.clearBit(48); - if (rc_num) - { - FAPI_ERR( "mss_ddr4_setup_pda: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - rc = fapiPutScom(i_target, DPHY01_DDRPHY_WC_CONFIG3_P0_0x8000CC050301143F, data_buffer); - if(rc) return rc; - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_WC_CONFIG3_P1_0x8001CC050301143F, data_buffer); - if(rc) return rc; - //Setting up CCS mode - rc_num = rc_num | data_buffer.clearBit(48); - if (rc_num) - { - FAPI_ERR( "mss_ddr4_setup_pda: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - rc = fapiPutScom(i_target, DPHY01_DDRPHY_WC_CONFIG3_P1_0x8001CC050301143F, data_buffer); - if(rc) return rc; - - FAPI_INF("Successfully exited out of PDA mode."); - io_ccs_inst_cnt = 0; - return rc; -} - -////////////////////////////////////////////////////////////////////////////////// -/// mss_ddr4_modify_mrs_pda -/// disables per-DRAM addressability funcitonality on both ports on the passed MBA -////////////////////////////////////////////////////////////////////////////////// -ReturnCode mss_ddr4_modify_mrs_pda(Target& i_target,ecmdDataBufferBase& address_16,uint32_t attribute_name,uint8_t attribute_data) { - ReturnCode rc; - uint32_t rc_num = 0; - uint8_t dram_bl = attribute_data; - uint8_t read_bt = attribute_data; //Read Burst Type - uint8_t dram_cl = attribute_data; - uint8_t test_mode = attribute_data; //TEST MODE - uint8_t dll_reset = attribute_data; //DLL Reset - uint8_t dram_wr = attribute_data; //DRAM write recovery - uint8_t dram_rtp = attribute_data; //DRAM RTP - read to precharge - uint8_t dram_wr_rtp = attribute_data; - uint8_t dll_precharge = attribute_data; //DLL Control For Precharge if (dll_precharge == ENUM_ATTR_EFF_DRAM_DLL_PPD_SLOWEXIT) - uint8_t dll_enable = attribute_data; //DLL Enable - uint8_t out_drv_imp_cntl = attribute_data; - uint8_t dram_rtt_nom = attribute_data; - uint8_t dram_al = attribute_data; - uint8_t wr_lvl = attribute_data; //write leveling enable - uint8_t tdqs_enable = attribute_data; //TDQS Enable - uint8_t q_off = attribute_name; //Qoff - Output buffer Enable - uint8_t lpasr = attribute_data; // Low Power Auto Self-Refresh -- new not yet supported - uint8_t cwl = attribute_data; // CAS Write Latency - uint8_t dram_rtt_wr = attribute_data; - uint8_t mpr_op = attribute_data; // MPR Op - uint8_t mpr_page = attribute_data; // MPR Page Selection - uint8_t geardown_mode = attribute_data; // Gear Down Mode - uint8_t temp_readout = attribute_data; // Temperature sensor readout - uint8_t fine_refresh = attribute_data; // fine refresh mode - uint8_t wr_latency = attribute_data; // write latency for CRC and DM - uint8_t write_crc = attribute_data; // CAS Write Latency - uint8_t read_format = attribute_data; // MPR READ FORMAT - uint8_t max_pd_mode = attribute_data; // Max Power down mode - uint8_t temp_ref_range = attribute_data; // Temp ref range - uint8_t temp_ref_mode = attribute_data; // Temp controlled ref mode - uint8_t vref_mon = attribute_data; // Internal Vref Monitor - uint8_t cs_cmd_latency = attribute_data; // CS to CMD/ADDR Latency - uint8_t ref_abort = attribute_data; // Self Refresh Abort - uint8_t rd_pre_train_mode = attribute_data; // Read Pre amble Training Mode - uint8_t rd_preamble = attribute_data; // Read Pre amble - uint8_t wr_preamble = attribute_data; // Write Pre amble - uint8_t ca_parity_latency = attribute_data; //C/A Parity Latency Mode - uint8_t crc_error_clear = attribute_data; //CRC Error Clear - uint8_t ca_parity_error_status = attribute_data; //C/A Parity Error Status - uint8_t odt_input_buffer = attribute_data; //ODT Input Buffer during power down - uint8_t rtt_park = attribute_data; //RTT_Park value - uint8_t ca_parity = attribute_data; //CA Parity Persistance Error - uint8_t data_mask = attribute_data; //Data Mask - uint8_t write_dbi = attribute_data; //Write DBI - uint8_t read_dbi = attribute_data; //Read DBI - uint8_t vrefdq_train_value = attribute_data; //vrefdq_train value - uint8_t vrefdq_train_range = attribute_data; //vrefdq_train range - uint8_t vrefdq_train_enable = attribute_data; //vrefdq_train enable - uint8_t tccd_l = attribute_data; //tccd_l - uint8_t dram_access; - - switch (attribute_name) { - case ATTR_EFF_DRAM_BL: - if (dram_bl == ENUM_ATTR_EFF_DRAM_BL_BL8) - { - dram_bl = 0x00; - } - else if (dram_bl == ENUM_ATTR_EFF_DRAM_BL_OTF) - { - dram_bl = 0x80; - } - else if (dram_bl == ENUM_ATTR_EFF_DRAM_BL_BC4) - { - dram_bl = 0x40; - } - rc_num = rc_num | address_16.insert((uint8_t) dram_bl, 0, 2, 0); - break; - case ATTR_EFF_DRAM_RBT: - if (read_bt == ENUM_ATTR_EFF_DRAM_RBT_SEQUENTIAL) - { - read_bt = 0x00; - } - else if (read_bt == ENUM_ATTR_EFF_DRAM_RBT_INTERLEAVE) - { - read_bt = 0xFF; - } - rc_num = rc_num | address_16.insert((uint8_t) read_bt, 3, 1, 0); - break; - case ATTR_EFF_DRAM_CL: - if ((dram_cl > 8)&&(dram_cl < 17)) - { - dram_cl = dram_cl - 9; - } - else if ((dram_cl > 17)&&(dram_cl < 25)) - { - dram_cl = (dram_cl >> 1) - 1; - } - dram_cl = mss_reverse_8bits(dram_cl); - rc_num = rc_num | address_16.insert((uint8_t) dram_cl, 2, 1, 0); - rc_num = rc_num | address_16.insert((uint8_t) dram_cl, 4, 3, 1); - break; - case ATTR_EFF_DRAM_TM: - if (test_mode == ENUM_ATTR_EFF_DRAM_TM_NORMAL) - { - test_mode = 0x00; - } - else if (test_mode == ENUM_ATTR_EFF_DRAM_TM_TEST) - { - test_mode = 0xFF; - } - rc_num = rc_num | address_16.insert((uint8_t) test_mode, 7, 1); - break; - case ATTR_EFF_DRAM_DLL_RESET: - dll_reset = 0x00; - FAPI_ERR( "ERROR: ATTR_EFF_DRAM_DLL_RESET accessed during PDA functionality, overwritten"); - rc_num = rc_num | address_16.insert((uint8_t) dll_reset, 8, 1); - break; - case ATTR_EFF_DRAM_WR: - if ( (dram_wr == 10) )//&& (dram_rtp == 5) ) - { - dram_wr_rtp = 0x00; - } - else if ( (dram_wr == 12) )//&& (dram_rtp == 6) ) - { - dram_wr_rtp = 0x80; - } - else if ( (dram_wr == 13) )//&& (dram_rtp == 7) ) - { - dram_wr_rtp = 0x40; - } - else if ( (dram_wr == 14) )//&& (dram_rtp == 8) ) - { - dram_wr_rtp = 0xC0; - } - else if ( (dram_wr == 18) )//&& (dram_rtp == 9) ) - { - dram_wr_rtp = 0x20; - } - else if ( (dram_wr == 20) )//&& (dram_rtp == 10) ) - { - dram_wr_rtp = 0xA0; - } - else if ( (dram_wr == 24) )//&& (dram_rtp == 12) ) - { - dram_wr_rtp = 0x60; - } - rc_num = rc_num | address_16.insert((uint8_t) dram_wr_rtp, 9, 3); - break; - case ATTR_EFF_DRAM_TRTP: - if ( (dram_rtp == 5) ) - { - dram_wr_rtp = 0x00; - } - else if ( (dram_rtp == 6) ) - { - dram_wr_rtp = 0x80; - } - else if ( (dram_rtp == 7) ) - { - dram_wr_rtp = 0x40; - } - else if ( (dram_rtp == 8) ) - { - dram_wr_rtp = 0xC0; - } - else if ( (dram_rtp == 9) ) - { - dram_wr_rtp = 0x20; - } - else if ( (dram_rtp == 10) ) - { - dram_wr_rtp = 0xA0; - } - else if ( (dram_rtp == 12) ) - { - dram_wr_rtp = 0x60; - } - rc_num = rc_num | address_16.insert((uint8_t) dram_wr_rtp, 9, 3); - break; - case ATTR_EFF_DRAM_DLL_PPD: - if (dll_precharge == ENUM_ATTR_EFF_DRAM_DLL_PPD_SLOWEXIT) - { - dll_precharge = 0x00; - } - else if (dll_precharge == ENUM_ATTR_EFF_DRAM_DLL_PPD_FASTEXIT) - { - dll_precharge = 0xFF; - } - FAPI_INF("ERROR: ATTR_EFF_DRAM_DLL_PPD is an unused MRS value!!! Skipping..."); - break; - case ATTR_EFF_DRAM_DLL_ENABLE: - if (dll_enable == ENUM_ATTR_EFF_DRAM_DLL_ENABLE_DISABLE) - { - dll_enable = 0x00; - } - else if (dll_enable == ENUM_ATTR_EFF_DRAM_DLL_ENABLE_ENABLE) - { - dll_enable = 0xFF; - } - rc_num = rc_num | address_16.insert((uint8_t) dll_enable, 0, 1, 0); - break; - case ATTR_VPD_DRAM_RON: - if (out_drv_imp_cntl == ENUM_ATTR_VPD_DRAM_RON_OHM34) - { - out_drv_imp_cntl = 0x00; - } - // Not currently supported - else if (out_drv_imp_cntl == ENUM_ATTR_VPD_DRAM_RON_OHM48) //not supported - { - out_drv_imp_cntl = 0x80; - } - rc_num = rc_num | address_16.insert((uint8_t) out_drv_imp_cntl, 1, 2, 0); - break; - case ATTR_VPD_DRAM_RTT_NOM: - if (dram_rtt_nom == ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE) - { - dram_rtt_nom = 0x00; - } - else if (dram_rtt_nom == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM240) //not supported - { - dram_rtt_nom = 0x20; - } - else if (dram_rtt_nom == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM48) //not supported - { - dram_rtt_nom = 0xA0; - } - else if (dram_rtt_nom == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40) - { - dram_rtt_nom = 0xC0; - } - else if (dram_rtt_nom == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM60) - { - dram_rtt_nom = 0x80; - } - else if (dram_rtt_nom == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM120) - { - dram_rtt_nom = 0x40; - } - else if (dram_rtt_nom == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM80) // not supported - { - dram_rtt_nom = 0x60; - } - else if (dram_rtt_nom == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM34) // not supported - { - dram_rtt_nom = 0xE0; - } - - rc_num = rc_num | address_16.insert((uint8_t) dram_rtt_nom, 8, 3, 0); - break; - case ATTR_EFF_DRAM_AL: - if (dram_al == ENUM_ATTR_EFF_DRAM_AL_DISABLE) - { - dram_al = 0x00; - } - else if (dram_al == ENUM_ATTR_EFF_DRAM_AL_CL_MINUS_1) - { - dram_al = 0x80; - } - else if (dram_al == ENUM_ATTR_EFF_DRAM_AL_CL_MINUS_2) - { - dram_al = 0x40; - } - rc_num = rc_num | address_16.insert((uint8_t) dram_al, 3, 2, 0); - break; - case ATTR_EFF_DRAM_WR_LVL_ENABLE: - if (wr_lvl == ENUM_ATTR_EFF_DRAM_WR_LVL_ENABLE_DISABLE) - { - wr_lvl = 0x00; - } - else if (wr_lvl == ENUM_ATTR_EFF_DRAM_WR_LVL_ENABLE_ENABLE) - { - wr_lvl = 0xFF; - } - rc_num = rc_num | address_16.insert((uint8_t) wr_lvl, 7, 1, 0); - break; - case ATTR_EFF_DRAM_TDQS: - if (tdqs_enable == ENUM_ATTR_EFF_DRAM_TDQS_DISABLE) - { - tdqs_enable = 0x00; - } - else if (tdqs_enable == ENUM_ATTR_EFF_DRAM_TDQS_ENABLE) - { - tdqs_enable = 0xFF; - } - rc_num = rc_num | address_16.insert((uint8_t) tdqs_enable, 11, 1, 0); - break; - case ATTR_EFF_DRAM_OUTPUT_BUFFER: - if (q_off == ENUM_ATTR_EFF_DRAM_OUTPUT_BUFFER_DISABLE) - { - q_off = 0xFF; - } - else if (q_off == ENUM_ATTR_EFF_DRAM_OUTPUT_BUFFER_ENABLE) - { - q_off = 0x00; - } - rc_num = rc_num | address_16.insert((uint8_t) q_off, 12, 1, 0); - break; - case ATTR_EFF_DRAM_LPASR: - if (lpasr == ENUM_ATTR_EFF_DRAM_LPASR_MANUAL_NORMAL) - { - lpasr = 0x00; - } - else if (lpasr == ENUM_ATTR_EFF_DRAM_LPASR_MANUAL_REDUCED) - { - lpasr = 0x80; - } - else if (lpasr == ENUM_ATTR_EFF_DRAM_LPASR_MANUAL_EXTENDED) - { - lpasr = 0x40; - } - else if (lpasr == ENUM_ATTR_EFF_DRAM_LPASR_ASR) - { - lpasr = 0xFF; - } - rc_num = rc_num | address_16.insert((uint8_t) lpasr, 6, 2); - break; - case ATTR_EFF_DRAM_CWL: - if ((cwl > 8)&&(cwl < 13)) - { - cwl = cwl - 9; - } - else if ((cwl > 13)&&(cwl < 19)) - { - cwl = (cwl >> 1) - 3; - } - else - { - //no correcct value for CWL was found - FAPI_INF("ERROR: Improper CWL value found. Setting CWL to 9 and continuing..."); - cwl = 0; - } - cwl = mss_reverse_8bits(cwl); - rc_num = rc_num | address_16.insert((uint8_t) cwl, 3, 3); - break; - case ATTR_VPD_DRAM_RTT_WR: - if (dram_rtt_wr == ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE) - { - dram_rtt_wr = 0x00; - } - else if (dram_rtt_wr == ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120) - { - dram_rtt_wr = 0x80; - } - else if (dram_rtt_wr == 240)//ENUM_ATTR_EFF_DRAM_RTT_WR_OHM240) - { - dram_rtt_wr = 0x40; - } - else if (dram_rtt_wr == 0xFF)//ENUM_ATTR_EFF_DRAM_RTT_WR_HIGHZ) - { - dram_rtt_wr = 0xFF; - } - rc_num = rc_num | address_16.insert((uint8_t) dram_rtt_wr, 9, 2); - break; - case ATTR_EFF_WRITE_CRC: - if ( write_crc == ENUM_ATTR_EFF_WRITE_CRC_ENABLE) - { - write_crc = 0xFF; - } - else if (write_crc == ENUM_ATTR_EFF_WRITE_CRC_DISABLE) - { - write_crc = 0x00; - } - rc_num = rc_num | address_16.insert((uint8_t) write_crc, 12, 1); - break; - case ATTR_EFF_MPR_MODE: - if (mpr_op == ENUM_ATTR_EFF_MPR_MODE_ENABLE) - { - mpr_op = 0xFF; - } - else if (mpr_op == ENUM_ATTR_EFF_MPR_MODE_DISABLE) - { - mpr_op = 0x00; - } - rc_num = rc_num | address_16.insert((uint8_t) mpr_op, 2, 1); - break; - case ATTR_EFF_MPR_PAGE: - mpr_page = mss_reverse_8bits(mpr_page); - rc_num = rc_num | address_16.insert((uint8_t) mpr_page, 0, 2); - break; - case ATTR_EFF_GEARDOWN_MODE: - if ( geardown_mode == ENUM_ATTR_EFF_GEARDOWN_MODE_HALF) - { - geardown_mode = 0x00; - } - else if ( geardown_mode == ENUM_ATTR_EFF_GEARDOWN_MODE_QUARTER) - { - geardown_mode = 0xFF; - } - - if (temp_readout == ENUM_ATTR_EFF_TEMP_READOUT_ENABLE) - { - temp_readout = 0xFF; - } - else if (temp_readout == ENUM_ATTR_EFF_TEMP_READOUT_DISABLE) - { - temp_readout = 0x00; - } - rc_num = rc_num | address_16.insert((uint8_t) geardown_mode, 3, 1); - break; - case ATTR_EFF_TEMP_READOUT: - if (temp_readout == ENUM_ATTR_EFF_TEMP_READOUT_ENABLE) - { - temp_readout = 0xFF; - } - else if (temp_readout == ENUM_ATTR_EFF_TEMP_READOUT_DISABLE) - { - temp_readout = 0x00; - } - rc_num = rc_num | address_16.insert((uint8_t) temp_readout, 5, 1); - break; - case ATTR_EFF_FINE_REFRESH_MODE: - if (fine_refresh == ENUM_ATTR_EFF_FINE_REFRESH_MODE_NORMAL) - { - fine_refresh = 0x00; - } - else if (fine_refresh == ENUM_ATTR_EFF_FINE_REFRESH_MODE_FIXED_2X) - { - fine_refresh = 0x80; - } - else if (fine_refresh == ENUM_ATTR_EFF_FINE_REFRESH_MODE_FIXED_4X) - { - fine_refresh = 0x40; - } - else if (fine_refresh == ENUM_ATTR_EFF_FINE_REFRESH_MODE_FLY_2X) - { - fine_refresh = 0xA0; - } - else if (fine_refresh == ENUM_ATTR_EFF_FINE_REFRESH_MODE_FLY_4X) - { - fine_refresh = 0x60; - } - rc_num = rc_num | address_16.insert((uint8_t) fine_refresh, 6, 3); - break; - case ATTR_EFF_CRC_WR_LATENCY: - if (wr_latency == ENUM_ATTR_EFF_CRC_WR_LATENCY_4NCK) - { - wr_latency = 0x00; - } - else if (wr_latency == ENUM_ATTR_EFF_CRC_WR_LATENCY_5NCK) - { - wr_latency = 0x80; - } - else if (wr_latency == ENUM_ATTR_EFF_CRC_WR_LATENCY_6NCK) - { - wr_latency = 0xC0; - } - rc_num = rc_num | address_16.insert((uint8_t) wr_latency, 9, 2); - break; - case ATTR_EFF_MPR_RD_FORMAT: - if (read_format == ENUM_ATTR_EFF_MPR_RD_FORMAT_SERIAL) - { - read_format = 0x00; - } - else if (read_format == ENUM_ATTR_EFF_MPR_RD_FORMAT_PARALLEL) - { - read_format = 0x80; - } - else if (read_format == ENUM_ATTR_EFF_MPR_RD_FORMAT_STAGGERED) - { - read_format = 0x40; - } - else if (read_format == ENUM_ATTR_EFF_MPR_RD_FORMAT_RESERVED_TEMP) - { - read_format = 0xC0; - } - rc_num = rc_num | address_16.insert((uint8_t) read_format, 11, 2); - break; - case ATTR_EFF_PER_DRAM_ACCESS: - FAPI_INF("ERROR: ATTR_EFF_PER_DRAM_ACCESS selected. Forcing PDA to be on for this function"); - dram_access = 0xFF; - rc_num = rc_num | address_16.insert((uint8_t) dram_access, 4, 1); - break; - case ATTR_EFF_MAX_POWERDOWN_MODE: - if ( max_pd_mode == ENUM_ATTR_EFF_MAX_POWERDOWN_MODE_ENABLE) - { - max_pd_mode = 0xF0; - } - else if ( max_pd_mode == ENUM_ATTR_EFF_MAX_POWERDOWN_MODE_DISABLE) - { - max_pd_mode = 0x00; - } - rc_num = rc_num | address_16.insert((uint8_t) max_pd_mode, 1, 1); - break; - case ATTR_EFF_TEMP_REF_RANGE: - if (temp_ref_range == ENUM_ATTR_EFF_TEMP_REF_RANGE_NORMAL) - { - temp_ref_range = 0x00; - } - else if ( temp_ref_range== ENUM_ATTR_EFF_TEMP_REF_RANGE_EXTEND) - { - temp_ref_range = 0xFF; - } - rc_num = rc_num | address_16.insert((uint8_t) temp_ref_range, 2, 1); - break; - case ATTR_EFF_TEMP_REF_MODE: - if (temp_ref_mode == ENUM_ATTR_EFF_TEMP_REF_MODE_ENABLE) - { - temp_ref_mode = 0x80; - } - else if (temp_ref_mode == ENUM_ATTR_EFF_TEMP_REF_MODE_DISABLE) - { - temp_ref_mode = 0x00; - } - rc_num = rc_num | address_16.insert((uint8_t) temp_ref_mode, 3, 1); - break; - case ATTR_EFF_INT_VREF_MON: - if ( vref_mon == ENUM_ATTR_EFF_INT_VREF_MON_ENABLE) - { - vref_mon = 0xFF; - } - else if ( vref_mon == ENUM_ATTR_EFF_INT_VREF_MON_DISABLE) - { - vref_mon = 0x00; - } - rc_num = rc_num | address_16.insert((uint8_t) vref_mon, 4, 1); - break; - case ATTR_EFF_CS_CMD_LATENCY: - if ( cs_cmd_latency == 3) - { - cs_cmd_latency = 0x80; - } - else if (cs_cmd_latency == 4) - { - cs_cmd_latency = 0x40; - } - else if (cs_cmd_latency == 5) - { - cs_cmd_latency = 0xC0; - } - else if (cs_cmd_latency == 6) - { - cs_cmd_latency = 0x20; - } - else if (cs_cmd_latency == 8) - { - cs_cmd_latency = 0xA0; - } - rc_num = rc_num | address_16.insert((uint8_t) cs_cmd_latency, 6, 3); - break; - case ATTR_EFF_SELF_REF_ABORT: - if (ref_abort == ENUM_ATTR_EFF_SELF_REF_ABORT_ENABLE) - { - ref_abort = 0xFF; - } - else if (ref_abort == ENUM_ATTR_EFF_SELF_REF_ABORT_DISABLE) - { - ref_abort = 0x00; - } - rc_num = rc_num | address_16.insert((uint8_t) ref_abort, 9, 1); - break; - case ATTR_EFF_RD_PREAMBLE_TRAIN: - if (rd_pre_train_mode == ENUM_ATTR_EFF_RD_PREAMBLE_TRAIN_ENABLE) - { - rd_pre_train_mode = 0xFF; - } - else if (rd_pre_train_mode == ENUM_ATTR_EFF_RD_PREAMBLE_TRAIN_DISABLE) - { - rd_pre_train_mode = 0x00; - } - rc_num = rc_num | address_16.insert((uint8_t) rd_pre_train_mode, 10, 1); - break; - case ATTR_EFF_RD_PREAMBLE: - if (rd_preamble == ENUM_ATTR_EFF_RD_PREAMBLE_1NCLK) - { - rd_preamble = 0x00; - } - else if (rd_preamble == ENUM_ATTR_EFF_RD_PREAMBLE_2NCLK) - { - rd_preamble = 0xFF; - } - rc_num = rc_num | address_16.insert((uint8_t) rd_preamble, 11, 1); - break; - case ATTR_EFF_WR_PREAMBLE: - if (wr_preamble == ENUM_ATTR_EFF_WR_PREAMBLE_1NCLK) - { - wr_preamble = 0x00; - } - else if (wr_preamble == ENUM_ATTR_EFF_WR_PREAMBLE_2NCLK) - { - wr_preamble = 0xFF; - } - rc_num = rc_num | address_16.insert((uint8_t) wr_preamble, 12, 1); - break; - case ATTR_EFF_CA_PARITY_LATENCY: - if (ca_parity_latency == 4) - { - ca_parity_latency = 0x80; - } - else if (ca_parity_latency == 5) - { - ca_parity_latency = 0x40; - } - else if (ca_parity_latency == 6) - { - ca_parity_latency = 0xC0; - } - else if (ca_parity_latency == 8) - { - ca_parity_latency = 0x20; - } - else if (ca_parity_latency == ENUM_ATTR_EFF_CA_PARITY_LATENCY_DISABLE) - { - ca_parity_latency = 0x00; - } - rc_num = rc_num | address_16.insert((uint8_t) ca_parity_latency, 0, 2); - break; - case ATTR_EFF_CRC_ERROR_CLEAR: - if (crc_error_clear == ENUM_ATTR_EFF_CRC_ERROR_CLEAR_ERROR) - { - crc_error_clear = 0xFF; - } - else if (crc_error_clear == ENUM_ATTR_EFF_CRC_ERROR_CLEAR_CLEAR) - { - crc_error_clear = 0x00; - } - rc_num = rc_num | address_16.insert((uint8_t) crc_error_clear, 3, 1); - break; - case ATTR_EFF_CA_PARITY_ERROR_STATUS: - if (ca_parity_error_status == ENUM_ATTR_EFF_CA_PARITY_ERROR_STATUS_ERROR) - { - ca_parity_error_status = 0xFF; - } - else if (ca_parity_error_status == ENUM_ATTR_EFF_CA_PARITY_ERROR_STATUS_CLEAR) - { - ca_parity_error_status = 0x00; - } - rc_num = rc_num | address_16.insert((uint8_t) ca_parity_error_status, 4, 1); - break; - case ATTR_EFF_ODT_INPUT_BUFF: - if (odt_input_buffer == ENUM_ATTR_EFF_ODT_INPUT_BUFF_ACTIVATED) - { - odt_input_buffer = 0x00; - } - else if (odt_input_buffer == ENUM_ATTR_EFF_ODT_INPUT_BUFF_DEACTIVATED) - { - odt_input_buffer = 0xFF; - } - rc_num = rc_num | address_16.insert((uint8_t) odt_input_buffer, 5, 1); - break; - case ATTR_EFF_RTT_PARK: - if (rtt_park == ENUM_ATTR_EFF_RTT_PARK_DISABLE) - { - rtt_park = 0x00; - } - else if (rtt_park == ENUM_ATTR_EFF_RTT_PARK_60OHM) - { - rtt_park = 0x80; - } - else if (rtt_park == ENUM_ATTR_EFF_RTT_PARK_40OHM) - { - rtt_park = 0xC0; - } - else if (rtt_park == ENUM_ATTR_EFF_RTT_PARK_120OHM) - { - rtt_park = 0x40; - } - else if (rtt_park == ENUM_ATTR_EFF_RTT_PARK_240OHM) - { - rtt_park = 0x20; - } - else if (rtt_park == ENUM_ATTR_EFF_RTT_PARK_48OHM) - { - rtt_park = 0xA0; - } - else if (rtt_park == ENUM_ATTR_EFF_RTT_PARK_80OHM) - { - rtt_park = 0x60; - } - else if (rtt_park == ENUM_ATTR_EFF_RTT_PARK_34OHM) - { - rtt_park = 0xE0; - } - rc_num = rc_num | address_16.insert((uint8_t) rtt_park, 6, 3); - break; - case ATTR_EFF_CA_PARITY: - if (ca_parity == ENUM_ATTR_EFF_CA_PARITY_ENABLE) - { - ca_parity = 0xFF; - } - else if (ca_parity == ENUM_ATTR_EFF_CA_PARITY_DISABLE) - { - ca_parity = 0x00; - } - rc_num = rc_num | address_16.insert((uint8_t) ca_parity, 9, 1); - break; - case ATTR_EFF_DATA_MASK: - if (data_mask == ENUM_ATTR_EFF_DATA_MASK_DISABLE) - { - data_mask = 0x00; - } - else if (data_mask == ENUM_ATTR_EFF_DATA_MASK_ENABLE) - { - data_mask = 0xFF; - } - rc_num = rc_num | address_16.insert((uint8_t) data_mask, 10, 1); - break; - case ATTR_EFF_WRITE_DBI: - if (write_dbi == ENUM_ATTR_EFF_WRITE_DBI_DISABLE) - { - write_dbi = 0x00; - } - else if (write_dbi == ENUM_ATTR_EFF_WRITE_DBI_ENABLE) - { - write_dbi = 0xFF; - } - rc_num = rc_num | address_16.insert((uint8_t) write_dbi, 11, 1); - break; - case ATTR_EFF_READ_DBI: - if (read_dbi == ENUM_ATTR_EFF_READ_DBI_DISABLE) - { - read_dbi = 0x00; - } - else if (read_dbi == ENUM_ATTR_EFF_READ_DBI_ENABLE) - { - read_dbi = 0xFF; - } - rc_num = rc_num | address_16.insert((uint8_t) read_dbi, 12, 1); - break; - case ATTR_VREF_DQ_TRAIN_VALUE: - vrefdq_train_value = mss_reverse_8bits(vrefdq_train_value); - rc_num = rc_num | address_16.insert((uint8_t) vrefdq_train_value, 0, 6); - break; - case ATTR_VREF_DQ_TRAIN_RANGE: - if (vrefdq_train_range == ENUM_ATTR_VREF_DQ_TRAIN_RANGE_RANGE1) - { - vrefdq_train_range = 0x00; - } - else if (vrefdq_train_range == ENUM_ATTR_VREF_DQ_TRAIN_RANGE_RANGE2) - { - vrefdq_train_range = 0xFF; - } - rc_num = rc_num | address_16.insert((uint8_t) vrefdq_train_range, 6, 1); - break; - case ATTR_VREF_DQ_TRAIN_ENABLE: - if (vrefdq_train_enable == ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE) - { - vrefdq_train_enable = 0xFF; - } - else if (vrefdq_train_enable == ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_DISABLE) - { - vrefdq_train_enable = 0x00; - } - rc_num = rc_num | address_16.insert((uint8_t) vrefdq_train_enable, 7, 1); - break; - case ATTR_TCCD_L: - if (tccd_l == 4) - { - tccd_l = 0x00; - } - else if (tccd_l == 5) - { - tccd_l = 0x80; - } - else if (tccd_l == 6) - { - tccd_l = 0x40; - } - else if (tccd_l == 7) - { - tccd_l = 0xC0; - } - else if (tccd_l == 8) - { - tccd_l = 0x20; - } - rc_num = rc_num | address_16.insert((uint8_t) tccd_l, 10, 3); - break; - //MRS attribute not found, error out - default: - const uint32_t NONMRS_ATTR_NAME = attribute_name; - const fapi::Target & MBA_TARGET = i_target; - FAPI_SET_HWP_ERROR(rc, RC_MSS_PDA_NONMRS_ATTR_NAME); - FAPI_ERR("ERROR!! Found attribute name not associated with an MRS! Exiting..."); - } - if (rc_num) - { - FAPI_ERR( "mss_ddr4_modify_mrs_pda: Error setting up buffers"); - rc.setEcmdError(rc_num); - return rc; - } - return rc; -} - -////////////////////////////////////////////////////////////////////////////////// -/// mss_ddr4_load_nominal_mrs_pda -/// disables per-DRAM addressability funcitonality on both ports on the passed MBA -////////////////////////////////////////////////////////////////////////////////// -ReturnCode mss_ddr4_load_nominal_mrs_pda(Target& i_target,ecmdDataBufferBase& bank_3,ecmdDataBufferBase& address_16,uint8_t MRS,uint8_t i_port_number, uint8_t dimm_number, uint8_t rank_number) { - ReturnCode rc; - ReturnCode rc_buff; - uint32_t rc_num = 0; - - rc_num = rc_num | address_16.clearBit(0,16); - rc_num = rc_num | bank_3.clearBit(0,3); - if (rc_num) - { - FAPI_ERR( "mss_mrs_load: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - - //Lines commented out in the following section are waiting for xml attribute adds - //MRS0 - if(MRS == MRS0_BA) { - uint8_t dram_bl; - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_BL, &i_target, dram_bl); - if(rc) return rc; - uint8_t read_bt; //Read Burst Type - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_RBT, &i_target, read_bt); - if(rc) return rc; - uint8_t dram_cl; - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_CL, &i_target, dram_cl); - if(rc) return rc; - uint8_t test_mode; //TEST MODE - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_TM, &i_target, test_mode); - if(rc) return rc; - uint8_t dll_reset; //DLL Reset - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_DLL_RESET, &i_target, dll_reset); - if(rc) return rc; - uint8_t dram_wr; //DRAM write recovery - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WR, &i_target, dram_wr); - if(rc) return rc; - uint8_t dram_rtp; //DRAM RTP - read to precharge - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_TRTP, &i_target, dram_rtp); - if(rc) return rc; - uint8_t dll_precharge; //DLL Control For Precharge - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_DLL_PPD, &i_target, dll_precharge); - if(rc) return rc; - - if (dram_bl == ENUM_ATTR_EFF_DRAM_BL_BL8) - { - dram_bl = 0x00; - } - else if (dram_bl == ENUM_ATTR_EFF_DRAM_BL_OTF) - { - dram_bl = 0x80; - } - else if (dram_bl == ENUM_ATTR_EFF_DRAM_BL_BC4) - { - dram_bl = 0x40; - } - - uint8_t dram_wr_rtp = 0x00; - if ( (dram_wr == 10) )//&& (dram_rtp == 5) ) - { - dram_wr_rtp = 0x00; - } - else if ( (dram_wr == 12) )//&& (dram_rtp == 6) ) - { - dram_wr_rtp = 0x80; - } - else if ( (dram_wr == 13) )//&& (dram_rtp == 7) ) - { - dram_wr_rtp = 0x40; - } - else if ( (dram_wr == 14) )//&& (dram_rtp == 8) ) - { - dram_wr_rtp = 0xC0; - } - else if ( (dram_wr == 18) )//&& (dram_rtp == 9) ) - { - dram_wr_rtp = 0x20; - } - else if ( (dram_wr == 20) )//&& (dram_rtp == 10) ) - { - dram_wr_rtp = 0xA0; - } - else if ( (dram_wr == 24) )//&& (dram_rtp == 12) ) - { - dram_wr_rtp = 0x60; - } - - if (read_bt == ENUM_ATTR_EFF_DRAM_RBT_SEQUENTIAL) - { - read_bt = 0x00; - } - else if (read_bt == ENUM_ATTR_EFF_DRAM_RBT_INTERLEAVE) - { - read_bt = 0xFF; - } - - if ((dram_cl > 8)&&(dram_cl < 17)) - { - dram_cl = dram_cl - 9; - } - else if ((dram_cl > 17)&&(dram_cl < 25)) - { - dram_cl = (dram_cl >> 1) - 1; - } - dram_cl = mss_reverse_8bits(dram_cl); - - if (test_mode == ENUM_ATTR_EFF_DRAM_TM_NORMAL) - { - test_mode = 0x00; - } - else if (test_mode == ENUM_ATTR_EFF_DRAM_TM_TEST) - { - test_mode = 0xFF; - } - - FAPI_INF("Overwriting DLL reset with values to not reset the DRAM."); - dll_reset = 0x00; - - if (dll_precharge == ENUM_ATTR_EFF_DRAM_DLL_PPD_SLOWEXIT) - { - dll_precharge = 0x00; - } - else if (dll_precharge == ENUM_ATTR_EFF_DRAM_DLL_PPD_FASTEXIT) - { - dll_precharge = 0xFF; - } - //For DDR4: - //Address 14 = Address 17, Address 15 = BG1 - rc_num = rc_num | address_16.insert((uint8_t) dram_bl, 0, 2, 0); - rc_num = rc_num | address_16.insert((uint8_t) dram_cl, 2, 1, 0); - rc_num = rc_num | address_16.insert((uint8_t) read_bt, 3, 1, 0); - rc_num = rc_num | address_16.insert((uint8_t) dram_cl, 4, 3, 1); - rc_num = rc_num | address_16.insert((uint8_t) test_mode, 7, 1); - rc_num = rc_num | address_16.insert((uint8_t) dll_reset, 8, 1); - rc_num = rc_num | address_16.insert((uint8_t) dram_wr_rtp, 9, 3); - rc_num = rc_num | address_16.insert((uint8_t) 0x00, 12, 4); - - rc_num = rc_num | bank_3.insert((uint8_t) MRS0_BA, 0, 1, 7); - rc_num = rc_num | bank_3.insert((uint8_t) MRS0_BA, 1, 1, 6); - rc_num = rc_num | bank_3.insert((uint8_t) MRS0_BA, 2, 1, 5); - if (rc_num) - { - FAPI_ERR( "mss_mrs_load: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - } - - //MRS1 - else if(MRS == MRS1_BA) { - uint8_t dll_enable; //DLL Enable - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_DLL_ENABLE, &i_target, dll_enable); - if(rc) return rc; - uint8_t out_drv_imp_cntl[2][2]; - rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_RON, &i_target, out_drv_imp_cntl); - if(rc) return rc; - uint8_t dram_rtt_nom[2][2][4]; - rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_RTT_NOM, &i_target, dram_rtt_nom); - if(rc) return rc; - uint8_t dram_al; - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_AL, &i_target, dram_al); - if(rc) return rc; - uint8_t wr_lvl; //write leveling enable - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WR_LVL_ENABLE, &i_target, wr_lvl); - if(rc) return rc; - uint8_t tdqs_enable; //TDQS Enable - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_TDQS, &i_target, tdqs_enable); - if(rc) return rc; - uint8_t q_off; //Qoff - Output buffer Enable - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_OUTPUT_BUFFER, &i_target, q_off); - if(rc) return rc; - - if (dll_enable == ENUM_ATTR_EFF_DRAM_DLL_ENABLE_DISABLE) - { - dll_enable = 0x00; - } - else if (dll_enable == ENUM_ATTR_EFF_DRAM_DLL_ENABLE_ENABLE) - { - dll_enable = 0xFF; - } - - if (dram_al == ENUM_ATTR_EFF_DRAM_AL_DISABLE) - { - dram_al = 0x00; - } - else if (dram_al == ENUM_ATTR_EFF_DRAM_AL_CL_MINUS_1) - { - dram_al = 0x80; - } - else if (dram_al == ENUM_ATTR_EFF_DRAM_AL_CL_MINUS_2) - { - dram_al = 0x40; - } - - if (wr_lvl == ENUM_ATTR_EFF_DRAM_WR_LVL_ENABLE_DISABLE) - { - wr_lvl = 0x00; - } - else if (wr_lvl == ENUM_ATTR_EFF_DRAM_WR_LVL_ENABLE_ENABLE) - { - wr_lvl = 0xFF; - } - - if (tdqs_enable == ENUM_ATTR_EFF_DRAM_TDQS_DISABLE) - { - tdqs_enable = 0x00; - } - else if (tdqs_enable == ENUM_ATTR_EFF_DRAM_TDQS_ENABLE) - { - tdqs_enable = 0xFF; - } - - if (q_off == ENUM_ATTR_EFF_DRAM_OUTPUT_BUFFER_DISABLE) - { - q_off = 0xFF; - } - else if (q_off == ENUM_ATTR_EFF_DRAM_OUTPUT_BUFFER_ENABLE) - { - q_off = 0x00; - } - if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE) - { - dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0x00; - } - else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM240) //not supported - { - dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0x20; - } - else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM48) //not supported - { - dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0xA0; - } - else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40) - { - dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0xC0; - } - else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM60) - { - dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0x80; - } - else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM120) - { - dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0x40; - } - else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM80) // not supported - { - dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0x60; - } - else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM34) // not supported - { - dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0xE0; - } - - if (out_drv_imp_cntl[i_port_number][dimm_number] == ENUM_ATTR_VPD_DRAM_RON_OHM34) - { - out_drv_imp_cntl[i_port_number][dimm_number] = 0x00; - } - // Not currently supported - else if (out_drv_imp_cntl[i_port_number][dimm_number] == ENUM_ATTR_VPD_DRAM_RON_OHM48) //not supported - { - out_drv_imp_cntl[i_port_number][dimm_number] = 0x80; - } - - //For DDR4: - //Address 14 = Address 17, Address 15 = BG1 - rc_num = rc_num | address_16.insert((uint8_t) dll_enable, 0, 1, 0); - rc_num = rc_num | address_16.insert((uint8_t) out_drv_imp_cntl[i_port_number][dimm_number], 1, 2, 0); - rc_num = rc_num | address_16.insert((uint8_t) dram_al, 3, 2, 0); - rc_num = rc_num | address_16.insert((uint8_t) 0x00, 5, 2); - rc_num = rc_num | address_16.insert((uint8_t) wr_lvl, 7, 1, 0); - rc_num = rc_num | address_16.insert((uint8_t) dram_rtt_nom[i_port_number][dimm_number][rank_number], 8, 3, 0); - rc_num = rc_num | address_16.insert((uint8_t) tdqs_enable, 11, 1, 0); - rc_num = rc_num | address_16.insert((uint8_t) q_off, 12, 1, 0); - rc_num = rc_num | address_16.insert((uint8_t) 0x00, 13, 3); - - rc_num = rc_num | bank_3.insert((uint8_t) MRS1_BA, 0, 1, 7); - rc_num = rc_num | bank_3.insert((uint8_t) MRS1_BA, 1, 1, 6); - rc_num = rc_num | bank_3.insert((uint8_t) MRS1_BA, 2, 1, 5); - if (rc_num) - { - FAPI_ERR( "mss_mrs_load: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - } - //MRS2 - else if(MRS == MRS2_BA) { - uint8_t lpasr; // Low Power Auto Self-Refresh -- new not yet supported - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_LPASR, &i_target, lpasr); - if(rc) return rc; - uint8_t cwl; // CAS Write Latency - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_CWL, &i_target, cwl); - if(rc) return rc; - uint8_t dram_rtt_wr[2][2][4]; - rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_RTT_WR, &i_target, dram_rtt_wr); - if(rc) return rc; - uint8_t write_crc; // CAS Write Latency - rc = FAPI_ATTR_GET(ATTR_EFF_WRITE_CRC, &i_target, write_crc); - if(rc) return rc; - - if (lpasr == ENUM_ATTR_EFF_DRAM_LPASR_MANUAL_NORMAL) - { - lpasr = 0x00; - } - else if (lpasr == ENUM_ATTR_EFF_DRAM_LPASR_MANUAL_REDUCED) - { - lpasr = 0x80; - } - else if (lpasr == ENUM_ATTR_EFF_DRAM_LPASR_MANUAL_EXTENDED) - { - lpasr = 0x40; - } - else if (lpasr == ENUM_ATTR_EFF_DRAM_LPASR_ASR) - { - lpasr = 0xFF; - } - - if ((cwl > 8)&&(cwl < 13)) - { - cwl = cwl - 9; - } - else if ((cwl > 13)&&(cwl < 19)) - { - cwl = (cwl >> 1) - 3; - } - else - { - //no correcct value for CWL was found - FAPI_INF("ERROR: Improper CWL value found. Setting CWL to 9 and continuing..."); - cwl = 0; - } - cwl = mss_reverse_8bits(cwl); - - if ( write_crc == ENUM_ATTR_EFF_WRITE_CRC_ENABLE) - { - write_crc = 0xFF; - } - else if (write_crc == ENUM_ATTR_EFF_WRITE_CRC_DISABLE) - { - write_crc = 0x00; - } - if (dram_rtt_wr[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE) - { - dram_rtt_wr[i_port_number][dimm_number][rank_number] = 0x00; - } - else if (dram_rtt_wr[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120) - { - dram_rtt_wr[i_port_number][dimm_number][rank_number] = 0x80; - } - else if (dram_rtt_wr[i_port_number][dimm_number][rank_number] == 240)//ENUM_ATTR_EFF_DRAM_RTT_WR_OHM240) - { - dram_rtt_wr[i_port_number][dimm_number][rank_number] = 0x40; - } - else if (dram_rtt_wr[i_port_number][dimm_number][rank_number] == 0xFF)//ENUM_ATTR_EFF_DRAM_RTT_WR_HIGHZ) - { - dram_rtt_wr[i_port_number][dimm_number][rank_number] = 0xFF; - } - - rc_num = rc_num | address_16.insert((uint8_t) 0x00, 0, 3); - rc_num = rc_num | address_16.insert((uint8_t) cwl, 3, 3); - rc_num = rc_num | address_16.insert((uint8_t) lpasr, 6, 2); - rc_num = rc_num | address_16.insert((uint8_t) 0x00, 8, 1); - rc_num = rc_num | address_16.insert((uint8_t) dram_rtt_wr[i_port_number][dimm_number][rank_number], 9, 2); - rc_num = rc_num | address_16.insert((uint8_t) 0x00, 11, 1); - rc_num = rc_num | address_16.insert((uint8_t) write_crc, 12, 1); - rc_num = rc_num | address_16.insert((uint8_t) 0x00, 13, 2); - - rc_num = rc_num | bank_3.insert((uint8_t) MRS2_BA, 0, 1, 7); - rc_num = rc_num | bank_3.insert((uint8_t) MRS2_BA, 1, 1, 6); - rc_num = rc_num | bank_3.insert((uint8_t) MRS2_BA, 2, 1, 5); - if (rc_num) - { - FAPI_ERR( "mss_mrs_load: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - } - //MRS3 - else if(MRS == MRS3_BA) { - uint8_t mpr_op; // MPR Op - rc = FAPI_ATTR_GET(ATTR_EFF_MPR_MODE, &i_target, mpr_op); - if(rc) return rc; - uint8_t mpr_page; // MPR Page Selection - NEW - rc = FAPI_ATTR_GET(ATTR_EFF_MPR_PAGE, &i_target, mpr_page); - if(rc) return rc; - uint8_t geardown_mode; // Gear Down Mode - NEW - rc = FAPI_ATTR_GET(ATTR_EFF_GEARDOWN_MODE, &i_target, geardown_mode); - if(rc) return rc; - uint8_t temp_readout; // Temperature sensor readout - NEW - rc = FAPI_ATTR_GET(ATTR_EFF_TEMP_READOUT, &i_target, temp_readout); - if(rc) return rc; - uint8_t fine_refresh; // fine refresh mode - NEW - rc = FAPI_ATTR_GET(ATTR_EFF_FINE_REFRESH_MODE, &i_target, fine_refresh); - if(rc) return rc; - uint8_t wr_latency; // write latency for CRC and DM - NEW - rc = FAPI_ATTR_GET(ATTR_EFF_CRC_WR_LATENCY, &i_target, wr_latency); - if(rc) return rc; - uint8_t read_format; // MPR READ FORMAT - NEW - rc = FAPI_ATTR_GET(ATTR_EFF_MPR_RD_FORMAT, &i_target, read_format); - if(rc) return rc; - - if (mpr_op == ENUM_ATTR_EFF_MPR_MODE_ENABLE) - { - mpr_op = 0xFF; - } - else if (mpr_op == ENUM_ATTR_EFF_MPR_MODE_DISABLE) - { - mpr_op = 0x00; - } - - mpr_page = mss_reverse_8bits(mpr_page); - - if ( geardown_mode == ENUM_ATTR_EFF_GEARDOWN_MODE_HALF) - { - geardown_mode = 0x00; - } - else if ( geardown_mode == ENUM_ATTR_EFF_GEARDOWN_MODE_QUARTER) - { - geardown_mode = 0xFF; - } - - if (temp_readout == ENUM_ATTR_EFF_TEMP_READOUT_ENABLE) - { - temp_readout = 0xFF; - } - else if (temp_readout == ENUM_ATTR_EFF_TEMP_READOUT_DISABLE) - { - temp_readout = 0x00; - } - - if (fine_refresh == ENUM_ATTR_EFF_FINE_REFRESH_MODE_NORMAL) - { - fine_refresh = 0x00; - } - else if (fine_refresh == ENUM_ATTR_EFF_FINE_REFRESH_MODE_FIXED_2X) - { - fine_refresh = 0x80; - } - else if (fine_refresh == ENUM_ATTR_EFF_FINE_REFRESH_MODE_FIXED_4X) - { - fine_refresh = 0x40; - } - else if (fine_refresh == ENUM_ATTR_EFF_FINE_REFRESH_MODE_FLY_2X) - { - fine_refresh = 0xA0; - } - else if (fine_refresh == ENUM_ATTR_EFF_FINE_REFRESH_MODE_FLY_4X) - { - fine_refresh = 0x60; - } - - if (wr_latency == ENUM_ATTR_EFF_CRC_WR_LATENCY_4NCK) - { - wr_latency = 0x00; - } - else if (wr_latency == ENUM_ATTR_EFF_CRC_WR_LATENCY_5NCK) - { - wr_latency = 0x80; - } - else if (wr_latency == ENUM_ATTR_EFF_CRC_WR_LATENCY_6NCK) - { - wr_latency = 0xC0; - } - - if (read_format == ENUM_ATTR_EFF_MPR_RD_FORMAT_SERIAL) - { - read_format = 0x00; - } - else if (read_format == ENUM_ATTR_EFF_MPR_RD_FORMAT_PARALLEL) - { - read_format = 0x80; - } - else if (read_format == ENUM_ATTR_EFF_MPR_RD_FORMAT_STAGGERED) - { - read_format = 0x40; - } - else if (read_format == ENUM_ATTR_EFF_MPR_RD_FORMAT_RESERVED_TEMP) - { - read_format = 0xC0; - } - - rc_num = rc_num | address_16.insert((uint8_t) mpr_page, 0, 2); - rc_num = rc_num | address_16.insert((uint8_t) mpr_op, 2, 1); - rc_num = rc_num | address_16.insert((uint8_t) geardown_mode, 3, 1); - rc_num = rc_num | address_16.insert((uint8_t) 0xFF, 4, 1); //has PDA mode enabled!!!! just for this code! - rc_num = rc_num | address_16.insert((uint8_t) temp_readout, 5, 1); - rc_num = rc_num | address_16.insert((uint8_t) fine_refresh, 6, 3); - rc_num = rc_num | address_16.insert((uint8_t) wr_latency, 9, 2); - rc_num = rc_num | address_16.insert((uint8_t) read_format, 11, 2); - rc_num = rc_num | address_16.insert((uint8_t) 0x00, 13, 2); - - rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 0, 1, 7); - rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 1, 1, 6); - rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 2, 1, 5); - if (rc_num) - { - FAPI_ERR( "mss_mrs_load: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - } - //MRS4 - else if(MRS == MRS4_BA) { - uint8_t max_pd_mode; // Max Power down mode - NEW - rc = FAPI_ATTR_GET(ATTR_EFF_MAX_POWERDOWN_MODE, &i_target, max_pd_mode); - if(rc) return rc; - uint8_t temp_ref_range; // Temp ref range - NEW - rc = FAPI_ATTR_GET(ATTR_EFF_TEMP_REF_RANGE, &i_target, temp_ref_range); - if(rc) return rc; - uint8_t temp_ref_mode; // Temp controlled ref mode - NEW - rc = FAPI_ATTR_GET(ATTR_EFF_TEMP_REF_MODE, &i_target, temp_ref_mode); - if(rc) return rc; - uint8_t vref_mon; // Internal Vref Monitor - NEW - rc = FAPI_ATTR_GET(ATTR_EFF_INT_VREF_MON, &i_target, vref_mon); - if(rc) return rc; - uint8_t cs_cmd_latency; // CS to CMD/ADDR Latency - NEW - rc = FAPI_ATTR_GET(ATTR_EFF_CS_CMD_LATENCY, &i_target, cs_cmd_latency); - if(rc) return rc; - uint8_t ref_abort; // Self Refresh Abort - NEW - rc = FAPI_ATTR_GET(ATTR_EFF_SELF_REF_ABORT, &i_target, ref_abort); - if(rc) return rc; - uint8_t rd_pre_train_mode; // Read Pre amble Training Mode - NEW - rc = FAPI_ATTR_GET(ATTR_EFF_RD_PREAMBLE_TRAIN, &i_target, rd_pre_train_mode); - if(rc) return rc; - uint8_t rd_preamble; // Read Pre amble - NEW - rc = FAPI_ATTR_GET(ATTR_EFF_RD_PREAMBLE, &i_target, rd_preamble); - if(rc) return rc; - uint8_t wr_preamble; // Write Pre amble - NEW - rc = FAPI_ATTR_GET(ATTR_EFF_WR_PREAMBLE, &i_target, wr_preamble); - if(rc) return rc; - - if ( max_pd_mode == ENUM_ATTR_EFF_MAX_POWERDOWN_MODE_ENABLE) - { - max_pd_mode = 0xF0; - } - else if ( max_pd_mode == ENUM_ATTR_EFF_MAX_POWERDOWN_MODE_DISABLE) - { - max_pd_mode = 0x00; - } - - if (temp_ref_range == ENUM_ATTR_EFF_TEMP_REF_RANGE_NORMAL) - { - temp_ref_range = 0x00; - } - else if ( temp_ref_range== ENUM_ATTR_EFF_TEMP_REF_RANGE_EXTEND) - { - temp_ref_range = 0xFF; - } - - if (temp_ref_mode == ENUM_ATTR_EFF_TEMP_REF_MODE_ENABLE) - { - temp_ref_mode = 0x80; - } - else if (temp_ref_mode == ENUM_ATTR_EFF_TEMP_REF_MODE_DISABLE) - { - temp_ref_mode = 0x00; - } - - if ( vref_mon == ENUM_ATTR_EFF_INT_VREF_MON_ENABLE) - { - vref_mon = 0xFF; - } - else if ( vref_mon == ENUM_ATTR_EFF_INT_VREF_MON_DISABLE) - { - vref_mon = 0x00; - } - - - if ( cs_cmd_latency == 3) - { - cs_cmd_latency = 0x80; - } - else if (cs_cmd_latency == 4) - { - cs_cmd_latency = 0x40; - } - else if (cs_cmd_latency == 5) - { - cs_cmd_latency = 0xC0; - } - else if (cs_cmd_latency == 6) - { - cs_cmd_latency = 0x20; - } - else if (cs_cmd_latency == 8) - { - cs_cmd_latency = 0xA0; - } - - if (ref_abort == ENUM_ATTR_EFF_SELF_REF_ABORT_ENABLE) - { - ref_abort = 0xFF; - } - else if (ref_abort == ENUM_ATTR_EFF_SELF_REF_ABORT_DISABLE) - { - ref_abort = 0x00; - } - - if (rd_pre_train_mode == ENUM_ATTR_EFF_RD_PREAMBLE_TRAIN_ENABLE) - { - rd_pre_train_mode = 0xFF; - } - else if (rd_pre_train_mode == ENUM_ATTR_EFF_RD_PREAMBLE_TRAIN_DISABLE) - { - rd_pre_train_mode = 0x00; - } - - if (rd_preamble == ENUM_ATTR_EFF_RD_PREAMBLE_1NCLK) - { - rd_preamble = 0x00; - } - else if (rd_preamble == ENUM_ATTR_EFF_RD_PREAMBLE_2NCLK) - { - rd_preamble = 0xFF; - } - - if (wr_preamble == ENUM_ATTR_EFF_WR_PREAMBLE_1NCLK) - { - wr_preamble = 0x00; - } - else if (wr_preamble == ENUM_ATTR_EFF_WR_PREAMBLE_2NCLK) - { - wr_preamble = 0xFF; - } - rc_num = rc_num | address_16.insert((uint8_t) 0x00, 0, 1); - rc_num = rc_num | address_16.insert((uint8_t) max_pd_mode, 1, 1); - rc_num = rc_num | address_16.insert((uint8_t) temp_ref_range, 2, 1); - rc_num = rc_num | address_16.insert((uint8_t) temp_ref_mode, 3, 1); - rc_num = rc_num | address_16.insert((uint8_t) vref_mon, 4, 1); - rc_num = rc_num | address_16.insert((uint8_t) 0x00, 5, 1); - rc_num = rc_num | address_16.insert((uint8_t) cs_cmd_latency, 6, 3); - rc_num = rc_num | address_16.insert((uint8_t) ref_abort, 9, 1); - rc_num = rc_num | address_16.insert((uint8_t) rd_pre_train_mode, 10, 1); - rc_num = rc_num | address_16.insert((uint8_t) rd_preamble, 11, 1); - rc_num = rc_num | address_16.insert((uint8_t) wr_preamble, 12, 1); - - rc_num = rc_num | bank_3.insert((uint8_t) MRS4_BA, 0, 1, 7); - rc_num = rc_num | bank_3.insert((uint8_t) MRS4_BA, 1, 1, 6); - rc_num = rc_num | bank_3.insert((uint8_t) MRS4_BA, 2, 1, 5); - if (rc_num) - { - FAPI_ERR( "mss_mrs_load: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - } - //MRS5 - else if(MRS == MRS5_BA) { - uint8_t ca_parity_latency; //C/A Parity Latency Mode - NEW - rc = FAPI_ATTR_GET(ATTR_EFF_CA_PARITY_LATENCY , &i_target, ca_parity_latency); - if(rc) return rc; - uint8_t crc_error_clear; //CRC Error Clear - NEW - rc = FAPI_ATTR_GET(ATTR_EFF_CRC_ERROR_CLEAR , &i_target, crc_error_clear); - if(rc) return rc; - uint8_t ca_parity_error_status; //C/A Parity Error Status - NEW - rc = FAPI_ATTR_GET(ATTR_EFF_CA_PARITY_ERROR_STATUS , &i_target, ca_parity_error_status); - if(rc) return rc; - uint8_t odt_input_buffer; //ODT Input Buffer during power down - NEW - rc = FAPI_ATTR_GET(ATTR_EFF_ODT_INPUT_BUFF , &i_target, odt_input_buffer); - if(rc) return rc; - uint8_t rtt_park[2][2][4]; //RTT_Park value - NEW - rc = FAPI_ATTR_GET(ATTR_EFF_RTT_PARK , &i_target, rtt_park); - if(rc) return rc; - uint8_t ca_parity; //CA Parity Persistance Error - NEW - rc = FAPI_ATTR_GET(ATTR_EFF_CA_PARITY , &i_target, ca_parity); - if(rc) return rc; - uint8_t data_mask; //Data Mask - NEW - rc = FAPI_ATTR_GET(ATTR_EFF_DATA_MASK , &i_target, data_mask); - if(rc) return rc; - uint8_t write_dbi; //Write DBI - NEW - rc = FAPI_ATTR_GET(ATTR_EFF_WRITE_DBI , &i_target, write_dbi); - if(rc) return rc; - uint8_t read_dbi; //Read DBI - NEW - rc = FAPI_ATTR_GET(ATTR_EFF_READ_DBI , &i_target, read_dbi); - if(rc) return rc; - - - if (ca_parity_latency == 4) - { - ca_parity_latency = 0x80; - } - else if (ca_parity_latency == 5) - { - ca_parity_latency = 0x40; - } - else if (ca_parity_latency == 6) - { - ca_parity_latency = 0xC0; - } - else if (ca_parity_latency == 8) - { - ca_parity_latency = 0x20; - } - else if (ca_parity_latency == ENUM_ATTR_EFF_CA_PARITY_LATENCY_DISABLE) - { - ca_parity_latency = 0x00; - } - - if (crc_error_clear == ENUM_ATTR_EFF_CRC_ERROR_CLEAR_ERROR) - { - crc_error_clear = 0xFF; - } - else if (crc_error_clear == ENUM_ATTR_EFF_CRC_ERROR_CLEAR_CLEAR) - { - crc_error_clear = 0x00; - } - - if (ca_parity_error_status == ENUM_ATTR_EFF_CA_PARITY_ERROR_STATUS_ERROR) - { - ca_parity_error_status = 0xFF; - } - else if (ca_parity_error_status == ENUM_ATTR_EFF_CA_PARITY_ERROR_STATUS_CLEAR) - { - ca_parity_error_status = 0x00; - } - - if (odt_input_buffer == ENUM_ATTR_EFF_ODT_INPUT_BUFF_ACTIVATED) - { - odt_input_buffer = 0x00; - } - else if (odt_input_buffer == ENUM_ATTR_EFF_ODT_INPUT_BUFF_DEACTIVATED) - { - odt_input_buffer = 0xFF; - } - - - if (ca_parity == ENUM_ATTR_EFF_CA_PARITY_ENABLE) - { - ca_parity = 0xFF; - } - else if (ca_parity == ENUM_ATTR_EFF_CA_PARITY_DISABLE) - { - ca_parity = 0x00; - } - - if (data_mask == ENUM_ATTR_EFF_DATA_MASK_DISABLE) - { - data_mask = 0x00; - } - else if (data_mask == ENUM_ATTR_EFF_DATA_MASK_ENABLE) - { - data_mask = 0xFF; - } - - if (write_dbi == ENUM_ATTR_EFF_WRITE_DBI_DISABLE) - { - write_dbi = 0x00; - } - else if (write_dbi == ENUM_ATTR_EFF_WRITE_DBI_ENABLE) - { - write_dbi = 0xFF; - } - - if (read_dbi == ENUM_ATTR_EFF_READ_DBI_DISABLE) - { - read_dbi = 0x00; - } - else if (read_dbi == ENUM_ATTR_EFF_READ_DBI_ENABLE) - { - read_dbi = 0xFF; - } - if (rtt_park[i_port_number][dimm_number][rank_number] == ENUM_ATTR_EFF_RTT_PARK_DISABLE) - { - rtt_park[i_port_number][dimm_number][rank_number] = 0x00; - } - else if (rtt_park[i_port_number][dimm_number][rank_number] == ENUM_ATTR_EFF_RTT_PARK_60OHM) - { - rtt_park[i_port_number][dimm_number][rank_number] = 0x80; - } - else if (rtt_park[i_port_number][dimm_number][rank_number] == ENUM_ATTR_EFF_RTT_PARK_40OHM) - { - rtt_park[i_port_number][dimm_number][rank_number] = 0xC0; - } - else if (rtt_park[i_port_number][dimm_number][rank_number] == ENUM_ATTR_EFF_RTT_PARK_120OHM) - { - rtt_park[i_port_number][dimm_number][rank_number] = 0x40; - } - else if (rtt_park[i_port_number][dimm_number][rank_number] == ENUM_ATTR_EFF_RTT_PARK_240OHM) - { - rtt_park[i_port_number][dimm_number][rank_number] = 0x20; - } - else if (rtt_park[i_port_number][dimm_number][rank_number] == ENUM_ATTR_EFF_RTT_PARK_48OHM) - { - rtt_park[i_port_number][dimm_number][rank_number] = 0xA0; - } - else if (rtt_park[i_port_number][dimm_number][rank_number] == ENUM_ATTR_EFF_RTT_PARK_80OHM) - { - rtt_park[i_port_number][dimm_number][rank_number] = 0x60; - } - else if (rtt_park[i_port_number][dimm_number][rank_number] == ENUM_ATTR_EFF_RTT_PARK_34OHM) - { - rtt_park[i_port_number][dimm_number][rank_number] = 0xE0; - } - - rc_num = rc_num | address_16.insert((uint8_t) ca_parity_latency, 0, 2); - rc_num = rc_num | address_16.insert((uint8_t) crc_error_clear, 3, 1); - rc_num = rc_num | address_16.insert((uint8_t) ca_parity_error_status, 4, 1); - rc_num = rc_num | address_16.insert((uint8_t) odt_input_buffer, 5, 1); - rc_num = rc_num | address_16.insert((uint8_t) rtt_park[i_port_number][dimm_number][rank_number], 6, 3); - rc_num = rc_num | address_16.insert((uint8_t) ca_parity, 9, 1); - rc_num = rc_num | address_16.insert((uint8_t) data_mask, 10, 1); - rc_num = rc_num | address_16.insert((uint8_t) write_dbi, 11, 1); - rc_num = rc_num | address_16.insert((uint8_t) read_dbi, 12, 1); - rc_num = rc_num | address_16.insert((uint8_t) 0x00, 13, 2); - - rc_num = rc_num | bank_3.insert((uint8_t) MRS5_BA, 0, 1, 7); - rc_num = rc_num | bank_3.insert((uint8_t) MRS5_BA, 1, 1, 6); - rc_num = rc_num | bank_3.insert((uint8_t) MRS5_BA, 2, 1, 5); - if (rc_num) - { - FAPI_ERR( "mss_mrs_load: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - } - //MRS6 - else if(MRS == MRS6_BA) { - uint8_t vrefdq_train_value[2][2][4]; //vrefdq_train value - NEW - rc = FAPI_ATTR_GET( ATTR_VREF_DQ_TRAIN_VALUE, &i_target, vrefdq_train_value); - if(rc) return rc; - uint8_t vrefdq_train_range[2][2][4]; //vrefdq_train range - NEW - rc = FAPI_ATTR_GET( ATTR_VREF_DQ_TRAIN_RANGE, &i_target, vrefdq_train_range); - if(rc) return rc; - uint8_t vrefdq_train_enable[2][2][4]; //vrefdq_train enable - NEW - rc = FAPI_ATTR_GET( ATTR_VREF_DQ_TRAIN_ENABLE, &i_target, vrefdq_train_enable); - if(rc) return rc; - uint8_t tccd_l; //tccd_l - NEW - rc = FAPI_ATTR_GET( ATTR_TCCD_L, &i_target, tccd_l); - if(rc) return rc; - if (tccd_l == 4) - { - tccd_l = 0x00; - } - else if (tccd_l == 5) - { - tccd_l = 0x80; - } - else if (tccd_l == 6) - { - tccd_l = 0x40; - } - else if (tccd_l == 7) - { - tccd_l = 0xC0; - } - else if (tccd_l == 8) - { - tccd_l = 0x20; - } - - vrefdq_train_value[i_port_number][dimm_number][rank_number] = mss_reverse_8bits(vrefdq_train_value[i_port_number][dimm_number][rank_number]); - - if (vrefdq_train_range[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VREF_DQ_TRAIN_RANGE_RANGE1) - { - vrefdq_train_range[i_port_number][dimm_number][rank_number] = 0x00; - } - else if (vrefdq_train_range[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VREF_DQ_TRAIN_RANGE_RANGE2) - { - vrefdq_train_range[i_port_number][dimm_number][rank_number] = 0xFF; - } - - if (vrefdq_train_enable[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE) - { - vrefdq_train_enable[i_port_number][dimm_number][rank_number] = 0xFF; - } - else if (vrefdq_train_enable[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_DISABLE) - { - vrefdq_train_enable[i_port_number][dimm_number][rank_number] = 0x00; - } - - rc_num = rc_num | address_16.insert((uint8_t) vrefdq_train_value[i_port_number][dimm_number][rank_number], 0, 6); - rc_num = rc_num | address_16.insert((uint8_t) vrefdq_train_range[i_port_number][dimm_number][rank_number], 6, 1); - rc_num = rc_num | address_16.insert((uint8_t) vrefdq_train_enable[i_port_number][dimm_number][rank_number], 7, 1); - rc_num = rc_num | address_16.insert((uint8_t) 0x00, 8, 2); - rc_num = rc_num | address_16.insert((uint8_t) tccd_l, 10, 3); - rc_num = rc_num | address_16.insert((uint8_t) 0x00, 13, 2); - - rc_num = rc_num | bank_3.insert((uint8_t) MRS6_BA, 0, 1, 7); - rc_num = rc_num | bank_3.insert((uint8_t) MRS6_BA, 1, 1, 6); - rc_num = rc_num | bank_3.insert((uint8_t) MRS6_BA, 2, 1, 5); - if (rc_num) - { - FAPI_ERR( "mss_mrs_load: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - } - else { - const uint32_t MRS_VALUE = MRS; - const fapi::Target & MBA_TARGET = i_target; - FAPI_SET_HWP_ERROR(rc, RC_MSS_PDA_MRS_NOT_FOUND); - FAPI_ERR("ERROR!! Found attribute name not associated with an MRS! Exiting..."); - } - - return rc; -} -} - diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_ddr4_pda.H b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_ddr4_pda.H deleted file mode 100644 index ac136bdfb..000000000 --- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_ddr4_pda.H +++ /dev/null @@ -1,177 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_ddr4_pda.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2015 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: mss_ddr4_pda.H,v 1.38 2015/07/27 14:49:59 sglancy Exp $ -//------------------------------------------------------------------------------ -// *! (C) Copyright International Business Machines Corp. 2013 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -//------------------------------------------------------------------------------ -// *! TITLE : mss_ddr4_pda.H -// *! DESCRIPTION : Tools for DDR4 DIMMs centaur procedures -// *! OWNER NAME : Stephen Glancy Email: sglancy@us.ibm.com -// *! BACKUP NAME : Andre Marin Email: aamarin@us.ibm.com -// #! ADDITIONAL COMMENTS : -// - -//------------------------------------------------------------------------------ -// Don't forget to create CVS comments when you check in your changes! -//------------------------------------------------------------------------------ -// CHANGE HISTORY: -//------------------------------------------------------------------------------ -// Version:| Author: | Date: | Comment: -//---------|----------|---------|----------------------------------------------- -// 1.5 | 05/13/15 | sglancy | Added dox and updated functions for better FFDC -// 1.4 | 05/11/15 | sglancy | Addressed FW comments -// 1.3 | 05/07/15 | sglancy | Updated Doxygen header -// 1.2 | 02/13/15 | sglancy | Updated to allow for file inputs -// 1.1 | 10/27/14 | sglancy | First revision - -#ifndef _MSS_DDR4_PDA_H -#define _MSS_DDR4_PDA_H -#include <fapi.H> -using namespace fapi; -using namespace std; -class PDA_MRS_Storage { -private: - char pda_string[MAX_ECMD_STRING_LEN]; //aware that this isn't threadsafe but should be called w/in each thread -public: - uint8_t attribute_data; - uint32_t attribute_name; - uint8_t MRS; - uint8_t dimm; - uint8_t dram; - uint8_t rank; - uint8_t port; - PDA_MRS_Storage(uint8_t ad,uint32_t an,uint8_t dr,uint8_t di,uint8_t r,uint8_t p); - ~PDA_MRS_Storage(); - bool operator> (const PDA_MRS_Storage &PDA2) const; - bool operator< (const PDA_MRS_Storage &PDA2) const; - void copy(PDA_MRS_Storage &temp); - ReturnCode setMRSbyAttr(Target& i_target); - ReturnCode checkPDAValid(Target& i_target); - char * c_str(); - void generatePDAString(); -}; - -class PDA_Scom_Storage { -public: - uint64_t scom_addr; - uint32_t start_bit; - uint32_t num_bits; - PDA_Scom_Storage(uint64_t sa, uint32_t sb, uint32_t nb); - ~PDA_Scom_Storage(); -}; - -typedef ReturnCode (*mss_ddr4_pda_FP_t)(Target& i_target, vector<PDA_MRS_Storage> pda); - -extern "C" -{ - -/** - * @runs through the vector of given PDA values and issues the PDA commands to the requested DRAMs - * - * @param[in] target: Reference to centaur.mba target, - * @param[in] vector: Vector of PDA_MRS_Storage class elements - initialized by the user and contains DRAM information and attribute override information - * - * @return ReturnCode - */ -ReturnCode mss_ddr4_run_pda(Target& i_target,vector<PDA_MRS_Storage> pda); -/** - * @Puts the DRAM in per-DRAM addressability mode (PDA mode) - * - * @param[in] target: Reference to centaur.mba target, - * @param[in/out] io_ccs_inst_cnt: starting point of CCS array - needed to properly setup CCS - * - * @return ReturnCode - */ -ReturnCode mss_ddr4_setup_pda(Target& i_target,uint32_t& io_ccs_inst_cnt); -/** - * @Takes the DRAM out of per-DRAM addressability mode (PDA mode) - * - * @param[in] target: Reference to centaur.mba target, - * @param[in/out] io_ccs_inst_cnt: starting point of CCS array - needed to properly setup CCS - * - * @return ReturnCode - */ -ReturnCode mss_ddr4_disable_pda(Target& i_target,uint32_t& io_ccs_inst_cnt); -/** - * @called by wrapper - sets up a PDA vector if it's not already configured - * - * @param[in] target: Reference to centaur.mba target, - * @param[in] vector: Vector of PDA_MRS_Storage class elements - initialized by the user and contains DRAM information and attribute override information - * - * @return ReturnCode - */ -ReturnCode mss_ddr4_pda(Target& i_target,vector<PDA_MRS_Storage> pda); -/** - * @Checks the passed in PDA vector to ensure that all entries are good. then sorts the vector to ensure more efficient command stream - * - * @param[in] target: Reference to centaur.mba target, - * @param[in/out] vector: Vector of PDA_MRS_Storage class elements - initialized by the user and contains DRAM information and attribute override information - * - * @return ReturnCode - */ -ReturnCode mss_ddr4_checksort_pda(Target& i_target, vector<PDA_MRS_Storage>& pda); -/** - * @Modifies the passed in address_16 buffer based upon the given attribute and data - * - * @param[in] target: Reference to centaur.mba target, - * @param[in/out] ecmdDataBufferBase& address_16: MRS values - this is modified by the given attribute name and data - * @param[in] uint32_t attribute_name: enumerated value containing the attribute name to be modified - attr_name tells the function which bits to modify - * @param[in] uint8_t attribute_data: data telss the function what values to set to the modified bits - * - * @return ReturnCode - */ -ReturnCode mss_ddr4_modify_mrs_pda(Target& i_target,ecmdDataBufferBase& address_16,uint32_t attribute_name,uint8_t attribute_data); -/** - * @Adds a given DRAM into the scom_storage vector - * - * @param[in] target: Reference to centaur.mba target, - * @param[in] uint8_t port: identifies which port the given DRAM is on - * @param[in] uint8_t dram: identifies which DRAM identifier is to be added - * @param[in/out] vector: list of all DRAMs being modified by PDA. contains address, bit, and length - * - * @return ReturnCode - */ -ReturnCode mss_ddr4_add_dram_pda(Target& i_target,uint8_t port,uint8_t dram,vector<PDA_Scom_Storage> & scom_storage); -/** - * @loads in a nominal MRS value into the address_16 and bank_3 - * - * @param[in] target: Reference to centaur.mba target, - * @param[out] ecmdDataBufferBase& bank_3: bank bits to be issued during MRS - * @param[out] ecmdDataBufferBase& address_16: 16 address lanes to be issued during MRS - setup during function - * @param[in] uint8_t MRS: which MRS to configure - * @param[in] uint8_t i_port_number: the port on which to configure the MRS - used for ID'ing which attributes to use - * @param[in] uint8_t dimm_number: the DIMM on which to configure the MRS - used for ID'ing which attributes to use - * @param[in] uint8_t rank_number: the rank on which to configure the MRS - used for ID'ing which attributes to use - * - * @return ReturnCode - */ -ReturnCode mss_ddr4_load_nominal_mrs_pda(Target& i_target,ecmdDataBufferBase& bank_3,ecmdDataBufferBase& address_16,uint8_t MRS,uint8_t i_port_number, uint8_t dimm_number, uint8_t rank_number); -} // extern "C" - -#endif /* _MSS_DDR4_PDA_H */ - - diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_draminit_training_advanced.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_draminit_training_advanced.C deleted file mode 100644 index c62c99695..000000000 --- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_draminit_training_advanced.C +++ /dev/null @@ -1,2036 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_draminit_training_advanced.C $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2012,2015 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: mss_draminit_training_advanced.C,v 1.50 2015/08/27 21:59:32 eliner Exp $ -/* File is created by SARAVANAN SETHURAMAN on Thur 29 Sept 2011. */ - -//------------------------------------------------------------------------------ -// *! (C) Copyright International Business Machines Corp. 2007 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -//------------------------------------------------------------------------------ -// *! TITLE :mss_draminit_training_advanced.C -// *! DESCRIPTION : Tools for centaur procedures -// *! OWNER NAME : Preetham Hosmane email: preeragh@in.ibm.com -// *! BACKUP NAME: Saravanan Sethuraman email ID:saravanans@in.ibm.com -// #! ADDITIONAL COMMENTS : -// -// General purpose funcs - -//------------------------------------------------------------------------------ -// Don't forget to create CVS comments when you check in your changes! -//------------------------------------------------------------------------------ -// CHANGE HISTORY: -//------------------------------------------------------------------------------ -// Version:| Author: | Date: | Comment: -//---------|----------|---------|----------------------------------------------- -// 1.1 | sasethur |30-Sep-11| Initial draft. -// 1.2 | sasethur |18-Nov-11| Changed function names -// 1.3 | sasethur |01-Dec-11| Added details on Vref shmoo, reg addresses -// 1.4 | sasethur |29-Jan-12| Updated wr&rd vref, removed ecmd workarounds -// 1.5 | sasethur |13-Feb-12| Updated register naming conventions -// 1.6 | sasethur |08-Mar-12| Changed rc_num, multiple changes to drv_imp, Vref funcs -// 1.7 | sasethur |23-Mar-12| Added Receiver Impedance shmoo & changes to mcbist call -// 1.8 | sasethur |30-Mar-12| Removed port from start_mcb, added 15,20,48 receiver imp settings -// 1.9 | sasethur |03-Apr-12| Fixed warning messages -// 1.13 | bellows |16-Jul-12| Added in Id tag -// 1.14 | bellows |18-Jul-12| Disabled some checking code -// 1.15 | gollub |05-Sep-12| Calling mss_unmask_draminit_training_advanced_errors after mss_draminit_training_advanced_cloned -// 1.16 | sasethur |15-Oct-12| Fixed FW review comments and modified function based on new attributes, added slew function -// 1.17 | sasethur |17-Oct-12| Updated index bound checks -// 1.18 | sasethur |17-Oct-12| Removed Hardcoding of Shmoo parameter value -// 1.19 | sasethur |26-Oct-12| Updated fapi::ReturnCode, const Target& and removed fapi::RC_SUCCSESS as per FW comments -// 1.20 | bellows |13-Nov-12| Updated for new SI attributes -// 1.21 | sasethur |11-Nov-12| Updated for new SI attribute change, fw review comments -// 1.22 | sasethur |07-Dec-12| Updated for FW review comments - multiple changes -// 1.23 | sasethur |14-Dec-12| Updated for FW review comments -// 1.24 | sasethur |17-Jan-13| Updated for mss_mcbist_common.C include file -// 1.25 | abhijsau |31-Jan-13| Removed mss_mcbist_common.C include file , needs to be included while compiling -// 1.26 | abhijsau |06-Mar-13| Fixed fw comment -// 1.27 | sasethur |09-Apr-13| Updated for port in parallel and pass shmoo param -// 1.28 | sasethur |22-Apr-13| Fixed fw comment -// 1.29 | sasethur |23-Apr-13| Fixed fw comment -// 1.30 | sasethur |24-Apr-13| Fixed fw comment -// 1.31 | sasethur |10-May-13| Added user input for test type, pattern from wrapper -// 1.32 | sasethur |04-Jun-13| Fixed for PortD cnfg, vref print for min setup, hold, fixed rdvref print, added set/reset mcbist attr -// 1.33 | sasethur |12-Jun-13| Updated mcbist setup attribute -// 1.34 | sasethur |20-Jun-13| Fixed read_vref print, setup attribute -// 1.35 | sasethur |08-Aug-13| Fixed fw comment -// 1.36 | sasethur |23-Aug-13| Ability to run MCBIST is enabled. -// 1.37 | sasethur |04-Sep-13| Fixed fw review comment -// 1.38 | bellows |19-SEP-13| fixed possible buffer overrun found by stradale -// 1.39 | abhijsau |17-OCT-13| fixed a logical bug -// 1.40 | abhijsau |17-DEC-13| added creation and deletion of schmoo object -// 1.41 | abhijsau |16-JAN-14| removed EFF_DIMM_TYPE attribute -// 1.42 | mjjones |17-Jan-14| Fixed layout and error handling for RAS Review -// 1.43 | jdsloat |10-MAR-14| Edited comments -// 1.44 |preeragh |06-NOV-14| Added Sanity checks for wr_vref and rd_vref only at nominal and disabled any other -// 1.45 |sglancy |09-FEB-14| Responded to FW comments -// 1.46 |preeragh |22-Jun-14| DDR4 Enhancements and Optimizations -// 1.47 |preeragh |22-Jul-14| 64 Bit compile Fix -// 1.48 |preeragh |19-Aug-14| Fix FW Review Comments -// 1.49 |eliner |27-Aug-15| Fixing Index Overflow Bug -// 1.50 |eliner |27-Aug-15| Fixing Index Overflow Bug -// This procedure Schmoo's DRV_IMP, SLEW, VREF (DDR, CEN), RCV_IMP based on attribute from effective config procedure -// DQ & DQS Driver impedance, Slew rate, WR_Vref shmoo would call only write_eye shmoo for margin calculation -// DQ & DQS VREF (rd_vref), RCV_IMP shmoo would call rd_eye for margin calculation -// Internal Vref controlled by this function & external vref - -// Not supported -// DDR4, DIMM Types -//---------------------------------------------------------------------- -// Includes - FAPI -//---------------------------------------------------------------------- - -#include <fapi.H> - -//---------------------------------------------------------------------- -//Centaur functions -//---------------------------------------------------------------------- -#include <mss_termination_control.H> -#include "mss_mcbist.H" -#include <mss_shmoo_common.H> -#include <mss_generic_shmoo.H> -#include <mss_draminit_training_advanced.H> -#include <mss_unmask_errors.H> -#include <mss_mrs6_DDR4.H> -#include <mss_ddr4_pda.H> -#include <vector> - -const uint32_t MASK = 1; -const uint32_t MAX_DIMM =2; - -enum shmoo_param -{ - PARAM_NONE = 0x00, - DELAY_REG = 0x01, - DRV_IMP = 0x02, - SLEW_RATE = 0x04, - WR_VREF = 0x08, - RD_VREF = 0x10, - RCV_IMP = 0x20 -}; - - -extern "C" -{ - - using namespace fapi; - - fapi::ReturnCode mss_draminit_training_advanced_cloned(const fapi::Target & i_target_mba); - - fapi::ReturnCode drv_imped_shmoo(const fapi::Target & i_target_mba, uint8_t i_port, - shmoo_type_t i_shmoo_type_valid); - - fapi::ReturnCode slew_rate_shmoo(const fapi::Target & i_target_mba, uint8_t i_port, - shmoo_type_t i_shmoo_type_valid); - - fapi::ReturnCode wr_vref_shmoo(const fapi::Target & i_target_mba, uint8_t i_port, - shmoo_type_t i_shmoo_type_valid); - - fapi::ReturnCode wr_vref_shmoo_ddr4(const fapi::Target & i_target_mba); - fapi::ReturnCode wr_vref_shmoo_ddr4_bin(const fapi::Target & i_target_mba); - fapi::ReturnCode rd_vref_shmoo_ddr4(const fapi::Target & i_target_mba); - - fapi::ReturnCode rd_vref_shmoo(const fapi::Target & i_target_mba, uint8_t i_port, - shmoo_type_t i_shmoo_type_valid); - - fapi::ReturnCode rcv_imp_shmoo(const fapi::Target & i_target_mba, uint8_t i_port, - shmoo_type_t i_shmoo_type_valid); - - fapi::ReturnCode delay_shmoo(const fapi::Target & i_target_mba, uint8_t i_port, - shmoo_type_t i_shmoo_type_valid, - uint32_t *o_left_margin, uint32_t *o_right_margin, - uint32_t i_shmoo_param); - fapi::ReturnCode delay_shmoo_ddr4(const fapi::Target & i_target_mba, uint8_t i_port, - shmoo_type_t i_shmoo_type_valid, - uint32_t *o_left_margin, uint32_t *o_right_margin, - uint32_t i_shmoo_param,uint32_t pda_nibble_table[2][2][16][2]); - - fapi::ReturnCode delay_shmoo_ddr4_pda(const fapi::Target & i_target_mba, uint8_t i_port, - shmoo_type_t i_shmoo_type_valid, - uint32_t *o_left_margin, uint32_t *o_right_margin, - uint32_t i_shmoo_param,uint32_t pda_nibble_table[2][2][16][2]); - - void find_best_margin(shmoo_param i_shmoo_param_valid,uint32_t i_left[], - uint32_t i_right[], const uint8_t l_max, - uint32_t i_param_nom, uint8_t& o_index); - - fapi::ReturnCode set_attribute(const fapi::Target & i_target_mba); - - fapi::ReturnCode reset_attribute(const fapi::Target & i_target_mba); - - - //----------------------------------------------------------------------------------- - //Function name: mss_draminit_training_advanced() - //Description: This function varies driver impedance, receiver impedance, slew, wr & rd vref - //based on attribute definition and runs either mcbist/delay shmoo based on attribute - //Also calls unmask function mss_unmask_draminit_training_advanced_errors() - //Input : const fapi::Target MBA, i_pattern = pattern selection during mcbist @ lab, - // l_test type = test type selection during mcbist @ lab - // Default vlaues are Zero - //----------------------------------------------------------------------------------- - - fapi::ReturnCode mss_draminit_training_advanced(const fapi::Target & i_target_mba) - { - // const fapi::Target is centaur.mba - fapi::ReturnCode rc; - //FAPI_INF(" pattern bit is %d and test_type_bit is %d"); - rc = mss_draminit_training_advanced_cloned(i_target_mba); - if (rc) - { - FAPI_ERR("Advanced DRAM Init training procedure is Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator()); - } - - // If mss_unmask_draminit_training_advanced_errors gets it's own bad rc, - // it will commit the passed in rc (if non-zero), and return it's own bad rc. - // Else if mss_unmask_draminit_training_advanced_errors runs clean, - // it will just return the passed in rc. - - rc = mss_unmask_draminit_training_advanced_errors(i_target_mba, rc); - if (rc) - { - FAPI_ERR("Unmask Function is Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator()); - return rc; - } - return rc; - } - -} -//end of extern C - -//----------------------------------------------------------------------------------- -// Function name: mss_draminit_training_advanced_cloned() -// Description: This function varies driver impedance, receiver impedance, slew, wr & rd vref -// based on attribute definition and runs either mcbist/delay shmoo based on attribute -// Input : const fapi::Target MBA -// i_pattern, i_test_type : Default = 0, mcbist lab function would use this arg -//----------------------------------------------------------------------------------- -fapi::ReturnCode mss_draminit_training_advanced_cloned(const fapi::Target & i_target_mba) -{ - //const fapi::Target is centaur.mba - fapi::ReturnCode rc; - - FAPI_INF("+++++++ Executing mss_draminit_training_advanced +++++++"); - - // Define attribute variables - uint32_t l_attr_mss_freq_u32 = 0; - uint32_t l_attr_mss_volt_u32 = 0; - uint8_t l_num_drops_per_port_u8 = 2; - uint8_t l_num_ranks_per_dimm_u8array[MAX_PORT][MAX_DIMM] = {{0}}; - uint8_t l_port = 0; - uint32_t l_left_margin=0; - uint32_t l_right_margin=0; - uint32_t l_shmoo_param=0; - uint8_t l_dram_type=0; - uint8_t bin_pda=0; - // Define local variables - uint8_t l_shmoo_type_valid_t=0; - uint8_t l_shmoo_param_valid_t=0; - enum dram_type { EMPTY = 0, DDR3 = 1, DDR4 = 2}; - //const fapi::Target is centaur - fapi::Target l_target_centaur; - rc = fapiGetParentChip(i_target_mba, l_target_centaur); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_MSS_FREQ, &l_target_centaur, l_attr_mss_freq_u32); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_MSS_VOLT, &l_target_centaur, l_attr_mss_volt_u32); - if(rc) return rc; - - //const fapi::Target is centaur.mba - rc = FAPI_ATTR_GET(ATTR_EFF_NUM_DROPS_PER_PORT, &i_target_mba, l_num_drops_per_port_u8); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target_mba, l_num_ranks_per_dimm_u8array); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_GEN, &i_target_mba, l_dram_type); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_MCBIST_USER_BANK, &i_target_mba, bin_pda); - if(rc) return rc; - - - FAPI_INF("+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++"); - FAPI_INF("freq = %d on %s.", l_attr_mss_freq_u32, l_target_centaur.toEcmdString()); - FAPI_INF("volt = %d on %s.", l_attr_mss_volt_u32, l_target_centaur.toEcmdString()); - FAPI_INF("num_drops_per_port = %d on %s.", l_num_drops_per_port_u8, i_target_mba.toEcmdString()); - FAPI_INF("num_ranks_per_dimm = [%02d][%02d][%02d][%02d]", - l_num_ranks_per_dimm_u8array[0][0], - l_num_ranks_per_dimm_u8array[0][1], - l_num_ranks_per_dimm_u8array[1][0], - l_num_ranks_per_dimm_u8array[1][1]); - FAPI_INF("+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++"); - - rc = FAPI_ATTR_GET(ATTR_EFF_SCHMOO_TEST_VALID, &i_target_mba, l_shmoo_type_valid_t); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_SCHMOO_PARAM_VALID, &i_target_mba, l_shmoo_param_valid_t); - if(rc) return rc; - - shmoo_type_t l_shmoo_type_valid; - shmoo_param l_shmoo_param_valid; - - l_shmoo_type_valid=(shmoo_type_t)l_shmoo_type_valid_t; - l_shmoo_param_valid=(shmoo_param)l_shmoo_param_valid_t; - FAPI_INF("+++++++++++++++++++++++++ Read Schmoo Attributes ++++++++++++++++++++++++++"); - FAPI_INF("Schmoo param valid = 0x%x on %s", l_shmoo_param_valid, i_target_mba.toEcmdString()); - FAPI_INF("Schmoo test valid = 0x%x on %s", l_shmoo_type_valid, i_target_mba.toEcmdString()); - FAPI_INF("+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++"); - //Check for Shmoo Parameter, if anyof them is enabled then go into the loop else the procedure exit - - if ((l_num_ranks_per_dimm_u8array[0][0] > 0) || - (l_num_ranks_per_dimm_u8array[0][1] > 0) || - (l_num_ranks_per_dimm_u8array[1][0] > 0) || - (l_num_ranks_per_dimm_u8array[1][1] > 0)) - { - if ((l_shmoo_param_valid != PARAM_NONE) || - (l_shmoo_type_valid != TEST_NONE)) - { - if ((l_shmoo_param_valid & DRV_IMP) != 0) - { - rc = drv_imped_shmoo(i_target_mba, l_port, l_shmoo_type_valid); - if (rc) - { - FAPI_ERR("Driver Impedance Schmoo function is Failed rc = 0x%08X (creator = %d)", - uint32_t(rc), rc.getCreator()); - return rc; - } - } - if ((l_shmoo_param_valid & SLEW_RATE) != 0) - { - rc = slew_rate_shmoo(i_target_mba, l_port, l_shmoo_type_valid); - if (rc) - { - FAPI_ERR("Slew Rate Schmoo Function is Failed rc = 0x%08X (creator = %d)", - uint32_t(rc), rc.getCreator()); - return rc; - } - } - if ((l_shmoo_param_valid & WR_VREF) != 0) - { - if(l_dram_type==DDR3){ - rc = wr_vref_shmoo(i_target_mba, l_port, l_shmoo_type_valid); - if (rc) - { - FAPI_ERR("Write Vref Schmoo Function is Failed rc = 0x%08X (creator = %d)", - uint32_t(rc), rc.getCreator()); - return rc; - } - } - else{ - if(bin_pda == 1) - { - FAPI_INF("************* Bin - PDA - Vref_Schmoo **************"); - - rc = wr_vref_shmoo_ddr4_bin(i_target_mba); - if (rc) - { - FAPI_ERR("Write Vref Schmoo Function is Failed rc = 0x%08X (creator = %d)", - uint32_t(rc), rc.getCreator()); - return rc; - } - } - else - { - rc = wr_vref_shmoo_ddr4(i_target_mba); - if (rc) - { - FAPI_ERR("Write Vref Schmoo Function is Failed rc = 0x%08X (creator = %d)", - uint32_t(rc), rc.getCreator()); - return rc; - } - } - } - } - if ((l_shmoo_param_valid & RD_VREF) != 0) - { - if(l_dram_type==DDR3){ - rc = rd_vref_shmoo(i_target_mba, l_port, l_shmoo_type_valid); - if (rc) - { - FAPI_ERR("Read Vref Schmoo Function is Failed rc = 0x%08X (creator = %d)", - uint32_t(rc), rc.getCreator()); - return rc; - } - } - else - { - rc = rd_vref_shmoo_ddr4(i_target_mba); - if (rc) - { - FAPI_ERR("rd_vref_shmoo_ddr4 Function is Failed rc = 0x%08X (creator = %d)", - uint32_t(rc), rc.getCreator()); - return rc; - } - } - } - if ((l_shmoo_param_valid & RCV_IMP) != 0) - { - rc = rcv_imp_shmoo(i_target_mba, l_port, l_shmoo_type_valid); - if (rc) - { - FAPI_ERR("Receiver Impedance Schmoo Function is Failed rc = 0x%08X (creator = %d)", - uint32_t(rc), rc.getCreator()); - return rc; - } - } - if (((l_shmoo_param_valid == PARAM_NONE))) - { - rc = delay_shmoo(i_target_mba, l_port, l_shmoo_type_valid, - &l_left_margin, &l_right_margin, - l_shmoo_param); - if (rc) - { - FAPI_ERR("Delay Schmoo Function is Failed rc = 0x%08X (creator = %d)", - uint32_t(rc), rc.getCreator()); - return rc; - } - } - } - } - return rc; -} - -//------------------------------------------------------------------------------- -// Function name: drv_imped_shmoo() -// This function varies the driver impedance in the nominal mode -// for both dq/dqs & adr/cmd signals - DQ_DQS<24,30,34,40>,CMD_CNTL<15,20,30,40> -// if there is any mcbist failure, that will be reported to put_bad_bits function -// Input param: const fapi::Target MBA, port = 0,1 -// Shmoo type: MCBIST, WR_EYE, RD_EYE, WR_DQS, RD_DQS -// Shmoo param: PARAM_NONE, DRV_IMP, SLEW_RATE, WR_VREF, RD_VREF, RCV_IMP -// Shmoo Mode: FEW_ADDR, QUARTER_ADDR, HALF_ADDR, FULL_ADDR -// i_pattern, i_test_type : Default = 0, mcbist lab function would use this arg -//------------------------------------------------------------------------------- - -fapi::ReturnCode drv_imped_shmoo(const fapi::Target & i_target_mba, -uint8_t i_port, -shmoo_type_t i_shmoo_type_valid) -{ - fapi::ReturnCode rc; - uint8_t l_drv_imp_dq_dqs[MAX_PORT] = {0}; - uint8_t l_drv_imp_dq_dqs_nom[MAX_PORT] = {0}; - //uint8_t l_drv_imp_dq_dqs_new[MAX_PORT] = {0}; - uint8_t index=0; - uint8_t l_slew_rate_dq_dqs[MAX_PORT] = {0}; - uint8_t l_slew_rate_dq_dqs_schmoo[MAX_PORT] = {0}; - uint32_t l_drv_imp_dq_dqs_schmoo[MAX_PORT] = {0}; - uint8_t l_drv_imp_dq_dqs_nom_fc = 0; - uint8_t l_drv_imp_dq_dqs_in = 0; - //Temporary - i_shmoo_type_valid = WR_EYE; //Hard coded, since no other schmoo is applicable for this parameter - uint32_t l_left_margin_drv_imp_array[MAX_DRV_IMP] = {0}; - uint32_t l_right_margin_drv_imp_array[MAX_DRV_IMP] = {0}; - uint32_t l_left_margin = 0; - uint32_t l_right_margin = 0; - uint8_t count = 0; - uint8_t shmoo_param_count = 0; - uint8_t l_slew_type = 0; // Hard coded since this procedure will touch only DQ_DQS and not address - - rc = FAPI_ATTR_GET(ATTR_EFF_CEN_DRV_IMP_DQ_DQS, &i_target_mba, l_drv_imp_dq_dqs_nom); - if (rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_CEN_SLEW_RATE_DQ_DQS, &i_target_mba, l_slew_rate_dq_dqs); - if (rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_CEN_DRV_IMP_DQ_DQS_SCHMOO, &i_target_mba, l_drv_imp_dq_dqs_schmoo); - if (rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SCHMOO, &i_target_mba, l_slew_rate_dq_dqs_schmoo); - if (rc) return rc; - - FAPI_INF("+++++++++++++++++Read DRIVER IMP Attributes values++++++++++++++++"); - FAPI_INF("CEN_DRV_IMP_DQ_DQS[%d] = [%02d] Ohms, on %s", - i_port, - l_drv_imp_dq_dqs_nom[i_port], - i_target_mba.toEcmdString()); - FAPI_INF("CEN_DRV_IMP_DQ_DQS_SCHMOO[0] = [0x%x], CEN_DRV_IMP_DQ_DQS_SCHMOO[1] = [0x%x] on %s", - l_drv_imp_dq_dqs_schmoo[0], - l_drv_imp_dq_dqs_schmoo[1], - i_target_mba.toEcmdString()); - FAPI_INF("CEN_SLEW_RATE_DQ_DQS[0] = [%02d]V/ns , CEN_SLEW_RATE_DQ_DQS[1] = [%02d]V/ns on %s", - l_slew_rate_dq_dqs[0], - l_slew_rate_dq_dqs[1], - i_target_mba.toEcmdString()); - FAPI_INF("CEN_SLEW_RATE_DQ_DQS_SCHMOO[0] = [0x%x], CEN_SLEW_RATE_DQ_DQS_SCHMOO[1] = [0x%x] on %s", - l_slew_rate_dq_dqs_schmoo[0], - l_slew_rate_dq_dqs_schmoo[1], - i_target_mba.toEcmdString()); - FAPI_INF("++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++"); - - if(l_drv_imp_dq_dqs_schmoo[i_port] == 0) //Check for any of the bits enabled in the shmoo - { - FAPI_INF("DRIVER IMP Shmoo set to FAST Mode and won't do anything"); - } - else - { - for (index = 0; index < MAX_DRV_IMP; index += 1) - { - if (l_drv_imp_dq_dqs_schmoo[i_port] & MASK) - { - l_drv_imp_dq_dqs[i_port] = drv_imp_array[index]; - FAPI_INF("Current Driver Impedance Value = %d Ohms", - drv_imp_array[index]); - FAPI_INF("Configuring Driver Impedance Registers:"); - rc = config_drv_imp(i_target_mba, i_port, - l_drv_imp_dq_dqs[i_port]); - if (rc) return rc; - l_drv_imp_dq_dqs_in = l_drv_imp_dq_dqs[i_port]; - FAPI_INF("Configuring Slew Rate Registers:"); - rc = config_slew_rate(i_target_mba, i_port, l_slew_type, - l_drv_imp_dq_dqs[i_port], - l_slew_rate_dq_dqs[i_port]); - if (rc) return rc; - FAPI_INF("Calling Shmoo for finding Timing Margin:"); - if (shmoo_param_count) - { - rc = set_attribute(i_target_mba); - if (rc) return rc; - } - rc = delay_shmoo(i_target_mba, i_port, i_shmoo_type_valid, - &l_left_margin, &l_right_margin, - l_drv_imp_dq_dqs_in); - if (rc) return rc; - l_left_margin_drv_imp_array[index] = l_left_margin; - l_right_margin_drv_imp_array[index] = l_right_margin; - shmoo_param_count++; - } - else - { - l_left_margin_drv_imp_array[index] = 0; - l_right_margin_drv_imp_array[index] = 0; - } - l_drv_imp_dq_dqs_schmoo[i_port] = (l_drv_imp_dq_dqs_schmoo[i_port] >> 1); - } - l_drv_imp_dq_dqs_nom_fc = l_drv_imp_dq_dqs_nom[i_port]; - find_best_margin(DRV_IMP, l_left_margin_drv_imp_array, - l_right_margin_drv_imp_array, MAX_DRV_IMP, - l_drv_imp_dq_dqs_nom_fc, count); - - if (count >= MAX_DRV_IMP) - { - FAPI_ERR("Driver Imp new input(%d) out of bounds, (>= %d)", count, - MAX_DRV_IMP); - const uint8_t & COUNT_DATA = count; - FAPI_SET_HWP_ERROR(rc, RC_DRV_IMPED_SHMOO_INVALID_MARGIN_DATA); - return rc; - } - else - { - FAPI_INF("Restoring the nominal values!"); - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_DRV_IMP_DQ_DQS, &i_target_mba, - l_drv_imp_dq_dqs_nom); - if (rc) return rc; - rc = config_drv_imp(i_target_mba, i_port, - l_drv_imp_dq_dqs_nom[i_port]); - if (rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_SLEW_RATE_DQ_DQS, &i_target_mba, - l_slew_rate_dq_dqs); - if (rc) return rc; - rc = config_slew_rate(i_target_mba, i_port, l_slew_type, - l_drv_imp_dq_dqs_nom[i_port], - l_slew_rate_dq_dqs[i_port]); - if (rc) return rc; - } - FAPI_INF("Restoring mcbist setup attribute..."); - rc = reset_attribute(i_target_mba); - if (rc) return rc; - FAPI_INF("++++ Driver impedance shmoo function executed successfully ++++"); - } - return rc; -} - -//----------------------------------------------------------------------------------------- -// Function name: slew_rate_shmoo() -// This function varies the slew rate of the data & adr signals (fast/slow) -// calls the write eye shmoo which internally calls mcbist function to see for failure -// if there is any mcbist failure, this function will report to baddqpins function -// Input param: const fapi::Target MBA, port = 0,1 -// Shmoo type: MCBIST, WR_EYE, RD_EYE, WR_DQS, RD_DQS -// Shmoo param: PARAM_NONE, DRV_IMP, SLEW_RATE, WR_VREF, RD_VREF, RCV_IMP -// Shmoo Mode: FEW_ADDR, QUARTER_ADDR, HALF_ADDR, FULL_ADDR -// i_pattern, i_test_type : Default = 0, mcbist lab function would use this arg -//----------------------------------------------------------------------------------------- - -fapi::ReturnCode slew_rate_shmoo(const fapi::Target & i_target_mba, -uint8_t i_port, -shmoo_type_t i_shmoo_type_valid) -{ - fapi::ReturnCode rc; - uint8_t l_slew_rate_dq_dqs[MAX_PORT] = {0}; - uint8_t l_slew_rate_dq_dqs_nom[MAX_PORT] = {0}; - uint8_t l_slew_rate_dq_dqs_nom_fc = 0; - uint8_t l_slew_rate_dq_dqs_in = 0; - uint32_t l_slew_rate_dq_dqs_schmoo[MAX_PORT] = {0}; - uint8_t l_drv_imp_dq_dqs_nom[MAX_PORT] = {0}; - i_shmoo_type_valid = WR_EYE; // Hard coded - Other shmoo type is not valid - Temporary - - uint8_t index = 0; - uint8_t count = 0; - uint8_t shmoo_param_count = 0; - uint32_t l_left_margin_slew_array[MAX_NUM_SLEW_RATES] = {0}; - uint32_t l_right_margin_slew_array[MAX_NUM_SLEW_RATES] = {0}; - uint32_t l_left_margin = 0; - uint32_t l_right_margin = 0; - uint8_t l_slew_type = 0; // Hard coded since this procedure will touch only DQ_DQS and not address - - //Read Attributes - DRV IMP, SLEW, SLEW RATES values to be Schmoo'ed - rc = FAPI_ATTR_GET(ATTR_EFF_CEN_DRV_IMP_DQ_DQS, &i_target_mba, l_drv_imp_dq_dqs_nom); - if (rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_CEN_SLEW_RATE_DQ_DQS, &i_target_mba, l_slew_rate_dq_dqs_nom); - if (rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_CEN_DRV_IMP_DQ_DQS_SCHMOO, &i_target_mba, l_slew_rate_dq_dqs_schmoo); - if (rc) return rc; - - FAPI_INF("+++++++++++++++++Read Slew Shmoo Attributes values+++++++++++++++"); - FAPI_INF("CEN_DRV_IMP_DQ_DQS[0] = [%02d] Ohms, CEN_DRV_IMP_DQ_DQS[1] = [%02d] Ohms on %s", - l_drv_imp_dq_dqs_nom[0], - l_drv_imp_dq_dqs_nom[1], - i_target_mba.toEcmdString()); - FAPI_INF("CEN_SLEW_RATE_DQ_DQS[0] = [%02d]V/ns , CEN_SLEW_RATE_DQ_DQS[1] = [%02d]V/ns on %s", - l_slew_rate_dq_dqs_nom[0], - l_slew_rate_dq_dqs_nom[1], - i_target_mba.toEcmdString()); - FAPI_INF("CEN_SLEW_RATE_DQ_DQS_SCHMOO[0] = [0x%x], CEN_SLEW_RATE_DQ_DQS_SCHMOO[1] = [0x%x] on %s", - l_slew_rate_dq_dqs_schmoo[0], - l_slew_rate_dq_dqs_schmoo[1], - i_target_mba.toEcmdString()); - FAPI_INF("+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++"); - - if(l_slew_rate_dq_dqs_schmoo == 0) //Check for any of the bits enabled in the shmoo - { - FAPI_INF("Slew Rate Shmoo set to FAST Mode and won't do anything"); - } - else - { - for (index = 0; index < MAX_NUM_SLEW_RATES; index += 1) - { - if (l_slew_rate_dq_dqs_schmoo[i_port] & MASK) - { - l_slew_rate_dq_dqs[i_port] = slew_rate_array[index]; - FAPI_INF("Current Slew rate value is %d V/ns", - slew_rate_array[index]); - FAPI_INF("Configuring Slew registers:"); - rc = config_slew_rate(i_target_mba, i_port, l_slew_type, - l_drv_imp_dq_dqs_nom[i_port], - l_slew_rate_dq_dqs[i_port]); - if (rc) return rc; - l_slew_rate_dq_dqs_in = l_slew_rate_dq_dqs[i_port]; - FAPI_INF("Calling Shmoo for finding Timing Margin:"); - if (shmoo_param_count) - { - rc = set_attribute(i_target_mba); - if (rc) return rc; - } - rc = delay_shmoo(i_target_mba, i_port, i_shmoo_type_valid, - &l_left_margin, &l_right_margin, - l_slew_rate_dq_dqs_in); - if (rc) return rc; - l_left_margin_slew_array[index] = l_left_margin; - l_right_margin_slew_array[index] = l_right_margin; - shmoo_param_count++; - } - else - { - l_left_margin_slew_array[index] = 0; - l_right_margin_slew_array[index] = 0; - } - l_slew_rate_dq_dqs_schmoo[i_port] - = (l_slew_rate_dq_dqs_schmoo[i_port] >> 1); - } - l_slew_rate_dq_dqs_nom_fc = l_slew_rate_dq_dqs_nom[i_port]; - find_best_margin(SLEW_RATE, l_left_margin_slew_array, - l_right_margin_slew_array, MAX_NUM_SLEW_RATES, - l_slew_rate_dq_dqs_nom_fc, count); - if (count >= MAX_NUM_SLEW_RATES) - { - FAPI_ERR("Driver Imp new input(%d) out of bounds, (>= %d)", count, - MAX_NUM_SLEW_RATES); - const uint8_t & COUNT_DATA = count; - FAPI_SET_HWP_ERROR(rc, RC_SLEW_RATE_SHMOO_INVALID_MARGIN_DATA); - return rc; - } - else - { - FAPI_INF("Restoring the nominal values!"); - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_DRV_IMP_DQ_DQS, &i_target_mba, - l_drv_imp_dq_dqs_nom); - if (rc) return rc; - rc = config_drv_imp(i_target_mba, i_port, - l_drv_imp_dq_dqs_nom[i_port]); - if (rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_SLEW_RATE_DQ_DQS, &i_target_mba, - l_slew_rate_dq_dqs_nom); - if (rc) return rc; - rc = config_slew_rate(i_target_mba, i_port, l_slew_type, - l_drv_imp_dq_dqs_nom[i_port], - l_slew_rate_dq_dqs_nom[i_port]); - if (rc) return rc; - } - FAPI_INF("Restoring mcbist setup attribute..."); - rc = reset_attribute(i_target_mba); - if (rc) return rc; - FAPI_INF("++++ Slew Rate shmoo function executed successfully ++++"); - } - return rc; -} - -//---------------------------------------------------------------------------------------------- -// Function name: wr_vref_shmoo() -// This function varies the DIMM vref using PC_VREF_DRV_CNTL register in 32 steps with vref sign -// Calls mcbist/write eye shmoo function and look for failure, incase of failure -// this function reports bad DQ pins matrix to put bad bits function -// Input param: const fapi::Target MBA, port = 0,1 -// Shmoo type: MCBIST, WR_EYE, RD_EYE, WR_DQS, RD_DQS -// Shmoo param: PARAM_NONE, DRV_IMP, SLEW_RATE, WR_VREF, RD_VREF, RCV_IMP -// Shmoo Mode: FEW_ADDR, QUARTER_ADDR, HALF_ADDR, FULL_ADDR -// i_pattern, i_test_type : Default = 0, mcbist lab function would use this arg -//---------------------------------------------------------------------------------------------- - -fapi::ReturnCode wr_vref_shmoo(const fapi::Target & i_target_mba, -uint8_t i_port, -shmoo_type_t i_shmoo_type_valid) -{ - fapi::ReturnCode rc; - uint32_t l_wr_dram_vref[MAX_PORT] = {0}; - uint32_t l_wr_dram_vref_nom[MAX_PORT] = {0}; - uint32_t l_wr_dram_vref_schmoo[MAX_PORT] = {0}; - uint32_t l_wr_dram_vref_nom_fc = 0; - uint32_t l_wr_dram_vref_in = 0; - i_shmoo_type_valid = MCBIST; - - uint8_t index = 0; - uint8_t count = 0; - //uint8_t shmoo_param_count = 0; - uint32_t l_left_margin = 0; - uint32_t l_right_margin = 0; - uint32_t l_left_margin_wr_vref_array[MAX_WR_VREF]= {0}; - uint32_t l_right_margin_wr_vref_array[MAX_WR_VREF]= {0}; - - //Read the write vref attributes - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WR_VREF, &i_target_mba, l_wr_dram_vref_nom); - if (rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WR_VREF_SCHMOO, &i_target_mba, l_wr_dram_vref_schmoo); - if (rc) return rc; - - FAPI_INF("+++++++++++++++++++++++++++++++++++++++++++++ Patch - Preet - WR_VREF - Check Sanity only at 500 +++++++++++++++++++++++++++"); - rc = delay_shmoo(i_target_mba, i_port, i_shmoo_type_valid, - &l_left_margin, &l_right_margin, - l_wr_dram_vref_in); - if(rc) return rc; - FAPI_INF(" Setup and Sanity - Check disabled from now on..... Continuing ....."); - rc = set_attribute(i_target_mba); - if (rc) return rc; - - - - i_shmoo_type_valid = WR_EYE; - - FAPI_INF("+++++++++++++++++WRITE DRAM VREF Shmoo Attributes Values+++++++++++++++"); - FAPI_INF("DRAM_WR_VREF[0] = %d , DRAM_WR_VREF[1] = %d on %s", - l_wr_dram_vref_nom[0], - l_wr_dram_vref_nom[1], - i_target_mba.toEcmdString()); - FAPI_INF("DRAM_WR_VREF_SCHMOO[0] = [%x],DRAM_WR_VREF_SCHMOO[1] = [%x] on %s", - l_wr_dram_vref_schmoo[0], - l_wr_dram_vref_schmoo[1], - i_target_mba.toEcmdString()); - FAPI_INF("+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++"); - - - if (l_wr_dram_vref_schmoo[i_port] == 0) - { - FAPI_INF("FAST Shmoo Mode: This function will not change any Write DRAM VREF settings"); - } - else - { - for (index = 0; index < MAX_WR_VREF; index += 1) - { - if (l_wr_dram_vref_schmoo[i_port] & MASK) - { - FAPI_INF("Current Vref multiplier value is %d", - wr_vref_array[index]); - l_wr_dram_vref[i_port] = wr_vref_array[index]; - rc = config_wr_dram_vref(i_target_mba, i_port, - l_wr_dram_vref[i_port]); - if (rc) return rc; - l_wr_dram_vref_in = l_wr_dram_vref[i_port]; - //FAPI_INF(" Calling Shmoo for finding Timing Margin:"); - - rc = delay_shmoo(i_target_mba, i_port, i_shmoo_type_valid, - &l_left_margin, &l_right_margin, - l_wr_dram_vref_in); - if (rc) return rc; - l_left_margin_wr_vref_array[index] = l_left_margin; - l_right_margin_wr_vref_array[index] = l_right_margin; - - FAPI_INF("Wr Vref = %d ; Min Setup time = %d; Min Hold time = %d", - wr_vref_array[index], - l_left_margin_wr_vref_array[index], - l_right_margin_wr_vref_array[index]); - } - else - { - l_left_margin_wr_vref_array[index] = 0; - l_right_margin_wr_vref_array[index] = 0; - } - l_wr_dram_vref_schmoo[i_port] = (l_wr_dram_vref_schmoo[i_port] >> 1); - //FAPI_INF("Wr Vref = %d ; Min Setup time = %d; Min Hold time = %d", wr_vref_array[index],l_left_margin_wr_vref_array[index], l_right_margin_wr_vref_array[index]); - //FAPI_INF("Configuring Vref registers_2:, index %d , max value %d, schmoo %x mask %d ", index, MAX_WR_VREF, l_wr_dram_vref_schmoo[i_port], MASK); - } - l_wr_dram_vref_nom_fc = l_wr_dram_vref_nom[i_port]; - find_best_margin(WR_VREF, l_left_margin_wr_vref_array, - l_right_margin_wr_vref_array, MAX_WR_VREF, - l_wr_dram_vref_nom_fc, count); - if (count >= MAX_WR_VREF) - { - FAPI_ERR("Write dram vref input(%d) out of bounds, (>= %d)", count, - MAX_WR_VREF); - const uint8_t & COUNT_DATA = count; - FAPI_SET_HWP_ERROR(rc, RC_WR_VREF_SHMOO_INVALID_MARGIN_DATA); - return rc; - } - else - { - // FAPI_INF("Nominal value will not be changed!- Restoring the original values!"); - FAPI_INF(" Restoring the nominal values!"); - rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_WR_VREF, &i_target_mba, - l_wr_dram_vref_nom); - if (rc) return rc; - rc = config_wr_dram_vref(i_target_mba, i_port, - l_wr_dram_vref_nom[i_port]); - if (rc) return rc; - } - FAPI_INF("Restoring mcbist setup attribute..."); - rc = reset_attribute(i_target_mba); - if (rc) return rc; - FAPI_INF("++++ Write DRAM Vref Shmoo function executed successfully ++++"); - } - return rc; -} - -//////////////////////////////////////////////wr_vref schmoo for ddr4 //////////////////////////////////////////////////////////// -fapi::ReturnCode wr_vref_shmoo_ddr4(const fapi::Target & i_target_mba) -{ - fapi::ReturnCode rc; - uint8_t max_port = 2; - uint8_t max_ddr4_vrefs1 = 52; - shmoo_type_t i_shmoo_type_valid = MCBIST; // Hard coded - Temporary - ecmdDataBufferBase l_data_buffer_64(64); - uint32_t l_left_margin = 0; - uint32_t l_right_margin = 0; - uint8_t l_attr_eff_dimm_type_u8 = 0; - uint8_t vrefdq_train_range[2][2][4]; - uint8_t num_ranks_per_dimm[2][2]; - uint8_t l_MAX_RANKS[2]; - uint32_t rc_num = 0; - uint8_t l_SCHMOO_NIBBLES=20; - uint8_t base_percent = 60; - - float index_mul_print = 0.65; - uint8_t l_attr_schmoo_test_type_u8 = 1; - float vref_val_print = 0; - rc = FAPI_ATTR_GET(ATTR_EFF_CUSTOM_DIMM, &i_target_mba, l_attr_eff_dimm_type_u8); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target_mba, num_ranks_per_dimm); if(rc) return rc; - rc = FAPI_ATTR_GET( ATTR_VREF_DQ_TRAIN_RANGE, &i_target_mba, vrefdq_train_range);if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_SCHMOO_TEST_VALID, &i_target_mba, l_attr_schmoo_test_type_u8); if(rc) return rc; - if(vrefdq_train_range[0][0][0] == 1) - { - base_percent = 45; - } - - l_MAX_RANKS[0]=num_ranks_per_dimm[0][0]+num_ranks_per_dimm[0][1]; - l_MAX_RANKS[1]=num_ranks_per_dimm[1][0]+num_ranks_per_dimm[1][1]; - FAPI_INF("\n ** l_max_rank 0 = %d",l_MAX_RANKS[0]); - if ( l_attr_eff_dimm_type_u8 == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES ) - { - l_SCHMOO_NIBBLES=20; - } - else - { - l_SCHMOO_NIBBLES=18; - } - FAPI_INF(" +++ l_SCHMOO_NIBBLES = %d +++ ",l_SCHMOO_NIBBLES); - ///// ddr4 vref ////// - fapi::Target l_target_centaur=i_target_mba; - - uint8_t vrefdq_train_value[2][2][4]; - uint8_t vrefdq_train_enable[2][2][4]; - //uint32_t best_margin[2][8][20]; - //uint32_t best_vref[50][2][8][20]; - //uint32_t best_vref_nibble[2][8][20]; - uint32_t vref_val=0; - uint32_t pda_nibble_table[2][2][16][2]; - uint8_t i=0; - uint8_t j=0; - uint8_t k=0; - uint8_t a=0; - uint8_t c=0; - uint8_t l_ranks = 0; - uint8_t l_vref_num = 0; - uint8_t i_port=0; - - FAPI_INF("+++++++++++++++++++++++++++++++++++++++++++++ Patch - WR_VREF - Check Sanity only at 500 ddr4 +++++++++++++++++++++++++++"); - rc = delay_shmoo_ddr4(i_target_mba, i_port, i_shmoo_type_valid, - &l_left_margin, &l_right_margin, - vref_val,pda_nibble_table); - - if(rc) return rc; - FAPI_INF(" Setup and Sanity - Check disabled from now on..... Continuing ....."); - rc = set_attribute(i_target_mba); - if (rc) return rc; - - - - i_shmoo_type_valid = WR_EYE; - l_attr_schmoo_test_type_u8 = 2; - rc = FAPI_ATTR_SET(ATTR_EFF_SCHMOO_TEST_VALID, &i_target_mba, l_attr_schmoo_test_type_u8); if(rc) return rc; - //Initialize all to zero - -for(l_vref_num=0; l_vref_num < max_ddr4_vrefs1; l_vref_num++){ - vref_val = l_vref_num; - vref_val_print = base_percent + (l_vref_num * index_mul_print); - - rc = fapiGetScom(i_target_mba,0x03010432,l_data_buffer_64); if(rc) return rc; - rc_num = rc_num | l_data_buffer_64.clearBit(0); if(rc_num) return rc; - rc = fapiPutScom(i_target_mba,0x03010432,l_data_buffer_64); if(rc) return rc; - //system("putscom cen.mba 03010432 0 1 0 -ib -all"); - FAPI_INF("\n After Clearing Refresh"); - for(i=0;i< max_port;i++){ - for(j=0;j<2;j++){ - for(k=0;k<4;k++){ - - vrefdq_train_enable[i][j][k]=0x00; - - } - } - } - - rc = FAPI_ATTR_SET( ATTR_VREF_DQ_TRAIN_RANGE, &i_target_mba, vrefdq_train_range);if(rc) return rc; - rc = FAPI_ATTR_SET( ATTR_VREF_DQ_TRAIN_ENABLE, &i_target_mba, vrefdq_train_enable);if(rc) return rc; - rc = mss_mrs6_DDR4(l_target_centaur); - if(rc) - { - //FAPI_ERR(" mrs_load Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator()); - return rc; - } - - - - for(a=0;a < max_port;a++){ - for(l_ranks=0;l_ranks < l_MAX_RANKS[0];l_ranks++){ - for(c=0;c<4;c++){ - - vrefdq_train_value[a][l_ranks][c]=vref_val; - - } - } - } - - rc = FAPI_ATTR_SET( ATTR_VREF_DQ_TRAIN_VALUE, &i_target_mba, vrefdq_train_value); - - - rc = mss_mrs6_DDR4(l_target_centaur); - if(rc) - { - //FAPI_ERR(" mrs_load Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator()); - return rc; - } - - FAPI_INF("The Vref value is %d .... The percent voltage bump = %f ",vref_val,vref_val_print); - - for(i=0;i< max_port;i++){ - for(j=0;j<l_MAX_RANKS[0];j++){ - for(k=0;k<4;k++){ - - vrefdq_train_enable[i][j][k]=0x01; - - } - } - } - rc = FAPI_ATTR_SET( ATTR_VREF_DQ_TRAIN_ENABLE, &i_target_mba, vrefdq_train_enable);if(rc) return rc; - rc = mss_mrs6_DDR4(l_target_centaur); - if(rc) - { - //FAPI_ERR(" mrs_load Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator()); - return rc; - } - - rc = fapiGetScom(i_target_mba,0x03010432,l_data_buffer_64); if(rc) return rc; - rc_num = rc_num | l_data_buffer_64.setBit(0); if(rc_num) return rc; - rc = fapiPutScom(i_target_mba,0x03010432,l_data_buffer_64); if(rc) return rc; - - //system("putscom cen.mba 03010432 0 1 1 -ib -all"); - - rc = delay_shmoo_ddr4(i_target_mba, i_port, i_shmoo_type_valid, - &l_left_margin, &l_right_margin, - vref_val,pda_nibble_table); - if (rc) return rc; - - FAPI_INF("Wr Vref = %f ; Min Setup time = %d; Min Hold time = %d", - vref_val_print, - l_left_margin, - l_right_margin); - - //vref_val=vref_val+1; - } - - - - - //Read the write vref attributes - - - - return rc; -} - - -fapi::ReturnCode wr_vref_shmoo_ddr4_bin(const fapi::Target & i_target_mba) -{ - fapi::ReturnCode rc; - uint8_t MAX_PORT = 2; - uint8_t max_ddr4_vrefs1 = 50; - shmoo_type_t i_shmoo_type_valid = MCBIST; - ecmdDataBufferBase l_data_buffer_64(64); - ecmdDataBufferBase refresh_reg(64); - uint32_t l_left_margin = 0; - uint32_t l_right_margin = 0; - uint8_t l_attr_eff_dimm_type_u8 = 0; - uint8_t vrefdq_train_range[2][2][4]; - uint8_t num_ranks_per_dimm[2][2]; - uint8_t l_MAX_RANKS[2]; - uint32_t rc_num = 0; - uint8_t l_SCHMOO_NIBBLES=20; - uint8_t base_percent = 60; - uint32_t pda_nibble_table[2][2][16][2]; - uint32_t best_pda_nibble_table[2][2][16][2]; - float index_mul_print = 0.65; - uint8_t l_attr_schmoo_test_type_u8 = 1; - float vref_val_print = 0; - rc = FAPI_ATTR_GET(ATTR_EFF_CUSTOM_DIMM, &i_target_mba, l_attr_eff_dimm_type_u8); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target_mba, num_ranks_per_dimm); if(rc) return rc; - rc = FAPI_ATTR_GET( ATTR_VREF_DQ_TRAIN_RANGE, &i_target_mba, vrefdq_train_range);if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_SCHMOO_TEST_VALID, &i_target_mba, l_attr_schmoo_test_type_u8); if(rc) return rc; - if(vrefdq_train_range[0][0][0] == 1) - { - base_percent = 45; - } - - l_MAX_RANKS[0]=num_ranks_per_dimm[0][0]+num_ranks_per_dimm[0][1]; - l_MAX_RANKS[1]=num_ranks_per_dimm[1][0]+num_ranks_per_dimm[1][1]; - FAPI_INF("\n ** l_max_rank 0 = %d Base Percent = %d",l_MAX_RANKS[0],base_percent); - if ( l_attr_eff_dimm_type_u8 == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES ) - { - l_SCHMOO_NIBBLES=20; - }else{ - l_SCHMOO_NIBBLES=18; - } - ///// ddr4 vref ////// - fapi::Target l_target_centaur=i_target_mba; - uint8_t vrefdq_train_value[2][2][4]; - uint8_t vrefdq_train_enable[2][2][4]; - uint32_t best_vref[50][1]; - uint32_t vref_val=0; - uint8_t index = 0; - uint8_t i=0; - uint8_t j=0; - uint8_t k=0; - uint8_t a=0; - uint8_t c=0; - uint8_t l_ranks = 0; - uint8_t i_port=0; - uint8_t l_vref_mid = 0; - vector<PDA_MRS_Storage> pda; - pda.clear(); - - FAPI_INF("+++++++++++++++++++++++++++++++++++++++++++++ Patch - Preet - WR_VREF - Check Sanity only at 500 ddr4 +++++++++++++++++++++++++++"); - rc = delay_shmoo_ddr4_pda(i_target_mba, i_port, i_shmoo_type_valid, - &l_left_margin, &l_right_margin, - vref_val,pda_nibble_table); - - if(rc) return rc; - FAPI_INF(" Setup and Sanity - Check disabled from now on..... Continuing ....."); - rc = set_attribute(i_target_mba); - if (rc) return rc; - i_shmoo_type_valid = WR_EYE; - l_attr_schmoo_test_type_u8 = 2; - rc = FAPI_ATTR_SET(ATTR_EFF_SCHMOO_TEST_VALID, &i_target_mba, l_attr_schmoo_test_type_u8); if(rc) return rc; - //Initialize all to zero - for(index = 0; index < max_ddr4_vrefs1;index++) - { - best_vref[index][0] = 0; - } - - //Initialise All to Zero - for(int k=0;k< MAX_PORT;k++) // port - { - for(int j=0;j < l_MAX_RANKS[0];j++) //Rank - { - for(int i=0;i<16;i++) //Nibble - { - pda_nibble_table[k][j][i][0] = 0; // Index 0 Are V-refs - pda_nibble_table[k][j][i][1] = 0; // Index 1 are Total Margin Values - best_pda_nibble_table[k][j][i][0] = 0; // Index 0 Are V-refs - best_pda_nibble_table[k][j][i][1] = 0; // Index 1 are Total Margin Values - } - } - } - uint8_t imax = 39; - uint8_t imin = 13; - uint8_t last_known_vref = 0; - uint8_t l_loop_count = 0; - //for(l_vref_num=0; l_vref_num < max_ddr4_vrefs1; l_vref_num++){ - //Sweep Right - while(imax >= imin){ - - if(l_loop_count==0) - l_vref_mid = imin; - else - l_vref_mid = (imax+imin)/2; - - vref_val = l_vref_mid; - vref_val_print = base_percent + (l_vref_mid * index_mul_print); - - rc = fapiGetScom(i_target_mba,0x03010432,l_data_buffer_64); if(rc) return rc; - rc_num = rc_num | l_data_buffer_64.clearBit(0); if(rc_num) return rc; - rc = fapiPutScom(i_target_mba,0x03010432,l_data_buffer_64); if(rc) return rc; - - //system("putscom cen.mba 03010432 0 1 0 -ib -all"); - FAPI_INF("\n After Clearing Refresh"); - - for(i=0;i<MAX_PORT;i++){ - for(j=0;j<l_MAX_RANKS[0];j++){ - for(k=0;k<4;k++){ - - vrefdq_train_enable[i][j][k]=0x00; - - } - } - } - - rc = FAPI_ATTR_SET( ATTR_VREF_DQ_TRAIN_RANGE, &i_target_mba, vrefdq_train_range);if(rc) return rc; - rc = FAPI_ATTR_SET( ATTR_VREF_DQ_TRAIN_ENABLE, &i_target_mba, vrefdq_train_enable);if(rc) return rc; - rc = mss_mrs6_DDR4(l_target_centaur); - if(rc) - { - //FAPI_ERR(" mrs_load Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator()); - return rc; - } - - for(a=0;a < MAX_PORT;a++) //Port - { - for(l_ranks=0;l_ranks < l_MAX_RANKS[0];l_ranks++){ - for(c=0;c < 4;c++){ - - vrefdq_train_value[a][l_ranks][c]=vref_val; - - } - } - } - - rc = FAPI_ATTR_SET( ATTR_VREF_DQ_TRAIN_VALUE, &i_target_mba, vrefdq_train_value); if(rc) return rc; - - - rc = mss_mrs6_DDR4(l_target_centaur); - if(rc) - { - //FAPI_ERR(" mrs_load Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator()); - return rc; - } - - FAPI_INF("The Vref value is %d .... The percent voltage bump = %f ",vref_val,vref_val_print); - - for(i=0;i < MAX_PORT;i++){ - for(j=0;j<l_MAX_RANKS[0];j++){ - for(k=0;k<4;k++){ - - vrefdq_train_enable[i][j][k]=0x01; - - } - } - } - rc = FAPI_ATTR_SET( ATTR_VREF_DQ_TRAIN_ENABLE, &i_target_mba, vrefdq_train_enable);if(rc) return rc; - rc = mss_mrs6_DDR4(l_target_centaur); - if(rc) - { - //FAPI_ERR(" mrs_load Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator()); - return rc; - } - - rc = fapiGetScom(i_target_mba,0x03010432,l_data_buffer_64); if(rc) return rc; - rc_num = rc_num | l_data_buffer_64.setBit(0); if(rc_num) return rc; - rc = fapiPutScom(i_target_mba,0x03010432,l_data_buffer_64); if(rc) return rc; - //system("putscom cen.mba 03010432 0 1 1 -ib -all"); - - rc = delay_shmoo_ddr4_pda(i_target_mba, i_port, i_shmoo_type_valid, - &l_left_margin, &l_right_margin, - vref_val,pda_nibble_table); - if (rc) return rc; - - FAPI_INF("Wr Vref = %f ; Min Setup time = %d; Min Hold time = %d", - vref_val_print, - l_left_margin, - l_right_margin); - best_vref[vref_val][0] = l_right_margin+l_left_margin; - - //Get proper Criteria HERE - if(best_vref[vref_val][0] > best_vref[last_known_vref][0]) - { - last_known_vref = vref_val; - //if(l_loop_count !=0) - imin = l_vref_mid+1; - } - //imax = l_vref_mid + (imax - l_vref_mid)/2; - else - { - if(l_loop_count ==0) - { FAPI_INF("Safety Fuse-1 !! "); - imin = l_vref_mid+1; - } - else - imax = ((l_vref_mid + imax )/2)-2; - } - l_loop_count ++; - for(int i_port=0;i_port < MAX_PORT;i_port++){ - for(int i_rank=0;i_rank < l_MAX_RANKS[0];i_rank++){ - for(int i_nibble=0;i_nibble < l_SCHMOO_NIBBLES;i_nibble++){ - if (best_pda_nibble_table[i_port][i_rank][i_nibble][1] < pda_nibble_table[i_port][i_rank][i_nibble][1]) - { - best_pda_nibble_table[i_port][i_rank][i_nibble][1] = pda_nibble_table[i_port][i_rank][i_nibble][1]; - best_pda_nibble_table[i_port][i_rank][i_nibble][0] = vref_val; - } - }}} - - } - - //imax = max_ddr4_vrefs1/2; - //imin = 0; - //Sweep Left - /*while(imax >= imin){ - -l_vref_mid = (imax+imin)/2; -vref_val = l_vref_mid; -vref_val_print = base_percent + (l_vref_mid * index_mul_print); -system("putscom cen.mba 03010432 0 1 0 -ib -all"); -FAPI_INF("\n After Clearing Refresh"); - - for(i=0;i<2;i++){ - for(j=0;j<l_MAX_RANKS[0];j++){ - for(k=0;k<4;k++){ - - vrefdq_train_enable[i][j][k]=0x00; - - } - } - } - - rc = FAPI_ATTR_SET( ATTR_VREF_DQ_TRAIN_RANGE, &i_target_mba, vrefdq_train_range);if(rc) return rc; - rc = FAPI_ATTR_SET( ATTR_VREF_DQ_TRAIN_ENABLE, &i_target_mba, vrefdq_train_enable);if(rc) return rc; - rc = mss_mrs6_DDR4(l_target_centaur); - if(rc) - { - //FAPI_ERR(" mrs_load Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator()); - return rc; - } - - for(a=0;a<2;a++){ - for(l_ranks=0;l_ranks < l_MAX_RANKS[0];l_ranks++){ - for(c=0;c<4;c++){ - - vrefdq_train_value[a][l_ranks][c]=vref_val; - - } - } - } - - rc = FAPI_ATTR_SET( ATTR_VREF_DQ_TRAIN_VALUE, &i_target_mba, vrefdq_train_value); - - - rc = mss_mrs6_DDR4(l_target_centaur); - if(rc) - { - //FAPI_ERR(" mrs_load Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator()); - return rc; - } - - FAPI_INF("The Vref value is %d .... The percent voltage bump = %f ",vref_val,vref_val_print); - - for(i=0;i<2;i++){ - for(j=0;j<l_MAX_RANKS[0];j++){ - for(k=0;k<4;k++){ - - vrefdq_train_enable[i][j][k]=0x01; - - } - } - } - rc = FAPI_ATTR_SET( ATTR_VREF_DQ_TRAIN_ENABLE, &i_target_mba, vrefdq_train_enable);if(rc) return rc; - rc = mss_mrs6_DDR4(l_target_centaur); - if(rc) - { - //FAPI_ERR(" mrs_load Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator()); - return rc; - } - - system("putscom cen.mba 03010432 0 1 1 -ib -all"); - - rc = delay_shmoo_ddr4(i_target_mba, i_port, i_shmoo_type_valid, - &l_left_margin, &l_right_margin, - vref_val); - if (rc) return rc; - - FAPI_INF("Wr Vref = %f ; Min Setup time = %d; Min Hold time = %d", - vref_val_print, - l_left_margin, - l_right_margin); - best_vref[vref_val][0] = l_right_margin+l_left_margin; - - //Get proper Criteria HERE - if(best_vref[vref_val][0] > best_vref[last_known_vref][0]) - { - last_known_vref = vref_val; - imin = l_vref_mid+1; - } - //last_known_vref = vref_val; - //imax = l_vref_mid + (imax - l_vref_mid)/2; - else - imax = (l_vref_mid + imax )/2; - } - - */ - vref_val_print = base_percent + (last_known_vref * index_mul_print); - FAPI_INF("Best V-Ref - %f ; Total Window = %d", - vref_val_print,best_vref[last_known_vref][0]); - // What do we do Once we know best V-Ref - for(a=0;a<50;a++) - { - vref_val_print = base_percent + (a * index_mul_print); - FAPI_INF("\n V-Ref - %f ; Total Window = %d",vref_val_print,best_vref[a][0]); - } - rc = fapiGetScom( i_target_mba, 0x03010432, refresh_reg); if(rc) return rc; - refresh_reg.clearBit(0); - fapiPutScom( i_target_mba, 0x03010432, refresh_reg);if(rc) return rc; - - /*for(int i_port=0;i_port < 2;i_port++){ - for(int i_rank=0;i_rank < 2;i_rank++){ - for(int i_nibble=0;i_nibble < 16;i_nibble++){ - FAPI_INF("\n Port %d Rank:%d Pda_Nibble: %d V-ref:%d Margin:%d",i_port,i_rank,i_nibble,best_pda_nibble_table[i_port][i_rank][i_nibble][0],best_pda_nibble_table[i_port][i_rank][i_nibble][1]); - pda.push_back(PDA_MRS_Storage(best_pda_nibble_table[i_port][i_rank][i_nibble][0],ATTR_VREF_DQ_TRAIN_VALUE,i_nibble,i_rank,0,i_port)); -} -FAPI_INF("FINAL %s PDA STRING: %d %s",i_target_mba.toEcmdString(),pda.size()-1,pda[pda.size()-1].c_str()); -}} - -rc = fapiGetScom( i_target_mba, 0x03010432, refresh_reg); - refresh_reg.setBit(0); - fapiPutScom( i_target_mba, 0x03010432, refresh_reg); - - - //Read the write vref attributes - - - rc = mss_ddr4_run_pda((fapi::Target &)i_target_mba,pda); -*/ - return rc; -} - - -//---------------------------------------------------------------------------------------------- -// Function name: rd_vref_shmoo() -// Description: This function varies the Centaur IO vref in 16 steps -// Calls write eye shmoo function -// Input param: const fapi::Target MBA, port = 0,1 -// Shmoo type: MCBIST, WR_EYE, RD_EYE, WR_DQS, RD_DQS -// Shmoo param: PARAM_NONE, DRV_IMP, SLEW_RATE, WR_VREF, RD_VREF, RCV_IMP -// Shmoo Mode: FEW_ADDR, QUARTER_ADDR, HALF_ADDR, FULL_ADDR -// i_pattern, i_test_type : Default = 0, mcbist lab function would use this arg -//---------------------------------------------------------------------------------------------- - -fapi::ReturnCode rd_vref_shmoo(const fapi::Target & i_target_mba, -uint8_t i_port, -shmoo_type_t i_shmoo_type_valid) -{ - fapi::ReturnCode rc; - uint32_t l_rd_cen_vref[MAX_PORT] = {0}; - uint32_t l_rd_cen_vref_nom[MAX_PORT] = {0}; - uint32_t l_rd_cen_vref_nom_fc = 0; - uint32_t l_rd_cen_vref_in = 0; - uint32_t l_rd_cen_vref_schmoo[MAX_PORT] = {0}; - uint8_t index = 0; - uint8_t count = 0; - //uint8_t shmoo_param_count = 0; - //i_shmoo_type_valid = RD_EYE; // Hard coded - Temporary - - uint32_t l_left_margin = 0; - uint32_t l_right_margin = 0; - uint32_t l_left_margin_rd_vref_array[MAX_RD_VREF] = {0}; - uint32_t l_right_margin_rd_vref_array[MAX_RD_VREF] = {0}; - - rc = FAPI_ATTR_GET(ATTR_EFF_CEN_RD_VREF, &i_target_mba, l_rd_cen_vref_nom); - if (rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_CEN_RD_VREF_SCHMOO, &i_target_mba, l_rd_cen_vref_schmoo); - if (rc) return rc; - i_shmoo_type_valid = MCBIST; - - - FAPI_INF("+++++++++++++++++++++++++++++++++++++++++++++ Patch - Preet - RD_VREF - Check Sanity only at 500000 +++++++++++++++++++++++++++"); - rc = delay_shmoo(i_target_mba, i_port, i_shmoo_type_valid, - &l_left_margin, &l_right_margin, - l_rd_cen_vref_in); - if(rc) return rc; - FAPI_INF(" Setup and Sanity - Check disabled from now on..... Continuing ....."); - rc = set_attribute(i_target_mba); - if (rc) return rc; - - i_shmoo_type_valid = RD_EYE; - FAPI_INF("+++++++++++++++++CENTAUR VREF Read Shmoo Attributes values+++++++++++++++"); - FAPI_INF("CEN_RD_VREF[0] = %d CEN_RD_VREF[1] = %d on %s", - l_rd_cen_vref_nom[0], - l_rd_cen_vref_nom[1], - i_target_mba.toEcmdString()); - FAPI_INF("CEN_RD_VREF_SCHMOO[0] = [%x], CEN_RD_VREF_SCHMOO[1] = [%x] on %s", - l_rd_cen_vref_schmoo[0], - l_rd_cen_vref_schmoo[1], - i_target_mba.toEcmdString()); - FAPI_INF("+++++++++++++++++++++++++++++++++++++++++++++ Patch - Preet - RD_VREF +++++++++++++++++++++++++++"); - - if (l_rd_cen_vref_schmoo[i_port] == 0) - { - FAPI_INF("FAST Shmoo Mode: This function will not change any Read Centaur VREF settings"); - } - else - { - for (index = 0; index < MAX_RD_VREF; index += 1) - { - if ((l_rd_cen_vref_schmoo[i_port] & MASK) == 1) - { - l_rd_cen_vref[i_port] = rd_cen_vref_array[index]; - FAPI_INF("Current Read Vref Multiplier value is %d", - rd_cen_vref_array[index]); - FAPI_INF("Configuring Read Vref Registers:"); - rc = config_rd_cen_vref(i_target_mba, i_port, - l_rd_cen_vref[i_port]); - if (rc) return rc; - l_rd_cen_vref_in = l_rd_cen_vref[i_port]; - //FAPI_INF(" Calling Shmoo function to find out Timing Margin:"); - - rc = delay_shmoo(i_target_mba, i_port, i_shmoo_type_valid, - &l_left_margin, &l_right_margin, - l_rd_cen_vref_in); - if (rc) return rc; - l_left_margin_rd_vref_array[index] = l_left_margin; - l_right_margin_rd_vref_array[index] = l_right_margin; - - FAPI_INF("Read Vref = %d ; Min Setup time = %d; Min Hold time = %d", - rd_cen_vref_array[index], - l_left_margin_rd_vref_array[index], - l_right_margin_rd_vref_array[index]); - } - else - { - l_left_margin_rd_vref_array[index] = 0; - l_right_margin_rd_vref_array[index] = 0; - } - l_rd_cen_vref_schmoo[i_port] = (l_rd_cen_vref_schmoo[i_port] >> 1); - /* FAPI_INF("Read Vref = %d ; Min Setup time = %d; Min Hold time = %d", rd_cen_vref_array[index],l_left_margin_rd_vref_array[index], l_right_margin_rd_vref_array[index]); */ - } - l_rd_cen_vref_nom_fc = l_rd_cen_vref_nom[i_port]; - find_best_margin(RD_VREF, l_left_margin_rd_vref_array, - l_right_margin_rd_vref_array, MAX_RD_VREF, - l_rd_cen_vref_nom_fc, count); - if (count >= MAX_RD_VREF) - { - FAPI_ERR("Read vref new input(%d) out of bounds, (>= %d)", count, - MAX_RD_VREF); - const uint8_t & COUNT_DATA = count; - FAPI_SET_HWP_ERROR(rc, RC_RD_VREF_SHMOO_INVALID_MARGIN_DATA); - return rc; - } - else - { - // FAPI_INF("Nominal value will not be changed!- Restoring the original values!"); - FAPI_INF("Restoring Nominal values!"); - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_RD_VREF, &i_target_mba, - l_rd_cen_vref_nom); - if (rc) return rc; - rc = config_rd_cen_vref(i_target_mba, i_port, - l_rd_cen_vref_nom[i_port]); - if (rc) return rc; - } - - FAPI_INF("++++ Centaur Read Vref Shmoo function executed successfully ++++"); - } - FAPI_INF("Restoring mcbist setup attribute..."); - rc = reset_attribute(i_target_mba);if (rc) return rc; - return rc; -} - -//------------------------------------------------------------------------------ -// Function name: rcv_imp_shmoo() -// Receiver impedance shmoo function varies 9 values -// Input param: const fapi::Target MBA, port = 0,1 -// Shmoo type: MCBIST, WR_EYE, RD_EYE, WR_DQS, RD_DQS -// Shmoo param: PARAM_NONE, DRV_IMP, SLEW_RATE, WR_VREF, RD_VREF, RCV_IMP -// Shmoo Mode: FEW_ADDR, QUARTER_ADDR, HALF_ADDR, FULL_ADDR -// i_pattern, i_test_type : Default = 0, mcbist lab function would use this arg -//------------------------------------------------------------------------------ -fapi::ReturnCode rcv_imp_shmoo(const fapi::Target & i_target_mba, -uint8_t i_port, -shmoo_type_t i_shmoo_type_valid) -{ - fapi::ReturnCode rc; - uint8_t l_rcv_imp_dq_dqs[MAX_PORT] = {0}; - uint8_t l_rcv_imp_dq_dqs_nom[MAX_PORT] = {0}; - uint8_t l_rcv_imp_dq_dqs_nom_fc = 0; - uint8_t l_rcv_imp_dq_dqs_in = 0; - uint32_t l_rcv_imp_dq_dqs_schmoo[MAX_PORT] = {0}; - uint8_t index = 0; - uint8_t count = 0; - uint8_t shmoo_param_count = 0; - i_shmoo_type_valid = RD_EYE; //Hard coded since no other shmoo is applicable - Temporary - - uint32_t l_left_margin = 0; - uint32_t l_right_margin = 0; - uint32_t l_left_margin_rcv_imp_array[MAX_RCV_IMP] = {0}; - uint32_t l_right_margin_rcv_imp_array[MAX_RCV_IMP] = {0}; - - rc = FAPI_ATTR_GET(ATTR_EFF_CEN_RCV_IMP_DQ_DQS, &i_target_mba, l_rcv_imp_dq_dqs_nom); - if (rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_CEN_RCV_IMP_DQ_DQS_SCHMOO, &i_target_mba, l_rcv_imp_dq_dqs_schmoo); - if (rc) return rc; - - FAPI_INF("+++++++++++++++++RECIVER IMP Read Shmoo Attributes values+++++++++++++++"); - FAPI_INF("CEN_RCV_IMP_DQ_DQS[0] = %d , CEN_RCV_IMP_DQ_DQS[1] = %d on %s", - l_rcv_imp_dq_dqs_nom[0], - l_rcv_imp_dq_dqs_nom[1], - i_target_mba.toEcmdString()); - FAPI_INF("CEN_RCV_IMP_DQ_DQS_SCHMOO[0] = [%d], CEN_RCV_IMP_DQ_DQS_SCHMOO[1] = [%d], on %s", - l_rcv_imp_dq_dqs_schmoo[0], - l_rcv_imp_dq_dqs_schmoo[1], - i_target_mba.toEcmdString()); - FAPI_INF("+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++"); - - if (l_rcv_imp_dq_dqs_schmoo[i_port] == 0) - { - FAPI_INF("FAST Shmoo Mode: This function will not change any Write DRAM VREF settings"); - } - else - { - for (index = 0; index < MAX_RCV_IMP; index += 1) - { - if ((l_rcv_imp_dq_dqs_schmoo[i_port] & MASK) == 1) - { - l_rcv_imp_dq_dqs[i_port] = rcv_imp_array[index]; - FAPI_INF("Current Receiver Impedance: %d Ohms ", - rcv_imp_array[index]); - FAPI_INF("Configuring Receiver impedance registers:"); - rc = config_rcv_imp(i_target_mba, i_port, - l_rcv_imp_dq_dqs[i_port]); - if (rc) return rc; - l_rcv_imp_dq_dqs_in = l_rcv_imp_dq_dqs[i_port]; - //FAPI_INF("Calling Shmoo function to find out timing margin:"); - if (shmoo_param_count) - { - rc = set_attribute(i_target_mba); - if (rc) return rc; - } - rc = delay_shmoo(i_target_mba, i_port, i_shmoo_type_valid, - &l_left_margin, &l_right_margin, - l_rcv_imp_dq_dqs_in); - if (rc) return rc; - l_left_margin_rcv_imp_array[index] = l_left_margin; - l_right_margin_rcv_imp_array[index] = l_right_margin; - shmoo_param_count++; - } - else - { - l_left_margin_rcv_imp_array[index] = 0; - l_right_margin_rcv_imp_array[index] = 0; - } - l_rcv_imp_dq_dqs_schmoo[i_port] = (l_rcv_imp_dq_dqs_schmoo[i_port] >> 1); - } - l_rcv_imp_dq_dqs_nom_fc = l_rcv_imp_dq_dqs_nom[i_port]; - find_best_margin(RCV_IMP, l_left_margin_rcv_imp_array, - l_right_margin_rcv_imp_array, MAX_RCV_IMP, - l_rcv_imp_dq_dqs_nom_fc, count); - if (count >= MAX_RCV_IMP) - { - FAPI_ERR("Receiver Imp new input(%d) out of bounds, (>= %d)", - count, MAX_RCV_IMP); - const uint8_t & COUNT_DATA = count; - FAPI_SET_HWP_ERROR(rc, RC_RCV_IMP_SHMOO_INVALID_MARGIN_DATA); - return rc; - } - else - { - // FAPI_INF("Nominal value will not be changed!- Restoring the original values!"); - FAPI_INF("Restoring the nominal values!"); - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_RCV_IMP_DQ_DQS, &i_target_mba, - l_rcv_imp_dq_dqs_nom); - if (rc) return rc; - rc = config_rcv_imp(i_target_mba, i_port, - l_rcv_imp_dq_dqs_nom[i_port]); - if (rc) return rc; - } - FAPI_INF("Restoring mcbist setup attribute..."); - rc = reset_attribute(i_target_mba); - if (rc) return rc; - FAPI_INF("++++ Receiver Impdeance Shmoo function executed successfully ++++"); - } - return rc; -} - -//------------------------------------------------------------------------------ -// Function name:delay_shmoo() -// Calls Delay shmoo function varies delay values of each dq and returns timing margin -// Input param: const fapi::Target MBA, port = 0,1 -// Shmoo type: MCBIST, WR_EYE, RD_EYE, WR_DQS, RD_DQS -// Shmoo Mode: FEW_ADDR, QUARTER_ADDR, HALF_ADDR, FULL_ADDR -// i_pattern, i_test_type : Default = 0, mcbist lab function would use this arg -// Output param: l_left_margin = Left Margin(Setup time), -// l_right_margin = Right Margin (Hold time) in ps -//------------------------------------------------------------------------------ - -fapi::ReturnCode delay_shmoo(const fapi::Target & i_target_mba, uint8_t i_port, -shmoo_type_t i_shmoo_type_valid, -uint32_t *o_left_margin, -uint32_t *o_right_margin, -uint32_t i_shmoo_param) -{ - fapi::ReturnCode rc; - //FAPI_INF(" Inside before the delay shmoo " ); - //Constructor CALL: generic_shmoo::generic_shmoo(uint8_t i_port, uint32_t shmoo_mask,shmoo_algorithm_t shmoo_algorithm) - //generic_shmoo mss_shmoo=generic_shmoo(i_port,2,SEQ_LIN); - generic_shmoo * l_pShmoo = new generic_shmoo(i_port,i_shmoo_type_valid,SEQ_LIN); - //generic_shmoo mss_shmoo=generic_shmoo(i_port,i_shmoo_type_valid,SEQ_LIN); - rc = l_pShmoo->run(i_target_mba, o_left_margin, o_right_margin,i_shmoo_param); - if(rc) - { - FAPI_ERR("Delay Schmoo Function is Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator()); - } - delete l_pShmoo; - return rc; -} - -//------------------------------------------------------------------------------ -// Function name:delay_shmoo() -// Calls Delay shmoo function varies delay values of each dq and returns timing margin -// Input param: const fapi::Target MBA, port = 0,1 -// Shmoo type: MCBIST, WR_EYE, RD_EYE, WR_DQS, RD_DQS -// Shmoo Mode: FEW_ADDR, QUARTER_ADDR, HALF_ADDR, FULL_ADDR -// i_pattern, i_test_type : Default = 0, mcbist lab function would use this arg -// Output param: l_left_margin = Left Margin(Setup time), -// l_right_margin = Right Margin (Hold time) in ps -//------------------------------------------------------------------------------ - -fapi::ReturnCode delay_shmoo_ddr4(const fapi::Target & i_target_mba, uint8_t i_port, -shmoo_type_t i_shmoo_type_valid, -uint32_t *o_left_margin, -uint32_t *o_right_margin, -uint32_t i_shmoo_param,uint32_t pda_nibble_table[2][2][16][2]) -{ - fapi::ReturnCode rc; - - generic_shmoo * l_pShmoo = new generic_shmoo(i_port,i_shmoo_type_valid,SEQ_LIN); - - rc = l_pShmoo->run(i_target_mba, o_left_margin, o_right_margin,i_shmoo_param); if (rc) return rc; - - - - delete l_pShmoo; - return rc; -} - -fapi::ReturnCode delay_shmoo_ddr4_pda(const fapi::Target & i_target_mba, uint8_t i_port, -shmoo_type_t i_shmoo_type_valid, -uint32_t *o_left_margin, -uint32_t *o_right_margin, -uint32_t i_shmoo_param,uint32_t pda_nibble_table[2][2][16][2]) -{ - fapi::ReturnCode rc; - - generic_shmoo * l_pShmoo = new generic_shmoo(i_port,i_shmoo_type_valid,SEQ_LIN); - - rc = l_pShmoo->run(i_target_mba, o_left_margin, o_right_margin,i_shmoo_param); if (rc) return rc; - - rc = l_pShmoo->get_nibble_pda(i_target_mba,pda_nibble_table); if (rc) return rc; - - delete l_pShmoo; - return rc; -} - -//------------------------------------------------------------------------------ -//Function name: set_attributes() -//Description: Sets the attribute used by all functions -//------------------------------------------------------------------------------ - -fapi::ReturnCode set_attribute(const fapi::Target & i_target_mba) -{ - fapi::ReturnCode rc; - uint8_t l_mcbist_setup_multiple_set = 1; //Hard coded it wont change - rc = FAPI_ATTR_SET(ATTR_SCHMOO_MULTIPLE_SETUP_CALL, &i_target_mba, l_mcbist_setup_multiple_set); - return rc; -} - -fapi::ReturnCode rd_vref_shmoo_ddr4(const fapi::Target & i_target_mba) -{ - fapi::ReturnCode rc; - shmoo_type_t i_shmoo_type_valid = MCBIST; // Hard coded - Temporary - ecmdDataBufferBase l_data_buffer_64(64); - ecmdDataBufferBase data_buffer(64); - uint32_t l_rd_cen_vref_schmoo[MAX_PORT] = {0}; - uint32_t l_left_margin = 0; - uint32_t l_right_margin = 0; - uint32_t l_rd_cen_vref_in = 0; - uint8_t l_attr_schmoo_test_type_u8 = 1; - rc = FAPI_ATTR_SET(ATTR_EFF_SCHMOO_TEST_VALID, &i_target_mba, l_attr_schmoo_test_type_u8); if(rc) return rc; - uint8_t i_port=0; - uint32_t diff_value = 1375; - uint32_t base = 70000; - uint32_t vref_value_print = 0; - uint32_t l_left_margin_rd_vref_array[16] = {0}; - uint32_t l_right_margin_rd_vref_array[16] = {0}; - uint32_t rc_num = 0; - uint8_t l_vref_num = 0; - - FAPI_INF("+++++++++++++++++++++++++++++++++++++++++++++ Patch - Preet - RD_VREF - Check Sanity only - DDR4 +++++++++++++++++++++++++++"); - rc = delay_shmoo(i_target_mba, i_port, i_shmoo_type_valid, - &l_left_margin, &l_right_margin, - l_rd_cen_vref_in); - if(rc) return rc; - FAPI_INF(" Setup and Sanity - Check disabled from now on..... Continuing ....."); - rc = set_attribute(i_target_mba); - if (rc) return rc; - - i_shmoo_type_valid = RD_EYE; - l_attr_schmoo_test_type_u8 = 4; - rc = FAPI_ATTR_SET(ATTR_EFF_SCHMOO_TEST_VALID, &i_target_mba, l_attr_schmoo_test_type_u8); if(rc) return rc; - //rc = FAPI_ATTR_GET(ATTR_EFF_CEN_RD_VREF, &i_target_mba, l_rd_cen_vref_nom);if (rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_CEN_RD_VREF_SCHMOO, &i_target_mba, l_rd_cen_vref_schmoo);if (rc) return rc; - - - FAPI_INF("CEN_RD_VREF_SCHMOO[0] = [%x], CEN_RD_VREF_SCHMOO[1] = [%x] on %s", - l_rd_cen_vref_schmoo[0], - l_rd_cen_vref_schmoo[1], - i_target_mba.toEcmdString()); - FAPI_INF("+++++++++++++++++++++++++++++++++++++++++++++ Patch - Preet - RD_VREF DDR4 +++++++++++++++++++++++++++"); - - //For DDR3 - DDR4 Range - if (l_rd_cen_vref_schmoo[i_port] == 1) - { - FAPI_INF("\n Testing Range - DDR3 to DDR4 - Vrefs"); - base = 50000; - } - else - { - FAPI_INF("\n Testing Range - DDR4 Range Only - Vrefs"); - - for(l_vref_num = 7; l_vref_num > 0 ; l_vref_num--) - { - l_rd_cen_vref_in = l_vref_num; - vref_value_print = base - (l_vref_num*diff_value); - FAPI_INF("Current Vref value is %d",vref_value_print); - FAPI_INF("Configuring Read Vref Registers:"); - rc = fapiGetScom(i_target_mba, - DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P0_0_0x800000060301143F, - data_buffer); if(rc) return rc; - rc_num = rc_num | data_buffer.insertFromRight(l_rd_cen_vref_in,56,4); - if (rc_num) - { - FAPI_ERR( "config_rd_vref: Error in setting up buffer "); - rc.setEcmdError(rc_num); - return rc; - } - rc_num = data_buffer.setBit(60); - if (rc_num) - { - FAPI_ERR( "config_rd_vref: Error in setting up buffer "); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P0_0_0x800000060301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P0_1_0x800004060301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P0_2_0x800008060301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P0_3_0x80000c060301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P0_4_0x800010060301143F, - data_buffer); if(rc) return rc; - rc = fapiGetScom(i_target_mba, - DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P1_0_0x800100060301143F, - data_buffer); if(rc) return rc; - rc_num = rc_num | data_buffer.insertFromRight(l_rd_cen_vref_in,56,4); - if (rc_num) - { - FAPI_ERR( "config_rd_vref: Error in setting up buffer "); - rc.setEcmdError(rc_num); - return rc; - } - rc_num = data_buffer.setBit(60); - if (rc_num) - { - FAPI_ERR( "config_rd_vref: Error in setting up buffer "); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P1_0_0x800100060301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P1_1_0x800104060301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P1_2_0x800108060301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P1_3_0x80010c060301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P1_4_0x800110060301143F, - data_buffer); if(rc) return rc; - - rc = delay_shmoo(i_target_mba, i_port, i_shmoo_type_valid,&l_left_margin, &l_right_margin,l_rd_cen_vref_in);if (rc) return rc; - l_left_margin_rd_vref_array[l_vref_num] = l_left_margin; - l_right_margin_rd_vref_array[l_vref_num] = l_right_margin; - - FAPI_INF("Read Vref = %d ; Min Setup time = %d; Min Hold time = %d",vref_value_print, l_left_margin_rd_vref_array[l_vref_num],l_right_margin_rd_vref_array[l_vref_num]); - } - // For base + values - - for(l_vref_num = 0; l_vref_num < 9; l_vref_num++) - { - - l_rd_cen_vref_in = l_vref_num; - vref_value_print = base + (l_vref_num*diff_value); - FAPI_INF("Current Vref value is %d",vref_value_print); - FAPI_INF("Configuring Read Vref Registers:"); - rc = fapiGetScom(i_target_mba, - DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P0_0_0x800000060301143F, - data_buffer); if(rc) return rc; - rc_num = rc_num | data_buffer.insertFromRight(l_rd_cen_vref_in,56,4); - if (rc_num) - { - FAPI_ERR( "config_rd_vref: Error in setting up buffer "); - rc.setEcmdError(rc_num); - return rc; - } - rc_num = data_buffer.setBit(60); - if (rc_num) - { - FAPI_ERR( "config_rd_vref: Error in setting up buffer "); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P0_0_0x800000060301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P0_1_0x800004060301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P0_2_0x800008060301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P0_3_0x80000c060301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P0_4_0x800010060301143F, - data_buffer); if(rc) return rc; - rc = fapiGetScom(i_target_mba, - DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P1_0_0x800100060301143F, - data_buffer); if(rc) return rc; - rc_num = rc_num | data_buffer.insertFromRight(l_rd_cen_vref_in,56,4); - if (rc_num) - { - FAPI_ERR( "config_rd_vref: Error in setting up buffer "); - rc.setEcmdError(rc_num); - return rc; - } - rc_num = data_buffer.setBit(60); - if (rc_num) - { - FAPI_ERR( "config_rd_vref: Error in setting up buffer "); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P1_0_0x800100060301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P1_1_0x800104060301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P1_2_0x800108060301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P1_3_0x80010c060301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P1_4_0x800110060301143F, - data_buffer); if(rc) return rc; - - rc = delay_shmoo(i_target_mba, i_port, i_shmoo_type_valid,&l_left_margin, &l_right_margin,l_rd_cen_vref_in);if (rc) return rc; - l_left_margin_rd_vref_array[l_vref_num] = l_left_margin; - l_right_margin_rd_vref_array[l_vref_num] = l_right_margin; - - FAPI_INF("Read Vref = %d ; Min Setup time = %d; Min Hold time = %d",vref_value_print, l_left_margin_rd_vref_array[l_vref_num],l_right_margin_rd_vref_array[l_vref_num]); - } - - - } - FAPI_INF("++++ Centaur Read Vref Shmoo function DDR4 done ! ++++"); - FAPI_INF("Restoring mcbist setup attribute..."); - rc = reset_attribute(i_target_mba); - return rc; -} - -//------------------------------------------------------------------------------ -//Function name: reset_attributes() -//Description: Sets the attribute used by all functions -//------------------------------------------------------------------------------ - -fapi::ReturnCode reset_attribute(const fapi::Target & i_target_mba) -{ - fapi::ReturnCode rc; - uint8_t l_mcbist_setup_multiple_reset = 0; //Hard coded it wont change - rc = FAPI_ATTR_SET(ATTR_SCHMOO_MULTIPLE_SETUP_CALL, &i_target_mba, l_mcbist_setup_multiple_reset); - return rc; -} - -//------------------------------------------------------------------------------ -// Function name:find_best_margin() -// Finds better timing margin and returns the index -// Input param: const fapi::Target MBA, port = 0,1 -// Shmoo param: PARAM_NONE, DRV_IMP, SLEW_RATE, WR_VREF, RD_VREF, RCV_IMP -// i_left[], i_right[] - timing margin arrays, i_max = Max enum value of schmoo param -// i_param_nom = selected shmoo parameter (DRV_IMP, SLEW_RATE, WR_VREF, RD_VREF, RCV_IMP -// Output param: o_index (returns index) -//------------------------------------------------------------------------------ - - -void find_best_margin(shmoo_param i_shmoo_param_valid, -uint32_t i_left[], -uint32_t i_right[], -const uint8_t i_max, -uint32_t i_param_nom, -uint8_t& o_index) -{ - uint32_t left_margin = 0; - uint32_t right_margin = 0; - uint32_t left_margin_nom = 0; - uint32_t right_margin_nom = 0; - uint32_t diff_margin_nom = 0; - //uint32_t total_margin = 0; - uint32_t diff_margin = 0; - uint8_t index = 0; - uint8_t index2 = 0; - - for (index = 0; index < i_max; index += 1) //send max from top function - { - if (i_shmoo_param_valid & DRV_IMP) - { - if (drv_imp_array[index] == i_param_nom) - { - left_margin_nom = i_left[index]; - right_margin_nom = i_right[index]; - diff_margin_nom = (i_left[index] >= i_right[index]) ? - (i_left[index]- i_right[index]) : - (i_right[index] - i_left[index]); - //FAPI_INF("Driver impedance value (NOM): %d Ohms Setup Margin: %d Hold Margin: %d", i_param_nom, i_left[index], i_right[index]); - break; - } - } - else if (i_shmoo_param_valid & SLEW_RATE) - { - if (slew_rate_array[index] == i_param_nom) - { - left_margin_nom = i_left[index]; - right_margin_nom = i_right[index]; - diff_margin_nom = (i_left[index] >= i_right[index]) ? - (i_left[index] - i_right[index]) : - (i_right[index] - i_left[index]); - //FAPI_INF("Slew rate value (NOM): %d V/ns Setup Margin: %d Hold Margin: %d", i_param_nom, i_left[index], i_right[index]); - break; - } - } - else if (i_shmoo_param_valid & WR_VREF) - { - if (wr_vref_array_fitness[index] == i_param_nom) - { - left_margin_nom = i_left[index]; - right_margin_nom = i_right[index]; - diff_margin_nom = (i_left[index] >= i_right[index]) ? - (i_left[index] - i_right[index]) : - (i_right[index] - i_left[index]); - //FAPI_INF("Write DRAM Vref Multiplier value (NOM): %d Setup Margin: %d Hold Margin: %d", i_param_nom, i_left[index], i_right[index]); - break; - } - } - else if (i_shmoo_param_valid & RD_VREF) - { - if (rd_cen_vref_array_fitness[index] == i_param_nom) - { - left_margin_nom = i_left[index]; - right_margin_nom = i_right[index]; - diff_margin_nom = (i_left[index] >= i_right[index]) ? - (i_left[index] - i_right[index]) : - (i_right[index] - i_left[index]); - //FAPI_INF("Centaur Read Vref Multiplier value (NOM): %d Setup Margin: %d Hold Margin: %d", i_param_nom, i_left[index], i_right[index]); - break; - } - } - else if (i_shmoo_param_valid & RCV_IMP) - { - if (rcv_imp_array[index] == i_param_nom) - { - left_margin_nom = i_left[index]; - right_margin_nom = i_right[index]; - diff_margin_nom = (i_left[index] >= i_right[index]) ? - (i_left[index] - i_right[index]) : - (i_right[index] - i_left[index]); - // FAPI_INF("Receiver Impedance value (NOM): %d Ohms Setup Margin: %d Hold Margin: %d", i_param_nom, i_left[index], i_right[index]); - break; - } - } - } - for (index2 = 0; index2 < i_max; index2 += 1) - { - left_margin = i_left[index2]; - right_margin = i_right[index2]; - //total_margin = i_left[index2] + i_right[index2]; - diff_margin = (i_left[index2] >= i_right[index2]) ? (i_left[index2] - - i_right[index2]) : (i_right[index2] - i_left[index2]); - if ((left_margin > 0 && right_margin > 0)) - { - if ((left_margin >= left_margin_nom) && (right_margin - >= right_margin_nom) && (diff_margin <= diff_margin_nom)) - { - o_index = index2; - //wont break this loop, since the purpose is to find the best parameter value & best timing margin The enum is constructed to do that - // FAPI_INF("Index value %d, Min Setup Margin: %d, Min Hold Margin: %d", o_index, i_left[index2], i_right[index2]); - } - } - } -} diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_draminit_training_advanced.H b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_draminit_training_advanced.H deleted file mode 100755 index 34f2c11f7..000000000 --- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_draminit_training_advanced.H +++ /dev/null @@ -1,85 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_draminit_training_advanced.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2012,2014 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: mss_draminit_training_advanced.H,v 1.17 2014/01/23 17:10:05 sasethur Exp $ -/* File is created by SARAVANAN SETHURAMAN on Thur Sept 28 2011. */ - -//------------------------------------------------------------------------------ -// *! (C) Copyright International Business Machines Corp. 2007 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -//------------------------------------------------------------------------------ -// *! TITLE :mss_draminit_training_advanced.H -// *! DESCRIPTION : Tools for centaur procedures -// *! OWNER NAME : SARAVANAN SETHURAMAN email id: saravanans@in.ibm.com -// *! BACKUP NAME :MARK D BELLOWS email id: bellows@us.ibm.com -// #! ADDITIONAL COMMENTS : -// -// General purpose funcs - -//------------------------------------------------------------------------------ -// Don't forget to create CVS comments when you check in your changes! -//------------------------------------------------------------------------------ -// CHANGE HISTORY: -//------------------------------------------------------------------------------ -// Version:| Author: | Date: | Comment: -//---------|---------- |--------- |----------------------------------------------- -// 1.0 | 28-Sep-11 | sasethur | First drop of Centaur -// 1.1 | 18-Nov-11 | sasethur | Added typedef and comment update -// 1.2 | 13-Feb-12 | sasethur | Updated scom address naming convention -// 1.9 | 16-Jul-12 | bellows | Added in Id tag -// 1.10 | 15-Oct-12 | sasethur | Updated user option -// 1.11 | 26-Oct-12 | sasethur | Updated fapi:: and const Target & for HB environment -// 1.12 | 15-Nov-12 | sasethur | Updated fw review comments -// 1.13 | 07-Dec-12 | sasethur | Updated for fw review in comment section -// 1.14 | 10-May-13 | sasethur | Added user input for test type, pattern from wrapper -// 1.15 | 10-May-13 | sasethur | changed uint8_t to uint32_t for test type, pattern -// 1.16 | 08-Aug-13 | sasethur | Removed Pattern and testype -// 1.17 | 17-Jan-14 | mjjones | RAS Review cleanup - -#ifndef _MSS_DRAMINIT_TRAINING_ADVANCED_H -#define _MSS_DRAMINIT_TRAINING_ADVANCED_H - -//---------------------------------------------------------------------- -// Includes -//---------------------------------------------------------------------- -#include <fapi.H> - -typedef fapi::ReturnCode (*mss_draminit_training_advanced_FP_t)(const fapi::Target &); - - -extern "C" -{ -/** - * @brief Draminit training advanced procedure shmoo's drv_impedance, slew, vref and receiver impedance and get the optimum value - * - * @param[in] i_target Reference to MBA target - * - * @return ReturnCode - */ -fapi::ReturnCode mss_draminit_training_advanced(const fapi::Target & i_target_mba); - -} // extern C - -#endif// _MSS_DRAMINIT_TRAINING_ADVANCED_H diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_generic_shmoo.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_generic_shmoo.C deleted file mode 100644 index 15177ebaf..000000000 --- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_generic_shmoo.C +++ /dev/null @@ -1,4500 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_generic_shmoo.C $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2012,2015 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: mss_generic_shmoo.C,v 1.101 2015/09/25 20:19:34 sglancy Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_generic_shmoo.C,v $ -// *!*************************************************************************** -// *! (C) Copyright International Business Machines Corp. 1997, 1998 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -// *!*************************************************************************** -// *! FILENAME : mss_generic_shmoo.C -// *! TITLE : MSS Generic Shmoo Implementation -// *! DESCRIPTION : Memory Subsystem Generic Shmoo -- abstraction for HB -// *! CONTEXT : To make all shmoos share a common abstraction layer -// *! -// *! OWNER NAME : Preetham Hosmane Email: preeragh@in.ibm.com -// *! BACKUP NAME : Saravanan Sethuraman -// *! -// *!*************************************************************************** -// CHANGE HISTORY: -//------------------------------------------------------------------------------ -// Version:|Author: | Date: | Comment: -// --------|--------|---------|-------------------------------------------------- -// 1.101 |sglancy |25-Sep-15| Fixed bug where shmoos only had a granularity of 2 ticks instead of 1 -// 1.100 |preeragh|25-Aug-15| More FW Review Comments -// 1.99 |preeragh|25-Aug-15| More FW Review Comments -// 1.98 |preeragh|19-Aug-15| FW Review Comments -// 1.97 |preeragh|11-Aug-15| Removed -composite/bin dependency for WRT_DQS -// 1.96 |preeragh|05-Aug-15| Optimized for Linear / Comp / Bin Schmoos -// 1.95 |preeragh|22-Jul-15| 64bit compile fix -// 1.94 |preeragh|22-Jun-15| DDR4 Enhancements and Optimizations -// 1.93 |sglancy |16-Feb-15| Merged FW comments with lab needs -// 1.92 |preeragh|15-Dec-14| Reverted Changes to v.1.87 -// 1.88 |rwheeler|10-Nov-14| Updated setup_mcbist for added variable. -// 1.87 |abhijsau|7-Feb-14| added sanity check and error call out for schmoo's , removed printing of disconnected DQS. -// 1.86 |abhijsau|24-Jan-14| Fixed code as per changes in access delay error check -// 1.85 |mjjones |24-Jan-14| Fixed layout and error handling for RAS Review -// 1.84 |abhijit |16-JAN-14| Changed EFF_DIMM_TYPE attribute to ATTR_EFF_CUSTOM_DIMM -// 1.83 |abhijit |17-DEC-13| Changed the whole code structure to enable run from firmware -// 1.81 |abhijit |07-nov-13| Fixed memory release as per fw suggestion -// 1.80 |abhijit |07-nov-13| Fixed array initialization of bad bit array as per fw suggestion -// 1.79 |abhijit |07-nov-13| Fixed array initialization of valid_ranks[] in schmoo constructor & modified prints in report function to support 2D script -// 1.78 |abhijit |29-oct-13| added feature of not schmooing on bad dq and also added the target prints -// 1.77 |abhijit |21-oct-13| fixed the printing for tdqss min and tdqss max -// 1.76 |abhijit |17-oct-13| fixed the printing for dqs by 4 -// 1.74 |abhijit |4-oct-13 | fixed fw comments -// 1.73 |abhijit |1-oct-13 | fixed write dqs by 8 for isdimm -// 1.72 |abhijit |20-sep-13| fixed printing of rd eye report as -1 for not finding left bound -// 1.71 |abhijit |18-sep-13| changed for mcbist call -// 1.70 |abhijit |12-sep-13| Fixed binary debug prints -// 1.69 |abhijit |12-sep-13| Fixed binary debug prints -// 1.68 |abhijit |11-sep-13| Added Binary Schmoo algorithm -// 1.67 |abhijit |4-sep-13 | fixed fw comment -// - - - - -//------------------------------------------------------------------------------ -#include <fapi.H> -#include "mss_generic_shmoo.H" -#include "mss_mcbist.H" -#include <mss_draminit_training.H> -#include <dimmBadDqBitmapFuncs.H> -#include <mss_access_delay_reg.H> - -//#define DBG 0 - -extern "C" -{ - using namespace fapi; - - // START IMPLEMENTATION OF generic_shmoo CLASS METHODS - //! shmoo_mask - What shmoos do you want to run ... encoded as Hex 0x2,0x4,0x8,0x16 - /*------------------------------------------------------------------------------ - * constructor: generic_shmoo - * Description :Constructor used to initialize variables and do the initial settings - * - @param uint8_t addr: - @param shmoo_type_t shmoo_mask: - @param shmoo_algorithm_t shmoo_algorithm: - * ---------------------------------------------------------------------------*/ - generic_shmoo::generic_shmoo(uint8_t addr,shmoo_type_t shmoo_mask,shmoo_algorithm_t shmoo_algorithm) - { - this->shmoo_mask=shmoo_mask; //! Sets what Shmoos the caller wants to run - this->algorithm=shmoo_algorithm ; - this->iv_shmoo_type = shmoo_mask; - this->iv_addr=addr; - iv_MAX_BYTES=10; - iv_DQS_ON=0; - iv_pattern=0; - iv_test_type=0; - iv_dmm_type=0; - iv_shmoo_param=0; - iv_binary_diff=2; - iv_vref_mul=0; - iv_SHMOO_ON = 0; - - for(int p=0; p<MAX_PORT; p++) - { - for(int i=0; i<MAX_RANK; i++) - { - valid_rank1[p][i]=0; - valid_rank[i]=0; - } - } - iv_MAX_RANKS[0]=4; - iv_MAX_RANKS[1]=4; - - if (shmoo_mask & TEST_NONE) - { - FAPI_INF("mss_generic_shmoo : NONE selected %d", shmoo_mask); - } - - if (shmoo_mask & MCBIST) - { - FAPI_INF("mss_generic_shmoo : MCBIST selected %d", shmoo_mask); - iv_shmoo_type = 1; - } - if (shmoo_mask & WR_EYE) - { - FAPI_INF("mss_generic_shmoo : WR_EYE selected %d", shmoo_mask); - iv_shmoo_type = 2; - } - - if (shmoo_mask & RD_EYE) - { - FAPI_INF("mss_generic_shmoo : RD_EYE selected %d", shmoo_mask); - iv_shmoo_type = 8; - } - if (shmoo_mask & WRT_DQS) - { - FAPI_INF("mss_generic_shmoo : WRT_DQS selected %d", shmoo_mask); - iv_shmoo_type = 4; - iv_DQS_ON = 1; - } - - if(iv_DQS_ON==1) { - for (int k = 0; k < MAX_SHMOO; k++) - { - for (int i = 0; i < MAX_PORT; i++) - { - for (int j = 0; j < iv_MAX_RANKS[i]; j++) - { - init_multi_array(SHMOO[k].MBA.P[i].S[j].K.nom_val, 250); - init_multi_array(SHMOO[k].MBA.P[i].S[j].K.lb_regval, 0); - init_multi_array(SHMOO[k].MBA.P[i].S[j].K.rb_regval, 512); - init_multi_array(SHMOO[k].MBA.P[i].S[j].K.last_pass, 0); - init_multi_array(SHMOO[k].MBA.P[i].S[j].K.last_fail, 0); - init_multi_array(SHMOO[k].MBA.P[i].S[j].K.curr_val, 0); - } - } - } - } - } - - /*------------------------------------------------------------------------------ - * Function: run - * Description : ! Delegator function that runs shmoo using other functions - * - * Parameters: i_target: mba; iv_port: 0, 1 - * ---------------------------------------------------------------------------*/ - fapi::ReturnCode generic_shmoo::run(const fapi::Target & i_target, - uint32_t *o_right_min_margin, - uint32_t *o_left_min_margin, - uint32_t i_vref_mul) - { - fapi::ReturnCode rc; - uint8_t num_ranks_per_dimm[2][2]; - uint8_t l_attr_eff_dimm_type_u8 = 0; - uint8_t l_attr_schmoo_test_type_u8 = 0; - uint8_t l_attr_schmoo_multiple_setup_call_u8 = 0; - uint8_t l_mcbist_prnt_off = 0; - uint64_t i_content_array[10]; - uint8_t l_rankpgrp0[2] = { 0 }; - uint8_t l_rankpgrp1[2] = { 0 }; - uint8_t l_rankpgrp2[2] = { 0 }; - uint8_t l_rankpgrp3[2] = { 0 }; - uint8_t l_totrg_0 = 0; - uint8_t l_totrg_1 = 0; - uint8_t l_pp = 0; - uint8_t l_shmoo_param = 0; - uint8_t rank_table_port0[8] = {0}; - uint8_t rank_table_port1[8] = {0}; - - rc = FAPI_ATTR_GET(ATTR_EFF_SCHMOO_MODE, &i_target, l_shmoo_param); - if (rc) return rc; - iv_shmoo_param = l_shmoo_param; - FAPI_INF(" +++++ The iv_shmoo_param = %d ++++ ",iv_shmoo_param); - iv_vref_mul = i_vref_mul; - - ecmdDataBufferBase l_data_buffer1_64(64); - uint8_t l_dram_width = 0; - - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target, l_dram_width); - if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_MCBIST_PRINTING_DISABLE, &i_target, l_mcbist_prnt_off); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target, num_ranks_per_dimm); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_CUSTOM_DIMM, &i_target, l_attr_eff_dimm_type_u8); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_SCHMOO_TEST_VALID, &i_target, l_attr_schmoo_test_type_u8); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_SCHMOO_MULTIPLE_SETUP_CALL, &i_target, l_attr_schmoo_multiple_setup_call_u8); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP0, &i_target, l_rankpgrp0); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP1, &i_target, l_rankpgrp1); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP2, &i_target, l_rankpgrp2); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP3, &i_target, l_rankpgrp3); - if(rc) return rc; - - iv_MAX_RANKS[0]=num_ranks_per_dimm[0][0]+num_ranks_per_dimm[0][1]; - iv_MAX_RANKS[1]=num_ranks_per_dimm[1][0]+num_ranks_per_dimm[1][1]; - iv_pattern=0; - iv_test_type=0; - if ( l_attr_eff_dimm_type_u8 == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES ) - { - iv_MAX_BYTES=10; - } - else - { - - iv_dmm_type=1; - iv_MAX_BYTES=9; - } - uint8_t i_rp = 0; - - for (int l_rnk=0; l_rnk< iv_MAX_RANKS[0]; l_rnk++) - { // Byte loop - rc = mss_getrankpair(i_target,0,0,&i_rp,rank_table_port0); - if(rc) return rc; - } - - for (int l_rnk=0; l_rnk< iv_MAX_RANKS[0]; l_rnk++) - { // Byte loop - rc = mss_getrankpair(i_target,1,0,&i_rp,rank_table_port1); - if(rc) return rc; - } - - for(int l_p =0; l_p < 2; l_p++) - { - for (int l_rnk=0; l_rnk < 8; l_rnk++) - { // Byte loop - if(l_p == 0) - valid_rank1[l_p][l_rnk] = rank_table_port0[l_rnk]; - else - valid_rank1[l_p][l_rnk] = rank_table_port1[l_rnk]; - - FAPI_INF("PORT - %d - RANK %d\n",l_p,valid_rank1[l_p][l_rnk]); - } - } - FAPI_DBG("mss_generic_shmoo : run() for shmoo type %d", shmoo_mask); - // Check if all bytes/bits are in a pass condition initially .Otherwise quit - - //Value of l_attr_schmoo_test_type_u8 are 0x01, 0x02, 0x04, 0x08, 0x10 === - // "MCBIST","WR_EYE","RD_EYE","WRT_DQS","RD_DQS" resp. - - if (l_attr_schmoo_test_type_u8 == 0) - { - FAPI_INF("%s:This procedure wont change any delay settings", - i_target.toEcmdString()); - return rc; - } - if (l_attr_schmoo_test_type_u8 == 1) - { - rc = sanity_check(i_target); // Run MCBIST only when ATTR_EFF_SCHMOO_TEST_VALID is mcbist only - - if (!rc.ok()) - { - FAPI_ERR("generic_shmoo::run MSS Generic Shmoo failed initial Sanity Check. Memory not in an all pass Condition"); - return rc; - } - } - else if (l_attr_schmoo_test_type_u8 == 8) - { - if (l_rankpgrp0[0] != 255) - { - l_totrg_0++; - } - if (l_rankpgrp1[0] != 255) - { - l_totrg_0++; - } - if (l_rankpgrp2[0] != 255) - { - l_totrg_0++; - } - if (l_rankpgrp3[0] != 255) - { - l_totrg_0++; - } - if (l_rankpgrp0[1] != 255) - { - l_totrg_1++; - } - if (l_rankpgrp1[1] != 255) - { - l_totrg_1++; - } - if (l_rankpgrp2[1] != 255) - { - l_totrg_1++; - } - if (l_rankpgrp3[1] != 255) - { - l_totrg_1++; - } - if ((l_totrg_0 == 1) || (l_totrg_1 == 1)) - { - rc = shmoo_save_rest(i_target, i_content_array, 0); - if(rc) return rc; - l_pp = 1; - } - - if (l_pp == 1) - { - FAPI_INF("%s:Ping pong is disabled", i_target.toEcmdString()); - } - else - { - FAPI_INF("%s:Ping pong is enabled", i_target.toEcmdString()); - } - - if ((l_pp = 1) && ((l_totrg_0 == 1) || (l_totrg_1 == 1))) - { - FAPI_INF("%s:Rank group is not good with ping pong. Hope you have set W2W gap to 10", - i_target.toEcmdString()); - } - - iv_shmoo_type=4; //for Gate Delays - rc=get_all_noms_dqs(i_target); - if(rc) return rc; - - iv_shmoo_type=2; // For Access delays - rc=get_all_noms(i_target); - if(rc) return rc; - - rc=schmoo_setup_mcb(i_target); - if(rc) return rc; - //Find RIGHT BOUND OR SETUP BOUND - rc=find_bound(i_target,RIGHT); - if(rc) return rc; - - //Find LEFT BOUND OR HOLD BOUND - rc=find_bound(i_target,LEFT); - if(rc) return rc; - iv_shmoo_type=4; - - if (l_dram_width == 4) - { - rc = get_margin_dqs_by4(i_target); - if (rc) return rc; - } - else - { - rc = get_margin_dqs_by8(i_target); - if (rc) return rc; - } - - rc = print_report_dqs(i_target); - if (rc) return rc; - - rc = get_min_margin_dqs(i_target, o_right_min_margin,o_left_min_margin); - if (rc) return rc; - - if ((l_totrg_0 == 1) || (l_totrg_1 == 1)) - { - rc = shmoo_save_rest(i_target, i_content_array, 1); - if(rc) return rc; - } - - FAPI_INF("%s: Least tDQSSmin(ps)=%d ps and Least tDQSSmax=%d ps",i_target.toEcmdString(), *o_left_min_margin,*o_right_min_margin); - } - else - { - FAPI_INF("************ ++++++++++++++++++ ***************** +++++++++++++ *****************"); - rc=get_all_noms(i_target); - if(rc) return rc; - if(l_attr_schmoo_multiple_setup_call_u8==0) { - rc=schmoo_setup_mcb(i_target); - if(rc) return rc; - } - rc=set_all_binary(i_target,RIGHT); - if(rc) return rc; - - //Find RIGHT BOUND OR SETUP BOUND - rc=find_bound(i_target,RIGHT); - if(rc) return rc; - rc=set_all_binary(i_target,LEFT); - if(rc) return rc; - //Find LEFT BOUND OR HOLD BOUND - rc=find_bound(i_target,LEFT); - if(rc) return rc; - - //Find the margins in Ps i.e setup margin ,hold margin,Eye width - rc=get_margin2(i_target); - if(rc) return rc; - //It is used to find the lowest of setup and hold margin - if(iv_shmoo_param==6) - { - - rc=get_min_margin2(i_target,o_right_min_margin,o_left_min_margin); - if(rc) return rc; - rc=print_report(i_target); - if(rc) return rc; - FAPI_INF("%s:Minimum hold margin=%d ps and setup margin=%d ps",i_target.toEcmdString(), *o_left_min_margin,*o_right_min_margin); - } - else - { - rc=get_min_margin2(i_target,o_right_min_margin,o_left_min_margin); - if(rc) return rc; - rc=print_report(i_target); - if(rc) return rc; - FAPI_INF("%s:Minimum hold margin=%d ps and setup margin=%d ps",i_target.toEcmdString(), *o_left_min_margin,*o_right_min_margin); - } - } - l_mcbist_prnt_off=0; - rc = FAPI_ATTR_SET(ATTR_MCBIST_PRINTING_DISABLE, &i_target, l_mcbist_prnt_off); - if(rc) return rc; - return rc; - } - - fapi::ReturnCode generic_shmoo::shmoo_save_rest(const fapi::Target & i_target, - uint64_t i_content_array[], - uint8_t i_mode) - { - ReturnCode rc; - uint32_t rc_num; - uint8_t l_index = 0; - uint64_t l_value = 0; - uint64_t l_val_u64 = 0; - ecmdDataBufferBase l_shmoo1ab(64); - uint64_t l_Databitdir[10] = { 0x800000030301143full, 0x800004030301143full, - 0x800008030301143full, 0x80000c030301143full, 0x800010030301143full, - 0x800100030301143full, 0x800104030301143full, 0x800108030301143full, - 0x80010c030301143full, 0x800110030301143full - }; - if (i_mode == 0) - { - FAPI_INF("%s: Saving DP18 data bit direction register contents", - i_target.toEcmdString()); - for (l_index = 0; l_index < MAX_BYTE; l_index++) - { - l_value = l_Databitdir[l_index]; - rc = fapiGetScom(i_target, l_value, l_shmoo1ab); - if (rc) return rc; - rc_num = l_shmoo1ab.setBit(57); - if (rc_num) - { - FAPI_ERR("Error in function shmoo_save_rest:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target, l_value, l_shmoo1ab); - if (rc) return rc; - i_content_array[l_index] = l_shmoo1ab.getDoubleWord(0); - } - } - else if (i_mode == 1) - { - FAPI_INF("%s: Restoring DP18 data bit direction register contents", - i_target.toEcmdString()); - for (l_index = 0; l_index < MAX_BYTE; l_index++) - { - l_val_u64 = i_content_array[l_index]; - l_value = l_Databitdir[l_index]; - rc_num = l_shmoo1ab.setDoubleWord(0, l_val_u64); - if (rc_num) - { - FAPI_ERR("Error in function shmoo_save_rest:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target, l_value, l_shmoo1ab); - if (rc) return rc; - } - } - else - { - FAPI_INF("%s:Invalid value of MODE", i_target.toEcmdString()); - } - return rc; - } - - /*------------------------------------------------------------------------------ - * Function: sanity_check - * Description : do intial mcbist check in nominal and report spd if any bad bit found - * - * Parameters: i_target: mba; - * ---------------------------------------------------------------------------*/ - fapi::ReturnCode generic_shmoo::sanity_check(const fapi::Target & i_target) - { - fapi::ReturnCode rc; - mcbist_mode = QUARTER_SLOW; - uint8_t l_mcb_status = 0; - uint8_t l_CDarray0[80] = { 0 }; - uint8_t l_CDarray1[80] = { 0 }; - uint8_t l_byte, l_rnk; - uint8_t l_nibble; - uint8_t l_n = 0; - uint8_t l_p = 0; - uint8_t rank = 0; - uint8_t l_faulted_rank = 255; - uint8_t l_faulted_port = 255; - uint8_t l_faulted_dimm = 255; - uint8_t l_memory_health = 0; - uint8_t l_max_byte = 10; - - struct Subtest_info l_sub_info[30]; - - rc = schmoo_setup_mcb(i_target); - if (rc) return rc; - //FAPI_INF("%s: starting mcbist now",i_target.toEcmdString()); - rc = start_mcb(i_target); - if (rc) return rc; - //FAPI_INF("%s: polling mcbist now",i_target.toEcmdString()); - rc = poll_mcb(i_target, &l_mcb_status, l_sub_info, 1); - if (rc) - { - FAPI_ERR("generic_shmoo::do_mcbist_test: POLL MCBIST failed !!"); - return rc; - } - //FAPI_INF("%s: checking error map ",i_target.toEcmdString()); - rc = mcb_error_map(i_target, mcbist_error_map, l_CDarray0, l_CDarray1, - count_bad_dq); - if (rc) return rc; - - for (l_p = 0; l_p < MAX_PORT; l_p++) - { - for (l_rnk = 0; l_rnk < iv_MAX_RANKS[l_p]; l_rnk++) - { // Byte loop - rank = valid_rank1[l_p][l_rnk]; - - l_n = 0; - for (l_byte = 0; l_byte < l_max_byte; l_byte++) - { - //Nibble loop - for (l_nibble = 0; l_nibble < MAX_NIBBLES; l_nibble++) - { - if (mcbist_error_map[l_p][rank][l_byte][l_nibble] == 1) - { - l_memory_health = 1; - l_faulted_rank = rank; - l_faulted_port = l_p; - if(rank>3) { - l_faulted_dimm = 1; - } else { - l_faulted_dimm = 0; - } - break; - } - - l_n++; - - } - } - } - } - - - //////////////// changed the check condition ... The error call out need to gard the dimm=l_faulted_dimm(0 or 1) //// port=l_faulted_port(0 or 1) target=i_target ... - if (l_memory_health) - { - FAPI_INF("generic_shmoo:sanity_check failed !! MCBIST failed on intial run , memory is not in good state needs investigation port=%d rank=%d dimm=%d", - l_faulted_port, l_faulted_rank, l_faulted_dimm); - const fapi::Target & MBA_CHIPLET = i_target; - const uint8_t & MBA_PORT_NUMBER = l_faulted_port; - const uint8_t & MBA_DIMM_NUMBER = l_faulted_dimm; - FAPI_SET_HWP_ERROR(rc, RC_MSS_GENERIC_SHMOO_MCBIST_FAILED); - return rc; - } - - return rc; - } - /*------------------------------------------------------------------------------ - * Function: do_mcbist_reset - * Description : do mcbist reset - * - * Parameters: i_target: mba,iv_port 0/1 , rank 0-7 , byte 0-7, nibble 0/1, pass; - * ---------------------------------------------------------------------------*/ - fapi::ReturnCode generic_shmoo::do_mcbist_reset(const fapi::Target & i_target) - { - fapi::ReturnCode rc; - uint32_t rc_num = 0; - - Target i_target_centaur; - rc = fapiGetParentChip(i_target, i_target_centaur); - if (rc) return rc; - - ecmdDataBufferBase l_data_buffer_64(64); - rc_num = l_data_buffer_64.flushTo0(); - if (rc_num) - { - FAPI_ERR("Error in function mcb_reset_trap:"); - rc.setEcmdError(rc_num); - return rc; - } - //PORT - A - rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MCBEMA1Q_0x0201166a, l_data_buffer_64); - if (rc) return (rc); - rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MCBEMA2Q_0x0201166b, l_data_buffer_64); - if (rc) return (rc); - rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MCBEMA3Q_0x0201166c, l_data_buffer_64); - if (rc) return (rc); - - //PORT - B - rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MCBEMB1Q_0x0201166d, l_data_buffer_64); - if (rc) return (rc); - rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MCBEMB2Q_0x0201166e, l_data_buffer_64); - if (rc) return (rc); - rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MCBEMB3Q_0x0201166f, l_data_buffer_64); - if (rc) return (rc); - - // MBS 23 - rc = fapiPutScom(i_target_centaur, 0x0201176a, l_data_buffer_64); - if (rc) return (rc); - rc = fapiPutScom(i_target_centaur, 0x0201176b, l_data_buffer_64); - if (rc) return (rc); - rc = fapiPutScom(i_target_centaur, 0x0201176c, l_data_buffer_64); - if (rc) return (rc); - - //PORT - B - rc = fapiPutScom(i_target_centaur, 0x0201176d, l_data_buffer_64); - if (rc) return (rc); - rc = fapiPutScom(i_target_centaur, 0x0201176e, l_data_buffer_64); - if (rc) return (rc); - rc = fapiPutScom(i_target_centaur, 0x0201176f, l_data_buffer_64); - if (rc) return (rc); - - return rc; - } - /*------------------------------------------------------------------------------ - * Function: do_mcbist_test - * Description : do mcbist check for error on particular nibble - * - * Parameters: i_target: mba,iv_port 0/1 , rank 0-7 , byte 0-7, nibble 0/1, pass; - * ---------------------------------------------------------------------------*/ - fapi::ReturnCode generic_shmoo::do_mcbist_test(const fapi::Target & i_target) - { - fapi::ReturnCode rc; - uint8_t l_mcb_status = 0; - struct Subtest_info l_sub_info[30]; - - rc = start_mcb(i_target); - if (rc) - { - FAPI_ERR("generic_shmoo::do_mcbist_test: Start MCBIST failed !!"); - return rc; - } - rc = poll_mcb(i_target, &l_mcb_status, l_sub_info, 1); - if (rc) - { - FAPI_ERR("generic_shmoo::do_mcbist_test: POLL MCBIST failed !!"); - return rc; - } - - return rc; - - } - /*------------------------------------------------------------------------------ - * Function: check_error_map - * Description : used by do_mcbist_test to check the error map for particular nibble - * - * Parameters: iv_port 0/1 , rank 0-7 , byte 0-7, nibble 0/1, pass; - * ---------------------------------------------------------------------------*/ - fapi::ReturnCode generic_shmoo::check_error_map(const fapi::Target & i_target, - uint8_t l_p, - uint8_t &pass) - { - fapi::ReturnCode rc; - uint8_t l_byte,l_rnk; - uint8_t l_nibble; - uint8_t l_byte_is; - uint8_t l_nibble_is; - uint8_t l_n=0; - pass=1; - input_type l_input_type_e = ISDIMM_DQ; - uint8_t i_input_index_u8=0; - uint8_t l_val =0; - uint8_t rank=0; - uint8_t l_max_byte=10; - uint8_t l_CDarray0[80]= {0}; - uint8_t l_CDarray1[80]= {0}; - - if(iv_dmm_type==1) - { - l_max_byte=9; - //l_max_nibble=18; - } - - rc=mcb_error_map(i_target,mcbist_error_map,l_CDarray0,l_CDarray1,count_bad_dq); - if(rc) - { - FAPI_ERR("generic_shmoo::do_mcbist_test: mcb_error_map failed!!"); - - return rc; - } - // for (l_p=0;l_p<MAX_PORT;l_p++){ - for (l_rnk=0; l_rnk<iv_MAX_RANKS[l_p]; l_rnk++) - { // Byte loop - ////// - rank=valid_rank1[l_p][l_rnk]; - - l_n=0; - for(l_byte=0; l_byte<l_max_byte; l_byte++) - { - //Nibble loop - for(l_nibble=0; l_nibble< MAX_NIBBLES; l_nibble++) - { - if(iv_dmm_type==1) - { - i_input_index_u8=8*l_byte+4*l_nibble; - - rc=rosetta_map(i_target,l_p,l_input_type_e,i_input_index_u8,0,l_val); - if(rc) return rc; - - l_byte_is=l_val/8; - l_nibble_is=l_val%8; - if(l_nibble_is>3) { - l_nibble_is=1; - } - else { - l_nibble_is=0; - } - - if( mcbist_error_map [l_p][rank][l_byte_is][l_nibble_is] == 1) { - schmoo_error_map[l_p][rank][l_n]=1; - pass = 1; - } - else - { - - schmoo_error_map[l_p][rank][l_n]=0; - pass = 0; - } - } - else { - if( mcbist_error_map [l_p][rank][l_byte][l_nibble] == 1) { - - schmoo_error_map[l_p][rank][l_n]=1; - pass = 1; - } - else - { - schmoo_error_map[l_p][rank][l_n]=0; - pass = 0; - } - } - l_n++; - }//end of nibble loop - }//end byte loop - }//end rank loop - //}//end port loop - - return rc; - } - - fapi::ReturnCode generic_shmoo::check_error_map2(const fapi::Target & i_target,uint8_t port,uint8_t &pass) - { - - fapi::ReturnCode rc; - uint8_t l_byte,l_rnk; - uint8_t l_nibble; - uint8_t l_byte_is; - uint8_t l_nibble_is; - uint8_t l_n=0; - pass=1; - uint8_t l_p=0; - input_type l_input_type_e = ISDIMM_DQ; - uint8_t i_input_index_u8=0; - uint8_t l_val =0; - uint8_t rank=0; - uint8_t l_max_byte=10; - uint8_t l_max_nibble=20; - uint8_t l_CDarray0[80]= {0}; - uint8_t l_CDarray1[80]= {0}; - - - - if(iv_dmm_type==1) - { - l_max_byte=9; - l_max_nibble=18; - } - - rc=mcb_error_map(i_target,mcbist_error_map,l_CDarray0,l_CDarray1,count_bad_dq); - if(rc) - { - FAPI_ERR("generic_shmoo::do_mcbist_test: mcb_error_map failed!!"); - - return rc; - } - for (l_p=0; l_p<MAX_PORT; l_p++) { - for (l_rnk=0; l_rnk<iv_MAX_RANKS[l_p]; l_rnk++) - { // Byte loop - - rank=valid_rank1[l_p][l_rnk]; - - l_n=0; - for(l_byte=0; l_byte<l_max_byte; l_byte++) - { - //Nibble loop - for(l_nibble=0; l_nibble< MAX_NIBBLES; l_nibble++) - { - if(iv_dmm_type==1) - { - i_input_index_u8=8*l_byte+4*l_nibble; - - rc=rosetta_map(i_target,l_p,l_input_type_e,i_input_index_u8,0,l_val); - if(rc) return rc; - - l_byte_is=l_val/8; - l_nibble_is=l_val%8; - if(l_nibble_is>3) { - l_nibble_is=1; - } - else { - l_nibble_is=0; - } - - if( mcbist_error_map [l_p][rank][l_byte_is][l_nibble_is] == 1) { - //pass=0; - schmoo_error_map[l_p][rank][l_n]=1; - - } - else - { - - schmoo_error_map[l_p][rank][l_n]=0; - - - } - - } else { - - - if( mcbist_error_map [l_p][rank][l_byte][l_nibble] == 1) { - //pass=0; - schmoo_error_map[l_p][rank][l_n]=1; - //FAPI_INF("We are in error and nibble is %d and rank is %d and port is %d \n",l_n,rank,l_p); - } - else - { - - schmoo_error_map[l_p][rank][l_n]=0; - - - } - } - l_n++; - } - } - } - } - for (l_p=0; l_p<MAX_PORT; l_p++) { - for (l_rnk=0; l_rnk<iv_MAX_RANKS[l_p]; l_rnk++) - { // Byte loop - rank=valid_rank1[l_p][l_rnk]; - for (l_n=0; l_n<l_max_nibble; l_n++) { - if(schmoo_error_map[l_p][rank][l_n]==0) { - - pass=0; - } - - } - } - } - - - return rc; - } - - - - /*------------------------------------------------------------------------------ - * Function: init_multi_array - * Description : This function do the initialization of various schmoo parameters - * - * Parameters: the array address and the initial value - * ---------------------------------------------------------------------------*/ - void generic_shmoo::init_multi_array(uint16_t(&array)[MAX_DQ], - uint16_t init_val) - { - - uint8_t l_byte, l_nibble, l_bit; - uint8_t l_dq = 0; - // Byte loop - - for (l_byte = 0; l_byte < iv_MAX_BYTES; l_byte++) - { //Nibble loop - for (l_nibble = 0; l_nibble < MAX_NIBBLES; l_nibble++) - { - //Bit loop - for (l_bit = 0; l_bit < MAX_BITS; l_bit++) - { - l_dq = 8 * l_byte + 4 * l_nibble + l_bit; - array[l_dq] = init_val; - } - } - } - - } - - fapi::ReturnCode generic_shmoo::set_all_binary(const fapi::Target & i_target,bound_t bound) - { - - fapi::ReturnCode rc; - uint8_t l_rnk,l_byte,l_nibble,l_bit; - uint8_t l_dq=0; - uint8_t l_p=0; - uint32_t l_max=512; - uint32_t l_max_offset=64; - uint8_t rank = 0; - - //if RD_EYE - if(iv_shmoo_type == 8) - { - l_max=127; - } - - for (l_p=0; l_p<MAX_PORT; l_p++) { - for (l_rnk=0; l_rnk<iv_MAX_RANKS[l_p]; l_rnk++) - { // Byte loop - - rank = valid_rank1[l_p][l_rnk]; - - for(l_byte=0; l_byte<iv_MAX_BYTES; l_byte++) - { //Nibble loop - for(l_nibble=0; l_nibble< MAX_NIBBLES; l_nibble++) - { - //Bit loop - for(l_bit=0; l_bit<MAX_BITS; l_bit++) - { - l_dq=8*l_byte+4*l_nibble+l_bit; - - - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_val[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]; - - if(bound==RIGHT) - { - if((SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]+l_max_offset)>l_max) { - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq]=l_max; - } - else { - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]+l_max_offset; - - } - } - - else - { - if(SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq] > 64) - { - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]-l_max_offset; - - } - else - { - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq]=0; - - } - } - } - } - } - } - } - return rc; - } - - - /*------------------------------------------------------------------------------ - * Function: get_all_noms - * Description : This function gets the nominal values for each DQ - * - * Parameters: Target:MBA - * ---------------------------------------------------------------------------*/ - fapi::ReturnCode generic_shmoo::get_all_noms(const fapi::Target & i_target) - { - fapi::ReturnCode rc; - uint8_t l_rnk,l_byte,l_nibble,l_bit; - uint8_t i_rnk=0; - uint16_t val=0; - uint8_t l_dq=0; - uint8_t l_p=0; - input_type_t l_input_type_e = WR_DQ; - access_type_t l_access_type_e = READ; - FAPI_DBG("mss_generic_shmoo : get_all_noms : Reading in all nominal values"); - - if(iv_shmoo_type == 2) - { - l_input_type_e = WR_DQ; - } - else if(iv_shmoo_type == 8) - { - l_input_type_e = RD_DQ; - } - else if(iv_shmoo_type == 16) - { - l_input_type_e = RD_DQS; - } - - for (l_p=0; l_p<MAX_PORT; l_p++) { - for (l_rnk=0; l_rnk<iv_MAX_RANKS[l_p]; l_rnk++) - { // Byte loop - i_rnk = valid_rank1[l_p][l_rnk]; - for(l_byte=0; l_byte<iv_MAX_BYTES; l_byte++) - { //Nibble loop - for(l_nibble=0; l_nibble< MAX_NIBBLES; l_nibble++) - { - //Bit loop - for(l_bit=0; l_bit<MAX_BITS; l_bit++) - { - l_dq=8*l_byte+4*l_nibble+l_bit; - //printf("Before access call"); - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,i_rnk,l_input_type_e,l_dq,0,val); - if(rc) return rc; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rnk].K.nom_val[l_dq]=val; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rnk].K.rb_regval[l_dq]=val; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rnk].K.lb_regval[l_dq]=val; - - } - } - } - } - } - return rc; - } - - //////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - - fapi::ReturnCode generic_shmoo::get_all_noms_dqs(const fapi::Target & i_target) - { - fapi::ReturnCode rc; - uint8_t l_rnk; - uint32_t val=0; - uint8_t l_p=0; - uint8_t l_max_nibble=20; - uint8_t rank=0; - uint8_t l_n=0; - FAPI_INF("%s:mss_generic_shmoo : get_all_noms_dqs : Reading in all nominal values and schmoo type=%d \n",i_target.toEcmdString(),1); - if(iv_dmm_type==1) - { - - l_max_nibble=18; - } - - input_type_t l_input_type_e = WR_DQS; - access_type_t l_access_type_e = READ ; - FAPI_DBG("mss_generic_shmoo : get_all_noms : Reading in all nominal values"); - - for (l_p=0; l_p<MAX_PORT; l_p++) { - for (l_rnk=0; l_rnk<iv_MAX_RANKS[l_p]; l_rnk++) - { // Byte loop - - rank=valid_rank1[l_p][l_rnk]; - - for (l_n=0; l_n<l_max_nibble; l_n++) { - - rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_n,0,val); - if(rc) return rc; - SHMOO[1].MBA.P[l_p].S[rank].K.nom_val[l_n]=val; - - } - } - } - return rc; - } - - /*------------------------------------------------------------------------------ - * Function: knob_update - * Description : This is a key function is used to find right and left bound using new algorithm -- there is an option u can chose not to use it by setting a flag - * - * Parameters: Target:MBA,bound:RIGHT/LEFT,scenario:type of schmoo,iv_port:0/1,rank:0-7,byte:0-7,nibble:0/1,bit:0-3,pass, - * ---------------------------------------------------------------------------*/ - fapi::ReturnCode generic_shmoo::knob_update(const fapi::Target & i_target,bound_t bound,uint8_t scenario,uint8_t bit,uint8_t pass,bool &flag) - { - fapi::ReturnCode rc; - ecmdDataBufferBase data_buffer_64(64); - ecmdDataBufferBase data_buffer_64_1(64); - input_type_t l_input_type_e = WR_DQ; - uint8_t l_dq=0; - access_type_t l_access_type_e = WRITE; - uint8_t l_n=0; - uint8_t l_i=0; - uint8_t l_p=0; - uint16_t l_delay=0; - uint16_t l_max_limit=500; - uint8_t rank=0; - uint8_t l_rank=0; - uint8_t l_SCHMOO_NIBBLES=20; - uint8_t l_CDarray0[80]= {0}; - uint8_t l_CDarray1[80]= {0}; - - if(iv_dmm_type==1) - { - l_SCHMOO_NIBBLES=18; - } - - //l_SCHMOO_NIBBLES = 2; //temp preet del this - rc=do_mcbist_reset(i_target); - if(rc) - { - FAPI_ERR("generic_shmoo::find_bound do_mcbist_reset failed"); - return rc; - } - - FAPI_INF("Linear in Progress FW --> %d",scenario); - - if(iv_shmoo_type == 2) - { - l_input_type_e = WR_DQ; - } - else if(iv_shmoo_type == 8) - { - l_input_type_e = RD_DQ; - l_max_limit=127; - } - else if(iv_shmoo_type == 4) - { - l_input_type_e = WR_DQS; - } - //else if(iv_shmoo_type == 16) - //{l_input_type_e = RD_DQS;} - - for (l_p=0; l_p < 2; l_p++) { - for(int i=0; i < iv_MAX_RANKS[l_p]; i++) { - - rank = valid_rank1[l_p][i]; - for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) { - schmoo_error_map[l_p][rank][l_n]=0; - } - } - } - - if(bound==RIGHT) - { - for (l_delay=1; ((pass==0)); l_delay=l_delay+1) { - - for (l_p=0; l_p<MAX_PORT; l_p++) { - for (l_rank=0; l_rank<iv_MAX_RANKS[l_p]; l_rank++) - { - l_dq=bit; - rank=valid_rank1[l_p][l_rank]; - for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) { - - - if(schmoo_error_map[l_p][rank][l_n]==0) { - - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]+l_delay; - - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]); - if(rc) return rc; - - } - rc=mcb_error_map(i_target,mcbist_error_map,l_CDarray0,l_CDarray1,count_bad_dq); - if(rc) return rc; - - - if(l_p == 0) { - - for(l_i=0; l_i<count_bad_dq[0]; l_i++) { - - if(l_CDarray0[l_i]==l_dq) { - - schmoo_error_map[l_p][rank][l_n]=1; - } - } - } - else { - for(l_i=0; l_i<count_bad_dq[1]; l_i++) { - - if(l_CDarray1[l_i]==l_dq) { - - schmoo_error_map[l_p][rank][l_n]=1; - } - } - } - if(SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq] > l_max_limit) { - schmoo_error_map[l_p][rank][l_n]=1; - } - - - l_dq=l_dq+4; - - } //end of nibble - } //end of rank - } //end of port loop - - rc=do_mcbist_test(i_target); - if(rc) - { - FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed"); - return rc; - } - - rc=check_error_map2(i_target,l_p,pass); - if(rc) - { - FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed"); - return rc; - } - if (l_delay > 35) - break; - } //end of Delay loop; - - - for (l_p=0; l_p<MAX_PORT; l_p++) { - for (l_rank=0; l_rank<iv_MAX_RANKS[l_p]; l_rank++) - { - l_dq=bit; - - rank=valid_rank1[l_p][l_rank]; - for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) { - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]); - if(rc) return rc; - l_dq=l_dq+4; - } - } - } - - - } - - if(bound==LEFT) - { - for (l_delay=1; (pass==0); l_delay+=1) { - for (l_p=0; l_p<MAX_PORT; l_p++) { - for (l_rank=0; l_rank<iv_MAX_RANKS[l_p]; l_rank++) - { - l_dq=bit; - - rank=valid_rank1[l_p][l_rank]; - - for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) { - - - - if(schmoo_error_map[l_p][rank][l_n]==0) { - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]-l_delay; - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]); - if(rc) return rc; - } - - rc=mcb_error_map(i_target,mcbist_error_map,l_CDarray0,l_CDarray1,count_bad_dq); - if(rc) return rc; - - if(l_p==0) { - for(l_i=0; l_i<count_bad_dq[0]; l_i++) { - if(l_CDarray0[l_i]==l_dq) { - schmoo_error_map[l_p][rank][l_n]=1; - } - } - } else { - for(l_i=0; l_i<count_bad_dq[1]; l_i++) { - if(l_CDarray1[l_i]==l_dq) { - schmoo_error_map[l_p][rank][l_n]=1; - } - } - } - - if(SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq] == 0) { - schmoo_error_map[l_p][rank][l_n] = 1; - } - - l_dq=l_dq+4; - - } - } - - } - rc=do_mcbist_test(i_target); - if(rc) - { - FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed"); - return rc; - } - - rc=check_error_map2(i_target,l_p,pass); - if(rc) - { - FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed"); - return rc; - } - - if (l_delay > 35) - break; - } - - - for (l_p=0; l_p<MAX_PORT; l_p++) { - for (l_rank=0; l_rank<iv_MAX_RANKS[l_p]; l_rank++) - { - l_dq=bit; - - rank=valid_rank1[l_p][l_rank]; - - for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) { - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]); - if(rc) return rc; - l_dq=l_dq+4; - } - } - } - - - - } - - return rc; - } - - - fapi::ReturnCode generic_shmoo::knob_update_bin(const fapi::Target & i_target,bound_t bound,uint8_t scenario,uint8_t bit,uint8_t pass,bool &flag) - { - fapi::ReturnCode rc; - ecmdDataBufferBase data_buffer_64(64); - ecmdDataBufferBase data_buffer_64_1(64); - input_type_t l_input_type_e = WR_DQ; - uint8_t l_dq=0; - access_type_t l_access_type_e = WRITE; - uint8_t l_n=0; - uint8_t l_i=0; - uint8_t l_flag_p0=0; - uint8_t l_flag_p1=0; - FAPI_INF("Inside - Binary Schmoo FW - %d",scenario); - uint8_t l_p=0; - uint8_t rank=0; - uint8_t l_rank=0; - uint8_t l_SCHMOO_NIBBLES=20; - uint8_t l_status=1; - uint8_t l_CDarray0[80]= {0}; - uint8_t l_CDarray1[80]= {0}; - - if(iv_dmm_type==1) - { - l_SCHMOO_NIBBLES=18; - } - - if(iv_shmoo_type == 2) - { - l_input_type_e = WR_DQ; - } - else if(iv_shmoo_type == 8) - { - l_input_type_e = RD_DQ; - } - else if(iv_shmoo_type == 4) - { - l_input_type_e = WR_DQS; - } - else if(iv_shmoo_type == 16) - { - l_input_type_e = RD_DQS; - } - - - rc=do_mcbist_reset(i_target); - if(rc) - { - FAPI_INF("generic_shmoo::find_bound do_mcbist_reset failed"); - return rc; - } - - - //Reset schmoo_error_map - - for(l_p = 0; l_p < MAX_PORT; l_p++) { - for(int i=0; i<iv_MAX_RANKS[l_p]; i++) { - - rank=valid_rank1[l_p][i]; - for (l_n=0; l_n < l_SCHMOO_NIBBLES; l_n++) { - schmoo_error_map[l_p][rank][l_n]=0; - binary_done_map[l_p][rank][l_n]=0; - } - } - } - int count_cycle = 0; - - if(bound==RIGHT) - { - - //FAPI_INF("Algorithm is %d vs seq_lin %d\n",algorithm,SEQ_LIN); - //FAPI_INF("\n.....Inside Right Bound \n"); - for(l_p = 0; l_p < MAX_PORT; l_p++) { - do { - - - l_status=0; - //////////////////////////////////////////// - //FAPI_INF("\n +++ Cycle %d +++ ",count_cycle); - //FAPI_INF(" . . . . ."); - - //////////////////////////////////////////// - - - //FAPI_INF("\nMBA = %d",l_mba); - rc=mcb_error_map(i_target,mcbist_error_map,l_CDarray0,l_CDarray1,count_bad_dq); - if(rc) return rc; - - - for (l_rank=0; l_rank<iv_MAX_RANKS[l_p]; l_rank++) - { - l_dq=bit; - ////// - rank=valid_rank1[l_p][l_rank]; - //FAPI_INF ("Current Rank : %d",rank ); - - - for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) { - if(binary_done_map[l_p][rank][l_n]==0) { - l_status=1; - } - l_flag_p0=0; - l_flag_p1=0; - if(l_p == 0) { - for(l_i=0; l_i<count_bad_dq[0]; l_i++) { - if(l_CDarray0[l_i]==l_dq) { - schmoo_error_map[l_p][rank][l_n]=1; - l_flag_p0=1; - //FAPI_INF(" \n I port=%d am the culprit %d ",l_p,l_dq); - //SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]+1; - } - } - } else { - for(l_i=0; l_i<count_bad_dq[1]; l_i++) { - - if(l_CDarray1[l_i]==l_dq) { - schmoo_error_map[l_p][rank][l_n]=1; - l_flag_p1=1; - - } - } - } - - if(schmoo_error_map[l_p][rank][l_n]==0) { - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_val[l_dq]; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_val[l_dq]=(SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq]+SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq])/2; - - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_val[l_dq]); - if(rc) return rc; - if(SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq]>SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq]) { - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_diff[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq]-SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq]; - } - else { - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_diff[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq]-SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq]; - } - - if(SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_diff[l_dq]<=1) { - binary_done_map[l_p][rank][l_n]=1; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq]; - // FAPI_INF("\n the right bound for port=%d rank=%d dq=%d is %d \n",l_p,rank,l_dq,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_val[l_dq]); - } - } - else { - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_val[l_dq]; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_val[l_dq]=(SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq]+SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq])/2; - - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_val[l_dq]); - if(rc) return rc; - if(SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq]>SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq]) { - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_diff[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq]-SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq]; - } else { - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_diff[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq]-SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq]; - } - if(l_p==0) { - if(l_flag_p0==1) { - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_diff[l_dq]=1; - } - } - else { - if(l_flag_p1==1) { - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_diff[l_dq]=1; - } - } - - if(SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_diff[l_dq]<=1) { - binary_done_map[l_p][rank][l_n]=1; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq]; - - } - } - l_dq=l_dq+4; - } - } - - - rc=do_mcbist_reset(i_target); - if(rc) - { - FAPI_INF("generic_shmoo::find_bound do_mcbist_reset failed"); - return rc; - } - rc=do_mcbist_test(i_target); - if(rc) - { - FAPI_INF("generic_shmoo::find_bound do_mcbist_test failed"); - return rc; - } - - rc=check_error_map(i_target,l_p,pass); - if(rc) - { - FAPI_INF("generic_shmoo::find_bound do_mcbist_test failed"); - return rc; - } - //printf("\n the status =%d \n",l_status); - count_cycle++; - } while(l_status==1); - } - - for(l_p = 0; l_p < MAX_PORT; l_p++) - { - for (l_rank=0; l_rank<iv_MAX_RANKS[l_p]; l_rank++) - { - l_dq=bit; - ////// - rank=valid_rank1[l_p][l_rank]; - - for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) { - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]); - if(rc) return rc; - l_dq=l_dq+4; - } - } - } - - - - - } - count_cycle = 0; - if(bound==LEFT) - { - for(l_p = 0; l_p < MAX_PORT; l_p++) - { - l_status = 1; - - while(l_status==1) - { - l_status=0; - - rc=mcb_error_map(i_target,mcbist_error_map,l_CDarray0,l_CDarray1,count_bad_dq); - if(rc) return rc; - - for (l_rank=0; l_rank<iv_MAX_RANKS[l_p]; l_rank++) { - l_dq=bit; - ////// - rank=valid_rank1[l_p][l_rank]; - - for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) { - - if(binary_done_map[l_p][rank][l_n]==0) { - l_status=1; - } - - l_flag_p0=0; - l_flag_p1=0; - if(l_p == 0) { - for(l_i=0; l_i<count_bad_dq[0]; l_i++) { - if(l_CDarray0[l_i]==l_dq) { - schmoo_error_map[l_p][rank][l_n]=1; - l_flag_p0=1; - - } - } - } - else { - for(l_i=0; l_i<count_bad_dq[1]; l_i++) { - - if(l_CDarray1[l_i]==l_dq) { - schmoo_error_map[l_p][rank][l_n]=1; - l_flag_p1=1; - - } - } - } - - if(schmoo_error_map[l_p][rank][l_n]==0) { - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_val[l_dq]; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_val[l_dq]=(SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq]+SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq])/2; - - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_val[l_dq]); - if(rc) return rc; - if(SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq]>SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq]) { - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_diff[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq]-SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq]; - } else { - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_diff[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq]-SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq]; - } - if(SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_diff[l_dq]<=1) { - binary_done_map[l_p][rank][l_n]=1; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq]; - - } - } else { - - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_val[l_dq]; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_val[l_dq]=(SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq]+SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq])/2; - - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_val[l_dq]); - if(rc) return rc; - if(SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq]>SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq]) { - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_diff[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq]-SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq]; - } else { - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_diff[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq]-SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq]; - } - - - if(l_p==0) { - if(l_flag_p0==1) { - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_diff[l_dq]=1; - } - } - else { - if(l_flag_p1==1) { - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_diff[l_dq]=1; - } - } - - if(SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_diff[l_dq]<=1) { - binary_done_map[l_p][rank][l_n]=1; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq]; - - } - } - l_dq=l_dq+4; - } - } - rc=do_mcbist_reset(i_target); - if(rc) - { - FAPI_INF("generic_shmoo::find_bound do_mcbist_reset failed"); - return rc; - } - rc=do_mcbist_test(i_target); - if(rc) - { - FAPI_INF("generic_shmoo::find_bound do_mcbist_test failed"); - return rc; - } - - rc=check_error_map(i_target,l_p,pass); - if(rc) - { - FAPI_INF("generic_shmoo::find_bound do_mcbist_test failed"); - return rc; - } - - count_cycle++; - } - } - - for(l_p = 0; l_p < MAX_PORT; l_p++) - { - for (l_rank=0; l_rank<iv_MAX_RANKS[l_p]; l_rank++) - { - l_dq=bit; - ////// - rank=valid_rank1[l_p][l_rank]; - //printf("Valid rank of %d %d %d %d %d %d %d %d",valid_rank1[0],valid_rank1[1],valid_rank1[2],valid_rank1[3],valid_rank1[4],valid_rank1[5],valid_rank1[6],valid_rank1[7]); - - for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) { - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]); - if(rc) return rc; - l_dq=l_dq+4; - } - } - } - - } // End of LEFT - - - return rc; - } - - /*------------------------------------------------------------------------------ - * Function: knob_update_dqs - * Description : This is a key function is used to find right and left bound using new algorithm -- there is an option u can chose not to use it by setting a flag - * - * Parameters: Target:MBA,bound:RIGHT/LEFT,iv_SHMOO_ON:type of schmoo,iv_port:0/1,rank:0-7,byte:0-7,nibble:0/1,bit:0-3,pass, - * --------------------------------------------------------------------------- */ - fapi::ReturnCode generic_shmoo::knob_update_dqs_by4(const fapi::Target & i_target,bound_t bound,uint8_t scenario,uint8_t bit,uint8_t pass,bool &flag) - { - fapi::ReturnCode rc; - ecmdDataBufferBase data_buffer_64(64); - ecmdDataBufferBase data_buffer_64_1(64); - - input_type_t l_input_type_e = WR_DQ; - input_type_t l_input_type_e_dqs = WR_DQS; - uint8_t l_dq=0; - access_type_t l_access_type_e = WRITE; - uint8_t l_n=0; - uint8_t l_dqs=1; - uint8_t l_p=0; - uint8_t l_i=0; - uint16_t l_delay=0; - //uint32_t l_max=0; - uint16_t l_max_limit=500; - uint8_t rank=0; - uint8_t l_rank=0; - uint8_t l_SCHMOO_NIBBLES=20; - - uint8_t l_CDarray0[80]= {0}; - uint8_t l_CDarray1[80]= {0}; - FAPI_INF("\nWRT_DQS --- > CDIMM X4 - Scenario = %d",scenario); - - rc=do_mcbist_test(i_target); - if(rc) - { - FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed"); - return rc; - } - - rc=mcb_error_map(i_target,mcbist_error_map,l_CDarray0,l_CDarray1,count_bad_dq); - if(rc) - { - FAPI_ERR("generic_shmoo::do_mcbist_test: mcb_error_map failed!!"); - - return rc; - } - - if(iv_dmm_type==1) - { - l_SCHMOO_NIBBLES=18; - } - - - for (l_p=0; l_p<MAX_PORT; l_p++) { - for(int i=0; i<iv_MAX_RANKS[l_p]; i++) { - - rank=valid_rank1[l_p][i]; - for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) { - schmoo_error_map[l_p][rank][l_n]=0; - } - } - } - - if(bound==RIGHT) - { - - for (l_delay=1; ((pass==0)); l_delay++) { - - for (l_p=0; l_p<MAX_PORT; l_p++) { - for (l_rank=0; l_rank<iv_MAX_RANKS[l_p]; l_rank++) - { - l_dq=0; - - rank=valid_rank1[l_p][l_rank]; - for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) { - l_dq=4*l_n; - if(l_p == 0) { - - for(l_i=0; l_i<count_bad_dq[0]; l_i++) { - - if(l_CDarray0[l_i]==l_dq) { - - schmoo_error_map[l_p][rank][l_n]=1; - } - } - } else { - for(l_i=0; l_i<count_bad_dq[1]; l_i++) { - - if(l_CDarray1[l_i]==l_dq) { - - schmoo_error_map[l_p][rank][l_n]=1; - } - } - } - if(schmoo_error_map[l_p][rank][l_n]==0) { - - SHMOO[l_dqs].MBA.P[l_p].S[rank].K.rb_regval[l_n]=SHMOO[l_dqs].MBA.P[l_p].S[rank].K.nom_val[l_n]+l_delay; - - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e_dqs,l_n,0,SHMOO[l_dqs].MBA.P[l_p].S[rank].K.rb_regval[l_n]); - if(rc) return rc; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]+l_delay; - - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]); - if(rc) return rc; - l_dq=l_dq+1; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]+l_delay; - - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]); - if(rc) return rc; - l_dq=l_dq+1; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]+l_delay; - - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]); - if(rc) return rc; - l_dq=l_dq+1; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]+l_delay; - - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]); - if(rc) return rc; - } - - if(SHMOO[l_dqs].MBA.P[l_p].S[rank].K.rb_regval[l_dq] > l_max_limit) { - schmoo_error_map[l_p][rank][l_n]=1; - } - - } - - - } - - } - - rc=do_mcbist_test(i_target); - if(rc) - { - FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed"); - return rc; - } - - rc=check_error_map2(i_target,l_p,pass); - if(rc) - { - FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed"); - return rc; - } - if (l_delay > 70) - break; - } //end of delay - - - for (l_p=0; l_p<MAX_PORT; l_p++) { - for (l_rank=0; l_rank<iv_MAX_RANKS[l_p]; l_rank++) - { - - - rank=valid_rank1[l_p][l_rank]; - - for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) { - - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e_dqs,l_n,0,SHMOO[l_dqs].MBA.P[l_p].S[rank].K.nom_val[l_n]); - if(rc) return rc; - - } - } - } - for(int l_bit=0; l_bit<4; l_bit++) { - for (l_p=0; l_p<MAX_PORT; l_p++) { - for (l_rank=0; l_rank<iv_MAX_RANKS[l_p]; l_rank++) - { - l_dq=l_bit; - - rank=valid_rank1[l_p][l_rank]; - - for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) { - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]); - if(rc) return rc; - l_dq=l_dq+4; - } - } - } - } - rc=do_mcbist_test(i_target); - if(rc) - { - FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed"); - return rc; - } - - rc=mcb_error_map(i_target,mcbist_error_map,l_CDarray0,l_CDarray1,count_bad_dq); - if(rc) - { - FAPI_ERR("generic_shmoo::do_mcbist_test: mcb_error_map failed!!"); - - return rc; - } - - - - } - - if(bound==LEFT) - { - - - for (l_delay=1; (pass==0); l_delay++) { - - for (l_p=0; l_p<MAX_PORT; l_p++) { - for (l_rank=0; l_rank<iv_MAX_RANKS[l_p]; l_rank++) - { - l_dq=0; - - rank=valid_rank1[l_p][l_rank]; - - for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) { - l_dq=4*l_n; - - if(l_p == 0) { - - for(l_i=0; l_i<count_bad_dq[0]; l_i++) { - - if(l_CDarray0[l_i]==l_dq) { - - schmoo_error_map[l_p][rank][l_n]=1; - } - } - } else { - for(l_i=0; l_i<count_bad_dq[1]; l_i++) { - - if(l_CDarray1[l_i]==l_dq) { - - schmoo_error_map[l_p][rank][l_n]=1; - } - } - } - if(schmoo_error_map[l_p][rank][l_n]==0) { - SHMOO[l_dqs].MBA.P[l_p].S[rank].K.lb_regval[l_n]=SHMOO[l_dqs].MBA.P[l_p].S[rank].K.nom_val[l_n]-l_delay; - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e_dqs,l_n,0,SHMOO[l_dqs].MBA.P[l_p].S[rank].K.lb_regval[l_n]); - if(rc) return rc; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]-l_delay; - - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]); - if(rc) return rc; - l_dq=l_dq+1; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]-l_delay; - - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]); - if(rc) return rc; - l_dq=l_dq+1; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]-l_delay; - - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]); - if(rc) return rc; - l_dq=l_dq+1; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]-l_delay; - - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]); - if(rc) return rc; - } - if(SHMOO[l_dqs].MBA.P[l_p].S[rank].K.lb_regval[l_n] == 0) { - schmoo_error_map[l_p][rank][l_n] = 1; - } - - - - } - } - - } - rc=do_mcbist_test(i_target); - if(rc) - { - FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed"); - return rc; - } - - rc=check_error_map2(i_target,l_p,pass); - if(rc) - { - FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed"); - return rc; - } - if (l_delay > 70) - break; - - } - - - for (l_p=0; l_p<MAX_PORT; l_p++) { - for (l_rank=0; l_rank<iv_MAX_RANKS[l_p]; l_rank++) - { - rank=valid_rank1[l_p][l_rank]; - for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) { - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e_dqs,l_n,0,SHMOO[l_dqs].MBA.P[l_p].S[rank].K.nom_val[l_n]); - if(rc) return rc; - - } - } - } - - for(int l_bit=0; l_bit<4; l_bit++) { - for (l_p=0; l_p<MAX_PORT; l_p++) { - for (l_rank=0; l_rank<iv_MAX_RANKS[l_p]; l_rank++) - { - l_dq=l_bit; - rank=valid_rank1[l_p][l_rank]; - for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) { - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]); - if(rc) return rc; - l_dq=l_dq+4; - } - } - } - } - - rc=do_mcbist_test(i_target); - if(rc) - { - FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed"); - return rc; - } - - rc=mcb_error_map(i_target,mcbist_error_map,l_CDarray0,l_CDarray1,count_bad_dq); - if(rc) - { - FAPI_ERR("generic_shmoo::do_mcbist_test: mcb_error_map failed!!"); - return rc; - } - } - return rc; - } - fapi::ReturnCode generic_shmoo::knob_update_dqs_by4_isdimm(const fapi::Target & i_target,bound_t bound,uint8_t scenario,uint8_t bit,uint8_t pass,bool &flag) - { - fapi::ReturnCode rc; - ecmdDataBufferBase data_buffer_64(64); - ecmdDataBufferBase data_buffer_64_1(64); - //uint8_t l_rp=0; - input_type_t l_input_type_e = WR_DQ; - input_type_t l_input_type_e_dqs = WR_DQS; - uint8_t l_dq=0; - access_type_t l_access_type_e = WRITE; - uint8_t l_n=0; - uint8_t l_dqs=1; - uint8_t l_my_dqs=0; - uint8_t l_CDarray0[80]= {0}; - uint8_t l_CDarray1[80]= {0}; - uint8_t l_p=0; - uint16_t l_delay=0; - uint16_t l_max_limit=500; - uint8_t rank=0; - uint8_t l_rank=0; - uint8_t l_SCHMOO_NIBBLES=20; - //uint8_t i_rp=0; - - rc=do_mcbist_test(i_target); - if(rc) - { - FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed"); - return rc; - } - - rc=mcb_error_map(i_target,mcbist_error_map,l_CDarray0,l_CDarray1,count_bad_dq); - if(rc) - { - FAPI_ERR("generic_shmoo::do_mcbist_test: mcb_error_map failed!!"); - - return rc; - } - - if(iv_dmm_type==1) - { - l_SCHMOO_NIBBLES=18; - } - uint8_t l_dqs_arr[18]= {0,9,1,10,2,11,3,12,4,13,5,14,6,15,7,16,8,17}; - - - for (l_p=0; l_p<MAX_PORT; l_p++) { - for(int i=0; i<iv_MAX_RANKS[l_p]; i++) { - - rank=valid_rank1[l_p][i]; - for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) { - schmoo_error_map[l_p][rank][l_n]=0; - } - } - } - - - - if(bound==RIGHT) - { - - for (l_delay=1; ((pass==0)); l_delay++) { - for (l_p=0; l_p<MAX_PORT; l_p++) { - for (l_rank=0; l_rank<iv_MAX_RANKS[l_p]; l_rank++) - { - l_dq=0; - l_my_dqs=0; - - rank=valid_rank1[l_p][l_rank]; - for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) { - l_dq=4*l_n; - l_my_dqs=l_dqs_arr[l_n]; - if(schmoo_error_map[l_p][rank][l_n]==0) { - - SHMOO[l_dqs].MBA.P[l_p].S[rank].K.rb_regval[l_my_dqs]=SHMOO[l_dqs].MBA.P[l_p].S[rank].K.nom_val[l_my_dqs]+l_delay; - - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e_dqs,l_my_dqs,0,SHMOO[l_dqs].MBA.P[l_p].S[rank].K.rb_regval[l_my_dqs]); - if(rc) return rc; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]+l_delay; - - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]); - if(rc) return rc; - l_dq=l_dq+1; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]+l_delay; - - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]); - if(rc) return rc; - l_dq=l_dq+1; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]+l_delay; - - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]); - if(rc) return rc; - l_dq=l_dq+1; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]+l_delay; - - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]); - if(rc) return rc; - } - - if(SHMOO[l_dqs].MBA.P[l_p].S[rank].K.rb_regval[l_dq]>l_max_limit) { - schmoo_error_map[l_p][rank][l_n]=1; - } - } //end of nibble loop - } //end of rank - } //end of port - - rc=do_mcbist_test(i_target); - if(rc) - { - FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed"); - return rc; - } - - rc=check_error_map2(i_target,l_p,pass); - if(rc) - { - FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed"); - return rc; - } - if (l_delay > 70) - break; - - } //end of delay loop - - ////////////////////////////////////////////////////////////// - - for (l_p=0; l_p<MAX_PORT; l_p++) { - for (l_rank=0; l_rank<iv_MAX_RANKS[l_p]; l_rank++) - { - rank=valid_rank1[l_p][l_rank]; - for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) { - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e_dqs,l_n,0,SHMOO[l_dqs].MBA.P[l_p].S[rank].K.nom_val[l_n]); - if(rc) return rc; - } - } - } - - for(int l_bit=0; l_bit<4; l_bit++) { - for (l_p=0; l_p<MAX_PORT; l_p++) { - for (l_rank=0; l_rank<iv_MAX_RANKS[l_p]; l_rank++) - { - l_dq=l_bit; - rank=valid_rank1[l_p][l_rank]; - for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) { - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]); - if(rc) return rc; - l_dq=l_dq+4; - } - } //end of rank - } //end of port - } //end of bit - - rc=do_mcbist_test(i_target); - if(rc) - { - FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed"); - return rc; - } - - rc=mcb_error_map(i_target,mcbist_error_map,l_CDarray0,l_CDarray1,count_bad_dq); - if(rc) - { - FAPI_ERR("generic_shmoo::do_mcbist_test: mcb_error_map failed!!"); - - return rc; - } - } - - if(bound==LEFT) - { - for (l_delay=1; (pass==0); l_delay++) { - for (l_p=0; l_p<MAX_PORT; l_p++) { - for (l_rank=0; l_rank<iv_MAX_RANKS[l_p]; l_rank++) - { - l_dq=0; - l_my_dqs=0; - - rank=valid_rank1[l_p][l_rank]; - for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) { - l_dq=4*l_n; - l_my_dqs=l_dqs_arr[l_n]; - - if(schmoo_error_map[l_p][rank][l_n]==0) { - SHMOO[l_dqs].MBA.P[l_p].S[rank].K.lb_regval[l_my_dqs]=SHMOO[l_dqs].MBA.P[l_p].S[rank].K.nom_val[l_my_dqs]-l_delay; - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e_dqs,l_my_dqs,0,SHMOO[l_dqs].MBA.P[l_p].S[rank].K.lb_regval[l_my_dqs]); - if(rc) return rc; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]-l_delay; - - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]); - if(rc) return rc; - l_dq=l_dq+1; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]-l_delay; - - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]); - if(rc) return rc; - l_dq=l_dq+1; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]-l_delay; - - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]); - if(rc) return rc; - l_dq=l_dq+1; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]-l_delay; - - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]); - if(rc) return rc; - } - - if(SHMOO[l_dqs].MBA.P[l_p].S[rank].K.lb_regval[l_dq] == 0) { - schmoo_error_map[l_p][rank][l_n] = 1; - } - } - } - } - - rc=do_mcbist_test(i_target); - if(rc) - { - FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed"); - return rc; - } - - rc=check_error_map2(i_target,l_p,pass); - if(rc) - { - FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed"); - return rc; - } - if (l_delay > 70) - break; - } //end of delay loop - - - for (l_p=0; l_p<MAX_PORT; l_p++) { - for (l_rank=0; l_rank<iv_MAX_RANKS[l_p]; l_rank++) - { - rank=valid_rank1[l_p][l_rank]; - for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) { - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e_dqs,l_n,0,SHMOO[l_dqs].MBA.P[l_p].S[rank].K.nom_val[l_n]); - if(rc) return rc; - } - } - } - - for(int l_bit=0; l_bit<4; l_bit++) { - for (l_p=0; l_p<MAX_PORT; l_p++) { - for (l_rank=0; l_rank<iv_MAX_RANKS[l_p]; l_rank++) - { - l_dq=l_bit; - rank=valid_rank1[l_p][l_rank]; - for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) { - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]); - if(rc) return rc; - l_dq=l_dq+4; - } //end of nibble - } //end of rank - } //port loop - } //bit loop - - rc=do_mcbist_test(i_target); - if(rc) - { - FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed"); - return rc; - } - - rc=mcb_error_map(i_target,mcbist_error_map,l_CDarray0,l_CDarray1,count_bad_dq); - if(rc) - { - FAPI_ERR("generic_shmoo::do_mcbist_test: mcb_error_map failed!!"); - - return rc; - } - } //end of Left - return rc; - } - - fapi::ReturnCode generic_shmoo::knob_update_dqs_by8(const fapi::Target & i_target,bound_t bound,uint8_t scenario,uint8_t bit,uint8_t pass,bool &flag) - { - fapi::ReturnCode rc; - ecmdDataBufferBase data_buffer_64(64); - ecmdDataBufferBase data_buffer_64_1(64); - //uint8_t l_rp=0; - input_type_t l_input_type_e = WR_DQ; - input_type_t l_input_type_e_dqs = WR_DQS; - uint8_t l_dq=0; - uint8_t l_dqs=0; - access_type_t l_access_type_e = WRITE; - uint8_t l_n=0; - uint8_t l_scen_dqs=1; - uint8_t l_CDarray0[80]= {0}; - uint8_t l_CDarray1[80]= {0}; - uint8_t l_p=0; - uint16_t l_delay=0; - uint16_t l_max_limit=500; - uint8_t rank=0; - uint8_t l_rank=0; - uint8_t l_SCHMOO_NIBBLES=20; - - FAPI_INF("\nWRT_DQS --- > CDIMM X8 - Scenario = %d",scenario); - rc=do_mcbist_test(i_target); - if(rc) - { - FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed"); - return rc; - } - - rc=mcb_error_map(i_target,mcbist_error_map,l_CDarray0,l_CDarray1,count_bad_dq); - if(rc) - { - FAPI_ERR("generic_shmoo::do_mcbist_test: mcb_error_map failed!!"); - return rc; - } - - if(iv_dmm_type==1) - { - l_SCHMOO_NIBBLES=18; - } - - for (l_p=0; l_p<MAX_PORT; l_p++) { - for(int i=0; i<iv_MAX_RANKS[l_p]; i++) { - - rank=valid_rank1[l_p][i]; - for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) { - schmoo_error_map[l_p][rank][l_n]=0; - } //end of nib - } //end of rank - } //end of port loop - - if(bound==RIGHT) - { - for (l_delay=1; ((pass==0)); l_delay++) { - for (l_p=0; l_p<MAX_PORT; l_p++) { - for (l_rank=0; l_rank<iv_MAX_RANKS[l_p]; l_rank++) - { - l_dq=0; - l_dqs=0; - - rank=valid_rank1[l_p][l_rank]; - for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) { - l_dq=4*l_n; - if((schmoo_error_map[l_p][rank][l_n]==0)&&(schmoo_error_map[l_p][rank][l_n+1]==0)) { - //Increase delay of DQS - SHMOO[l_scen_dqs].MBA.P[l_p].S[rank].K.rb_regval[l_n]=SHMOO[l_scen_dqs].MBA.P[l_p].S[rank].K.nom_val[l_n]+l_delay; - //Write it to register DQS delay - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e_dqs,l_n,0,SHMOO[l_scen_dqs].MBA.P[l_p].S[rank].K.rb_regval[l_n]); - if(rc) return rc; - - //Increase Delay of DQ - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]+l_delay; - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]); - if(rc) return rc; - - l_dq=l_dq+1; - - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]+l_delay; - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]); - if(rc) return rc; - l_dq=l_dq+1; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]+l_delay; - - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]); - if(rc) return rc; - l_dq=l_dq+1; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]+l_delay; - - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]); - if(rc) return rc; - l_dq=l_dq+1; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]+l_delay; - - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]); - if(rc) return rc; - l_dq=l_dq+1; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]+l_delay; - - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]); - if(rc) return rc; - l_dq=l_dq+1; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]+l_delay; - - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]); - if(rc) return rc; - l_dq=l_dq+1; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]+l_delay; - - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]); - if(rc) return rc; - - } - - if(SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq] > l_max_limit) { - schmoo_error_map[l_p][rank][l_n]=1; - schmoo_error_map[l_p][rank][l_n+1]=1; - } - - if((schmoo_error_map[l_p][rank][l_n]==1)||(schmoo_error_map[l_p][rank][l_n+1]==1)) { - - schmoo_error_map[l_p][rank][l_n]=1; - schmoo_error_map[l_p][rank][l_n+1]=1; - } - l_n=l_n+1; - l_dqs=l_dqs+1; - - } //end of nibble loop - } //end of rank loop - } //end of port loop - - - rc=do_mcbist_test(i_target); - if(rc) - { - FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed"); - return rc; - } - - rc=check_error_map2(i_target,l_p,pass); - if(rc) - { - FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed"); - return rc; - } - if (l_delay > 70) - break; - } //end of delay loop - - - for (l_p=0; l_p<MAX_PORT; l_p++) { - for (l_rank=0; l_rank<iv_MAX_RANKS[l_p]; l_rank++) - { rank=valid_rank1[l_p][l_rank]; - for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) { - - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e_dqs,l_n,0,SHMOO[l_scen_dqs].MBA.P[l_p].S[rank].K.nom_val[l_n]); - if(rc) return rc; - - } //end of nib - } //end of rank - } //end of port loop - - for(int l_bit=0; l_bit<4; l_bit++) { - for (l_p=0; l_p<MAX_PORT; l_p++) { - for (l_rank=0; l_rank<iv_MAX_RANKS[l_p]; l_rank++) - { - l_dq=l_bit; - rank=valid_rank1[l_p][l_rank]; - for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) { - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]); - if(rc) return rc; - l_dq=l_dq+4; - } //end of nib - } //end of rank - } //end of port loop - } //end of bit loop - - rc=do_mcbist_test(i_target); - if(rc) - { - FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed"); - return rc; - } - - rc=mcb_error_map(i_target,mcbist_error_map,l_CDarray0,l_CDarray1,count_bad_dq); - if(rc) - { - FAPI_ERR("generic_shmoo::do_mcbist_test: mcb_error_map failed!!"); - - return rc; - } - } - - if(bound==LEFT) - { - for (l_delay=1; (pass==0); l_delay++) { - for (l_p=0; l_p<MAX_PORT; l_p++) { - for (l_rank=0; l_rank<iv_MAX_RANKS[l_p]; l_rank++) - { - l_dq=0; - l_dqs=0; - - rank=valid_rank1[l_p][l_rank]; - - for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) { - l_dq=4*l_n; - - - - if((schmoo_error_map[l_p][rank][l_n]==0)&&(schmoo_error_map[l_p][rank][l_n+1]==0)) { - SHMOO[l_scen_dqs].MBA.P[l_p].S[rank].K.lb_regval[l_n]=SHMOO[l_scen_dqs].MBA.P[l_p].S[rank].K.nom_val[l_n]-l_delay; - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e_dqs,l_n,0,SHMOO[l_scen_dqs].MBA.P[l_p].S[rank].K.lb_regval[l_n]); - if(rc) return rc; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]-l_delay; - - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]); - if(rc) return rc; - l_dq=l_dq+1; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]-l_delay; - - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]); - if(rc) return rc; - l_dq=l_dq+1; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]-l_delay; - - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]); - if(rc) return rc; - l_dq=l_dq+1; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]-l_delay; - - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]); - if(rc) return rc; - l_dq=l_dq+1; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]-l_delay; - - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]); - if(rc) return rc; - l_dq=l_dq+1; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]-l_delay; - - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]); - if(rc) return rc; - l_dq=l_dq+1; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]-l_delay; - - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]); - if(rc) return rc; - l_dq=l_dq+1; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]-l_delay; - - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]); - if(rc) return rc; - } - if(SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq] == 0) { - schmoo_error_map[l_p][rank][l_n] = 1; - schmoo_error_map[l_p][rank][l_n+1] = 1; - } - - if((schmoo_error_map[l_p][rank][l_n]==1)||(schmoo_error_map[l_p][rank][l_n+1]==1)) { - - schmoo_error_map[l_p][rank][l_n]=1; - schmoo_error_map[l_p][rank][l_n+1]=1; - } - - l_n=l_n+1; - l_dqs=l_dq+1; - - } //nibble loop - } //rank loop - } //port loop - - rc=do_mcbist_test(i_target); - if(rc) - { - FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed"); - return rc; - } - - rc=check_error_map2(i_target,l_p,pass); - if(rc) - { - FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed"); - return rc; - } - if (l_delay > 70) - break; - - } //end of l delay loop - - - for (l_p=0; l_p<MAX_PORT; l_p++) { - for (l_rank=0; l_rank<iv_MAX_RANKS[l_p]; l_rank++) - { - rank=valid_rank1[l_p][l_rank]; - for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) { - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e_dqs,l_n,0,SHMOO[l_scen_dqs].MBA.P[l_p].S[rank].K.nom_val[l_n]); - if(rc) return rc; - - } - } - } - - for(int l_bit=0; l_bit<4; l_bit++) { - for (l_p=0; l_p<MAX_PORT; l_p++) { - for (l_rank=0; l_rank<iv_MAX_RANKS[l_p]; l_rank++) - { - l_dq=l_bit; - rank=valid_rank1[l_p][l_rank]; - for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) { - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]); - if(rc) return rc; - l_dq=l_dq+4; - } - } - } - } - - rc=do_mcbist_test(i_target); - if(rc) - { - FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed"); - return rc; - } - - rc=mcb_error_map(i_target,mcbist_error_map,l_CDarray0,l_CDarray1,count_bad_dq); - if(rc) - { - FAPI_ERR("generic_shmoo::do_mcbist_test: mcb_error_map failed!!"); - - return rc; - } - } //end of bound Left - - return rc; - } - fapi::ReturnCode generic_shmoo::knob_update_dqs_by8_isdimm(const fapi::Target & i_target,bound_t bound,uint8_t scenario,uint8_t bit,uint8_t pass,bool &flag) - { - fapi::ReturnCode rc; - ecmdDataBufferBase data_buffer_64(64); - ecmdDataBufferBase data_buffer_64_1(64); - //uint8_t l_rp=0; - input_type_t l_input_type_e = WR_DQ; - input_type_t l_input_type_e_dqs = WR_DQS; - uint8_t l_dq=0; - uint8_t l_dqs=0; - access_type_t l_access_type_e = WRITE; - uint8_t l_n=0; - uint8_t l_scen_dqs=1; - uint8_t l_CDarray0[80]= {0}; - uint8_t l_CDarray1[80]= {0}; - uint8_t l_p=0; - uint16_t l_delay=0; - uint16_t l_max_limit=500; - uint8_t rank=0; - uint8_t l_rank=0; - uint8_t l_SCHMOO_NIBBLES=20; - //uint8_t i_rp=0; - - rc=do_mcbist_test(i_target); - if(rc) - { - FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed"); - return rc; - } - - rc=mcb_error_map(i_target,mcbist_error_map,l_CDarray0,l_CDarray1,count_bad_dq); - if(rc) - { - FAPI_ERR("generic_shmoo::do_mcbist_test: mcb_error_map failed!!"); - - return rc; - } - - if(iv_dmm_type==1) - { - - l_SCHMOO_NIBBLES=18; - } - - - for (l_p=0; l_p<MAX_PORT; l_p++) { - for(int i=0; i<iv_MAX_RANKS[l_p]; i++) { - - rank=valid_rank1[l_p][i]; - for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) { - schmoo_error_map[l_p][rank][l_n]=0; - } - } - } - - if(bound==RIGHT) - { - - for (l_delay=1; ((pass==0)); l_delay++) { - for (l_p=0; l_p<MAX_PORT; l_p++) { - for (l_rank=0; l_rank<iv_MAX_RANKS[l_p]; l_rank++) - { - l_dq=0; - l_dqs=0; - rank=valid_rank1[l_p][l_rank]; - for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) { - l_dq=4*l_n; - l_dqs=l_n/2; - - if((schmoo_error_map[l_p][rank][l_n]==0)&&(schmoo_error_map[l_p][rank][l_n+1]==0)) { - - SHMOO[l_scen_dqs].MBA.P[l_p].S[rank].K.rb_regval[l_dqs]=SHMOO[l_scen_dqs].MBA.P[l_p].S[rank].K.nom_val[l_dqs]+l_delay; - - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e_dqs,l_dqs,0,SHMOO[l_scen_dqs].MBA.P[l_p].S[rank].K.rb_regval[l_dqs]); - if(rc) return rc; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]+l_delay; - - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]); - if(rc) return rc; - l_dq=l_dq+1; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]+l_delay; - - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]); - if(rc) return rc; - l_dq=l_dq+1; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]+l_delay; - - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]); - if(rc) return rc; - l_dq=l_dq+1; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]+l_delay; - - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]); - if(rc) return rc; - l_dq=l_dq+1; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]+l_delay; - - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]); - if(rc) return rc; - l_dq=l_dq+1; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]+l_delay; - - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]); - if(rc) return rc; - l_dq=l_dq+1; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]+l_delay; - - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]); - if(rc) return rc; - l_dq=l_dq+1; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]+l_delay; - - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]); - if(rc) return rc; - - } - - if(SHMOO[l_scen_dqs].MBA.P[l_p].S[rank].K.rb_regval[l_dqs]>l_max_limit) { - - schmoo_error_map[l_p][rank][l_n]=1; - schmoo_error_map[l_p][rank][l_n+1]=1; - } - - if((schmoo_error_map[l_p][rank][l_n]==1)||(schmoo_error_map[l_p][rank][l_n+1]==1)) { - - schmoo_error_map[l_p][rank][l_n]=1; - schmoo_error_map[l_p][rank][l_n+1]=1; - } - - l_n=l_n+1; - - } - - - } - - } - rc=do_mcbist_test(i_target); - if(rc) - { - FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed"); - return rc; - } - - rc=check_error_map2(i_target,l_p,pass); - if(rc) - { - FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed"); - return rc; - } - if (l_delay > 70) - break; - } - - - for (l_p=0; l_p<MAX_PORT; l_p++) { - for (l_rank=0; l_rank<iv_MAX_RANKS[l_p]; l_rank++) - { - rank=valid_rank1[l_p][l_rank]; - for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) { - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e_dqs,l_n,0,SHMOO[l_scen_dqs].MBA.P[l_p].S[rank].K.nom_val[l_n]); - if(rc) return rc; - } - } - } - - for(int l_bit=0; l_bit<4; l_bit++) { - for (l_p=0; l_p<MAX_PORT; l_p++) { - for (l_rank=0; l_rank<iv_MAX_RANKS[l_p]; l_rank++) - { - l_dq=l_bit; - rank=valid_rank1[l_p][l_rank]; - for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) { - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]); - if(rc) return rc; - l_dq=l_dq+4; - } - } - } - } - - rc=do_mcbist_test(i_target); - if(rc) - { - FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed"); - return rc; - } - - rc=mcb_error_map(i_target,mcbist_error_map,l_CDarray0,l_CDarray1,count_bad_dq); - if(rc) - { - FAPI_ERR("generic_shmoo::do_mcbist_test: mcb_error_map failed!!"); - - return rc; - } - - } - - if(bound==LEFT) - { - - for (l_delay=1; (pass==0); l_delay++) { - for (l_p=0; l_p<MAX_PORT; l_p++) { - for (l_rank=0; l_rank<iv_MAX_RANKS[l_p]; l_rank++) - { - l_dq=0; - l_dqs=0; - rank=valid_rank1[l_p][l_rank]; - for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) { - l_dq=4*l_n; - - l_dqs=l_n/2; - - if((schmoo_error_map[l_p][rank][l_n]==0)&&(schmoo_error_map[l_p][rank][l_n+1]==0)) { - SHMOO[l_scen_dqs].MBA.P[l_p].S[rank].K.lb_regval[l_dqs]=SHMOO[l_scen_dqs].MBA.P[l_p].S[rank].K.nom_val[l_dqs]-l_delay; - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e_dqs,l_dqs,0,SHMOO[l_scen_dqs].MBA.P[l_p].S[rank].K.lb_regval[l_dqs]); - if(rc) return rc; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]-l_delay; - - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]); - if(rc) return rc; - l_dq=l_dq+1; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]-l_delay; - - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]); - if(rc) return rc; - l_dq=l_dq+1; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]-l_delay; - - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]); - if(rc) return rc; - l_dq=l_dq+1; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]-l_delay; - - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]); - if(rc) return rc; - l_dq=l_dq+1; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]-l_delay; - - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]); - if(rc) return rc; - l_dq=l_dq+1; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]-l_delay; - - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]); - if(rc) return rc; - l_dq=l_dq+1; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]-l_delay; - - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]); - if(rc) return rc; - l_dq=l_dq+1; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]-l_delay; - - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]); - if(rc) return rc; - } - if(SHMOO[l_scen_dqs].MBA.P[l_p].S[rank].K.lb_regval[l_dqs] == 0) { - schmoo_error_map[l_p][rank][l_n] = 1; - schmoo_error_map[l_p][rank][l_n+1] = 1; - } - - if((schmoo_error_map[l_p][rank][l_n]==1)||(schmoo_error_map[l_p][rank][l_n+1]==1)) { - - schmoo_error_map[l_p][rank][l_n]=1; - schmoo_error_map[l_p][rank][l_n+1]=1; - } - - l_n=l_n+1; - - } //nibble loop - } //rank loop - } //port loop - - rc=do_mcbist_test(i_target); - if(rc) - { - FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed"); - return rc; - } - - rc=check_error_map2(i_target,l_p,pass); - if(rc) - { - FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed"); - return rc; - } - if (l_delay > 70) - break; - - } - - - for (l_p=0; l_p<MAX_PORT; l_p++) { - for (l_rank=0; l_rank<iv_MAX_RANKS[l_p]; l_rank++) - { - rank=valid_rank[l_rank]; - for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) { - - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e_dqs,l_n,0,SHMOO[l_scen_dqs].MBA.P[l_p].S[rank].K.nom_val[l_n]); - if(rc) return rc; - - } - } - } - - for(int l_bit=0; l_bit<4; l_bit++) { - for (l_p=0; l_p<MAX_PORT; l_p++) { - for (l_rank=0; l_rank<iv_MAX_RANKS[l_p]; l_rank++) - { - l_dq=l_bit; - - rank=valid_rank1[l_p][l_rank]; - for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) { - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]); - if(rc) return rc; - l_dq=l_dq+4; - } - } //rank loop - } //port loop - } //bit loop - - rc=do_mcbist_test(i_target); - if(rc) - { - FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed"); - return rc; - } - - rc=mcb_error_map(i_target,mcbist_error_map,l_CDarray0,l_CDarray1,count_bad_dq); - if(rc) - { - FAPI_ERR("generic_shmoo::do_mcbist_test: mcb_error_map failed!!"); - - return rc; - } - - } //end of LEFT - - return rc; - } - - ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - /*------------------------------------------------------------------------------ - * Function: find_bound - * Description : This function calls the knob_update for each DQ which is used to find bound that is left/right according to schmoo type - * - * Parameters: Target:MBA,bound:RIGHT/LEFT, - * ---------------------------------------------------------------------------*/ - fapi::ReturnCode generic_shmoo::find_bound(const fapi::Target & i_target, - bound_t bound) - { - uint8_t l_bit = 0; - fapi::ReturnCode rc; - uint8_t l_comp = 0; - uint8_t pass = 0; - uint8_t l_dram_width = 0; - bool flag = false; - - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target, l_dram_width); - if (rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_SCHMOO_MODE, &i_target, l_comp); - if(rc) return rc; - - FAPI_INF("%s:\n SCHMOO IS IN PROGRESS ...... \n", i_target.toEcmdString()); - - //WRT_DQS Portion - if(iv_DQS_ON == 1) - { - rc=do_mcbist_reset(i_target); - if(rc) - { - FAPI_ERR("generic_shmoo::find_bound do_mcbist_reset failed"); - return rc; - } - pass=0; - if(l_dram_width == 4) { - if(iv_dmm_type==1) - { - rc=knob_update_dqs_by4_isdimm(i_target,bound,iv_shmoo_type,l_bit,pass,flag); - if(rc) return rc; - } - else { - rc=knob_update_dqs_by4(i_target,bound,iv_shmoo_type,l_bit,pass,flag); - if(rc) return rc; - } - } //end of if dram_width 4 - else { - if(iv_dmm_type==1) - { - rc=knob_update_dqs_by8_isdimm(i_target,bound,iv_shmoo_type,l_bit,pass,flag); - if(rc) return rc; - } - else { - rc=knob_update_dqs_by8(i_target,bound,iv_shmoo_type,l_bit,pass,flag); - if(rc) return rc; - } - } - } //end of if iv_DQS_ON 1 or WRT_DQS - - else if(l_comp == 6) { - pass=0; - rc=knob_update_bin_composite(i_target,bound,iv_shmoo_type,l_bit,pass,flag); - if(rc) return rc; - } - else - { - //Bit loop - for (l_bit = 0; l_bit < MAX_BITS; l_bit++) - { - // preetham function here - pass = 0; - - //////////////////////////////////////////////////////////////////////////////////// - if (l_comp == 4) - { - FAPI_INF("Calling Binary - %d",iv_shmoo_type); - rc = knob_update_bin(i_target, bound, iv_shmoo_type, l_bit, pass, flag); - if (rc) return rc; - } - else - { - - - rc = knob_update(i_target, bound, iv_shmoo_type, l_bit, pass, flag); - if (rc) return rc; - } - } - } - - return rc; - } - /*------------------------------------------------------------------------------ - * Function: print_report - * Description : This function is used to print the information needed such as freq,voltage etc, and also the right,left and total margin - * - * Parameters: Target:MBA - * ---------------------------------------------------------------------------*/ - fapi::ReturnCode generic_shmoo::print_report(const fapi::Target & i_target) - { - fapi::ReturnCode rc; - - uint8_t l_rnk,l_byte,l_nibble,l_bit; - uint8_t l_dq=0; - //uint8_t l_rp=0; - uint8_t l_p=0; - uint8_t i_rank=0; - uint8_t l_mbapos = 0; - uint32_t l_attr_mss_freq_u32 = 0; - uint32_t l_attr_mss_volt_u32 = 0; - uint8_t l_attr_eff_dimm_type_u8 = 0; - uint8_t l_attr_eff_num_drops_per_port_u8 = 0; - uint8_t l_attr_eff_dram_width_u8 = 0; - - fapi::Target l_target_centaur; - - - rc = fapiGetParentChip(i_target, l_target_centaur); - if(rc) return rc; - - rc = FAPI_ATTR_GET(ATTR_MSS_FREQ, &l_target_centaur, l_attr_mss_freq_u32); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_MSS_VOLT, &l_target_centaur, l_attr_mss_volt_u32); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_CUSTOM_DIMM, &i_target, l_attr_eff_dimm_type_u8); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_NUM_DROPS_PER_PORT, &i_target, l_attr_eff_num_drops_per_port_u8); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target, l_attr_eff_dram_width_u8); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target, l_mbapos); - if(rc) return rc; - - - - FAPI_INF("%s:freq = %d on %s.",i_target.toEcmdString(),l_attr_mss_freq_u32, l_target_centaur.toEcmdString()); - FAPI_INF("%s: volt = %d on %s.",i_target.toEcmdString(), l_attr_mss_volt_u32, l_target_centaur.toEcmdString()); - FAPI_INF("%s: dimm_type = %d on %s.",i_target.toEcmdString(), l_attr_eff_dimm_type_u8, i_target.toEcmdString()); - if ( l_attr_eff_dimm_type_u8 == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES ) - { - FAPI_INF("%s: It is a CDIMM",i_target.toEcmdString()); - } - else - { - FAPI_INF("%s: It is an ISDIMM",i_target.toEcmdString()); - } - FAPI_INF("%s: \n Number of ranks on port = 0 is %d ",i_target.toEcmdString(),iv_MAX_RANKS[0]); - FAPI_INF("%s: \n Number of ranks on port = 1 is %d \n \n",i_target.toEcmdString(),iv_MAX_RANKS[1]); - FAPI_INF("%s:+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++",i_target.toEcmdString()); - //// Based on schmoo param the print will change eventually - if(iv_shmoo_type==2) - { - FAPI_INF("%s:Schmoo POS\tPort\tRank\tByte\tnibble\tbit\tNominal\t\tSetup_Limit\tHold_Limit\tWrD_Setup(ps)\tWrD_Hold(ps)\tEye_Width(ps)\tBitRate\tVref_Multiplier ",i_target.toEcmdString()); - } - else { - FAPI_INF("%s:Schmoo POS\tPort\tRank\tByte\tnibble\tbit\tNominal\t\tSetup_Limit\tHold_Limit\tRdD_Setup(ps)\tRdD_Hold(ps)\tEye_Width(ps)\tBitRate\tVref_Multiplier ",i_target.toEcmdString()); - } - - - for (l_p=0; l_p < 2; l_p++) { - for (l_rnk=0; l_rnk < iv_MAX_RANKS[l_p]; l_rnk++) - { i_rank = valid_rank1[l_p][l_rnk]; - for(l_byte=0; l_byte < 10; l_byte++) - { - - //Nibble loop - for(l_nibble=0; l_nibble< 2; l_nibble++) - { - for(l_bit=0; l_bit< 4; l_bit++) - { - l_dq=8*l_byte+4*l_nibble+l_bit; - - if(iv_shmoo_type==2) - { - FAPI_INF("%s:WR_EYE %d\t%d\t%d\t%d\t%d\t%d\t%d\t\t%d\t\t%d\t\t%d\t\t%d\t\t%d\t\t%d\t\t%d\n ",i_target.toEcmdString(),l_mbapos,l_p,i_rank,l_byte,l_nibble,l_bit,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.nom_val[l_dq],SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.rb_regval[l_dq],SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.lb_regval[l_dq],SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.right_margin_val[l_dq],SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.left_margin_val[l_dq],SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.total_margin[l_dq],l_attr_mss_freq_u32,iv_vref_mul); - } - if(iv_shmoo_type==8) - { - FAPI_INF("%s:RD_EYE %d\t%d\t%d\t%d\t%d\t%d\t%d\t\t%d\t\t%d\t\t%d\t\t%d\t\t%d\t\t%d\t\t%d\n ",i_target.toEcmdString(),l_mbapos,l_p,i_rank,l_byte,l_nibble,l_bit,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.nom_val[l_dq],SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.lb_regval[l_dq],SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.rb_regval[l_dq],SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.left_margin_val[l_dq],SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.right_margin_val[l_dq],SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.total_margin[l_dq],l_attr_mss_freq_u32,iv_vref_mul); - } - - } - } - } - } - } - - return rc; - } - - fapi::ReturnCode generic_shmoo::print_report_dqs(const fapi::Target & i_target) - { - fapi::ReturnCode rc; - - uint8_t l_rnk, l_nibble; - uint8_t l_p = 0; - uint8_t i_rank = 0; - uint8_t l_mbapos = 0; - uint16_t l_total_margin = 0; - uint32_t l_attr_mss_freq_u32 = 0; - uint32_t l_attr_mss_volt_u32 = 0; - uint8_t l_attr_eff_dimm_type_u8 = 0; - uint8_t l_attr_eff_num_drops_per_port_u8 = 0; - uint8_t l_attr_eff_dram_width_u8 = 0; - fapi::Target l_target_centaur; - uint8_t l_SCHMOO_NIBBLES = 20; - uint8_t l_by8_dqs = 0; - char * l_pMike = new char[128]; - char * l_str = new char[128]; - - uint8_t l_i = 0; - uint8_t l_dq = 0; - uint8_t l_flag = 0; - uint8_t l_CDarray0[80] = { 0 }; - uint8_t l_CDarray1[80] = { 0 }; - - rc = mcb_error_map(i_target, mcbist_error_map, l_CDarray0, l_CDarray1, - count_bad_dq); - if (rc) - { - FAPI_ERR("generic_shmoo::print report: mcb_error_map failed!!"); - return rc; - } - - if (iv_dmm_type == 1) - { - l_SCHMOO_NIBBLES = 18; - } - - rc = fapiGetParentChip(i_target, l_target_centaur); - if (rc) return rc; - - rc = FAPI_ATTR_GET(ATTR_MSS_FREQ, &l_target_centaur, l_attr_mss_freq_u32); - if (rc) return rc; - rc = FAPI_ATTR_GET(ATTR_MSS_VOLT, &l_target_centaur, l_attr_mss_volt_u32); - if (rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_CUSTOM_DIMM, &i_target, l_attr_eff_dimm_type_u8); - if (rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_NUM_DROPS_PER_PORT, &i_target, - l_attr_eff_num_drops_per_port_u8); - if (rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target, - l_attr_eff_dram_width_u8); - if (rc) return rc; - rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target, l_mbapos); - if (rc) return rc; - - if (l_attr_eff_dram_width_u8 == 8) - { - l_SCHMOO_NIBBLES = 10; - if (iv_dmm_type == 1) - { - l_SCHMOO_NIBBLES = 9; - } - } - - //FAPI_INF("%s:Shmoonibbles val is=%d",l_SCHMOO_NIBBLES); - - FAPI_INF("%s: freq = %d on %s.", i_target.toEcmdString(), - l_attr_mss_freq_u32, l_target_centaur.toEcmdString()); - FAPI_INF("%s:volt = %d on %s.", i_target.toEcmdString(), - l_attr_mss_volt_u32, l_target_centaur.toEcmdString()); - FAPI_INF("%s:dimm_type = %d on %s.", i_target.toEcmdString(), - l_attr_eff_dimm_type_u8, i_target.toEcmdString()); - FAPI_INF("%s:\n Number of ranks on port=0 is %d ", i_target.toEcmdString(), - iv_MAX_RANKS[0]); - FAPI_INF("%s:\n Number of ranks on port=1 is %d ", i_target.toEcmdString(), - iv_MAX_RANKS[1]); - - if (l_attr_eff_dimm_type_u8 == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES) - { - FAPI_INF("%s:It is a CDIMM", i_target.toEcmdString()); - } - else - { - FAPI_INF("%s:It is an ISDIMM", i_target.toEcmdString()); - } - - FAPI_INF("%s:\n Number of ranks on port=0 is %d ", i_target.toEcmdString(), - iv_MAX_RANKS[0]); - FAPI_INF("%s:\n Number of ranks on port=1 is %d \n \n", - i_target.toEcmdString(), iv_MAX_RANKS[1]); - - FAPI_INF( - "+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++"); - sprintf(l_pMike, "Schmoo POS\tPort\tRank\tDQS\tNominal\t\ttDQSSmin_PR_limit\ttDQSSmax_PR_limit\ttDQSSmin(ps)\ttDQSSmax(ps)\ttDQSS_Window(ps)\tBitRate "); - FAPI_INF("%s", l_pMike); - delete[] l_pMike; - - for (l_p = 0; l_p < MAX_PORT; l_p++) - { - for (l_rnk = 0; l_rnk < iv_MAX_RANKS[l_p]; l_rnk++) - { - //// - - i_rank = valid_rank1[l_p][l_rnk]; - // - if (rc) return rc; - - for (l_nibble = 0; l_nibble < l_SCHMOO_NIBBLES; l_nibble++) - { - l_by8_dqs = l_nibble; - if (iv_dmm_type == 0) - { - if (l_attr_eff_dram_width_u8 == 8) - { - l_nibble = l_nibble * 2; - } - } - l_dq=4* l_nibble; - l_flag=0; - if (l_p == 0) - { - for (l_i = 0; l_i < count_bad_dq[0]; l_i++) - { - if (l_CDarray0[l_i] == l_dq) - { - l_flag=1; - - } - } - } - else - { - for (l_i = 0; l_i < count_bad_dq[1]; l_i++) - { - if (l_CDarray1[l_i] == l_dq) - { - l_flag=1; - - } - } - } - - if(l_flag==1) - { - continue; - } - - l_total_margin - = SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.left_margin_val[l_nibble] - + SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.right_margin_val[l_nibble]; - sprintf(l_str, "%d\t%d\t%d\t%d\t%d\t\t%d\t\t%d\t\t%d\t\t%d\t\t%d\t\t%d", - l_mbapos, l_p, i_rank, l_nibble, - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.curr_val[l_nibble], - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.lb_regval[l_nibble], - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.rb_regval[l_nibble], - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.left_margin_val[l_nibble], - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.right_margin_val[l_nibble], - l_total_margin, l_attr_mss_freq_u32); - - FAPI_INF("WR_DQS %s", l_str); - - if (iv_dmm_type == 0) - { - if (l_attr_eff_dram_width_u8 == 8) - { - l_nibble = l_by8_dqs; - } - } - - } - } - } - delete[] l_str; - return rc; - } - - - - - fapi::ReturnCode generic_shmoo::print_report_dqs2(const fapi::Target & i_target) - { - fapi::ReturnCode rc; - uint8_t l_rnk,l_nibble; - uint8_t l_p=0; - uint8_t i_rank=0; - uint8_t l_mbapos = 0; - uint32_t l_attr_mss_freq_u32 = 0; - uint32_t l_attr_mss_volt_u32 = 0; - uint8_t l_attr_eff_dimm_type_u8 = 0; - uint8_t l_attr_eff_num_drops_per_port_u8 = 0; - uint8_t l_attr_eff_dram_width_u8 = 0; - fapi::Target l_target_centaur; - uint8_t l_SCHMOO_NIBBLES=20; - uint8_t l_by8_dqs=0; - - - if(iv_dmm_type==1) - { - l_SCHMOO_NIBBLES=18; - } - - rc = fapiGetParentChip(i_target, l_target_centaur); - if(rc) return rc; - - rc = FAPI_ATTR_GET(ATTR_MSS_FREQ, &l_target_centaur, l_attr_mss_freq_u32); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_MSS_VOLT, &l_target_centaur, l_attr_mss_volt_u32); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_CUSTOM_DIMM, &i_target, l_attr_eff_dimm_type_u8); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_NUM_DROPS_PER_PORT, &i_target, l_attr_eff_num_drops_per_port_u8); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target, l_attr_eff_dram_width_u8); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target, l_mbapos); - if(rc) return rc; - - if(l_attr_eff_dram_width_u8 == 8) { - l_SCHMOO_NIBBLES=10; - if(iv_dmm_type==1) - { - l_SCHMOO_NIBBLES=9; - } - } - FAPI_INF("%s:freq = %d on %s.",i_target.toEcmdString(), l_attr_mss_freq_u32, l_target_centaur.toEcmdString()); - FAPI_INF("%s:volt = %d on %s.",i_target.toEcmdString(), l_attr_mss_volt_u32, l_target_centaur.toEcmdString()); - FAPI_INF("%s:dimm_type = %d on %s.",i_target.toEcmdString(), l_attr_eff_dimm_type_u8, i_target.toEcmdString()); - FAPI_INF("%s:\n Number of ranks on port=0 is %d ",i_target.toEcmdString(),iv_MAX_RANKS[0]); - FAPI_INF("%s:\n Number of ranks on port=1 is %d ",i_target.toEcmdString(),iv_MAX_RANKS[1]); - - - if ( l_attr_eff_dimm_type_u8 == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES ) - { - FAPI_INF("%s:It is a CDIMM",i_target.toEcmdString()); - } - else - { - FAPI_INF("%s:It is an ISDIMM",i_target.toEcmdString()); - } - - FAPI_INF("%s:\n Number of ranks on port=0 is %d ",i_target.toEcmdString(),iv_MAX_RANKS[0]); - FAPI_INF("%s:\n Number of ranks on port=1 is %d \n \n",i_target.toEcmdString(),iv_MAX_RANKS[1]); - - FAPI_INF("%s:+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++",i_target.toEcmdString()); - FAPI_INF("%s:Schmoo POS\tPort\tRank\tDQS\tNominal\t\ttDQSSmin_PR_limit\ttDQSSmax_PR_limit\ttDQSSmin(ps)\ttDQSSmax(ps)\ttDQSS_Window(ps)\tBitRate ",i_target.toEcmdString()); - - iv_shmoo_type=4; - - - for (l_p=0; l_p<MAX_PORT; l_p++) { - for (l_rnk=0; l_rnk<iv_MAX_RANKS[l_p]; l_rnk++) - { - i_rank=valid_rank1[l_p][l_rnk]; - for(l_nibble=0; l_nibble< l_SCHMOO_NIBBLES; l_nibble++) - { - l_by8_dqs=l_nibble; - if(iv_dmm_type==0) - { - if(l_attr_eff_dram_width_u8 == 8) - { - l_nibble=l_nibble*2; - } - } - - FAPI_INF("%s:WR_DQS %d\t%d\t%d\t%d\t%d\t\t%d\t\t%d\t\t%d\t\t%d\t\t%d\t\t%d\n ",i_target.toEcmdString(),l_mbapos,l_p,i_rank,l_nibble,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.nom_val[l_nibble],SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.lb_regval[l_nibble],SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.rb_regval[l_nibble],SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.left_margin_val[l_nibble],SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.right_margin_val[l_nibble],SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.total_margin[l_nibble],l_attr_mss_freq_u32); - - if(iv_dmm_type==0) - { - if(l_attr_eff_dram_width_u8 == 8) - { - l_nibble=l_by8_dqs; - } - } - - - } - } - } - - //fclose(fp); - return rc; - } -/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - /*------------------------------------------------------------------------------ - * Function: get_margin - * Description : This function is used to get margin for setup,hold and total eye width in Ps by using frequency - * - * Parameters: Target:MBA - * ---------------------------------------------------------------------------*/ - fapi::ReturnCode generic_shmoo::get_margin(const fapi::Target & i_target) - { - fapi::ReturnCode rc; - uint8_t l_rnk, l_byte, l_nibble, l_bit; - uint32_t l_attr_mss_freq_margin_u32 = 0; - uint32_t l_freq = 0; - uint64_t l_cyc = 1000000000000000ULL; - uint8_t l_dq = 0; - uint8_t l_p = 0; - uint8_t i_rank = 0; - uint64_t l_factor = 0; - uint64_t l_factor_ps = 1000000000; - fapi::Target l_target_centaur; - rc = fapiGetParentChip(i_target, l_target_centaur); - if (rc) return rc; - rc = FAPI_ATTR_GET(ATTR_MSS_FREQ, &l_target_centaur, - l_attr_mss_freq_margin_u32); - if (rc) return rc; - l_freq = l_attr_mss_freq_margin_u32 / 2; - l_cyc = l_cyc / l_freq;// converting to zepto to get more accurate data - l_factor = l_cyc / 128; - //FAPI_INF("l_factor is % llu ",l_factor); - - for (l_p = 0; l_p < MAX_PORT; l_p++) - { - for (l_rnk = 0; l_rnk < iv_MAX_RANKS[l_p]; l_rnk++) - { - //// - - i_rank = valid_rank1[l_p][l_rnk]; - // - if (rc) return rc; - for (l_byte = 0; l_byte < iv_MAX_BYTES; l_byte++) - { - //Nibble loop - for (l_nibble = 0; l_nibble < MAX_NIBBLES; l_nibble++) - { - for (l_bit = 0; l_bit < MAX_BITS; l_bit++) - { - l_dq = 8 * l_byte + 4 * l_nibble + l_bit; - - if (iv_shmoo_type == 1) - { - if (SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.lb_regval[l_dq] == 0) - { - - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.lb_regval[l_dq] = 0; - - - } - } - - if (iv_shmoo_param == 4) - { - if (SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.rb_regval[l_dq] - > SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.nom_val[l_dq]) - { - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.rb_regval[l_dq] - = SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.rb_regval[l_dq] - 1; - } - if (SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.lb_regval[l_dq] - < SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.nom_val[l_dq]) - { - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.lb_regval[l_dq] - = SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.lb_regval[l_dq] + 1; - } - } - else - { - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.rb_regval[l_dq] - = SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.rb_regval[l_dq]- 1; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.lb_regval[l_dq] - = SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.lb_regval[l_dq] + 1; - } - - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.right_margin_val[l_dq] - = ((SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.rb_regval[l_dq] - - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.nom_val[l_dq]) - * l_factor) / l_factor_ps; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.left_margin_val[l_dq] - = ((SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.nom_val[l_dq] - - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.lb_regval[l_dq]) - * l_factor) / l_factor_ps; - } - } - } - } - } - - return rc; - } - - fapi::ReturnCode generic_shmoo::get_margin2(const fapi::Target & i_target) - { - fapi::ReturnCode rc; - uint8_t l_rnk,l_byte,l_nibble,l_bit; - uint32_t l_attr_mss_freq_margin_u32 = 0; - uint32_t l_freq=0; - uint64_t l_cyc = 1000000000000000ULL; - uint8_t l_dq=0; - uint8_t l_p=0; - uint8_t i_rank=0; - uint64_t l_factor=0; - uint64_t l_factor_ps=1000000000; - fapi::Target l_target_centaur; - rc = fapiGetParentChip(i_target, l_target_centaur); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_MSS_FREQ, &l_target_centaur, l_attr_mss_freq_margin_u32); - if(rc) return rc; - l_freq=l_attr_mss_freq_margin_u32/2; - l_cyc=l_cyc/l_freq;// converting to zepto to get more accurate data - l_factor=l_cyc/128; - - for (l_p=0; l_p< 2; l_p++) { - for (l_rnk=0; l_rnk<iv_MAX_RANKS[l_p]; l_rnk++) - { - ////// - i_rank=valid_rank1[l_p][l_rnk]; - ////// - for(l_byte=0; l_byte< 10; l_byte++) - { - - //Nibble loop - for(l_nibble=0; l_nibble< 2; l_nibble++) - { - for(l_bit=0; l_bit< 4; l_bit++) - { - l_dq=8*l_byte+4*l_nibble+l_bit; - - if(iv_shmoo_type==8) - { - if(SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.lb_regval[l_dq] == 0) { - - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.lb_regval[l_dq]=0; - if((iv_shmoo_param==4)||(iv_shmoo_param==6)) { - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.lb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.lb_regval[l_dq]-1; - } else { - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.lb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.lb_regval[l_dq]-2; - } - //FAPI_INF("\n the value of left bound after is %d \n",SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.lb_regval[l_dq]); - } - } - - if((iv_shmoo_param==4)||(iv_shmoo_param==6)) { - if(SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.rb_regval[l_dq]>SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.nom_val[l_dq]) { - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.rb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.rb_regval[l_dq]-1; - } - if(SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.lb_regval[l_dq]<SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.nom_val[l_dq]) { - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.lb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.lb_regval[l_dq]+1; - } - } else { - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.rb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.rb_regval[l_dq]-1; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.lb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.lb_regval[l_dq]+1; - } - - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.right_margin_val[l_dq]=((SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.rb_regval[l_dq]-SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.nom_val[l_dq])*l_factor)/l_factor_ps; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.left_margin_val[l_dq]= ((SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.nom_val[l_dq]-SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.lb_regval[l_dq])*l_factor)/l_factor_ps;//((1/uint32_t_freq*1000000)/128); - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.total_margin[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.right_margin_val[l_dq]+SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.left_margin_val[l_dq]; - } - } - } - } - } - - return rc; - } - - /* - fapi::ReturnCode generic_shmoo::print_report2(const fapi::Target & i_target) - { - fapi::ReturnCode rc; - FAPI_INF("\nIn print report!!!\n"); - uint8_t l_rnk, l_nibble; - uint8_t l_p = 0; - uint8_t i_rank = 0; - uint8_t l_mbapos = 0; - uint16_t l_total_margin = 0; - //uint8_t l_SCHMOO_NIBBLES = 20; - char * l_pMike = new char[128]; - char * l_str = new char[128]; - uint8_t l_i = 0; - uint8_t l_dq = 0; - uint8_t l_byte = 0; - uint8_t l_bit = 0; - uint8_t l_flag = 0; - uint8_t l_CDarray0[80] = { 0 }; - uint8_t l_CDarray1[80] = { 0 }; - uint8_t vrefdq_train_range[2][2][4]; - uint32_t l_attr_mss_freq_u32 = 0; - uint32_t l_attr_mss_volt_u32 = 0; - uint8_t l_attr_eff_dimm_type_u8 = 0; - uint8_t l_attr_eff_num_drops_per_port_u8 = 0; - uint8_t l_attr_eff_dram_width_u8 = 0; - fapi::Target l_target_centaur; - uint8_t l_dram_gen = 1; - uint8_t base_percent = 60; - float index_mul_print = 0.65; - float vref_val_print = 0; - - - rc = fapiGetParentChip(i_target, l_target_centaur); if(rc) return rc; - rc = FAPI_ATTR_GET( ATTR_VREF_DQ_TRAIN_RANGE, &i_target, vrefdq_train_range);if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_MSS_FREQ, &l_target_centaur, l_attr_mss_freq_u32); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_MSS_VOLT, &l_target_centaur, l_attr_mss_volt_u32); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_CUSTOM_DIMM, &i_target, l_attr_eff_dimm_type_u8); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_NUM_DROPS_PER_PORT, &i_target, l_attr_eff_num_drops_per_port_u8); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target, l_attr_eff_dram_width_u8); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target, l_mbapos);if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_GEN, &i_target, l_dram_gen); if(rc) return rc; - - - - if(vrefdq_train_range[0][0][0] == 1) - { - base_percent = 45; - } - - vref_val_print = base_percent + (iv_vref_mul * index_mul_print); - FAPI_INF("%s: freq = %d on %s.",i_target.toEcmdString(),l_attr_mss_freq_u32, l_target_centaur.toEcmdString()); - FAPI_INF("%s: volt = %d on %s.",i_target.toEcmdString(), l_attr_mss_volt_u32, l_target_centaur.toEcmdString()); - FAPI_INF("%s: dimm_type = %d on %s.",i_target.toEcmdString(), l_attr_eff_dimm_type_u8, i_target.toEcmdString()); - if ( l_attr_eff_dimm_type_u8 == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES ) - { - FAPI_INF("%s: It is a CDIMM",i_target.toEcmdString()); - } - else - { - FAPI_INF("%s: It is an ISDIMM",i_target.toEcmdString()); - } - FAPI_INF("%s: \n Number of ranks on port = 0 is %d ",i_target.toEcmdString(),iv_MAX_RANKS[0]); - FAPI_INF("%s: \n Number of ranks on port = 1 is %d \n \n",i_target.toEcmdString(),iv_MAX_RANKS[1]); - if (iv_shmoo_type == 2) - { - FAPI_INF("\n\n********************* WR_EYE Margins ********************** \n\n"); - sprintf(l_pMike, "\nSchmoo\tP\tP\tR\tB\tN\tBi\tNom\t\tRb\t\tLb\t\tSetup\t\tHold\t\tTotal\tfreq\tiv_ref_mul "); - - } - else - { - FAPI_INF("\n\n********************* RD_EYE Margins ********************** \n\n"); - sprintf(l_pMike, "\nSchmoo\tP\tP\tR\tB\tN\tBi\tNom\t\tRb\t\tLb\t\tSetup\t\tHold\t\tTotal\t\tfreq\t\tiv_ref_mul "); - } - //printf("Schmoo POS\tPort\tRank\tByte\tnibble\tbit\tNominal\t\tSetup_Limit\tHold_Limit \n"); - FAPI_INF("%s", l_pMike); - delete[] l_pMike; - - - - rc=mcb_error_map(i_target,mcbist_error_map,l_CDarray0,l_CDarray1,count_bad_dq);if(rc)return rc; - - - for (l_p = 0; l_p < MAX_PORT; l_p++) - { - for (l_rnk = 0; l_rnk < iv_MAX_RANKS[l_p]; l_rnk++) - { - ////// - - i_rank = valid_rank1[l_p][l_rnk]; - //// - - for (l_byte = 0; l_byte < iv_MAX_BYTES; l_byte++) - { - //Nibble loop - for (l_nibble = 0; l_nibble < MAX_NIBBLES; l_nibble++) - { - - l_dq=8 * l_byte + 4 * l_nibble; - l_flag=0; - if (l_p == 0) - { - for (l_i = 0; l_i < count_bad_dq[0]; l_i++) - { - if (l_CDarray0[l_i] == l_dq) - { - l_flag=1; - - } - } - } - else - { - for (l_i = 0; l_i < count_bad_dq[1]; l_i++) - { - if (l_CDarray1[l_i] == l_dq) - { - l_flag=1; - - } - } - } - - if(l_flag==1) - { - //printf("Would normally skip prints...\n"); - //continue; - } - for (l_bit = 0; l_bit < MAX_BITS; l_bit++) - { - l_dq = 8 * l_byte + 4 * l_nibble + l_bit; - l_total_margin - = SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.left_margin_val[l_dq] - + SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.right_margin_val[l_dq]; - if(l_dram_gen ==2) - { - sprintf(l_str, "%d\t%d\t%d\t%d\t%d\t%d\t%d\t\t%d\t\t%d\t\t%d\t\t%d\t\t%d\t\t%d\t\t%f", - l_mbapos, l_p, i_rank, l_byte, l_nibble, l_bit, - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.nom_val[l_dq], - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.rb_regval[l_dq], - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.lb_regval[l_dq], - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.right_margin_val[l_dq], - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.left_margin_val[l_dq], - l_total_margin, l_attr_mss_freq_u32, vref_val_print); - - } - else - { - sprintf(l_str, "%d\t%d\t%d\t%d\t%d\t%d\t%d\t\t%d\t\t%d\t\t%d\t\t%d\t\t%d\t\t%d\t\t%d", - l_mbapos, l_p, i_rank, l_byte, l_nibble, l_bit, - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.nom_val[l_dq], - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.rb_regval[l_dq], - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.lb_regval[l_dq], - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.right_margin_val[l_dq], - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.left_margin_val[l_dq], - l_total_margin, l_attr_mss_freq_u32, iv_vref_mul); - } - if (iv_shmoo_type == 2) - { - FAPI_INF("\nWR_EYE %s ", l_str); - - } - else if (iv_shmoo_type == 8) - { - FAPI_INF("\nRD_EYE %s ", l_str); - - } - } - } - } - } - } - - delete[] l_str; - - return rc; - } - */ //end of print report test code - - fapi::ReturnCode generic_shmoo::get_margin_dqs_by4(const fapi::Target & i_target) - { - fapi::ReturnCode rc; - uint8_t l_rnk; - uint32_t l_attr_mss_freq_margin_u32 = 0; - uint32_t l_freq=0; - uint64_t l_cyc = 1000000000000000ULL; - uint8_t l_nibble=0; - uint8_t l_p=0; - uint8_t i_rank=0; - uint64_t l_factor=0; - uint64_t l_factor_ps=1000000000; - uint8_t l_SCHMOO_NIBBLES=20; - - if(iv_dmm_type==1) - { - l_SCHMOO_NIBBLES=18; - } - - //FAPI_INF(" the factor is % llu ",l_cyc); - - fapi::Target l_target_centaur; - rc = fapiGetParentChip(i_target, l_target_centaur); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_MSS_FREQ, &l_target_centaur, l_attr_mss_freq_margin_u32); - if(rc) return rc; - l_freq=l_attr_mss_freq_margin_u32/2; - l_cyc=l_cyc/l_freq;// converting to zepto to get more accurate data - l_factor=l_cyc/128; - - for (l_p=0; l_p<MAX_PORT; l_p++) { - - for (l_rnk=0; l_rnk<iv_MAX_RANKS[l_p]; l_rnk++) - { - i_rank=valid_rank1[l_p][l_rnk]; - //Nibble loop - - for(l_nibble=0; l_nibble<l_SCHMOO_NIBBLES; l_nibble++) - { - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.rb_regval[l_nibble]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.rb_regval[l_nibble]-1; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.lb_regval[l_nibble]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.lb_regval[l_nibble]+1; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.right_margin_val[l_nibble]=((SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.rb_regval[l_nibble]-SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.nom_val[l_nibble])*l_factor)/l_factor_ps; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.left_margin_val[l_nibble]= ((SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.nom_val[l_nibble]-SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.lb_regval[l_nibble])*l_factor)/l_factor_ps;//((1/uint32_t_freq*1000000)/128); - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.total_margin[l_nibble]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.right_margin_val[l_nibble]+SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.left_margin_val[l_nibble]; - - } - } - } - return rc; - } - - fapi::ReturnCode generic_shmoo::get_margin_dqs_by8(const fapi::Target & i_target) - { - fapi::ReturnCode rc; - uint8_t l_rnk; - uint32_t l_attr_mss_freq_margin_u32 = 0; - uint32_t l_freq=0; - uint64_t l_cyc = 1000000000000000ULL; - //uint8_t l_dq=0; - uint8_t l_nibble=0; - - uint8_t l_p=0; - uint8_t i_rank=0; - uint64_t l_factor=0; - uint64_t l_factor_ps=1000000000; - uint8_t l_SCHMOO_NIBBLES=20; - - if(iv_dmm_type==1) - { - l_SCHMOO_NIBBLES=9; - } - - //FAPI_INF(" the factor is % llu ",l_cyc); - - fapi::Target l_target_centaur; - rc = fapiGetParentChip(i_target, l_target_centaur); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_MSS_FREQ, &l_target_centaur, l_attr_mss_freq_margin_u32); - if(rc) return rc; - l_freq=l_attr_mss_freq_margin_u32/2; - l_cyc=l_cyc/l_freq;// converting to zepto to get more accurate data - l_factor=l_cyc/128; - //FAPI_INF("l_factor is % llu ",l_factor); - - - - - for (l_p=0; l_p<MAX_PORT; l_p++) { - //FAPI_INF("\n Abhijit is here before %d \n",l_p); - for (l_rnk=0; l_rnk<iv_MAX_RANKS[l_p]; l_rnk++) - { - i_rank=valid_rank1[l_p][l_rnk]; - //Nibble loop - for(l_nibble=0; l_nibble < l_SCHMOO_NIBBLES; l_nibble++) - { - if(iv_dmm_type==0) - { - if((l_nibble%2)) { - continue ; - } - } - - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.rb_regval[l_nibble]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.rb_regval[l_nibble]-1; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.lb_regval[l_nibble]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.lb_regval[l_nibble]+1; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.right_margin_val[l_nibble]=((SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.rb_regval[l_nibble]-SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.nom_val[l_nibble])*l_factor)/l_factor_ps; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.left_margin_val[l_nibble]= ((SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.nom_val[l_nibble]-SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.lb_regval[l_nibble])*l_factor)/l_factor_ps;//((1/uint32_t_freq*1000000)/128); - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.total_margin[l_nibble]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.right_margin_val[l_nibble]+SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.left_margin_val[l_nibble]; - } - } - - } - return rc; - } - - fapi::ReturnCode generic_shmoo::knob_update_bin_composite(const fapi::Target & i_target,bound_t bound,uint8_t scenario,uint8_t bit,uint8_t pass,bool &flag) - { - - fapi::ReturnCode rc; - ecmdDataBufferBase data_buffer_64(64); - ecmdDataBufferBase data_buffer_64_1(64); - input_type_t l_input_type_e = WR_DQ; - uint8_t l_n=0; - access_type_t l_access_type_e = WRITE; - uint8_t l_dq = 0; - uint8_t l_i=0; - uint8_t l_flag_p0=0; - uint8_t l_flag_p1=0; - FAPI_INF("SHMOOING VIA COMPOSITE EYE FW !!!!"); - uint8_t l_p=0; - uint8_t rank=0; - uint8_t l_rank=0; - uint8_t l_SCHMOO_NIBBLES=20; - uint8_t l_status=1; - uint8_t l_CDarray0[80]= {0}; - uint8_t l_CDarray1[80]= {0}; - - if(iv_dmm_type==1) - { - l_SCHMOO_NIBBLES=18; - } - - if(iv_shmoo_type == 2) - { - l_input_type_e = WR_DQ; - } - else if(iv_shmoo_type == 8) - { - l_input_type_e = RD_DQ; - } - else if(iv_shmoo_type == 4) - { - l_input_type_e = WR_DQS; - } - else if(iv_shmoo_type == 16) - { - l_input_type_e = RD_DQS; - } - - rc=do_mcbist_reset(i_target); - if(rc) - { - FAPI_INF("generic_shmoo::find_bound do_mcbist_reset failed"); - return rc; - } - - - //Reset schmoo_error_map - - for(l_p = 0; l_p < MAX_PORT; l_p++) { - for(int i=0; i<iv_MAX_RANKS[l_p]; i++) { - - rank=valid_rank1[l_p][i]; - for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) { - schmoo_error_map[l_p][rank][l_n]=0; - binary_done_map[l_p][rank][l_n]=0; - } - } - } - int count_cycle = 0; - - if(bound==RIGHT) - { - - for(l_p = 0; l_p < MAX_PORT; l_p++) { - do { - - - l_status=0; - - - rc=mcb_error_map(i_target,mcbist_error_map,l_CDarray0,l_CDarray1,count_bad_dq); - if(rc) return rc; - - - for (l_rank=0; l_rank<iv_MAX_RANKS[l_p]; l_rank++) - { - //l_dq+l_n*4=bit; - ////// - rank=valid_rank1[l_p][l_rank]; - //printf ("Current Rank : %d",rank ); - - for(l_dq = 0; l_dq < 4; l_dq++) { - for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) { - if(binary_done_map[l_p][rank][l_n]==0) { - l_status=1; - } - l_flag_p0=0; - l_flag_p1=0; - if(l_p == 0) { - for(l_i=0; l_i<count_bad_dq[0]; l_i++) { - if(l_CDarray0[l_i]==l_dq+l_n*4) { - schmoo_error_map[l_p][rank][l_n]=1; - l_flag_p0=1; - - } - } - } else { - for(l_i=0; l_i<count_bad_dq[1]; l_i++) { - - if(l_CDarray1[l_i]==l_dq+l_n*4) { - schmoo_error_map[l_p][rank][l_n]=1; - l_flag_p1=1; - - } - } - } - - if(schmoo_error_map[l_p][rank][l_n]==0) { - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq+l_n*4]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_val[l_dq+l_n*4]; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_val[l_dq+l_n*4]=(SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq+l_n*4]+SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq+l_n*4])/2; - - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq+l_n*4,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_val[l_dq+l_n*4]); - if(rc) return rc; - if(SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq+l_n*4]>SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq+l_n*4]) { - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_diff[l_dq+l_n*4]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq+l_n*4]-SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq+l_n*4]; - } - else { - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_diff[l_dq+l_n*4]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq+l_n*4]-SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq+l_n*4]; - } - - if(SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_diff[l_dq+l_n*4]<=1) { - binary_done_map[l_p][rank][l_n]=1; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq+l_n*4]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq+l_n*4]; - // printf("\n the right bound for port=%d rank=%d dq=%d is %d \n",l_p,rank,l_dq+l_n*4,FAPI_INF.MBA.P[l_p].S[rank].K.curr_val[l_dq+l_n*4]); - } - } - else { - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq+l_n*4]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_val[l_dq+l_n*4]; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_val[l_dq+l_n*4]=(SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq+l_n*4]+SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq+l_n*4])/2; - - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq+l_n*4,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_val[l_dq+l_n*4]); - if(rc) return rc; - if(SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq+l_n*4]>SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq+l_n*4]) { - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_diff[l_dq+l_n*4]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq+l_n*4]-SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq+l_n*4]; - } else { - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_diff[l_dq+l_n*4]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq+l_n*4]-SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq+l_n*4]; - } - if(l_p==0) { - if(l_flag_p0==1) { - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_diff[l_dq+l_n*4]=1; - } - } - else { - if(l_flag_p1==1) { - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_diff[l_dq+l_n*4]=1; - } - } - - if(SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_diff[l_dq+l_n*4]<=1) { - binary_done_map[l_p][rank][l_n]=1; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq+l_n*4]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq+l_n*4]; - - } - } - //l_dq+l_n*4=l_dq+l_n*4+4; - } - } - } - - - rc=do_mcbist_reset(i_target); - if(rc) - { - FAPI_INF("generic_shmoo::find_bound do_mcbist_reset failed"); - return rc; - } - rc=do_mcbist_test(i_target); - if(rc) - { - FAPI_INF("generic_shmoo::find_bound do_mcbist_test failed"); - return rc; - } - - rc=check_error_map(i_target,l_p,pass); - if(rc) - { - FAPI_INF("generic_shmoo::find_bound do_mcbist_test failed"); - return rc; - } - //FAPI_INF("\n the status =%d \n",l_status); - count_cycle++; - } while(l_status==1); - } - - for(l_p = 0; l_p < MAX_PORT; l_p++) - { - for (l_rank=0; l_rank<iv_MAX_RANKS[l_p]; l_rank++) - { - //l_dq+l_n*4=bit; - ////// - rank=valid_rank1[l_p][l_rank]; - for(l_dq = 0; l_dq < 4; l_dq++) { - for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) { - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq+l_n*4,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq+l_n*4]); - if(rc) return rc; - //l_dq+l_n*4=l_dq+l_n*4+4; - } - } - } - } - - - - - } - count_cycle = 0; - if(bound==LEFT) - { - for(l_p = 0; l_p < MAX_PORT; l_p++) - { - l_status = 1; - //printf("\n +++ Inside LEFT bound -- bin "); - while(l_status==1) - { - l_status=0; - - - rc=mcb_error_map(i_target,mcbist_error_map,l_CDarray0,l_CDarray1,count_bad_dq); - if(rc) return rc; - - for (l_rank=0; l_rank<iv_MAX_RANKS[l_p]; l_rank++) { - //l_dq+l_n*4=bit; - ////// - rank=valid_rank1[l_p][l_rank]; - //printf ("Current Rank : %d",rank ); - - for(l_dq = 0; l_dq < 4; l_dq++) { - for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) { - - if(binary_done_map[l_p][rank][l_n]==0) { - l_status=1; - } - - l_flag_p0=0; - l_flag_p1=0; - if(l_p == 0) { - for(l_i=0; l_i<count_bad_dq[0]; l_i++) { - if(l_CDarray0[l_i]==l_dq+l_n*4) { - schmoo_error_map[l_p][rank][l_n]=1; - l_flag_p0=1; - - } - } - } - else { - for(l_i=0; l_i<count_bad_dq[1]; l_i++) { - - if(l_CDarray1[l_i]==l_dq+l_n*4) { - schmoo_error_map[l_p][rank][l_n]=1; - l_flag_p1=1; - - } - } - } - - if(schmoo_error_map[l_p][rank][l_n]==0) { - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq+l_n*4]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_val[l_dq+l_n*4]; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_val[l_dq+l_n*4]=(SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq+l_n*4]+SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq+l_n*4])/2; - - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq+l_n*4,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_val[l_dq+l_n*4]); - if(rc) return rc; - if(SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq+l_n*4]>SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq+l_n*4]) { - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_diff[l_dq+l_n*4]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq+l_n*4]-SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq+l_n*4]; - } else { - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_diff[l_dq+l_n*4]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq+l_n*4]-SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq+l_n*4]; - } - if(SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_diff[l_dq+l_n*4]<=1) { - binary_done_map[l_p][rank][l_n]=1; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq+l_n*4]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq+l_n*4]; - - } - } else { - - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq+l_n*4]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_val[l_dq+l_n*4]; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_val[l_dq+l_n*4]=(SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq+l_n*4]+SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq+l_n*4])/2; - - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq+l_n*4,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_val[l_dq+l_n*4]); - if(rc) return rc; - if(SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq+l_n*4]>SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq+l_n*4]) { - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_diff[l_dq+l_n*4]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq+l_n*4]-SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq+l_n*4]; - } else { - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_diff[l_dq+l_n*4]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq+l_n*4]-SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq+l_n*4]; - } - - - if(l_p==0) { - if(l_flag_p0==1) { - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_diff[l_dq+l_n*4]=1; - } - } - else { - if(l_flag_p1==1) { - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_diff[l_dq+l_n*4]=1; - } - } - - if(SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_diff[l_dq+l_n*4]<=1) { - binary_done_map[l_p][rank][l_n]=1; - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq+l_n*4]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq+l_n*4]; - - } - } - //l_dq+l_n*4=l_dq+l_n*4+4; - } - } - } - rc=do_mcbist_reset(i_target); - if(rc) - { - FAPI_INF("generic_shmoo::find_bound do_mcbist_reset failed"); - return rc; - } - rc=do_mcbist_test(i_target); - if(rc) - { - FAPI_INF("generic_shmoo::find_bound do_mcbist_test failed"); - return rc; - } - - rc=check_error_map(i_target,l_p,pass); - if(rc) - { - FAPI_INF("generic_shmoo::find_bound do_mcbist_test failed"); - return rc; - } - - - //printf("\n the status =%d \n",l_status); - count_cycle++; - } - } - - for(l_p = 0; l_p < MAX_PORT; l_p++) - { - for (l_rank=0; l_rank<iv_MAX_RANKS[l_p]; l_rank++) - { - //l_dq+l_n*4=bit; - ////// - rank=valid_rank1[l_p][l_rank]; - //printf("Valid rank of %d %d %d %d %d %d %d %d",valid_rank1[0],valid_rank1[1],valid_rank1[2],valid_rank1[3],valid_rank1[4],valid_rank1[5],valid_rank1[6],valid_rank1[7]); - for(l_dq = 0; l_dq < 4; l_dq++) { - for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) { - rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq+l_n*4,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq+l_n*4]); - if(rc) return rc; - //l_dq+l_n*4=l_dq+l_n*4+4; - } - } - } - } - - } // End of LEFT - - - return rc; - - - } - - fapi::ReturnCode generic_shmoo::get_nibble_pda(const fapi::Target & i_target,uint32_t pda_nibble_table[2][2][16][2]) - { - fapi::ReturnCode rc; - uint8_t i_rank = 0; - - for (int l_p=0; l_p < MAX_PORT; l_p++) { - for (int l_rnk=0; l_rnk<iv_MAX_RANKS[l_p]; l_rnk++) - { - //// - i_rank=valid_rank1[l_p][l_rnk]; - for(int l_dq = 0; l_dq < 4; l_dq++) { - for (int l_n=0; l_n < 16; l_n++) { - // do necessary - //if(pda_nibble_table[l_p][i_rank][l_n][1] < FAPI_INF.MBA.P[l_p].S[i_rank].K.total_margin[l_dq+l_n*4]) - { - pda_nibble_table[l_p][i_rank][l_n][0] = iv_vref_mul; - pda_nibble_table[l_p][i_rank][l_n][1] = SHMOO[iv_DQS_ON].MBA.P[l_p].S[i_rank].K.total_margin[l_dq+l_n*4]; - } - //FAPI_INF("\n Port %d Rank:%d Pda_Nibble: %d V-ref:%d Margin:%d",l_p,i_rank,l_n,pda_nibble_table[l_p][i_rank][l_n][0],pda_nibble_table[l_p][i_rank][l_n][1]); - } - } - - } - } - return rc; - } - /*------------------------------------------------------------------------------ - * Function: get_min_margin - * Description : This function is used to get the minimum margin of all the schmoo margins - * - * Parameters: Target:MBA,right minimum margin , left minimum margin, pass fail - * ---------------------------------------------------------------------------*/ - - fapi::ReturnCode generic_shmoo::get_min_margin2(const fapi::Target & i_target,uint32_t *o_right_min_margin,uint32_t *o_left_min_margin) - { - fapi::ReturnCode rc; - uint8_t l_rnk,l_byte,l_nibble,l_bit,i_rank; - uint16_t l_temp_right=4800; - uint16_t l_temp_left=4800; - uint8_t l_dq=0; - uint8_t l_p=0; - FAPI_INF("In GET_MIN_MARGIN - iv_shmoo_type = %d",iv_shmoo_type); - - for (l_p = 0; l_p < 2; l_p++) - { - for (l_rnk = 0; l_rnk < iv_MAX_RANKS[l_p]; l_rnk++) - { - - i_rank = valid_rank1[l_p][l_rnk]; - //// - if (rc) return rc; - for (l_byte = 0; l_byte < 10; l_byte++) - { - //Nibble loop - for (l_nibble = 0; l_nibble < 2; l_nibble++) - { - //l_dq=8 * l_byte + 4 * l_nibble; - - - for (l_bit = 0; l_bit < 4; l_bit++) - { - l_dq = 8 * l_byte + 4 * l_nibble + l_bit; - if ((SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.right_margin_val[l_dq] - < l_temp_right) && (SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.right_margin_val[l_dq] != 0 )) - { - l_temp_right - = SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.right_margin_val[l_dq]; - } - if ((SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.left_margin_val[l_dq] - < l_temp_left) && (SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.left_margin_val[l_dq] !=0)) - { - l_temp_left - = SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.left_margin_val[l_dq]; - } - } - } - } - } - } - - - - if(iv_shmoo_type==8) - { - *o_right_min_margin=l_temp_left; - *o_left_min_margin=l_temp_right; - } else { - *o_right_min_margin=l_temp_right; - *o_left_min_margin=l_temp_left; - } - return rc; - } - - - fapi::ReturnCode generic_shmoo::get_min_margin_dqs(const fapi::Target & i_target,uint32_t *o_right_min_margin,uint32_t *o_left_min_margin) - { - fapi::ReturnCode rc; - uint8_t l_rnk,l_nibble,i_rank; - uint16_t l_temp_right=4800; - uint16_t l_temp_left=4800; - uint8_t l_p=0; - uint8_t l_attr_eff_dram_width_u8=0; - uint8_t l_SCHMOO_NIBBLES=20; - uint8_t l_by8_dqs=0; - - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target, l_attr_eff_dram_width_u8); - if(rc) return rc; - - if(iv_dmm_type==1) - { - l_SCHMOO_NIBBLES=18; - } - - if(l_attr_eff_dram_width_u8 == 8) { - l_SCHMOO_NIBBLES=10; - if(iv_dmm_type==1) - { - l_SCHMOO_NIBBLES=9; - } - } - iv_shmoo_type=4; - - for (l_p=0; l_p<MAX_PORT; l_p++) { - for (l_rnk=0; l_rnk<iv_MAX_RANKS[l_p]; l_rnk++) - { - i_rank=valid_rank1[l_p][l_rnk]; - - - for(l_nibble=0; l_nibble< l_SCHMOO_NIBBLES; l_nibble++) - { - - l_by8_dqs=l_nibble; - if(iv_dmm_type==0) - { - if(l_attr_eff_dram_width_u8 == 8) - { - l_nibble=l_nibble*2; - } - } - - if(SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.right_margin_val[l_nibble]<l_temp_right) - { - l_temp_right=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.right_margin_val[l_nibble]; - } - if(SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.left_margin_val[l_nibble]<l_temp_left) - { - l_temp_left=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.left_margin_val[l_nibble]; - } - - if(iv_dmm_type==0) - { - if(l_attr_eff_dram_width_u8 == 8) - { - l_nibble=l_by8_dqs; - } - } - } - } - } - - - // hacked for now till schmoo is running - if(iv_shmoo_type==8) - { - *o_right_min_margin=l_temp_left; - *o_left_min_margin=l_temp_right; - } else { - *o_right_min_margin=l_temp_right; - *o_left_min_margin=l_temp_left; - } - return rc; - } - /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - - fapi::ReturnCode generic_shmoo::schmoo_setup_mcb(const fapi::Target & i_target) - { - - struct Subtest_info l_sub_info[30]; - uint32_t l_pattern = 0; - uint32_t l_testtype = 0; - mcbist_byte_mask i_mcbbytemask1; - char l_str_cust_addr[] = "ba0,ba1,mr3,mr2,mr1,mr0,ba2,ba3,cl2,cl3,cl4,cl5,cl6,cl7,cl8,cl9,cl11,cl13,r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15,r16,sl2,sl1,sl0"; - - i_mcbbytemask1 = UNMASK_ALL; - - fapi::ReturnCode rc; - - l_pattern = iv_pattern; - l_testtype = iv_test_type; - - if (iv_shmoo_type == 16) - { - FAPI_INF("%s:\n Read DQS is running \n", i_target.toEcmdString()); - if (iv_SHMOO_ON == 1) - { - l_testtype = 3; - } - if (iv_SHMOO_ON == 2) - { - l_testtype = 4; - } - } - //send shmoo mode to vary the address range - if (iv_shmoo_type == 16) - { - rc = FAPI_ATTR_SET(ATTR_MCBIST_PATTERN, &i_target, l_pattern); - if (rc) return rc;//-----------i_mcbpatt------->run - rc = FAPI_ATTR_SET(ATTR_MCBIST_TEST_TYPE, &i_target, l_testtype); - if (rc) return rc;//---------i_mcbtest------->run - } - - rc = setup_mcbist(i_target, i_mcbbytemask1, 0,0x0ull ,l_sub_info,l_str_cust_addr); - if (rc) return rc; - - return rc; - } - -}//Extern C diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_generic_shmoo.H b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_generic_shmoo.H deleted file mode 100644 index f18bb550d..000000000 --- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_generic_shmoo.H +++ /dev/null @@ -1,232 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_generic_shmoo.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2012,2015 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: mss_generic_shmoo.H,v 1.29 2015/08/07 11:28:52 sasethur Exp $ -// *!*************************************************************************** -// *! (C) Copyright International Business Machines Corp. 1997, 1998 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -// *!*************************************************************************** -// *! FILENAME : mss_generic_shmoo.H -// *! TITLE : MSS Generic Shmoo -// *! DESCRIPTION : Memory Subsystem Generic Shmoo -- abstraction for HB -// *! CONTEXT : To make all shmoos share a common abstraction layer -// *! -// *! OWNER NAME : Preetham Hosmane Email: preeragh@in.ibm.com -// *! BACKUP NAME : Saravanan Sethuraman -// *! -// *!*************************************************************************** -// CHANGE HISTORY: -//------------------------------------------------------------------------------ -// Version:|Author: | Date: | Comment: -// --------|--------|--------|-------------------------------------------------- -// 1.29 |preeragh|30/07/15| Optimized for FW Linear/Composite/Bin -// 1.28 |preeragh|06/22/14|DDR4 Mods -// 1.27 |mjjones |01/24/14|RAS Review Updates -// 1.26 |abhijit |01/17/14|enabled one more function -// 1.24 |abhijit |12/17/13|modified as per to support firmware -// 1.22 |abhijit |8/08/13 |added binary schmoo functions -// 1.20 |abhijit |7/17/13 |added functions for read dqs -// 1.11 |abhijit |1/21/13 |fixed constructor definition -// 1.9 |abhijit |06/12/12|fixed fw review comments -// 1.4 |abhijit |09/27/11|made changes according to new design -// 1.5 |abhijit |10/29/12|made changes after target and returncode -// 1.6 |abhijit |10/29/12|made changes -// 1.7 |abhijit |11/15/12|made changes for fw review comments -//------------------------------------------------------------------------------ -#include <fapi.H> - -#ifndef generic_shmoo_H -#define generic_shmoo_H - -using namespace fapi; -//! Globals -#define SHMOO_DEBUG 0 -#define SHMOO_DEBUG2 0 -#include "mss_shmoo_common.H" -#include "mss_mcbist.H" - -//! MSS Generic Shmoo Class.. Inherits from PHY access class and the knob abstraction -class generic_shmoo -{ -private: - - //! MBS Config : Port + Socket + Knobs - struct SHMOO_SCENARIO - { - struct MBS_CONFIG - { - struct PORT - { - struct RANK - { - shmoo_knob_data_t K; // Set of knobs used by this shmoo - }S[MAX_RANK]; //Max Rank are 8 - }P[MAX_PORT]; // Max Port 2 - }MBA; - shmoo_knob_config_t static_knob; // Static info regarding the knob - }SHMOO[MAX_SHMOO]; // Denote max shmoo scenarios we have; Have 2; so that one for WR/RD and other Clock. - - //! Result Data - uint8_t convergence_gap; - shmoo_algorithm_t algorithm; - shmoo_mode mcbist_mode; - uint8_t mcbist_error_map[MAX_PORT][MAX_RANK][MAX_BYTE][MAX_NIBBLES]; //MAX byte is 10; Max Nibble are 2; - uint8_t count_bad_dq[MAX_PORT]; - uint8_t schmoo_error_map[MAX_PORT][MAX_RANK][20]; - uint8_t binary_done_map[MAX_PORT][MAX_RANK][20]; - shmoo_type_t shmoo_mask; - uint8_t iv_addr; - uint8_t iv_MAX_RANKS[MAX_PORT]; - uint8_t iv_MAX_BYTES; - uint32_t iv_pattern; - uint32_t iv_test_type; - uint8_t iv_dmm_type; - uint8_t iv_SHMOO_ON; - uint8_t iv_DQS_ON; - uint8_t iv_shmoo_type; - uint16_t iv_shmoo_param; - uint16_t iv_binary_diff; - uint16_t iv_vref_mul; - uint8_t valid_rank[MAX_RANK]; - uint8_t valid_rank1[MAX_PORT][MAX_RANK]; - -public: - - enum bound_t {LEFT, RIGHT}; - - generic_shmoo(uint8_t iv_addr,shmoo_type_t shmoo_mask,shmoo_algorithm_t shmoo_algorithm);// Constructor - generic_shmoo(){}; - ~generic_shmoo(){}; - - //initialize multi dim arrays to known value - void init_multi_array(uint16_t (&array)[MAX_DQ], - uint16_t init_val); - - // Read in all the Nominal values of the relevant knobs - fapi::ReturnCode get_all_noms(const fapi::Target & i_target); - - fapi::ReturnCode set_all_binary(const fapi::Target & i_target, - bound_t bound); - - // Read in all the Nominal values of the relevant knobs - fapi::ReturnCode get_all_noms_dqs(const fapi::Target & i_target); - - // generic Right bound - fapi::ReturnCode find_bound(const fapi::Target & i_target,bound_t); - - // Increment or decrement the knob - fapi::ReturnCode knob_update(const fapi::Target & i_target, - bound_t bound, - uint8_t scenario, - uint8_t bit, - uint8_t pass, - bool &flag); - - fapi::ReturnCode knob_update_bin(const fapi::Target & i_target, - bound_t bound, - uint8_t scenario, - uint8_t bit, - uint8_t pass, - bool &flag); - - fapi::ReturnCode knob_update_dqs_by8(const fapi::Target & i_target, - bound_t bound, - uint8_t scenario, - uint8_t bit, - uint8_t pass, - bool &flag); - - fapi::ReturnCode knob_update_dqs_by4(const fapi::Target & i_target, - bound_t bound, - uint8_t scenario, - uint8_t bit, - uint8_t pass, - bool &flag); - - // Print Shmoo report to STDOUT - fapi::ReturnCode print_report(const fapi::Target & i_target); - - fapi::ReturnCode print_report_dqs(const fapi::Target & i_target); - fapi::ReturnCode print_report_dqs2(const fapi::Target & i_target); - - fapi::ReturnCode get_margin(const fapi::Target & i_target); - fapi::ReturnCode get_margin2(const fapi::Target & i_target); - - fapi::ReturnCode get_margin_dqs_by8(const fapi::Target & i_target); - - fapi::ReturnCode get_margin_dqs_by4(const fapi::Target & i_target); - - fapi::ReturnCode get_min_margin(const fapi::Target & i_target, - uint32_t *o_right_min_margin, - uint32_t *o_left_min_margin); - fapi::ReturnCode get_min_margin2(const fapi::Target & i_target, - uint32_t *o_right_min_margin, - uint32_t *o_left_min_margin); - - fapi::ReturnCode get_min_margin_dqs(const fapi::Target & i_target, - uint32_t *o_right_min_margin, - uint32_t *o_left_min_margin); - - fapi::ReturnCode do_mcbist_test(const fapi::Target & i_target); - - fapi::ReturnCode do_mcbist_reset(const fapi::Target & i_target); - - fapi::ReturnCode check_error_map(const fapi::Target & i_target, - uint8_t port,uint8_t &pass); - fapi::ReturnCode check_error_map2(const fapi::Target & i_target, - uint8_t port,uint8_t &pass); - - fapi::ReturnCode sanity_check(const fapi::Target & i_target); - - fapi::ReturnCode schmoo_setup_mcb(const fapi::Target & i_target); - - fapi::ReturnCode knob_update_dqs_by8_isdimm(const fapi::Target & i_target, - bound_t bound, - uint8_t scenario, - uint8_t bit, - uint8_t pass, - bool &flag); - - fapi::ReturnCode knob_update_dqs_by4_isdimm(const fapi::Target & i_target, - bound_t bound, - uint8_t scenario, - uint8_t bit, - uint8_t pass, - bool &flag); - - fapi::ReturnCode run(const fapi::Target & i_target, - uint32_t *right_min_margin, - uint32_t *left_min_margin, - uint32_t i_vref_mul); - - fapi::ReturnCode shmoo_save_rest(const fapi::Target & i_target, - uint64_t i_content_array[], - uint8_t i_mode); - fapi::ReturnCode get_nibble_pda(const fapi::Target & i_target,uint32_t pda_nibble_table[2][2][16][2]); - fapi::ReturnCode knob_update_bin_composite(const fapi::Target & i_target,bound_t bound,uint8_t scenario,uint8_t bit,uint8_t pass,bool &flag); - fapi::ReturnCode print_report2(const fapi::Target & i_target); - -}; -#endif diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist.C deleted file mode 100755 index c70653e08..000000000 --- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist.C +++ /dev/null @@ -1,1145 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist.C $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2012,2015 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: mss_mcbist.C,v 1.57 2015/08/26 16:17:41 sasethur Exp $ -// *!*************************************************************************** -// *! (C) Copyright International Business Machines Corp. 1997, 1998 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -// *!*************************************************************************** -// *! FILENAME : mss_mcbist.C -// *! TITLE : -// *! DESCRIPTION : MCBIST Procedures -// *! CONTEXT : -// *! -// *! OWNER NAME : Hosmane, Preetham Email: preeragh@in.ibm.com -// *! BACKUP : Sethuraman, Saravanan Email: saravanans@in.ibm.com -// *!*************************************************************************** -// CHANGE HISTORY: -//------------------------------------------------------------------------------ -// Version:|Author: | Date: | Comment: -// --------|--------|--------|-------------------------------------------------- -// 1.57 |preeragh|08/25/15| FW Review Comments MPR -// 1.53 |preeragh|06/22/15| Added MPR -// 1.52 |sglancy |02/16/15| Merged in FW comments with lab needs -// 1.51 |sglancy |02/09/15| Fixed FW comments and adjusted whitespace -// 1.50 |preeragh|01/16/15| Fixed FW comments -// 1.48 |preeragh|01/05/15| Added FW workaround for drand -// 1.48 |preeragh|12/16/14| Revert back changes. v.1.46 -// 1.47 |rwheeler|11/19/14|option to pass in rotate data seed -// 1.46 |mjjones |01/20/14|RAS Review Updates -// 1.45 |aditya |12/17/13|Added Simple_fix_rf -// 1.43 |aditya |10/05/13|Updated fw comments -// 1.42 |aditya |09/18/13|Updated Call for functions -// 1.41 |aditya |08/10/13|Minor Fix for Hostboot compile -// 1.40 |aditya |06/11/13|Added attributes ATTR_MCBIST_PRINTING_DISABLE and ATTR_MCBIST_DATA_ENABLE -// 1.39 |aditya |05/22/13|updated parameters for Subtest Printing -// 1.38 |aditya |05/14/13|updated parameters for cfg_mcb_dgen -// 1.37 |aditya |02/19/13|updated testtypes -// 1.34 |aditya |02/13/13|updated testtypes -// 1.33 |aditya |02/12/13|updated testtypes -// 1.32 |aditya |02/11/13|updated testtypes -// 1.31 |aditya |02/06/13|Updated SIMPLE_RAND test_type -// 1.30 |aditya |01/30/13|Updated fw comments -// 1.29 |aditya |01/11/13|Updated cfg_mcb_dgen function -// 1.28 |aditya |01/11/13|Updated cfg_mcb_dgen function -// 1.27 |aditya |01/11/13|Updated cfg_mcb_dgen function -// 1.26 |aditya |01/07/13|Updated Review Comments -// 1.25 |aditya |01/03/13| Updated FW Comments -// 1.23 |aditya |12/18/12| Updated Review Comments -// 1.22 |aditya |12/14/12| Updated FW review comments -// 1.22 |aditya |12/6/12 | Updated Review Comments -// 1.21 |aditya |11/15/12| Updated for FIRMWARE REVIEW COMMENTS -// 1.20 |aditya |10/29/12| updated fw review comments -// 1.18 |aditya |10/29/12| Updated from ReturnCode to fapi::ReturnCode and Target to const fapi::Target & -// 1.17 |aditya |10/18/12| Replaced insertFromHexRight by SetDoubleWord -// 1.16 |aditya |10/17/12| updated code to be compatible with ecmd 13 release -// 1.15 |aditya |10/01/12| updated fw review comments, datapattern, testtype, addressing -// 1.14 |mwuu |07/17/12| updated dram_width tests to new definition -// 1.13 |bellows |07/16/12| added in Id tag -// 1.10 |gaushard|04/26/12| Added ONE_SHMOO parameter -// 1.9 |gaushard|03/26/12| Updated start_mcbist -// 1.8 |gaushard|03/26/12| Removed Extra Comments/Codes -// 1.7 |gaushard|03/26/12| Added new shmoo modes -// 1.6 |sasethur|03/23/12| Corrected Warning Messages -// 1.5 |sasethur|03/23/12| Corrected Warning messages -// 1.4 |gaushard|03/22/12| Added Address generation -// 1.3 |gaushard|02/29/12| Added rc_num for Buffer operation -// 1.2 |gaushard|02/14/12| Added rc_buff for buffer access -// 1.1 |gaushard|02/13/12| Updated scom addresses -// 1.0 |gaushard|01/19/12| Initial Version -//------------------------------------------------------------------------------ - -#include "mss_mcbist.H" -extern "C" -{ -using namespace fapi; - -const uint8_t MAX_BYTE = 10; -//*****************************************************************/ -// Funtion name : cfg_mcb_test_mem -// Description : This function executes different MCBIST subtests -// Input Parameters : -// const fapi::Target & i_target_mba Centaur.mba -// mcbist_test_mem i_test_type Subtest Type -//****************************************************************/ - -fapi::ReturnCode cfg_mcb_test_mem(const fapi::Target & i_target_mba, - mcbist_test_mem i_test_type, - struct Subtest_info l_sub_info[30]) -{ - fapi::ReturnCode rc; - uint8_t l_print = 0; - uint32_t l_mcbtest; - uint8_t l_index, l_data_flag, l_random_flag, l_count, l_data_attr; - l_index = 0; - l_data_flag = 0; - l_random_flag = 0; - l_data_attr = 0; - uint8_t test_array_count[44] = { 0, 2, 2, 1, 1, 1, 6, 6, 30, 30, - 2, 7, 4, 2, 1, 5, 4, 2, 1, 1, - 3, 1, 1, 4, 2, 1, 1, 1, 1, 10, - 0, 5, 3, 3, 3, 3, 9, 4, 30, 1, - 2, 2, 3, 3 }; - rc = FAPI_ATTR_GET(ATTR_MCBIST_PRINTING_DISABLE, &i_target_mba, l_print); - if (rc) return rc; - if (l_print == 0) - { - FAPI_INF("Function Name: cfg_mcb_test_mem"); - FAPI_INF("Start Time"); - } - rc = FAPI_ATTR_GET(ATTR_MCBIST_TEST_TYPE, &i_target_mba, l_mcbtest); - if (rc) return rc; - - if (l_print == 0) - { - FAPI_INF("Function - cfg_mcb_test_mem"); - } - - uint8_t l_done_bit = 0; - rc = FAPI_ATTR_SET(ATTR_MCBIST_ADDR_BANK, &i_target_mba, l_done_bit); - if (rc) return rc; - - if (i_test_type == CENSHMOO) - { - if (l_print == 0) - { - FAPI_INF("Current MCBIST TESTTYPE : CENSHMOO "); - } - rc = mcb_write_test_mem(i_target_mba, MBA01_MCBIST_MCBMR0Q_0x030106a8, - W, 0, SF, FIX, 0, DEFAULT, FIX_ADDR, 0, 0, 1, l_sub_info); - if (rc) return rc; - rc = mcb_write_test_mem(i_target_mba, MBA01_MCBIST_MCBMR0Q_0x030106a8, - R, 0, SF, FIX, 1, DEFAULT, FIX_ADDR, 1, 1, 1, l_sub_info); - if (rc) return rc; - } - else if (i_test_type == MEMWRITE) - { - if (l_print == 0) - { - FAPI_INF("Current MCBIST TESTTYPE : MEMWRITE "); - } - rc = mcb_write_test_mem(i_target_mba, MBA01_MCBIST_MCBMR0Q_0x030106a8, - W, 0, SF, FIX, 1, DEFAULT, FIX_ADDR, 0, 0, 0, l_sub_info); - if (rc) return rc; - } - else if (i_test_type == MEMREAD) - { - if (l_print == 0) - { - FAPI_INF("Current MCBIST TESTTYPE : MEMREAD "); - } - rc = mcb_write_test_mem(i_target_mba, MBA01_MCBIST_MCBMR0Q_0x030106a8, - R, 0, SF, FIX, 1, DEFAULT, FIX_ADDR, 0, 0, 0, l_sub_info); - if (rc) return rc; - } - else if (i_test_type == SIMPLE_FIX) - { - if (l_print == 0) - { - FAPI_INF("Current MCBIST TESTTYPE : SIMPLE_FIX "); - } - rc = mcb_write_test_mem(i_target_mba, MBA01_MCBIST_MCBMR0Q_0x030106a8, - W, 0, SF, FIX, 0, DEFAULT, FIX_ADDR, 0, 0, 4, l_sub_info); - if (rc) return rc; - rc = mcb_write_test_mem(i_target_mba, MBA01_MCBIST_MCBMR0Q_0x030106a8, - R, 0, SF, FIX, 1, DEFAULT, FIX_ADDR, 1, 1, 4, l_sub_info); - if (rc) return rc; - - l_done_bit = 1; - rc = FAPI_ATTR_SET(ATTR_MCBIST_ADDR_BANK, &i_target_mba, l_done_bit); - if (rc) return rc; - - rc = mcb_write_test_mem(i_target_mba, MBA01_MCBIST_MCBMR0Q_0x030106a8, - R, 0, SF, FIX, 1, DEFAULT, FIX_ADDR, 2, 2, 4, l_sub_info); - if (rc) return rc; - rc = mcb_write_test_mem(i_target_mba, MBA01_MCBIST_MCBMR0Q_0x030106a8, - OPER_RAND, 0, RF, FIX, 1, DEFAULT, FIX_ADDR, 3, 3, 4, l_sub_info); - if (rc) return rc; - - rc = mcb_write_test_mem(i_target_mba, MBA01_MCBIST_MCBMR1Q_0x030106a9, - RW, 4, RF, DATA_RF, 0, DEFAULT, FIX_ADDR, 0, 4, 4, l_sub_info); - if (rc) - return rc; - } - else if (i_test_type == SIMPLE_RAND) - { - if (l_print == 0) - FAPI_INF("Current MCBIST TESTTYPE : SIMPLE_RAND "); - rc = mcb_write_test_mem(i_target_mba, MBA01_MCBIST_MCBMR0Q_0x030106a8, - WR, 0, SF, DATA_RF, 1, DEFAULT, FIX_ADDR, 0, 0, 4, l_sub_info); - if (rc) return rc; - - l_done_bit = 1; - rc = FAPI_ATTR_SET(ATTR_MCBIST_ADDR_BANK, &i_target_mba, l_done_bit); - if (rc) return rc; - - rc = mcb_write_test_mem(i_target_mba, MBA01_MCBIST_MCBMR0Q_0x030106a8, - R, 1, SF, DATA_RF, 0, DEFAULT, FIX_ADDR, 1, 1, 4, l_sub_info); - if (rc) return rc; - rc = mcb_write_test_mem(i_target_mba, MBA01_MCBIST_MCBMR0Q_0x030106a8, - W, 0, RF, DATA_RF, 0, DEFAULT, FIX_ADDR, 2, 2, 4, l_sub_info); - if (rc) return rc; - rc = mcb_write_test_mem(i_target_mba, MBA01_MCBIST_MCBMR0Q_0x030106a8, - R, 0, RF, DATA_RF, 1, DEFAULT, FIX_ADDR, 3, 3, 4, l_sub_info); - if (rc) return rc; - - rc = mcb_write_test_mem(i_target_mba, MBA01_MCBIST_MCBMR1Q_0x030106a9, - RW, 4, RF, DATA_RF, 0, DEFAULT, FIX_ADDR, 0, 4, 4, l_sub_info); - if (rc) return rc; - } - else if (i_test_type == WR_ONLY) - { - if (l_print == 0) - { - FAPI_INF("Current MCBIST TESTTYPE : WR_ONLY "); - } - rc = mcb_write_test_mem(i_target_mba, MBA01_MCBIST_MCBMR0Q_0x030106a8, - W, 0, SF, DATA_RF, 0, DEFAULT, FIX_ADDR, 0, 0, 4, l_sub_info); - if (rc) return rc; - rc = mcb_write_test_mem(i_target_mba, MBA01_MCBIST_MCBMR0Q_0x030106a8, - R, 0, SF, DATA_RF, 1, DEFAULT, FIX_ADDR, 1, 1, 4, l_sub_info); - if (rc) return rc; - - l_done_bit = 1; - rc = FAPI_ATTR_SET(ATTR_MCBIST_ADDR_BANK, &i_target_mba, l_done_bit); - if (rc) return rc; - - rc = mcb_write_test_mem(i_target_mba, MBA01_MCBIST_MCBMR0Q_0x030106a8, - W, 0, RF, FIX, 0, DEFAULT, FIX_ADDR, 2, 2, 4, l_sub_info); - if (rc) return rc; - rc = mcb_write_test_mem(i_target_mba, MBA01_MCBIST_MCBMR0Q_0x030106a8, - OPER_RAND, 0, RF, FIX, 1, DEFAULT, FIX_ADDR, 3, 3, 4, l_sub_info); - if (rc) return rc; - - rc = mcb_write_test_mem(i_target_mba, MBA01_MCBIST_MCBMR1Q_0x030106a9, - RW, 4, RF, DATA_RF, 0, DEFAULT, FIX_ADDR, 0, 4, 4, l_sub_info); - if (rc) return rc; - } - else if (i_test_type == W_ONLY) - { - if (l_print == 0) - { - FAPI_INF("Current MCBIST TESTTYPE : W_ONLY "); - } - rc = mcb_write_test_mem(i_target_mba, MBA01_MCBIST_MCBMR0Q_0x030106a8, - W, 0, SF, DATA_RF, 1, DEFAULT, FIX_ADDR, 0, 0, 4, l_sub_info); - if (rc) return rc; - - l_done_bit = 1; - rc = FAPI_ATTR_SET(ATTR_MCBIST_ADDR_BANK, &i_target_mba, l_done_bit); - if (rc) return rc; - - rc = mcb_write_test_mem(i_target_mba, MBA01_MCBIST_MCBMR0Q_0x030106a8, - R, 0, SF, FIX, 1, DEFAULT, FIX_ADDR, 1, 1, 4, l_sub_info); - if (rc) return rc; - rc = mcb_write_test_mem(i_target_mba, MBA01_MCBIST_MCBMR0Q_0x030106a8, - W, 0, RF, FIX, 0, DEFAULT, FIX_ADDR, 2, 2, 4, - l_sub_info); - if (rc) return rc; - rc = mcb_write_test_mem(i_target_mba, MBA01_MCBIST_MCBMR0Q_0x030106a8, - OPER_RAND, 0, RF, FIX, 1, DEFAULT, FIX_ADDR, 3, 3, 4, l_sub_info); - if (rc) return rc; - - rc = mcb_write_test_mem(i_target_mba, MBA01_MCBIST_MCBMR1Q_0x030106a9, - RW, 4, RF, DATA_RF, 0, DEFAULT, FIX_ADDR, 0, 4, 4, l_sub_info); - if (rc) return rc; - } - else if (i_test_type == R_ONLY) - { - if (l_print == 0) - { - FAPI_INF("Current MCBIST TESTTYPE : R_ONLY "); - } - rc = mcb_write_test_mem(i_target_mba, MBA01_MCBIST_MCBMR0Q_0x030106a8, - R, 0, SF, DATA_RF, 1, DEFAULT, FIX_ADDR, 0, 0, 4, l_sub_info); - if (rc) return rc; - - l_done_bit = 1; - rc = FAPI_ATTR_SET(ATTR_MCBIST_ADDR_BANK, &i_target_mba, l_done_bit); - if (rc) return rc; - - rc = mcb_write_test_mem(i_target_mba, MBA01_MCBIST_MCBMR0Q_0x030106a8, - GOTO, 0, SF, FIX, 0, DEFAULT, FIX_ADDR, 1, 1, 4, l_sub_info); - if (rc) return rc; - rc = mcb_write_test_mem(i_target_mba, MBA01_MCBIST_MCBMR0Q_0x030106a8, - W, 0, RF, FIX, 0, DEFAULT, FIX_ADDR, 2, 2, 4, l_sub_info); - if (rc) return rc; - rc = mcb_write_test_mem(i_target_mba, MBA01_MCBIST_MCBMR0Q_0x030106a8, - OPER_RAND, 0, RF, FIX, 1, DEFAULT, FIX_ADDR, 3, 3, 4, l_sub_info); - if (rc) return rc; - - rc = mcb_write_test_mem(i_target_mba, MBA01_MCBIST_MCBMR1Q_0x030106a9, - RW, 4, RF, DATA_RF, 0, DEFAULT, FIX_ADDR, 0, 4, 4, l_sub_info); - if (rc) return rc; - } - else if (i_test_type == SIMPLE_FIX_RF) - { - FAPI_DBG("%s:Current MCBIST TESTTYPE : SIMPLE_FIX_RF ", - i_target_mba.toEcmdString()); - rc = mcb_write_test_mem(i_target_mba, MBA01_MCBIST_MCBMR0Q_0x030106a8, - W, 0, SF, DATA_RF, 0, DEFAULT, FIX_ADDR, 0, 0, 4, l_sub_info); - if (rc) return rc; - rc = mcb_write_test_mem(i_target_mba, MBA01_MCBIST_MCBMR0Q_0x030106a8, - R, 0, SF, DATA_RF, 1, DEFAULT, FIX_ADDR, 1, 1, 4, l_sub_info); - if (rc) return rc; - l_done_bit = 1; - rc = FAPI_ATTR_SET(ATTR_MCBIST_ADDR_BANK, &i_target_mba, l_done_bit); - if (rc) return rc; - } - else - { - FAPI_ERR("Invalid MCBIST test type (%d)! cfg_mcb_test_mem Function", - i_test_type); - const mcbist_test_mem & TEST_TYPE_PARAM = i_test_type; - FAPI_SET_HWP_ERROR(rc, RC_CFG_MCB_TEST_MEM_INVALID_INPUT); - return rc; - } - - if (l_print == 0) - { - FAPI_INF("Function Name: cfg_mcb_test_mem"); - FAPI_INF("Stop Time"); - } - - l_count = test_array_count[l_mcbtest]; - for (l_index = 0; l_index < l_count; l_index++) - { - if (l_sub_info[l_index].l_fixed_data_enable == 1) - { - l_data_flag = 1; - } - if (l_sub_info[l_index].l_random_data_enable == 1) - { - l_random_flag = 1; - } - } - if ((l_data_flag == 0) && (l_random_flag == 1)) - { - l_data_attr = 1; - } - else if ((l_data_flag == 1) && (l_random_flag == 0)) - { - l_data_attr = 2; - } - else if ((l_data_flag == 1) && (l_random_flag == 1)) - { - l_data_attr = 3; - } - else - { - l_data_attr = 3; - } - rc = FAPI_ATTR_SET(ATTR_MCBIST_DATA_ENABLE, &i_target_mba, l_data_attr); - if (rc) return rc; - - return rc; - -} - -//*****************************************************************/ -// Funtion name : cfg_mcb_dgen -// Description : This function writes data patterns based on i_datamode passed -// Input Parameters : -// const fapi::Target & i_target_mba Centaur.mba -// mcbist_data_gen i_datamode MCBIST Data mode -// uint8_t i_mcbrotate Provides the number of bit to shift per burst -// uint64_t i_mcbrotdata Provides the data seed to shift per burst -//****************************************************************/ -fapi::ReturnCode cfg_mcb_dgen(const fapi::Target & i_target_mba, - mcbist_data_gen i_datamode, - uint8_t i_mcbrotate, - uint64_t i_mcbrotdata) -{ - uint8_t l_print = 0; - - uint8_t l_data_attr, l_random_flag, l_data_flag; - l_data_flag = 1; - l_random_flag = 1; - l_data_attr = 3; - uint8_t l_seed_choice; - uint32_t i_seed; - i_seed = 0x20; - l_seed_choice = 1; - ecmdDataBufferBase l_data_buffer_64(64); - ecmdDataBufferBase l_var_data_buffer_64(64); - ecmdDataBufferBase l_var1_data_buffer_64(64); - ecmdDataBufferBase l_spare_data_buffer_64(64); - ecmdDataBufferBase l_data_buffer_32(32); - ecmdDataBufferBase l_data_buffer_16(16); - ecmdDataBufferBase l_data_buffer_4(4); - ecmdDataBufferBase l_data_buffer1_4(4); - uint64_t l_var = 0x0000000000000000ull; - uint64_t l_var1 = 0x0000000000000000ull; - uint64_t l_spare = 0x0000000000000000ull; - uint8_t l_rotnum = 0; - uint32_t l_mba01_mcb_pseudo_random[MAX_BYTE] = { - MBA01_MCBIST_MCBFD0Q_0x030106be, MBA01_MCBIST_MCBFD1Q_0x030106bf, - MBA01_MCBIST_MCBFD2Q_0x030106c0, MBA01_MCBIST_MCBFD3Q_0x030106c1, - MBA01_MCBIST_MCBFD4Q_0x030106c2, MBA01_MCBIST_MCBFD5Q_0x030106c3, - MBA01_MCBIST_MCBFD6Q_0x030106c4, MBA01_MCBIST_MCBFD7Q_0x030106c5, - MBA01_MCBIST_MCBFDQ_0x030106c6, MBA01_MCBIST_MCBFDSPQ_0x030106c7 }; - uint32_t l_mba01_mcb_random[MAX_BYTE] = { MBA01_MCBIST_MCBRDS0Q_0x030106b2, - MBA01_MCBIST_MCBRDS1Q_0x030106b3, MBA01_MCBIST_MCBRDS2Q_0x030106b4, - MBA01_MCBIST_MCBRDS3Q_0x030106b5, MBA01_MCBIST_MCBRDS4Q_0x030106b6, - MBA01_MCBIST_MCBRDS5Q_0x030106b7, MBA01_MCBIST_MCBRDS6Q_0x030106b8, - MBA01_MCBIST_MCBRDS7Q_0x030106b9, MBA01_MCBIST_MCBRDS8Q_0x030106ba, - 0x030106bb }; - uint32_t l_mbs01_mcb_random[MAX_BYTE] = { 0x02011675, 0x02011676, - 0x02011677, 0x02011678, 0x02011679, 0x0201167a, 0x0201167b, 0x0201167c, - 0x0201167d, 0x0201167e }; - uint32_t l_mbs23_mcb_random[MAX_BYTE] = { 0x02011775, 0x02011776, - 0x02011777, 0x02011778, 0x02011779, 0x0201177a, 0x0201177b, 0x0201177c, - 0x0201177d, 0x0201177e }; - - uint8_t l_index, l_index1 = 0; - uint32_t l_rand_32 = 0; - uint32_t l_rand_8 = 0; - fapi::ReturnCode rc; - uint32_t rc_num = 0; - if (l_print == 0) - { - FAPI_INF("Function Name: cfg_mcb_dgen"); - FAPI_INF(" Data mode is %d ", i_datamode); - } - uint8_t l_mbaPosition = 0; - - fapi::Target i_target_centaur; - rc = fapiGetParentChip(i_target_mba, i_target_centaur); - if (rc) - { - if (l_print == 0) - { - FAPI_INF("Error in getting parent chip!"); - } - return rc; - } - - if (l_print == 0) - { - FAPI_INF("Function cfg_mcb_dgen"); - } - //Read MBA position attribute 0 - MBA01 1 - MBA23 - rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target_mba, l_mbaPosition); - if (rc) - { - FAPI_ERR("Error getting MBA position"); - return rc; - } - rc = FAPI_ATTR_GET(ATTR_MCBIST_PRINTING_DISABLE, &i_target_mba, l_print); - if (rc) return rc; - - rc = FAPI_ATTR_GET(ATTR_MCBIST_DATA_ENABLE, &i_target_mba, l_data_attr); - if (rc) return rc; - - if (l_data_attr == 1) - { - l_data_flag = 0; - l_random_flag = 1; - } - else if (l_data_attr == 2) - { - l_data_flag = 1; - l_random_flag = 0; - } - else if (l_data_attr == 3) - { - l_data_flag = 1; - l_random_flag = 1; - } - else - { - l_data_flag = 1; - l_random_flag = 1; - } - - if (l_data_flag == 1) - { - if (i_datamode == MCBIST_2D_CUP_PAT5) - { - l_var = 0xFFFF0000FFFF0000ull; - l_var1 = 0x0000FFFF0000FFFFull; - l_spare = 0xFF00FF00FF00FF00ull; - - rc_num = l_var_data_buffer_64.setDoubleWord(0, l_var); - rc_num |= l_var1_data_buffer_64.setDoubleWord(0, l_var1); - rc_num |= l_spare_data_buffer_64.setDoubleWord(0, l_spare); - if (rc_num) - { - FAPI_ERR("cfg_mcb_dgen:"); - rc.setEcmdError(rc_num); - return rc; - } - - rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD0Q_0x030106be, l_var_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD1Q_0x030106bf, l_var1_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD2Q_0x030106c0, l_var_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD3Q_0x030106c1, l_var1_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD4Q_0x030106c2, l_var_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD5Q_0x030106c3, l_var1_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD6Q_0x030106c4, l_var_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD7Q_0x030106c5, l_var1_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFDQ_0x030106c6, l_spare_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFDSPQ_0x030106c7, l_spare_data_buffer_64); - if (rc) return rc; - } - else if (i_datamode == MCBIST_2D_CUP_PAT8) - { - l_var = 0xFFFFFFFFFFFFFFFFull; - l_var1 = 0x0000000000000000ull; - l_spare = 0xFFFF0000FFFF0000ull; - rc_num = l_var_data_buffer_64.setDoubleWord(0, l_var); - rc_num |= l_var1_data_buffer_64.setDoubleWord(0, l_var1); - rc_num |= l_spare_data_buffer_64.setDoubleWord(0, l_spare); - if (rc_num) - { - FAPI_ERR("cfg_mcb_dgen:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD0Q_0x030106be, l_var_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD1Q_0x030106bf, l_var_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD2Q_0x030106c0, l_var1_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD3Q_0x030106c1, l_var1_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD4Q_0x030106c2, l_var_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD5Q_0x030106c3, l_var_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD6Q_0x030106c4, l_var1_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD7Q_0x030106c5, l_var1_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFDQ_0x030106c6, l_spare_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFDSPQ_0x030106c7, l_spare_data_buffer_64); - if (rc) return rc; - } - else if (i_datamode == ABLE_FIVE) - { - l_var = 0xA5A5A5A5A5A5A5A5ull; - l_var1 = 0x5A5A5A5A5A5A5A5Aull; - l_spare = 0xA55AA55AA55AA55Aull; - - rc_num = l_spare_data_buffer_64.setDoubleWord(0, l_spare); - rc_num |= l_var_data_buffer_64.setDoubleWord(0, l_var); - rc_num |= l_var1_data_buffer_64.setDoubleWord(0, l_var1); - if (rc_num) - { - FAPI_ERR("cfg_mcb_dgen:"); - rc.setEcmdError(rc_num); - return rc; - } - - rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD0Q_0x030106be, l_var_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD1Q_0x030106bf, l_var1_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD2Q_0x030106c0, l_var_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD3Q_0x030106c1, l_var1_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD4Q_0x030106c2, l_var_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD5Q_0x030106c3, l_var1_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD6Q_0x030106c4, l_var_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD7Q_0x030106c5, l_var1_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFDQ_0x030106c6, l_spare_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFDSPQ_0x030106c7, l_spare_data_buffer_64); - if (rc) return rc; - } - else if(i_datamode == MPR) - { - l_var = 0x0000000000000000ull; - l_var1 =0xFFFFFFFFFFFFFFFFull; - l_spare = 0x00FF00FF00FF00FFull; - - rc_num = l_spare_data_buffer_64.setDoubleWord(0, l_spare); - rc_num |= l_var_data_buffer_64.setDoubleWord(0, l_var); - rc_num |= l_var1_data_buffer_64.setDoubleWord(0, l_var1); - if (rc_num) - { - FAPI_ERR("cfg_mcb_dgen:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD0Q_0x030106be, l_var_data_buffer_64); if(rc) return rc; - - rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD1Q_0x030106bf, l_var1_data_buffer_64); if(rc) return rc; - - rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD2Q_0x030106c0, l_var_data_buffer_64); if(rc) return rc; - - rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD3Q_0x030106c1, l_var1_data_buffer_64); if(rc) return rc; - - rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD4Q_0x030106c2, l_var_data_buffer_64); if(rc) return rc; - - rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD5Q_0x030106c3, l_var1_data_buffer_64); if(rc) return rc; - - rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD6Q_0x030106c4, l_var_data_buffer_64); if(rc) return rc; - - rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD7Q_0x030106c5, l_var1_data_buffer_64); if(rc) return rc; - - rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFDQ_0x030106c6 , l_spare_data_buffer_64); if(rc) return rc; - - rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFDSPQ_0x030106c7 , l_spare_data_buffer_64); if(rc) return rc; - } - else if ((i_datamode == DATA_GEN_DELTA_I) || - (i_datamode == MCBIST_2D_CUP_PAT0)) - { - l_var = 0xFFFFFFFFFFFFFFFFull; - l_var1 = 0x0000000000000000ull; - l_spare = 0xFF00FF00FF00FF00ull; - rc_num = l_spare_data_buffer_64.setDoubleWord(0, l_spare); - rc_num |= l_var_data_buffer_64.setDoubleWord(0, l_var); - rc_num |= l_var1_data_buffer_64.setDoubleWord(0, l_var1); - if (rc_num) - { - FAPI_ERR("cfg_mcb_dgen:"); - rc.setEcmdError(rc_num); - return rc; - } - - rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD0Q_0x030106be, l_var_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD1Q_0x030106bf, l_var1_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD2Q_0x030106c0, l_var_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD3Q_0x030106c1, l_var1_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD4Q_0x030106c2, l_var_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD5Q_0x030106c3, l_var1_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD6Q_0x030106c4, l_var_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD7Q_0x030106c5, l_var1_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFDQ_0x030106c6, l_spare_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFDSPQ_0x030106c7, l_spare_data_buffer_64); - if (rc) return rc; - } - else if (i_datamode == PSEUDORANDOM) - { - l_rand_32 = 0xFFFFFFFF;//Hard Coded Temporary Fix till random function is fixed - // srand(2); - if (l_seed_choice == 1) - { - if (i_seed == 0) - { - i_seed = 0xFFFFFFFF; - } - l_rand_32 = i_seed; - } - - for (l_index = 0; l_index < (MAX_BYTE); l_index++) - { - //l_rand_32 = rand(); - - rc_num |= l_data_buffer_32.insertFromRight(l_rand_32, 0, 32); - rc_num |= l_data_buffer_64.insert(l_data_buffer_32, 0, 32, 0); - //l_rand_32 = rand(); - rc_num |= l_data_buffer_32.insertFromRight(l_rand_32, 0, 32); - rc_num |= l_data_buffer_64.insert(l_data_buffer_32, 32, 32, 0); - if (rc_num) - { - FAPI_ERR("cfg_mcb_dgen:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, l_mba01_mcb_pseudo_random[l_index], - l_data_buffer_64); - if (rc) return rc; - } - } - else - { - FAPI_ERR("cfg_mcb_dgen: Invalid data mode (%d)", i_datamode); - const mcbist_data_gen & DATA_MODE_PARAM = i_datamode; - FAPI_SET_HWP_ERROR(rc, RC_CFG_MCB_DGEN_INVALID_INPUT); - return rc; - } - - if (i_datamode == MCBIST_2D_CUP_PAT5) - { - l_var = 0xFFFF0000FFFF0000ull; - l_var1 = 0x0000FFFF0000FFFFull; - l_spare = 0xFF00FF00FF00FF00ull; - - rc_num = l_var_data_buffer_64.setDoubleWord(0, l_var); - rc_num |= l_var1_data_buffer_64.setDoubleWord(0, l_var1); - rc_num |= l_spare_data_buffer_64.setDoubleWord(0, l_spare); - if (rc_num) - { - FAPI_ERR("cfg_mcb_dgen:"); - rc.setEcmdError(rc_num); - return rc; - } - - if (l_mbaPosition == 0) - { - //Writing MBS 01 pattern registers for comparison mode - rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD0Q_0x02011681, l_var_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD1Q_0x02011682, l_var1_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD2Q_0x02011683, l_var_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD3Q_0x02011684, l_var1_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD4Q_0x02011685, l_var_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD5Q_0x02011686, l_var1_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD6Q_0x02011687, l_var_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD7Q_0x02011688, l_var1_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFDQ_0x02011689, l_spare_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFDSPQ_0x0201168A, l_spare_data_buffer_64); - if (rc) return rc; - } - else if (l_mbaPosition == 1) - { - //Writing MBS 23 pattern registers for comparison mode - rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD0Q_0x02011781, l_var_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD1Q_0x02011782, l_var1_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD2Q_0x02011783, l_var_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD3Q_0x02011784, l_var1_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD4Q_0x02011785, l_var_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD5Q_0x02011786, l_var1_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD6Q_0x02011787, l_var_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD7Q_0x02011788, l_var1_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFDQ_0x02011789, l_spare_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFDSPQ_0x0201178A, l_spare_data_buffer_64); - if (rc) return rc; - } - } - else if (i_datamode == MCBIST_2D_CUP_PAT8) - { - l_var = 0xFFFFFFFFFFFFFFFFull; - l_var1 = 0x0000000000000000ull; - l_spare = 0xFFFF0000FFFF0000ull; - - rc_num = l_var_data_buffer_64.setDoubleWord(0, l_var); - rc_num |= l_var1_data_buffer_64.setDoubleWord(0, l_var1); - rc_num |= l_spare_data_buffer_64.setDoubleWord(0, l_spare); - if (rc_num) - { - FAPI_ERR("cfg_mcb_dgen:"); - rc.setEcmdError(rc_num); - return rc; - } - - if (l_mbaPosition == 0) - { - //Writing MBS 01 pattern registers for comparison mod - rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD0Q_0x02011681, l_var_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD1Q_0x02011682, l_var_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD2Q_0x02011683, l_var1_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD3Q_0x02011684, l_var1_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD4Q_0x02011685, l_var_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD5Q_0x02011686, l_var_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD6Q_0x02011687, l_var1_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD7Q_0x02011688, l_var1_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFDQ_0x02011689, l_spare_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFDSPQ_0x0201168A, l_spare_data_buffer_64); - if (rc) return rc; - } - else if (l_mbaPosition == 1) - { - //Writing MBS 23 pattern registers for comparison mod - rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD0Q_0x02011781, l_var_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD1Q_0x02011782, l_var_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD2Q_0x02011783, l_var1_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD3Q_0x02011784, l_var1_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD4Q_0x02011785, l_var_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD5Q_0x02011786, l_var_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD6Q_0x02011787, l_var1_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD7Q_0x02011788, l_var1_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFDQ_0x02011789, l_spare_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFDSPQ_0x0201178A, l_spare_data_buffer_64); - if (rc) return rc; - } - } - else if (i_datamode == ABLE_FIVE) - { - l_var = 0xA5A5A5A5A5A5A5A5ull; - l_var1 = 0x5A5A5A5A5A5A5A5Aull; - l_spare = 0xA55AA55AA55AA55Aull; - - rc_num = l_var_data_buffer_64.setDoubleWord(0, l_var); - rc_num |= l_var1_data_buffer_64.setDoubleWord(0, l_var1); - rc_num |= l_spare_data_buffer_64.setDoubleWord(0, l_spare); - if (rc_num) - { - FAPI_ERR("cfg_mcb_dgen:"); - rc.setEcmdError(rc_num); - return rc; - } - - if (l_mbaPosition == 0) - { - //Writing MBS 01 pattern registers for comparison mod - rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD0Q_0x02011681, l_var_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD1Q_0x02011682, l_var1_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD2Q_0x02011683, l_var_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD3Q_0x02011684, l_var1_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD4Q_0x02011685, l_var_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD5Q_0x02011686, l_var1_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD6Q_0x02011687, l_var_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD7Q_0x02011688, l_var1_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFDQ_0x02011689, l_spare_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFDSPQ_0x0201168A, l_spare_data_buffer_64); - if (rc) return rc; - } - else if (l_mbaPosition == 1) - { - //Writing MBS 23 pattern registers for comparison mod - rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD0Q_0x02011781, l_var_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD1Q_0x02011782, l_var1_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD2Q_0x02011783, l_var_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD3Q_0x02011784, l_var1_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD4Q_0x02011785, l_var_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD5Q_0x02011786, l_var1_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD6Q_0x02011787, l_var_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD7Q_0x02011788, l_var1_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFDQ_0x02011789, l_spare_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFDSPQ_0x0201178A, l_spare_data_buffer_64); - if (rc) return rc; - } - } - else if ((i_datamode == DATA_GEN_DELTA_I) || (i_datamode - == MCBIST_2D_CUP_PAT0)) - { - l_var = 0xFFFFFFFFFFFFFFFFull; - l_var1 = 0x0000000000000000ull; - l_spare = 0xFF00FF00FF00FF00ull; - - rc_num = l_var_data_buffer_64.setDoubleWord(0, l_var); - rc_num |= l_var1_data_buffer_64.setDoubleWord(0, l_var1); - rc_num |= l_spare_data_buffer_64.setDoubleWord(0, l_spare); - if (rc_num) - { - FAPI_ERR("cfg_mcb_dgen:"); - rc.setEcmdError(rc_num); - return rc; - } - - if (l_mbaPosition == 0) - { - //Writing MBS 01 pattern registers for comparison mod - rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD0Q_0x02011681, l_var_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_centaur,MBS_MCBIST01_MBS_MCBFD1Q_0x02011682, l_var1_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD2Q_0x02011683, l_var_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD3Q_0x02011684, l_var1_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD4Q_0x02011685, l_var_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD5Q_0x02011686, l_var1_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD6Q_0x02011687, l_var_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD7Q_0x02011688, l_var1_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFDQ_0x02011689, l_spare_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFDSPQ_0x0201168A, l_spare_data_buffer_64); - if (rc) return rc; - } - else if (l_mbaPosition == 1) - { - //Writing MBS 23 pattern registers for comparison mod - rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD0Q_0x02011781, l_var_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD1Q_0x02011782, l_var1_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD2Q_0x02011783, l_var_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD3Q_0x02011784, l_var1_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD4Q_0x02011785, l_var_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD5Q_0x02011786, l_var1_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD6Q_0x02011787, l_var_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD7Q_0x02011788, l_var1_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFDQ_0x02011789, l_spare_data_buffer_64); - if (rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFDSPQ_0x0201178A, l_spare_data_buffer_64); - if (rc) return rc; - } - } - else - { - FAPI_ERR("cfg_mcb_dgen: Invalid data mode (%d)", i_datamode); - const mcbist_data_gen & DATA_MODE_PARAM = i_datamode; - FAPI_SET_HWP_ERROR(rc, RC_CFG_MCB_DGEN_INVALID_INPUT); - return rc; - } - } - - if (l_random_flag == 1) - { - for (l_index = 0; l_index < MAX_BYTE; l_index++) - { - - for (l_index1 = 0; l_index1 < 8; l_index1++) - { - //l_rand_8 = rand(); - l_rand_8 = 0xFF; - rc_num = l_data_buffer_64.insert(l_rand_8, 8 * l_index1, 8, 24); - if (rc_num) - { - FAPI_ERR("cfg_mcb_dgen:"); - rc.setEcmdError(rc_num); - return rc; - } // Source start in sn is given as 24 -- need to ask - } - rc = fapiPutScom(i_target_mba, l_mba01_mcb_random[l_index], l_data_buffer_64); - if (rc) return rc; - - if (l_mbaPosition == 0) - { - rc = fapiPutScom(i_target_centaur, l_mbs01_mcb_random[l_index], l_data_buffer_64); - if (rc) return rc; - - } - else - { - rc = fapiPutScom(i_target_centaur, l_mbs23_mcb_random[l_index], l_data_buffer_64); - if (rc) return rc; - } - } - } - - #ifdef FAPI_MSSLABONLY - struct drand48_data randBuffer; - double l_rand_D = 0; - uint8_t l_rand_l = 0; - #endif - uint64_t l_data_buffer_64_value = 0; - - // get the rotate value loaded into reg, if rotate value 0 / not defined the default to rotate =13 - if(i_mcbrotate == 0) - { - FAPI_DBG("%s:i_mcbrotate == 0 , the l_rotnum is set to 13",i_target_mba.toEcmdString()); - l_rotnum = 13; // for random data generation - basic setup - } - else - { - l_rotnum = i_mcbrotate; - } - - - rc_num = rc_num | l_data_buffer_64.flushTo0(); - - // get the rotate data seed loaded into reg, if rotate data value = 0 / not defined the default rotate pttern is randomlly generated. - if(i_mcbrotdata == 0) - { // generate the random number - - #ifdef FAPI_MSSLABONLY - for(l_index1 = 0; l_index1 < 8; l_index1++) - { - //l_rand_8 = drand48_r(); - drand48_r(&randBuffer, &l_rand_D); - //l_rand_l = (uint8_t)l_rand_D; - l_rand_l = static_cast<unsigned int>((l_rand_D * 100) + 0.5); - if(l_rand_l == 0x00) - { - l_rand_l = 0xFF; - } - //FAPI_INF("%s:Value of seed drand48_r : %02X",i_target_mba.toEcmdString(), l_rand_l ); - rc_num = rc_num | l_data_buffer_64.insert(l_rand_l,8*l_index1,8); // Source start in sn is given as 24 -- need to ask - if (rc_num) - { - FAPI_ERR( "cfg_mcb_dgen: setting up mcbrotate data error"); // Error setting up buffers - rc.setEcmdError(rc_num); - return rc; - } - } - #else - rc_num = rc_num | l_data_buffer_64.setDoubleWord(0,0x863A822CDF2924C4ull); - if (rc_num) - { - FAPI_ERR( "cfg_mcb_dgen: setting up mcbrotate data error"); // Error setting up buffers - rc.setEcmdError(rc_num); - return rc; - } - #endif - } - else - { - rc_num = rc_num | l_data_buffer_64.setDoubleWord(0,i_mcbrotdata); - if (rc_num) - { - FAPI_ERR( "cfg_mcb_dgen:"); // Error setting up buffers - rc.setEcmdError(rc_num); - return rc; - } - } - - // load the mcbist and mba with rotnum and rotdata. - rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBDRSRQ_0x030106bc , l_data_buffer_64); if(rc) return rc;//added - if(l_mbaPosition == 0) - { - rc = fapiPutScom(i_target_centaur, 0x0201167F , l_data_buffer_64); if(rc) return rc; - l_data_buffer_64_value = l_data_buffer_64.getDoubleWord (0); - FAPI_INF("%s:Value of Rotate data seed %016llX for reg %08X",i_target_mba.toEcmdString(), l_data_buffer_64_value, 0x0201167F ); - - rc_num = rc_num | l_data_buffer_16.insert(l_data_buffer_64,0,16); - rc = fapiGetScom(i_target_centaur, 0x02011680 , l_data_buffer_64); if(rc) return rc; - rc_num = rc_num | l_data_buffer_64.insert(l_rotnum,0,4,4); - rc_num = rc_num | l_data_buffer_64.insert(l_data_buffer_16,4,16); - if (rc_num) - { - FAPI_ERR( "cfg_mcb_dgen:"); // Error setting up buffers - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_centaur, 0x02011680 , l_data_buffer_64); if(rc) return rc; - - } - else - { - rc = fapiPutScom(i_target_centaur, 0x0201177F , l_data_buffer_64); if(rc) return rc;//added - l_data_buffer_64_value = l_data_buffer_64.getDoubleWord (0); - FAPI_INF("%s:Value of Rotate data seed %016llX for reg %08X",i_target_mba.toEcmdString(), l_data_buffer_64_value, 0x0201177F ); - - rc_num = rc_num | l_data_buffer_16.insert(l_data_buffer_64,0,16); - rc = fapiGetScom(i_target_centaur, 0x02011780 , l_data_buffer_64); if(rc) return rc; - rc_num = rc_num | l_data_buffer_64.insert(l_rotnum,0,4,4); - rc_num = rc_num | l_data_buffer_64.insert(l_data_buffer_16,4,16); - if (rc_num) - { - FAPI_ERR( "cfg_mcb_dgen:"); // Error setting up buffers - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_centaur, 0x02011780 , l_data_buffer_64); if(rc) return rc; - - } - - FAPI_DBG("%s: Preet Clearing bit 20 of MBA01_MCBIST_MCBDRCRQ_0x030106bd to avoid inversion of data to the write data flow",i_target_mba.toEcmdString()); - rc_num = rc_num | l_data_buffer_64.clearBit(20,2); - if (rc_num) - { - FAPI_ERR( "cfg_mcb_dgen:"); // Error setting up buffers - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba,MBA01_MCBIST_MCBDRCRQ_0x030106bd,l_data_buffer_64); - - return rc; -} - -} diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist.H b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist.H deleted file mode 100755 index 9782c338a..000000000 --- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist.H +++ /dev/null @@ -1,368 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2012,2015 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: mss_mcbist.H,v 1.49 2015/08/07 11:09:15 sasethur Exp $ -// *!*************************************************************************** -// *! (C) Copyright International Business Machines Corp. 1997, 1998 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -// *!*************************************************************************** -// *! FILENAME : mss_mcbist.H -// *! TITLE : -// *! DESCRIPTION : MCBIST procedures -// *! CONTEXT : -// *! -// *! OWNER NAME : Preetham Hosmane Email: preeragh@in.ibm.com -// *! BACKUP : Sethuraman, Saravanan Email: saravanans@in.ibm.com -// *!*************************************************************************** -// CHANGE HISTORY: -//------------------------------------------------------------------------------- -// Version:|Author: | Date: | Comment: -// --------|--------|---------|-------------------------------------------------- -// 1.49 |preeragh|7/26/15 | Added RW infinite -// 1.48 |lapietra|6/26/15 | Added RMWFIX and RMWFIX_I tests -// 1.47 |sglancy |12/16/14| Merged FW comments with lab debugging needs -// 1.46 |preeragh|12/15/14| Revert back, removed rwheeler changes -// 1.43 |rwheeler|11/19/14|option to pass in rotate data seed -// 1.42 |mjjones |01/20/14 |RAS Review Updates -// 1.41 |aditya |12/17/13 |Updated mcb_error_map function parameters -// 1.40 |rwheeler|10/29/13 |added W_ONLY_INFINITE_RAND test -// 1.39 |aditya |10/29/13 |Updated mcb_error_map function parameters -// 1.38 |aditya |09/18/13 |Updated parameters for random seed attribute -// 1.37 |aditya |08/02/13 |Updated parameters in mcb_error_map_print function -// 1.36 |aditya |07/09/13 |Added l_random_addr_enable and l_fixed_addr_enable for struct Subtest_info -// 1.35 |aditya |06/11/13 |Added l_random_data_enable and l_fixed_data_enable for struct Subtest_info -// 1.34 |aditya |05/23/13 |Added TEST_RR and TEST_RF testtypes -// 1.33 |aditya |05/22/13 |updated parameters for Subtest Printing -// 1.32 |aditya |05/14/13 |updated parameters for cfg_mcb_dgen and random seed details -// 1.31 |aditya |05/07/13 |Changed Parameter Passing in Functions -// 1.30 |aditya |04/22/13 |updated testtypes -// 1.27 |aditya |02/13/13 |updated testtypes -// 1.25 |aditya |02/12/13 |updated testtypes -// 1.24 |aditya |01/30/13 |Updated fw comments -// 1.23 |aditya |01/16/13 |added a parameter to setup_mcbist function -// 1.22 |aditya |01/11/13 |added a parameter to setup_mcbist function -// 1.21 |aditya |01/07/13 | Updated FW Review Comments -// 1.20 |aditya |01/03/13 | Updated FW Comments -// 1.18 |aditya |12/18/12 | Updated Review Comments -// 1.17 |aditya |12/14/12 |Updated FW review comments -// 1.16 |aditya |12/6/12 | Updated Review Comments -// 1.15 |aditya |11/15/12 | Updated for FW REVIEW COMMENTS -// 1.13 |aditya |10/29/12 | Updated from ReturnCode to fapi::ReturnCode and Target to const fapi::Target & -// 1.12 |aditya |10/18/12 | Changed Parameters for Function mcb_write_test_mem -// 1.11 |aditya |10/17/12 | updated code to be compatible with ecmd 13 release -// 1.10 |aditya |15-Oct-12| Moved scom address to cen_scom_addresses.H, added user option -// 1.9 |bellows |16-Jul-12| Added in Id tag -// 1.6 |gaushard|26/03/12 | Removed Extra Comments/Codes -// 1.5 |gaushard|26/03/12 | Updated Function Declaration -// 1.4 |sasethur|23/03/12 | Added enum for shmoo mode -// 1.3 |gaushard|22/03/12 | Added address generation function -// 1.2 |sasethur|24/02/12 | Updated Typo -// 1.1 |gaushard|14/02/12 | Shifted register address from .C file to .H file -// 1.0 |gaushard|12/01/12 | Initial version -//------------------------------------------------------------------------------ -#ifndef MSS_MCBIST_H -#define MSS_MCBIST_H -/****************************************************************************************/ -/* mss_mcbist.H */ -/****************************************************************************************/ -#include <fapi.H> -#include <cen_scom_addresses.H> -#include <mss_access_delay_reg.H> - -extern "C" -{ -using namespace fapi; - -//############### Global variables ################ - -enum mcbist_test_mem -{ - USER_MODE, - CENSHMOO, - SUREFAIL, - MEMWRITE, - MEMREAD, - CBR_REFRESH, - MCBIST_SHORT, - SHORT_SEQ, - DELTA_I, - DELTA_I_LOOP, - SHORT_RAND, - LONG1, - BUS_TAT, - SIMPLE_FIX, - SIMPLE_RAND, - SIMPLE_RAND_2W, - SIMPLE_RAND_FIXD, - SIMPLE_RA_RD_WR, - SIMPLE_RA_RD_R, - SIMPLE_RA_FD_R, - SIMPLE_RA_FD_R_INF, - SIMPLE_SA_FD_R, - SIMPLE_RA_FD_W, - INFINITE, - WR_ONLY, - W_ONLY, - R_ONLY, - W_ONLY_RAND, - R_ONLY_RAND, - R_ONLY_MULTI, - SHORT, - SIMPLE_RAND_BARI, - W_R_INFINITE, - W_R_RAND_INFINITE, - R_INFINITE1, - R_INFINITE_RF, - MARCH, - SIMPLE_FIX_RF, - SHMOO_STRESS, - SIMPLE_RAND_RA, - SIMPLE_FIX_RA, - SIMPLE_FIX_RF_RA, - TEST_RR, - TEST_RF, - W_ONLY_INFINITE_RAND, - MCB_2D_CUP_SEQ, - MCB_2D_CUP_RAND, - SHMOO_STRESS_INFINITE, - HYNIX_1_COL, - RMWFIX, - RMWFIX_I, - W_INFINITE, - R_INFINITE -}; - -enum mcbist_data_gen -{ - ABLE_FIVE, - USR_MODE, - ONEHOT, - DQ0_00011111_RESTALLONE, - DQ0_11100000_RESTALLZERO, - ALLZERO, - ALLONE, - BYTE_BURST_SIGNATURE, - BYTE_BURST_SIGNATURE_V1, - BYTE_BURST_SIGNATURE_V2, - BYTE_BURST_SIGNATURE_V3, - DATA_GEN_DELTA_I, - MCBIST_2D_CUP_PAT0, - MPR, - MPR03, - MPR25, - MPR47, - DELTA_I1, - MCBIST_2D_CUP_PAT1, - MHC_55, - MHC_DQ_SIM, - MCBIST_2D_CUP_PAT2, - MCBIST_2D_CUP_PAT3, - MCBIST_2D_CUP_PAT4, - MCBIST_2D_CUP_PAT5, - MCBIST_2D_CUP_PAT6, - MCBIST_2D_CUP_PAT7, - MCBIST_2D_CUP_PAT8, - MCBIST_2D_CUP_PAT9, - CWLPATTERN, - GREY1, - DC_ONECHANGE, - DC_ONECHANGEDIAG, - GREY2, - FIRST_XFER, - MCBIST_222_XFER, - MCBIST_333_XFER, - MCBIST_444_XFER, - MCBIST_555_XFER, - MCBIST_666_XFER, - MCBIST_777_XFER, - MCBIST_888_XFER, - FIRST_XFER_X4MODE, - MCBIST_LONG, - PSEUDORANDOM, - CASTLE -}; - -enum mcbist_oper_type -{ - W, - R, - RW, - WR, - RWR, - RWW, - OPER_RAND, - GOTO -}; - -enum mcbist_data_mode -{ - FIX, - DATA_RF, - DATA_RR, - RECCF, - RECCB, - DEA, - DRL, - DRR - -}; - -enum mcbist_addr_mode -{ - SF, - SR, - RF, - RR -}; - -enum mcbist_add_select_mode -{ - FIX_ADDR, - PORTA0_RANDOM, - PORTA1_RANDOM, - PORTA0_SEQ -}; - -enum mcbist_data_select_mode -{ - DEFAULT, - BURST0, - BURST1, - BURST2 -}; - -enum mcbist_byte_mask -{ - BYTE0, - BYTE1, - BYTE2, - BYTE3, - BYTE4, - BYTE5, - BYTE6, - BYTE7, - BYTE8, - BYTE9, - UNMASK_ALL, - NONE -}; - -enum shmoo_mode -{ - FAST = 0, - ONE_SLOW = 1, - QUARTER_SLOW = 2, - HALF_SLOW = 3, - FULL_SLOW = 4, - ONE_CHAR = 5, - QUARTER_CHAR = 6, - HALF_CHAR = 7, - FULL_CHAR = 8 -}; - -enum shmoo_addr_mode -{ - FEW_ADDR= 0, - QUARTER_ADDR = 1, - HALF_ADDR = 2, - FULL_ADDR = 3 -}; - -struct Subtest_info -{ -uint8_t l_operation_type; -uint8_t l_data_mode; -uint8_t l_addr_mode; -uint8_t l_random_data_enable; -uint8_t l_fixed_data_enable; -uint8_t l_random_addr_enable; -uint8_t l_fixed_addr_enable; -}; - - -fapi::ReturnCode poll_mcb(const fapi::Target & i_target_mba, - uint8_t *o_mcb_status, - struct Subtest_info l_sub_info[30], - uint8_t i_flag); - -fapi::ReturnCode mcb_error_map(const fapi::Target & i_target_mba, - uint8_t o_error_map[][8][10][2], - uint8_t i_CDarray0[80], - uint8_t i_CDarray1[80], - uint8_t count_bad_dq[2]); - -fapi::ReturnCode mcb_write_test_mem(const fapi::Target & i_target_mba, - const uint64_t i_reg_addr, - mcbist_oper_type i_operation_type, - uint8_t i_cfg_test_123_cmd, - mcbist_addr_mode i_addr_mode, - mcbist_data_mode i_data_mode, - uint8_t i_done, - mcbist_data_select_mode i_data_select_mode, - mcbist_add_select_mode i_addr_select_mode, - uint8_t i_testnumber, - uint8_t i_testnumber1, - uint8_t i_total_no, - struct Subtest_info l_sub_info[30]); - -fapi::ReturnCode cfg_mcb_test_mem(const fapi::Target & i_target_mba, - mcbist_test_mem i_test_type, - struct Subtest_info l_sub_info[30]); - -fapi::ReturnCode mcb_reset_trap(const fapi::Target & i_target_mba); - -fapi::ReturnCode cfg_mcb_dgen(const fapi::Target & i_target_mba, - mcbist_data_gen i_datamode, - uint8_t i_mcbrotate, - uint64_t i_mcbrotdata); - -fapi::ReturnCode cfg_byte_mask(const fapi::Target & i_target_mba); - -fapi::ReturnCode start_mcb(const fapi::Target & i_target_mba); - -fapi::ReturnCode setup_mcbist(const fapi::Target & i_target_mba, - mcbist_byte_mask i_mcbbytemask, - uint8_t i_mcbrotate, - uint64_t i_mcbrotdata, - struct Subtest_info l_sub_info[30], - char * l_str_cust_addr); - -fapi::ReturnCode mcb_error_map_print(const fapi::Target & i_target_mba, - ecmdDataBufferBase & l_mcb_fail_160, - uint8_t i_port, - uint8_t l_array[80], - uint8_t l_number, - ecmdDataBufferBase l_data_buf_port, - ecmdDataBufferBase l_data_buf_spare); - -fapi::ReturnCode mss_conversion_testtype(const fapi::Target & i_target_mba, - uint8_t l_pattern, - mcbist_test_mem &i_mcbtest); - -fapi::ReturnCode mss_conversion_data(const fapi::Target & i_target_mba, - uint8_t l_pattern, - mcbist_data_gen &i_mcbpatt); -} -#endif diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_address.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_address.C deleted file mode 100644 index 2d353e388..000000000 --- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_address.C +++ /dev/null @@ -1,1692 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_address.C $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2013,2015 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: mss_mcbist_address.C,v 1.26 2015/07/24 08:32:13 sasethur Exp $ -// *!*************************************************************************** -// *! (C) Copyright International Business Machines Corp. 1997, 1998, 2013 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -// *!*************************************************************************** -// *! FILENAME : mss_mcbist_address_default.C -// *! TITLE : -// *! DESCRIPTION : MCBIST procedures -// *! CONTEXT : -// *! -// *! OWNER NAME : Preetham Hosmane | preeragh@in.ibm.com -// *! BACKUP : Saravanan Sethuraman -// *!*************************************************************************** -// CHANGE HISTORY: -//------------------------------------------------------------------------------- -// Version:|Author: | Date: | Comment: -// --------|--------|---------|-------------------------------------------------- -// 1.26 |preeragh|22-Jul-15| 64bit compile fix -// 1.25 |preeragh|22-Jun-15| DDR4 - Mods and fixes -// 1.24 |lwmulkey|15-JUN-15| Add 2H CDIMM support -// 1.20 |lwmulkey|06-JUN-15| Add slave rank support -// 1.17 |sglancy |16-FEB-15| Merged FW comments with lab debugging needs -// 1.17 |preeragh|15-Dec-14| Fix FW Review Comments -// 1.16 |rwheeler|10-Nov-14| Update to address_generation for custom address string -// 1.15 |preeragh|03-Nov-14| Fix for 128GB Schmoo -// 1.14 |mjjones |20-Jan-13| RAS Review Updates -// 1.13 |preet |18-Dec-13| Added 64K default for few addr_mode -// 1.12 |preet |17-Dec-13| Added Addr modes -// 1.11 |preeragh|17-May-13| Fixed FW Review Comments -// 1.10 |preeragh|30-Apr-13| Fixed FW Review Comment -// 1.9 |bellows |04-Apr-13| Changed program to be Hostboot compliant -// 1.2 |bellows |03-Apr-13| Added Id and cleaned up a warning msg. -// 1.1 | |xx-Apr-13| Copied from original which is now known as mss_mcbist_address_default/_lab.C -// 1.2 Preetham | xx - Apr -13| Fixed rc_num call -//------------------------------------------------------------------------------ - -#include "mss_mcbist_address.H" -extern "C" -{ -using namespace fapi; - -#define MAX_ADDR_BITS 37 -#define MAX_VALUE_TWO 2 - -#define DELIMITERS "," - -fapi::ReturnCode address_generation(const fapi:: Target & i_target_mba,uint8_t i_port,mcbist_addr_mode i_addr_type,interleave_type i_add_inter_type,uint8_t i_rank,uint64_t &io_start_address, uint64_t &io_end_address, char * l_str_cust_addr) -{ - fapi::ReturnCode rc; - uint8_t l_num_ranks_per_dimm[MAX_VALUE_TWO][MAX_VALUE_TWO]; - uint8_t l_num_master_ranks[MAX_VALUE_TWO][MAX_VALUE_TWO]; - uint8_t l_dram_banks = 0; - uint8_t l_dram_rows = 0; - uint8_t l_dram_cols = 0; - //uint8_t l_dram_density = 0; - //uint8_t l_dram_width = 0; - uint8_t l_addr_inter = 0; - uint8_t l_num_ranks_p0_dim0,l_num_ranks_p0_dim1,l_num_ranks_p1_dim0,l_num_ranks_p1_dim1; - uint8_t l_master_ranks_p0_dim0,l_master_ranks_p0_dim1,l_master_ranks_p1_dim0; - uint8_t mr3_valid, mr2_valid, mr1_valid,sl0_valid,sl1_valid,sl2_valid; - uint32_t rc_num; - char S0[] = "b"; - //Choose a default buffer for the below - //0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 - //MR0(MSB) MR1 MR2 MR3 BA0 BA1 BA2 BA3 C3 C4 C5 C6 C7 C8 C9 C10 C11 R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 SL0(MSB) SL1 SL2 - ecmdDataBufferBase l_default_add_buffer(64); - ecmdDataBufferBase l_new_add_buffer(64); - - rc_num = l_default_add_buffer.flushTo0(); - rc_num |= l_new_add_buffer.flushTo0(); - if (rc_num) - { - FAPI_ERR("Error in function addr_gen:"); - rc.setEcmdError(rc_num); - return rc; - } - - rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target_mba, l_num_ranks_per_dimm); - if (rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM, &i_target_mba,l_num_master_ranks); - if (rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_BANKS, &i_target_mba, l_dram_banks); - if (rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_ROWS, &i_target_mba, l_dram_rows); - if (rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_COLS, &i_target_mba, l_dram_cols); - if (rc) return rc; - //rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_DENSITY, &i_target_mba, l_dram_density); - //if (rc) return rc; - //rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target_mba, l_dram_width); - //if (rc) return rc; - rc = FAPI_ATTR_GET(ATTR_MCBIST_ADDR_INTER, &i_target_mba, l_addr_inter); - if (rc) return rc; - - //------------------------------ Debug Stuff ------------------------------- - //FAPI_INF("ATTR_EFF_NUM_RANKS_PER_DIMM is %d ",l_num_ranks_per_dimm[0][0]); - //FAPI_INF("ATTR_EFF_NUM_RANKS_PER_DIMM is %d ",l_num_ranks_per_dimm[0][1]); - //FAPI_INF("ATTR_EFF_NUM_RANKS_PER_DIMM is %d ",l_num_ranks_per_dimm[1][0]); - //FAPI_INF("ATTR_EFF_NUM_RANKS_PER_DIMM is %d ",l_num_ranks_per_dimm[1][1]); - //------------------------------ Debug Stuff ------------------------------- - //FAPI_INF("ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM l_num_master_p0_dim0 is %d ",l_num_master_ranks[0][0]); - //FAPI_INF("ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM l_num_master_p0_dim1 is %d ",l_num_master_ranks[0][1]); - //FAPI_INF("ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM l_num_master_p1_dim0 is %d ",l_num_master_ranks[1][0]); - //FAPI_INF("ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM l_num_master_p1_dim1 is %d ",l_num_master_ranks[1][1]); - //------------------------------------------------------------------------------- - -l_num_ranks_p0_dim0 = l_num_ranks_per_dimm[0][0]; -l_num_ranks_p0_dim1 = l_num_ranks_per_dimm[0][1]; -l_num_ranks_p1_dim0 = l_num_ranks_per_dimm[1][0]; -l_num_ranks_p1_dim1 = l_num_ranks_per_dimm[1][1]; -l_master_ranks_p0_dim0 = l_num_master_ranks[0][0]; -l_master_ranks_p0_dim1 = l_num_master_ranks[0][1]; -l_master_ranks_p1_dim0 = l_num_master_ranks[1][0]; -//l_master_ranks_p1_dim1 = l_num_master_ranks[1][1]; -//Initial all ranks are invalid -mr3_valid = 0; -mr2_valid = 0; -mr1_valid = 0; -sl2_valid = 0; -sl1_valid = 0; -sl0_valid = 0; - -if( (l_num_ranks_p0_dim0 == 1 && l_num_ranks_p0_dim1 == 0) || (l_num_ranks_p1_dim0 == 1 && l_num_ranks_p1_dim1 == 0) ) //Single Rank case -- default0 - { - //do rank-only stuff for this - FAPI_DBG("%s:--- INSIDE 1R",i_target_mba.toEcmdString()); - l_addr_inter=3; - } - -else if ( (l_num_ranks_p0_dim0 == 1 && l_num_ranks_p0_dim1 == 1) || (l_num_ranks_p1_dim0 == 1 && l_num_ranks_p1_dim1 == 1) ) -{ - FAPI_DBG("%s:--- INSIDE p0d0 valid and p0d1 valid --- 0 4---- 2R",i_target_mba.toEcmdString()); - mr1_valid=1; -} - -else if ( (l_num_ranks_p0_dim0 == 2 && l_num_ranks_p0_dim1 == 0) || (l_num_ranks_p1_dim0 == 2 && l_num_ranks_p1_dim1 == 0) ) -{ - FAPI_DBG("%s:--- INSIDE p0d0 valid and p0d1 valid --- 0 1---- 2R",i_target_mba.toEcmdString()); - mr3_valid=1; -} -else if (((l_num_ranks_p0_dim0 == 2 && l_num_ranks_p0_dim1 == 2)|| (l_num_ranks_p1_dim0 == 2 && l_num_ranks_p1_dim1 == 2)) && (l_master_ranks_p0_dim0 != 1 && l_master_ranks_p0_dim1 != 1)) //Rank 01 and 45 case - { - FAPI_DBG("%s:--- INSIDE --- 2R 0145",i_target_mba.toEcmdString()); - mr3_valid = 1; - mr1_valid=1; - } - -else if((l_num_ranks_p0_dim0 == 4 && l_num_ranks_p0_dim1 == 0 )|| (l_num_ranks_p1_dim0 == 4 && l_num_ranks_p1_dim1 == 0 )) //Rank 0123 on single dimm case - { - mr3_valid = 1;mr2_valid = 1; - } -else if (((l_num_ranks_p0_dim0 == 4 && l_num_ranks_p0_dim1 == 4) || (l_num_ranks_p1_dim0 == 4 && l_num_ranks_p1_dim1 == 4)) && l_master_ranks_p0_dim0 == 1) //1r 4h stack -{ - mr1_valid = 0; //DDC - sl1_valid = 1; - sl2_valid = 1; -} - -else if (((l_num_ranks_p0_dim0 == 8 && l_num_ranks_p0_dim1 == 0) || (l_num_ranks_p1_dim0 == 8 && l_num_ranks_p1_dim1 == 0)) && ((l_master_ranks_p0_dim0 == 2) || (l_master_ranks_p0_dim1 == 0 && l_master_ranks_p1_dim0 == 2))) //2rx4 4h ddr4 3ds -{ - l_addr_inter = 4; - //l_str_cust_addr = "sl2,sl1,ba0,mr3,cl3,cl4,cl5,ba1,cl6,cl7,cl8,ba2,r0,r1,r2,ba3,cl2,cl9,cl11,cl13,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15,r16,sl0,mr2,mr1,mr0"; //DDC - mr3_valid = 1; //DDC - sl1_valid = 1; - sl2_valid = 1; -} -else if ((l_num_ranks_p0_dim0 == 4 && l_num_ranks_p0_dim1 == 4) || (l_num_ranks_p1_dim0 == 4 && l_num_ranks_p1_dim1 == 4)) //Rank 0123 and 4567 case -{ - mr3_valid = 1; - mr2_valid = 1; - mr1_valid = 1; -} - else if (((l_num_ranks_p0_dim0 == 2 && l_num_ranks_p0_dim1 == 2) || - (l_num_ranks_p1_dim0 == 2 && l_num_ranks_p1_dim1 == 2)) && - (l_master_ranks_p0_dim0 == 1 && l_master_ranks_p0_dim1 == 1)) //1rx4 2h ddr4 3ds 2 dimm, CDIMM - { - sl1_valid = 0; - sl2_valid = 1; - mr1_valid = 1; - } - - else - { - FAPI_INF("-- Error ---- mcbist_addr_Check dimm_Config ----- "); - } - - //FAPI_INF("ATTR_EFF_DRAM_GEN is %d ",l_dram_gen); - //FAPI_INF("ATTR_EFF_DRAM_BANKS is %d ",l_dram_banks); - //FAPI_INF("ATTR_EFF_DRAM_ROWS is %d ",l_dram_rows); - //FAPI_INF("ATTR_EFF_DRAM_COLS is %d ",l_dram_cols); - //FAPI_INF("ATTR_EFF_DRAM_DENSITY is %d ",l_dram_density); - //FAPI_INF("ATTR_EFF_DRAM_WIDTH is %d ",l_dram_width); - //FAPI_INF("ATTR_ADDR_INTER Mode is %d ",l_addr_inter); - //FAPI_INF("--- BANK-RANK Address interleave ---"); - //custom addressing string is not to be used - if(l_addr_inter != 4) { - rc = parse_addr(i_target_mba, S0, mr3_valid, mr2_valid, mr1_valid, - l_dram_rows, l_dram_cols, l_addr_inter,sl2_valid,sl1_valid,sl0_valid); - if (rc) return rc; - } - else { - FAPI_DBG("Custom addressing flag was selected"); - rc = parse_addr(i_target_mba, l_str_cust_addr, mr3_valid, mr2_valid, mr1_valid, - l_dram_rows, l_dram_cols, l_addr_inter,sl2_valid,sl1_valid,sl0_valid); - if (rc) return rc; - } - - return rc; -} - -fapi::ReturnCode parse_addr(const fapi::Target & i_target_mba, - char addr_string[], - uint8_t mr3_valid, - uint8_t mr2_valid, - uint8_t mr1_valid, - uint8_t l_dram_rows, - uint8_t l_dram_cols, - uint8_t l_addr_inter, - uint8_t sl2_valid, - uint8_t sl1_valid, - uint8_t sl0_valid) -{ - fapi::ReturnCode rc; - uint8_t i = MAX_ADDR_BITS; - - uint8_t l_value; - uint32_t l_value32 = 0; - uint32_t l_sbit, rc_num; - uint32_t l_start = 0; - uint32_t l_len = 0; - uint64_t l_readscom_value = 0; - uint64_t l_end = 0; - uint64_t l_start_addr = 0; - uint8_t l_value_zero = 0; - uint8_t l_user_end_addr = 0; - ecmdDataBufferBase l_data_buffer_64(64); - ecmdDataBufferBase l_data_buffer_rd64(64); - uint8_t l_attr_addr_mode = 0; - uint8_t l_num_cols = 0; - uint8_t l_num_rows = 0; - uint8_t l_dram_gen = 0; - - rc = FAPI_ATTR_GET(ATTR_EFF_SCHMOO_ADDR_MODE, &i_target_mba, l_attr_addr_mode); - if (rc) return rc; - rc = FAPI_ATTR_GET(ATTR_MCBIST_ADDR_NUM_COLS, &i_target_mba, l_num_cols); - if (rc) return rc; - rc = FAPI_ATTR_GET(ATTR_MCBIST_ADDR_NUM_ROWS, &i_target_mba, l_num_rows); - if (rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_GEN, &i_target_mba, l_dram_gen); - if (rc) return rc; - - if (l_num_cols == 0) - { - l_num_cols = l_dram_cols; - } - - if (l_num_rows == 0) - { - l_num_rows = l_dram_rows; - } - - //Set all the addr reg to 0 - //Define Custom String - //Set all Params based on the string. - rc_num = l_data_buffer_64.flushTo0(); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - - l_sbit = 0; - l_value = i; - rc = fapiGetScom(i_target_mba, 0x030106c9, l_data_buffer_64); - if (rc) return rc; - rc_num = l_data_buffer_64.insertFromRight(l_value, l_sbit, 6); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, 0x030106c9, l_data_buffer_64); - if (rc) return rc; - i--; - - l_sbit = 54; - l_value = i; - rc = fapiGetScom(i_target_mba, 0x030106c8, l_data_buffer_64); - if (rc) return rc; - rc_num = l_data_buffer_64.insertFromRight(l_value, l_sbit, 6); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, 0x030106c8, l_data_buffer_64); - if (rc) return rc; - i--; - - ////FAPI_INF("Inside strcmp mr3"); - l_sbit = 18; - l_value = i; - rc = fapiGetScom(i_target_mba, 0x030106c8, l_data_buffer_64); - if (rc) return rc; - if (mr3_valid == 1) - { - rc_num = l_data_buffer_64.insertFromRight(l_value, l_sbit, 6); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, 0x030106c8, l_data_buffer_64); - if (rc) return rc; - i--; - } - else - { - rc_num = l_data_buffer_64.insertFromRight(l_value_zero, l_sbit, 6); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, 0x030106c8, l_data_buffer_64); - if (rc) return rc; - //FAPI_INF("mr3 Invalid"); - - - } - - ////FAPI_INF("Inside strcmp mr2"); - l_sbit = 12; - l_value = i; - rc = fapiGetScom(i_target_mba, 0x030106c8, l_data_buffer_64); - if (rc) return rc; - if (mr2_valid == 1) - { - rc_num = l_data_buffer_64.insertFromRight(l_value, l_sbit, 6); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - //FAPI_INF("Inside mr2 --- l_addr_inter"); - rc = fapiPutScom(i_target_mba, 0x030106c8, l_data_buffer_64); - if (rc) return rc; - i--; - } - else - { - rc_num = l_data_buffer_64.insertFromRight(l_value_zero, l_sbit, 6); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, 0x030106c8, l_data_buffer_64); - if (rc) return rc; - //FAPI_INF("mr2 Invalid"); - - - } - - ////FAPI_INF("Inside strcmp mr1"); - l_sbit = 6; - l_value = i; - rc = fapiGetScom(i_target_mba, 0x030106c8, l_data_buffer_64); - if (rc) return rc; - if (mr1_valid == 1) - { - rc_num = l_data_buffer_64.insertFromRight(l_value, l_sbit, 6); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - //FAPI_INF("Inside mr1 --- l_addr_inter"); - rc = fapiPutScom(i_target_mba, 0x030106c8, l_data_buffer_64); - if (rc) return rc; - i--; - } - else - { - rc_num = l_data_buffer_64.insertFromRight(l_value_zero, l_sbit, 6); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, 0x030106c8, l_data_buffer_64); - if (rc) return rc; - //FAPI_INF("mr1 Invalid"); - - - } - - - ////FAPI_INF("Inside strcmp ba2"); - l_sbit = 48; - l_value = i; - rc = fapiGetScom(i_target_mba, 0x030106c8, l_data_buffer_64); - if (rc) return rc; - rc_num = l_data_buffer_64.insertFromRight(l_value, l_sbit, 6); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, 0x030106c8, l_data_buffer_64); - if (rc) return rc; - i--; - - ////FAPI_INF("Inside strcmp ba3"); - l_sbit = 42; - l_value = i; - //------- Enable these for DDR4 --- for now constant map to zero - rc = fapiGetScom(i_target_mba, 0x030106c8, l_data_buffer_64); - if (rc) return rc; - //FAPI_INF("ba3 Invalid"); - if (l_dram_gen == 2){ - rc_num = l_data_buffer_64.insertFromRight(l_value, l_sbit, 6); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, 0x030106c8, l_data_buffer_64); - if (rc) return rc; - i--; -} -else -{ - rc_num = l_data_buffer_64.insertFromRight(l_value_zero, l_sbit, 6); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, 0x030106c8, l_data_buffer_64); - if (rc) return rc; - -} - - - ////FAPI_INF("Inside strcmp mr0"); - l_sbit = 0; - l_value = i; - //------- Enable these for DDR4 --- for now constant map to zero - rc = fapiGetScom(i_target_mba, 0x030106c8, l_data_buffer_64); - if (rc) return rc; - rc_num = l_data_buffer_64.insertFromRight(l_value_zero, l_sbit, 6); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, 0x030106c8, l_data_buffer_64); - if (rc) return rc; - - - ////FAPI_INF("Value of i = %d",i); - //FAPI_INF("mr0 Invalid\n"); - - ////FAPI_INF("Inside strcmp cl3"); - l_sbit = 42; - l_value = i; - rc = fapiGetScom(i_target_mba, 0x030106cb, l_data_buffer_64); - if (rc) return rc; - rc_num = l_data_buffer_64.insertFromRight(l_value_zero, l_sbit, 6); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, 0x030106cb, l_data_buffer_64); - if (rc) return rc; - - /////////////////////////////////////////////////////////////////// - - //FAPI_INF("col2 Invalid"); - ////FAPI_INF("Value of i = %d",i); - ////FAPI_INF("Inside strcmp cl3"); - l_sbit = 36; - l_value = i; - rc = fapiGetScom(i_target_mba, 0x030106cb, l_data_buffer_64); - if (rc) return rc; - if (l_num_cols >= 1) - { - rc_num = l_data_buffer_64.insertFromRight(l_value, l_sbit, 6); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, 0x030106cb, l_data_buffer_64); - if (rc) return rc; - i--; - } - else - { - rc_num = l_data_buffer_64.insertFromRight(l_value_zero, l_sbit, 6); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, 0x030106cb, l_data_buffer_64); - if (rc) return rc; - - //FAPI_INF("Col 3 -- Invalid"); - - } - - ////FAPI_INF("Inside strcmp cl4"); - l_sbit = 30; - l_value = i; - rc = fapiGetScom(i_target_mba, 0x030106cb, l_data_buffer_64); - if (rc) return rc; - if (l_num_cols >= 2) - { - rc_num = l_data_buffer_64.insertFromRight(l_value, l_sbit, 6); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, 0x030106cb, l_data_buffer_64); - if (rc) return rc; - i--; - } - ////FAPI_INF("Value of i = %d",i); - else - { - rc_num = l_data_buffer_64.insertFromRight(l_value_zero, l_sbit, 6); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, 0x030106cb, l_data_buffer_64); - if (rc) return rc; - - //FAPI_INF("Col 4 -- Invalid"); - - } - - ////FAPI_INF("Inside strcmp cl5"); - l_sbit = 24; - l_value = i; - rc = fapiGetScom(i_target_mba, 0x030106cb, l_data_buffer_64); - if (rc) return rc; - if (l_num_cols >= 3) - { - rc_num = l_data_buffer_64.insertFromRight(l_value, l_sbit, 6); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, 0x030106cb, l_data_buffer_64); - if (rc) return rc; - i--; - } - else - { - rc_num = l_data_buffer_64.insertFromRight(l_value_zero, l_sbit, 6); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, 0x030106cb, l_data_buffer_64); - if (rc) return rc; - - //FAPI_INF("Col 5 -- Invalid"); - - } - - ////FAPI_INF("Inside strcmp cl6"); - l_sbit = 18; - l_value = i; - rc = fapiGetScom(i_target_mba, 0x030106cb, l_data_buffer_64); - if (rc) return rc; - if (l_num_cols >= 4) - { - rc_num = l_data_buffer_64.insertFromRight(l_value, l_sbit, 6); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, 0x030106cb, l_data_buffer_64); - if (rc) return rc; - i--; - } - ////FAPI_INF("Value of i = %d",i); - else - { - rc_num = l_data_buffer_64.insertFromRight(l_value_zero, l_sbit, 6); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, 0x030106cb, l_data_buffer_64); - if (rc) return rc; - - //FAPI_INF("Col 6 -- Invalid"); - - } - - ////FAPI_INF("Inside strcmp cl7"); - l_sbit = 12; - l_value = i; - rc = fapiGetScom(i_target_mba, 0x030106cb, l_data_buffer_64); - if (rc) return rc; - if (l_num_cols >= 5) - { - rc_num = l_data_buffer_64.insertFromRight(l_value, l_sbit, 6); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, 0x030106cb, l_data_buffer_64); - if (rc) return rc; - i--; - } - ////FAPI_INF("Value of i = %d",i); - else - { - rc_num = l_data_buffer_64.insertFromRight(l_value_zero, l_sbit, 6); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, 0x030106cb, l_data_buffer_64); - if (rc) return rc; - - //FAPI_INF("Col 7 -- Invalid"); - - } - - ////FAPI_INF("Inside strcmp cl8"); - l_sbit = 6; - l_value = i; - rc = fapiGetScom(i_target_mba, 0x030106cb, l_data_buffer_64); - if (rc) return rc; - if (l_num_cols >= 6) - { - rc_num = l_data_buffer_64.insertFromRight(l_value, l_sbit, 6); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, 0x030106cb, l_data_buffer_64); - if (rc) return rc; - i--; - } - ////FAPI_INF("Value of i = %d",i); - else - { - rc_num = l_data_buffer_64.insertFromRight(l_value_zero, l_sbit, 6); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, 0x030106cb, l_data_buffer_64); - if (rc) return rc; - - //FAPI_INF("Col 8 -- Invalid"); - - } - - ////FAPI_INF("Inside strcmp cl9"); - l_sbit = 0; - l_value = i; - rc = fapiGetScom(i_target_mba, 0x030106cb, l_data_buffer_64); - if (rc) return rc; - if (l_num_cols >= 7) - { - rc_num = l_data_buffer_64.insertFromRight(l_value, l_sbit, 6); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, 0x030106cb, l_data_buffer_64); - if (rc) return rc; - i--; - } - - else - { - rc_num = l_data_buffer_64.insertFromRight(l_value_zero, l_sbit, 6); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, 0x030106cb, l_data_buffer_64); - if (rc) return rc; - - //FAPI_INF("Col 9 -- Invalid"); - - } - - ////FAPI_INF("Inside strcmp cl11"); - l_sbit = 54; - l_value = i; - rc = fapiGetScom(i_target_mba, 0x030106ca, l_data_buffer_64); - if (rc) return rc; - if (l_num_cols >= 11) - { - if (l_dram_cols >= 11) - { - rc_num = l_data_buffer_64.insertFromRight(l_value, l_sbit, 6); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, 0x030106ca, l_data_buffer_64); - if (rc) return rc; - //FAPI_DBG("%s: Inside l_dram_cols > 10"); - i--; - } - else - { - rc_num = l_data_buffer_64.insertFromRight(l_value_zero, l_sbit, 6); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, 0x030106ca, l_data_buffer_64); - if (rc) return rc; - - FAPI_DBG("%s:Col 11 -- Invalid", i_target_mba.toEcmdString()); - - } - } - else - { - rc_num = l_data_buffer_64.insertFromRight(l_value_zero, l_sbit, 6); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, 0x030106ca, l_data_buffer_64); - if (rc) return rc; - - //FAPI_INF("Col 11 -- Invalid"); - - } - - ////FAPI_INF("Value of i = %d",i); - ////FAPI_INF("Inside strcmp cl13"); - l_sbit = 48; - l_value = i; - rc = fapiGetScom(i_target_mba, 0x030106ca, l_data_buffer_64); - if (rc) return rc; - if (l_num_cols >= 12) - { - rc_num = l_data_buffer_64.insertFromRight(l_value, l_sbit, 6); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, 0x030106ca, l_data_buffer_64); - if (rc) return rc; - i--; - } - else - { - rc_num = l_data_buffer_64.insertFromRight(l_value_zero, l_sbit, 6); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, 0x030106ca, l_data_buffer_64); - if (rc) return rc; - - //FAPI_INF("Col 13 Invalid"); - - } - ////FAPI_INF("Value of i = %d",i); - ////FAPI_INF("Inside strcmp r0"); - l_sbit = 42; - l_value = i; - rc = fapiGetScom(i_target_mba, 0x030106ca, l_data_buffer_64); - if (rc) return rc; - if (l_num_rows > 0) - { - rc_num = l_data_buffer_64.insertFromRight(l_value, l_sbit, 6); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, 0x030106ca, l_data_buffer_64); - if (rc) return rc; - i--; - } - ////FAPI_INF("Value of i = %d",i); - else - { - rc_num = l_data_buffer_64.insertFromRight(l_value_zero, l_sbit, 6); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, 0x030106ca, l_data_buffer_64); - if (rc) return rc; - - //FAPI_INF("row 0 -- Invalid"); - - } - - ////FAPI_INF("Inside strcmp r1"); - l_sbit = 36; - l_value = i; - rc = fapiGetScom(i_target_mba, 0x030106ca, l_data_buffer_64); - if (rc) return rc; - if (l_num_rows > 1) - { - rc_num = l_data_buffer_64.insertFromRight(l_value, l_sbit, 6); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, 0x030106ca, l_data_buffer_64); - if (rc) return rc; - i--; - } - ////FAPI_INF("Value of i = %d",i); - else - { - rc_num = l_data_buffer_64.insertFromRight(l_value_zero, l_sbit, 6); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, 0x030106ca, l_data_buffer_64); - if (rc) return rc; - - //FAPI_INF("row 1 -- Invalid"); - - } - - ////FAPI_INF("Inside strcmp r2"); - l_sbit = 30; - l_value = i; - rc = fapiGetScom(i_target_mba, 0x030106ca, l_data_buffer_64); - if (rc) return rc; - if (l_num_rows > 2) - { - rc_num = l_data_buffer_64.insertFromRight(l_value, l_sbit, 6); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, 0x030106ca, l_data_buffer_64); - if (rc) return rc; - i--; - } - ////FAPI_INF("Value of i = %d",i); - else - { - rc_num = l_data_buffer_64.insertFromRight(l_value_zero, l_sbit, 6); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, 0x030106ca, l_data_buffer_64); - if (rc) return rc; - - //FAPI_INF("row 2 -- Invalid"); - - } - - ////FAPI_INF("Inside strcmp r3"); - l_sbit = 24; - l_value = i; - rc = fapiGetScom(i_target_mba, 0x030106ca, l_data_buffer_64); - if (rc) return rc; - if (l_num_rows > 3) - { - rc_num = l_data_buffer_64.insertFromRight(l_value, l_sbit, 6); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, 0x030106ca, l_data_buffer_64); - if (rc) return rc; - i--; - } - ////FAPI_INF("Value of i = %d",i); - else - { - rc_num = l_data_buffer_64.insertFromRight(l_value_zero, l_sbit, 6); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, 0x030106ca, l_data_buffer_64); - if (rc) return rc; - - //FAPI_INF("row 3 -- Invalid"); - - } - - ////FAPI_INF("Inside strcmp r4"); - l_sbit = 18; - l_value = i; - rc = fapiGetScom(i_target_mba, 0x030106ca, l_data_buffer_64); - if (rc) return rc; - if (l_num_rows > 4) - { - rc_num = l_data_buffer_64.insertFromRight(l_value, l_sbit, 6); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, 0x030106ca, l_data_buffer_64); - if (rc) return rc; - i--; - } - ////FAPI_INF("Value of i = %d",i); - else - { - rc_num = l_data_buffer_64.insertFromRight(l_value_zero, l_sbit, 6); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, 0x030106ca, l_data_buffer_64); - if (rc) return rc; - - //FAPI_INF("row 4 -- Invalid"); - - } - - ////FAPI_INF("Inside strcmp r5"); - l_sbit = 12; - l_value = i; - rc = fapiGetScom(i_target_mba, 0x030106ca, l_data_buffer_64); - if (rc) return rc; - if (l_num_rows > 5) - { - rc_num = l_data_buffer_64.insertFromRight(l_value, l_sbit, 6); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, 0x030106ca, l_data_buffer_64); - if (rc) return rc; - i--; - } - ////FAPI_INF("Value of i = %d",i); - else - { - rc_num = l_data_buffer_64.insertFromRight(l_value_zero, l_sbit, 6); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, 0x030106ca, l_data_buffer_64); - if (rc) return rc; - - //FAPI_INF("row 5 -- Invalid"); - - } - - ////FAPI_INF("Inside strcmp r6"); - l_sbit = 6; - l_value = i; - rc = fapiGetScom(i_target_mba, 0x030106ca, l_data_buffer_64); - if (rc) return rc; - if (l_num_rows > 6) - { - rc_num = l_data_buffer_64.insertFromRight(l_value, l_sbit, 6); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, 0x030106ca, l_data_buffer_64); - if (rc) return rc; - i--; - } - ////FAPI_INF("Value of i = %d",i); - else - { - rc_num = l_data_buffer_64.insertFromRight(l_value_zero, l_sbit, 6); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, 0x030106ca, l_data_buffer_64); - if (rc) return rc; - - //FAPI_INF("row 6 -- Invalid"); - - } - - ////FAPI_INF("Inside strcmp r7"); - l_sbit = 0; - l_value = i; - rc = fapiGetScom(i_target_mba, 0x030106ca, l_data_buffer_64); - if (rc) return rc; - if (l_num_rows > 7) - { - rc_num = l_data_buffer_64.insertFromRight(l_value, l_sbit, 6); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, 0x030106ca, l_data_buffer_64); - if (rc) return rc; - i--; - } - ////FAPI_INF("Value of i = %d",i); - else - { - rc_num = l_data_buffer_64.insertFromRight(l_value_zero, l_sbit, 6); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, 0x030106ca, l_data_buffer_64); - if (rc) return rc; - - //FAPI_INF("row 7 -- Invalid"); - - } - - ////FAPI_INF("Inside strcmp r8"); - l_sbit = 54; - l_value = i; - rc = fapiGetScom(i_target_mba, 0x030106c9, l_data_buffer_64); - if (rc) return rc; - if (l_num_rows > 8) - { - rc_num = l_data_buffer_64.insertFromRight(l_value, l_sbit, 6); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, 0x030106c9, l_data_buffer_64); - if (rc) return rc; - i--; - } - ////FAPI_INF("Value of i = %d",i); - else - { - rc_num = l_data_buffer_64.insertFromRight(l_value_zero, l_sbit, 6); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, 0x030106c9, l_data_buffer_64); - if (rc) return rc; - - //FAPI_INF("row 8 -- Invalid"); - - } - - ////FAPI_INF("Inside strcmp r9"); - l_sbit = 48; - l_value = i; - rc = fapiGetScom(i_target_mba, 0x030106c9, l_data_buffer_64); - if (rc) return rc; - if (l_num_rows > 9) - { - rc_num = l_data_buffer_64.insertFromRight(l_value, l_sbit, 6); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, 0x030106c9, l_data_buffer_64); - if (rc) return rc; - i--; - } - ////FAPI_INF("Value of i = %d",i); - else - { - rc_num = l_data_buffer_64.insertFromRight(l_value_zero, l_sbit, 6); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, 0x030106c9, l_data_buffer_64); - if (rc) return rc; - - //FAPI_INF("row 9 -- Invalid"); - - } - - ////FAPI_INF("Inside strcmp r10"); - l_sbit = 42; - l_value = i; - rc = fapiGetScom(i_target_mba, 0x030106c9, l_data_buffer_64); - if (rc) return rc; - if (l_num_rows > 10) - { - rc_num = l_data_buffer_64.insertFromRight(l_value, l_sbit, 6); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, 0x030106c9, l_data_buffer_64); - if (rc) return rc; - i--; - } - ////FAPI_INF("Value of i = %d",i); - else - { - rc_num = l_data_buffer_64.insertFromRight(l_value_zero, l_sbit, 6); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, 0x030106c9, l_data_buffer_64); - if (rc) return rc; - - //FAPI_INF("row 10 -- Invalid"); - - } - - ////FAPI_INF("Inside strcmp r11"); - l_sbit = 36; - l_value = i; - rc = fapiGetScom(i_target_mba, 0x030106c9, l_data_buffer_64); - if (rc) return rc; - if (l_num_rows > 11) - { - rc_num = l_data_buffer_64.insertFromRight(l_value, l_sbit, 6); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, 0x030106c9, l_data_buffer_64); - if (rc) return rc; - i--; - } - ////FAPI_INF("Value of i = %d",i); - else - { - rc_num = l_data_buffer_64.insertFromRight(l_value_zero, l_sbit, 6); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, 0x030106c9, l_data_buffer_64); - if (rc) return rc; - - //FAPI_INF("row 11 -- Invalid"); - - } - - ////FAPI_INF("Inside strcmp r12"); - l_sbit = 30; - l_value = i; - rc = fapiGetScom(i_target_mba, 0x030106c9, l_data_buffer_64); - if (rc) return rc; - if (l_num_rows > 12) - { - rc_num = l_data_buffer_64.insertFromRight(l_value, l_sbit, 6); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, 0x030106c9, l_data_buffer_64); - if (rc) return rc; - i--; - } - ////FAPI_INF("Value of i = %d",i); - else - { - rc_num = l_data_buffer_64.insertFromRight(l_value_zero, l_sbit, 6); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, 0x030106c9, l_data_buffer_64); - if (rc) return rc; - - //FAPI_INF("row 12 -- Invalid"); - - } - - ////FAPI_INF("Inside strcmp r13"); - l_sbit = 24; - l_value = i; - rc = fapiGetScom(i_target_mba, 0x030106c9, l_data_buffer_64); - if (rc) return rc; - if (l_num_rows > 13) - { - rc_num = l_data_buffer_64.insertFromRight(l_value, l_sbit, 6); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, 0x030106c9, l_data_buffer_64); - if (rc) return rc; - i--; - } - ////FAPI_INF("Value of i = %d",i); - else - { - rc_num = l_data_buffer_64.insertFromRight(l_value_zero, l_sbit, 6); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, 0x030106c9, l_data_buffer_64); - if (rc) return rc; - - //FAPI_INF("row 13 -- Invalid"); - - } - - ////FAPI_INF("Inside strcmp r14"); - l_sbit = 18; - l_value = i; - rc = fapiGetScom(i_target_mba, 0x030106c9, l_data_buffer_64); - if (rc) return rc; - if (l_num_rows > 14) - { - rc_num = l_data_buffer_64.insertFromRight(l_value, l_sbit, 6); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, 0x030106c9, l_data_buffer_64); - if (rc) return rc; - i--; - } - ////FAPI_INF("Value of i = %d",i); - else - { - rc_num = l_data_buffer_64.insertFromRight(l_value_zero, l_sbit, 6); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, 0x030106c9, l_data_buffer_64); - if (rc) return rc; - - //FAPI_INF("row 14 -- Invalid"); - - } - - ////FAPI_INF("Inside strcmp r15"); - l_sbit = 12; - l_value = i; - rc = fapiGetScom(i_target_mba, 0x030106c9, l_data_buffer_64); - if (rc) return rc; - if (l_num_rows > 15) - { - rc_num = l_data_buffer_64.insertFromRight(l_value, l_sbit, 6); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, 0x030106c9, l_data_buffer_64); - if (rc) return rc; - i--; - } - else - { - rc_num = l_data_buffer_64.insertFromRight(l_value_zero, l_sbit, 6); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, 0x030106c9, l_data_buffer_64); - if (rc) return rc; - - //FAPI_INF("row 15 -- Invalid"); - - } - ////FAPI_INF("Value of i = %d",i); - ////FAPI_INF("Inside strcmp r16 and l_dram_rows = %d",l_dram_rows); - l_sbit = 6; - l_value = i; - rc = fapiGetScom(i_target_mba, 0x030106c9, l_data_buffer_64); - if (rc) return rc; - if (l_dram_rows >= 17) - { - rc_num = l_data_buffer_64.insertFromRight(l_value, l_sbit, 6); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, 0x030106c9, l_data_buffer_64); - if (rc) return rc; - i--; - } - else - { - ////FAPI_INF("r16 not used"); - rc_num = l_data_buffer_64.insertFromRight(l_value_zero, l_sbit, 6); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - //FAPI_INF("Row 16 Invalid"); - rc = fapiPutScom(i_target_mba, 0x030106c9, l_data_buffer_64); - if (rc) return rc; - - - } - ////FAPI_INF("Value of i = %d",i); - - - ////FAPI_INF("Inside strcmp sl2"); - l_sbit = 36; - l_value = i; - rc = fapiGetScom(i_target_mba, 0x030106c8, l_data_buffer_64); - if (rc) return rc; - if(sl2_valid==1) - { - rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value,l_sbit ,6); - if (rc_num) - { - FAPI_ERR( "Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba,0x030106c8,l_data_buffer_64); - i--; - } - else - { - rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value_zero,l_sbit ,6); - if (rc_num) - { - FAPI_ERR( "Error in function parse_addr:");rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba,0x030106c8,l_data_buffer_64); - if(rc) return rc; - FAPI_DBG("%s:sl2 Invalid",i_target_mba.toEcmdString()); - //FAPI_DBG("%s:Value of i = %d",i); - } - - ////FAPI_INF("Inside strcmp sl1"); - l_sbit = 30; - l_value = i; - rc = fapiGetScom(i_target_mba, 0x030106c8, l_data_buffer_64); - if (rc) return rc; - //------- Enable these for later --- for now constant map to zero - if(sl1_valid==1) - { - - rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value,l_sbit ,6); - if (rc_num) - { - FAPI_ERR( "Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba,0x030106c8,l_data_buffer_64); - if(rc) return rc; - i--; - } - else - { - rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value_zero,l_sbit ,6); - if (rc_num) - { - FAPI_ERR( "Error in function parse_addr:");rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba,0x030106c8,l_data_buffer_64); - if(rc) return rc; - FAPI_DBG("%s:sl1 Invalid",i_target_mba.toEcmdString()); - //FAPI_DBG("%s:Value of i = %d",i); - } - FAPI_INF("Inside strcmp sl0"); - l_sbit = 24; - l_value = i; - rc = fapiGetScom(i_target_mba, 0x030106c8, l_data_buffer_64); - if (rc) return rc; - //------- Enable these for later --- for now constant map to zero - if(sl0_valid==1) - { - - rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value,l_sbit ,6); - if (rc_num) - { - FAPI_ERR( "Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba,0x030106c8,l_data_buffer_64); - if(rc) return rc; - i--; - } - else - { - rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value_zero,l_sbit ,6); - if (rc_num) - { - FAPI_ERR( "Error in function parse_addr:");rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba,0x030106c8,l_data_buffer_64); - if(rc) return rc; - FAPI_DBG("%s:sl0 Invalid",i_target_mba.toEcmdString()); - //FAPI_DBG("%s:Value of i = %d",i); - } - - - - //------ Setting Start and end addr counters - - FAPI_INF("Debug - --------------- Setting Start and End Counters -----------\n"); - rc_num = l_data_buffer_rd64.flushTo0(); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, 0x030106d0, l_data_buffer_rd64); - if (rc) return rc; - l_value = i+1; - FAPI_INF("Setting end_addr Value of i = %d",i); - rc_num = l_data_buffer_rd64.flushTo0(); - - //Calculate and set Valid bits for end_addr - for (i = l_value; i <= 37; i++) - { - rc_num |= l_data_buffer_rd64.clearBit(i); - rc_num |= l_data_buffer_rd64.setBit(i); - } - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - - l_readscom_value = l_data_buffer_rd64.getDoubleWord(0); - - rc = FAPI_ATTR_GET(ATTR_EFF_SCHMOO_ADDR_MODE, &i_target_mba, l_attr_addr_mode); - if (rc) return rc; - rc = FAPI_ATTR_GET(ATTR_MCBIST_START_ADDR, &i_target_mba, l_start_addr); - if (rc) return rc; - //FAPI_INF("User Defined ATTR - Start = %016llX",l_start_addr); - rc = FAPI_ATTR_GET(ATTR_MCBIST_END_ADDR, &i_target_mba, l_end); - if (rc) return rc; - rc = FAPI_ATTR_GET(ATTR_MCBIST_RANK, &i_target_mba, l_user_end_addr); - if (rc) return rc; - - if (l_user_end_addr == 1) - { - //Setting start and end Temp - rc_num = l_data_buffer_rd64.setDoubleWord(0, l_start_addr); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, 0x030106d0, l_data_buffer_rd64); - if (rc) return rc; - rc = fapiPutScom(i_target_mba, 0x030106d1, l_data_buffer_rd64); - if (rc) return rc; - - rc_num = l_data_buffer_rd64.setDoubleWord(0, l_end); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, 0x030106d2, l_data_buffer_rd64); - if (rc) return rc; - rc = fapiPutScom(i_target_mba, 0x030106d3, l_data_buffer_rd64); - if (rc) return rc; - } - - else - { - if (l_attr_addr_mode == 0) - { - FAPI_INF("ATTR_EFF_SCHMOO_ADDR_MODE - %d ---- Few Address Mode --------",l_attr_addr_mode); - l_sbit = 32; - rc_num = l_data_buffer_rd64.flushTo0(); - l_start = 24; - l_len = 8; - l_value32 = 28; - rc_num |= l_data_buffer_rd64.insert(l_value32, l_sbit, l_len, l_start); - l_readscom_value = 0x000003FFF8000000ull; - rc_num |= l_data_buffer_rd64.setDoubleWord(0, l_readscom_value); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - - rc = fapiPutScom(i_target_mba, 0x030106d2, l_data_buffer_rd64); - if (rc) return rc; - rc = fapiPutScom(i_target_mba, 0x030106d3, l_data_buffer_rd64); - if (rc) return rc; - l_readscom_value = l_data_buffer_rd64.getDoubleWord(0); - //FAPI_INF("Debug - Final End addr for 0x030106d2 = %016llX",l_readscom_value); - } - else if (l_attr_addr_mode == 1) - { - FAPI_INF("ATTR_EFF_SCHMOO_ADDR_MODE - %d ---- QUARTER ADDRESSING Mode --------",l_attr_addr_mode); - l_readscom_value = l_readscom_value >> 2; - FAPI_INF("Debug - Final End addr for 0x030106d2 = %016llX",l_readscom_value); - rc_num = l_data_buffer_rd64.setDoubleWord(0, l_readscom_value); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, 0x030106d2, l_data_buffer_rd64); - if (rc) return rc; - rc = fapiPutScom(i_target_mba, 0x030106d3, l_data_buffer_rd64); - if (rc) return rc; - } - else if (l_attr_addr_mode == 2) - { - FAPI_INF("ATTR_EFF_SCHMOO_ADDR_MODE - %d ---- HALF ADDRESSING Mode --------",l_attr_addr_mode); - l_readscom_value = l_readscom_value >> 1; - FAPI_INF("Debug - Final End addr for 0x030106d2 = %016llX",l_readscom_value); - rc_num = l_data_buffer_rd64.setDoubleWord(0, l_readscom_value); - if (rc_num) - { - FAPI_ERR("Error in function parse_addr:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, 0x030106d2, l_data_buffer_rd64); - if (rc) return rc; - rc = fapiPutScom(i_target_mba, 0x030106d3, l_data_buffer_rd64); - if (rc) return rc; - } - else - { - FAPI_INF("ATTR_EFF_SCHMOO_ADDR_MODE - %d ---- FULL Address Mode --------",l_attr_addr_mode); - FAPI_INF("Debug - Final End addr for 0x030106d2 = %016llX",l_readscom_value); - rc = fapiPutScom(i_target_mba, 0x030106d2, l_data_buffer_rd64); - if (rc) return rc; - rc = fapiPutScom(i_target_mba, 0x030106d3, l_data_buffer_rd64); - if (rc) return rc; - } - } - - return rc; -} -} diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_address.H b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_address.H deleted file mode 100644 index ecf6f2ed9..000000000 --- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_address.H +++ /dev/null @@ -1,94 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_address.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2013,2015 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: mss_mcbist_address.H,v 1.9 2015/06/03 15:09:03 lwmulkey Exp $ -// *!*************************************************************************** -// *! (C) Copyright International Business Machines Corp. 1997, 1998, 2013 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -// *!*************************************************************************** -// *! FILENAME : mss_mcbist_address.H -// *! TITLE : -// *! DESCRIPTION : MCBIST procedures -// *! CONTEXT : -// *! -// *! OWNER NAME : -// *! BACKUP : -// *!*************************************************************************** -// CHANGE HISTORY: -//------------------------------------------------------------------------------- -// Version:|Author: | Date: | Comment: -// 1.3 |bellows |03-Apr-13| Added Id for firmware -// 1.4 |preeragh|17-Dec-14| Removed unwanted header includes -// 1.5 |mjjones |20-Jan-14| RAS Review Updates -// 1.7 |preeragh|15-Dec-14| Fix FW review comments -// 1.8 |preeragh|16-FEB-14| Added in lab needs -// --------|--------|---------|-------------------------------------------------- -//------------------------------------------------------------------------------ -#ifndef MSS_MCBIST_ADDRESS_H -#define MSS_MCBIST_ADDRESS_H - -/*****************************************************************************/ -/* mss_mcbist_address.H */ -/*****************************************************************************/ -#include <fapi.H> -#include <cen_scom_addresses.H> -#include <mss_access_delay_reg.H> -#include <mss_mcbist.H> -#include <string.h> -extern "C" -{ -using namespace fapi; - -enum interleave_type -{ - BANK_RANK, - RANK_BANK, - BANK_ONLY, - RANK_ONLY, - RANKS_DIMM0, - RANKS_DIMM1, - USER_PATTERN -}; - -fapi::ReturnCode address_generation(const fapi:: Target & i_target_mba, - uint8_t i_port, - mcbist_addr_mode i_addr_type, - interleave_type i_add_inter_type, - uint8_t i_rank, - uint64_t &io_start_address, - uint64_t &io_end_address, - char * l_str_cust_addr); - -fapi::ReturnCode parse_addr(const fapi:: Target & i_target_mba, - char addr_string[], - uint8_t mr3_valid, - uint8_t mr2_valid, - uint8_t mr1_valid, - uint8_t l_dram_rows, - uint8_t l_dram_cols, - uint8_t l_addr_inter,uint8_t sl2_valid,uint8_t sl1_valid,uint8_t sl0_valid); - -} -#endif diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_common.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_common.C deleted file mode 100644 index a8929723b..000000000 --- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_common.C +++ /dev/null @@ -1,3040 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_common.C $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2012,2015 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: mss_mcbist_common.C,v 1.76 2015/08/07 11:08:45 sasethur Exp $ -// *!*************************************************************************** -// *! (C) Copyright International Business Machines Corp. 1997, 1998 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -// *!*************************************************************************** -// *! FILENAME : mss_mcbist_common.C -// *! TITLE : -// *! DESCRIPTION : MCBIST Procedures -// *! CONTEXT : -// *! -// *! OWNER NAME : Preetham Hosmane Email: preeragh@in.ibm.com -// *! BACKUP : Sethuraman, Saravanan Email: saravanans@in.ibm.com -// *!*************************************************************************** -// CHANGE HISTORY: -//------------------------------------------------------------------------------ -// Version:|Author: | Date: | Comment: -// --------|--------|--------|-------------------------------------------------- -// 1.76 |preeragh|07/15/15|R_W Infinite Added -// 1.75 |lapietra|06/26/15|added RMWFIX and RMWFIX_I tests -// 1.74 |preeragh|06/15/15|o_error_map Correction -// 1.73 |sglancy |02/16/15|Merged in lab needs -// 1.72 |sglancy |02/09/15|Fixed FW comments and addressed bugs -// 1.71 |preeragh|01/16/15|Fixed FW comments -// 1.70 |preeragh|12/16/14|Revert to FW build v.1.66 -// 1.68 |rwheeler|11/19/14|option to pass in rotate data seed -// 1.67 |sglancy |11/03/14|Fixed MCBIST to allow for a custom user generated address - removed forcing of l_new_addr=1 -// 1.66 |preeragh|11/03/14|Fix Addressing Map and enable Refresh -// 1.65 | | - | - -// 1.64 |rwheeler|10/24/14|Added thermal sensor data -// 1.63 |adityamd|02/07/14|RAS Review Updates -// 1.62 |mjjones |01/17/14|RAS Review Updates -// 1.61 |aditya |01/15/14|Updated attr ATTR_EFF_CUSTOM_DIMM -// 1.60 |aditya |12/20/13|Updated max timeout for Mcbist Polling -// 1.59 |aditya |12/17/13|Updated mcb_error_map function parameters -// 1.58 |aditya |12/10/13|Updated Target for MBS registers -// 1.57 |rwheeler|10/29/13 |added W_ONLY_INFINITE_RAND test -// 1.56 |aditya |10/29/13|Updated mcb_error_map function parameters -// 1.55 |aditya |10/24/13|Removed DD2.0 attribute check for ECC setup -// 1.54 |aditya |10/17/13|Minor fix in byte mask function -// 1.53 |aditya |10/05/13|Updated fw comments -// 1.52 |aditya |09/27/13|Updated for Host Boot Compile -// 1.51 |aditya |09/18/13|Updated parameters for random seed attribute and Error map masking -// 1.50 |aditya |08/08/13|Updated for Host Boot Compile -// 1.49 |aditya |08/02/13|Updated Error Map function -// 1.48 |aditya |07/09/13|Added l_random_addr_enable and l_fixed_addr_enable for struct Subtest_info -// 1.47 |aditya |06/11/13|Replaced FAPI_INF to FAPI_DBG,Added target details for Prints -// 1.46 |aditya |06/11/13|Enabled pattern and testtype prints -// 1.45 |aditya |06/11/13|Added attributes ATTR_MCBIST_PRINTING_DISABLE -// 1.44 |aditya |05/23/13|Added TEST_RR and TEST_RF testtypes -// 1.43 |aditya |05/22/13|updated parameters for Subtest Printing -// 1.41 |aditya |05/14/13|updated parameters for random seed details -// 1.40 |aditya |05/07/13|Small Fix -// 1.39 |aditya |05/07/13|Moved some parameters to attributes. -// 1.38 |aditya |04/30/13|Minor fix for firmware -// 1.37 |aditya |04/22/13|Minor Fix -// 1.36 |aditya |04/09/13|Updated cfg_byte_mask and setup_mcbist functions -// 1.35 |aditya |03/18/13|Updated cfg_byte_mask and error map functions -// 1.34 |aditya |03/15/13|Added ISDIMM error map -// 1.33 |aditya |03/06/13|Updated Error map and addressing -// 1.32 |aditya |02/27/13|removed Port looping -// 1.29 |aditya |02/19/13|Updated Testtypes and removed rank looping -// 1.26 |aditya |02/13/13|Modified Addressing -// 1.24 |aditya |02/12/13|Modified Addressing -// 1.23 |aditya |02/07/13|Added MBS23 registers -// 1.22 |abhijit |02/06/13|Updated cfg_byte_mask function -// 1.21 |abhijit |01/30/13|Updated cfg_byte_mask function -// 1.20 |aditya |01/30/13|Updated fw comments -// 1.18 |aditya |01/30/13|Updated fw comments -// 1.17 |aditya |01/16/13|Updated setup_mcbist function -// 1.16 |aditya |01/11/13|Updated function headers -// 1.15 |aditya |01/11/13|added parameters to setup_mcbist function -// 1.14 |aditya |01/07/13|Updated Review Comments -// 1.13 |aditya |01/03/13| Updated FW Comments -// 1.10 |sasethur|12/14/12| Updated for warnings -// 1.9 |aditya |12/14/12| Updated FW review comments -// 1.8 |aditya |12/6/12 | Updated Review Comments -// 1.7 |aditya |11/15/12| Updated for FW REVIEW COMMENTS -// 1.6 |aditya |10/31/12| Fixed issue in mcb_error_map function -// 1.5 |abhijit |10/29/12| fixed issue in byte mask function -// 1.4 |aditya |10/29/12| Updated from ReturnCode to fapi::ReturnCode and Target to const fapi::Target & -// 1.3 |aditya |10/18/12| Replaced insertFromBin by InsertFromRight -// 1.2 |aditya |10/17/12| updated code to be compatible with ecmd 13 release -// 1.1 |aditya |10/01/12| updated fw review comments, datapattern, testtype, addressing -// -// -//This File mss_mcbist_common.C contains the definition of common procedures for the files mss_mcbist.C and mss_mcbist_lab.C -//------------------------------------------------------------------------------ -#include "mss_mcbist.H" -#include "mss_mcbist_address.H" -#include <mss_access_delay_reg.H> -#include <fapiTestHwpDq.H> -#include <dimmBadDqBitmapFuncs.H> -#ifdef FAPI_MSSLABONLY -#include <mss_cen_dimm_temp_sensor.H> -#endif -extern "C" -{ -using namespace fapi; - -#define MCB_DEBUG -#define MCB_DEBUG1 -#define MCB_DEBUG2 - -const uint8_t MAX_PORT = 2; -const uint8_t MAX_DRAM = 20; -const uint8_t MAX_ISDIMM_DQ = 72; -const uint8_t MAX_BYTE = 10; -const uint8_t MAX_RANK = 8; -const uint8_t MAX_NIBBLES = 2; -const uint8_t MCB_TEST_NUM = 16; -const uint64_t MCB_MAX_TIMEOUT = 0000000000060000ull; -const uint64_t DELAY_100US = 100000; // general purpose 100 usec delay for HW mode (2000000 sim cycles if simclk = 20ghz) -const uint64_t DELAY_2000SIMCYCLES = 2000; // general purpose 2000 sim cycle delay for sim mode (100 ns if simclk = 20Ghz) - -const uint64_t END_ADDRESS = 0x0000000010000000ull; //Will be fixed later, once the address generation function is ready -const uint64_t START_ADDRESS = 0x0000000004000000ull; -const uint64_t FEW_INTERVAL = 0x000000000C000000ull; -const uint64_t FOUR = 0x0000000000000004ull; - -//*****************************************************************/ -// Funtion name : setup_mcbist -// Description : Will setup the required MCBIST configuration register -// Input Parameters : -// const fapi::Target & Centaur.mba -// uint8_t i_port Port on which we are operating. - -// mcbist_data_gen i_mcbpatt Data pattern -// mcbist_test_mem i_mcbtest subtest Type -// mcbist_byte_mask i_mcbbytemask It is used to mask bad bits read from SPD -// uint8_t i_mcbrotate Provides the number of bit to shift per burst -// uint64_t i_mcbrotdata Provides the rotate data to shift per burst - -// uint8_t i_pattern Data Pattern -// uint8_t i_test_type Subtest Type -// uint8_t i_rank Current Rank -// ,uint8_t i_bit32 Flag to set bit 32 of register 02011674 -//uint64_t i_start Flag to set start address -// uint64_t i_end Flag to set End address -//uint8_t new_address_map Flag to Enable Custom Address Map -//****************************************************************/ - -fapi::ReturnCode setup_mcbist(const fapi::Target & i_target_mba, - mcbist_byte_mask i_mcbbytemask, - uint8_t i_mcbrotate, - uint64_t i_mcbrotdata, - struct Subtest_info l_sub_info[30], - char * l_str_cust_addr) -{ - fapi::ReturnCode rc; - uint32_t rc_num = 0; - uint8_t l_bit32 = 0; - - FAPI_DBG("%s:Function Setup_MCBIST", i_target_mba.toEcmdString()); - FAPI_DBG("Custom Addr Mode %s",l_str_cust_addr); - ecmdDataBufferBase l_data_buffer_64(64); - ecmdDataBufferBase l_data_bufferx1_64(64); - ecmdDataBufferBase l_data_bufferx2_64(64); - ecmdDataBufferBase l_data_bufferx3_64(64); - ecmdDataBufferBase l_data_bufferx4_64(64); - uint64_t io_start_address = 0; - uint64_t io_end_address = 0; - uint8_t l_new_addr = 1; - uint32_t i_mcbpatt, i_mcbtest; - - mcbist_test_mem i_mcbtest1; - mcbist_data_gen i_mcbpatt1; - i_mcbtest1 = CENSHMOO; - i_mcbpatt1 = ABLE_FIVE; - - uint8_t l_index = 0; - uint8_t l_flag = 0; - uint64_t scom_array[8] = { - MBA01_MBABS0_0x03010440, MBA01_MBABS1_0x03010441, - MBA01_MBABS2_0x03010442, MBA01_MBABS3_0x03010443, - MBA01_MBABS4_0x03010444, MBA01_MBABS5_0x03010445, - MBA01_MBABS6_0x03010446, MBA01_MBABS7_0x03010447 }; - - uint64_t l_scom_array_MBS[16] = { - MBS_ECC0_MBSBS2_0x02011460, MBS_ECC0_MBSBS3_0x02011461, - MBS_ECC0_MBSBS4_0x02011462, MBS_ECC0_MBSBS5_0x02011463, - MBS_ECC0_MBSBS6_0x02011464, MBS_ECC0_MBSBS7_0x02011465, - MBS_ECC1_MBSBS0_0x0201149E, MBS_ECC1_MBSBS1_0x0201149F, - MBS_ECC1_MBSBS2_0x020114A0, MBS_ECC1_MBSBS3_0x020114A1, - MBS_ECC1_MBSBS4_0x020114A2, MBS_ECC1_MBSBS5_0x020114A3, - MBS_ECC1_MBSBS6_0x020114A4, MBS_ECC1_MBSBS7_0x020114A5, - MBS_ECC0_MBSBS0_0x0201145E, MBS_ECC0_MBSBS1_0x0201145F }; - - Target i_target_centaur; - rc = fapiGetParentChip(i_target_mba, i_target_centaur); - if (rc) return rc; - - rc = FAPI_ATTR_GET(ATTR_MCBIST_PATTERN, &i_target_mba, i_mcbpatt); - if (rc) return rc;//-----------i_mcbpatt------->run - rc = FAPI_ATTR_GET(ATTR_MCBIST_TEST_TYPE, &i_target_mba, i_mcbtest); - if (rc) return rc;//---------i_mcbtest------->run - - rc = mss_conversion_testtype(i_target_mba, i_mcbtest, i_mcbtest1); - if (rc) return rc; - rc = mss_conversion_data(i_target_mba, i_mcbpatt, i_mcbpatt1); - if (rc) return rc; - - rc = mcb_reset_trap(i_target_mba); - if (rc) return rc; - //shd set attr for this 1st 8 or last 8 - rc = FAPI_ATTR_GET(ATTR_MCBIST_ERROR_CAPTURE, &i_target_mba, l_bit32); - if (rc) return rc; - if (l_bit32 == 1) - { - FAPI_DBG("%s: error capture set to last 8 Bits", i_target_mba.toEcmdString()); - rc = fapiGetScom(i_target_centaur, MBS_MCBIST01_MCBCMABQ_0x02011674, l_data_buffer_64); - if (rc) return rc; - rc_num = l_data_buffer_64.setBit(32); - if (rc_num) - { - FAPI_ERR("Error in function setup_mcbist:"); - rc.setEcmdError(rc_num); - return rc; - } - - rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MCBCMABQ_0x02011674, l_data_buffer_64); - if (rc) return rc; - - rc = fapiGetScom(i_target_centaur, 0x02011774, l_data_buffer_64); - if (rc) return rc; - rc_num = l_data_buffer_64.setBit(32); - if (rc_num) - { - FAPI_ERR("Buffer error in function setup_mcbist"); - rc.setEcmdError(rc_num); - return rc; - } - - rc = fapiPutScom(i_target_centaur, 0x02011774, l_data_buffer_64); - if (rc) return rc; - } - - rc = fapiGetScom(i_target_mba, 0x0301040d, l_data_buffer_64); - if (rc) return rc; - rc_num = l_data_buffer_64.clearBit(5); - if (rc_num) - { - FAPI_ERR("Buffer error in function setup_mcbist"); - rc.setEcmdError(rc_num); - return rc; - } - - rc = fapiPutScom(i_target_mba, 0x0301040d, l_data_buffer_64); - if (rc) return rc; - - //#RRQ FIFO Mode OFF - rc = fapiGetScom(i_target_mba, 0x0301040e, l_data_buffer_64); - if (rc) return rc; - rc_num = l_data_buffer_64.setBit(6); - rc_num |= l_data_buffer_64.setBit(7); - rc_num |= l_data_buffer_64.setBit(8); - rc_num |= l_data_buffer_64.setBit(9); - rc_num |= l_data_buffer_64.setBit(10); - if (rc_num) - { - FAPI_ERR("Buffer error in function setup_mcbist"); - rc.setEcmdError(rc_num); - return rc; - } - - rc = fapiPutScom(i_target_mba, 0x0301040e, l_data_buffer_64); - if (rc) return rc; - - //power bus ECC setting for random data - //# MBA01_MBA_WRD_MODE - disbale powerbus ECC checking and correction - rc = fapiGetScom(i_target_mba, 0x03010449, l_data_buffer_64); - if (rc) return rc; - rc_num = l_data_buffer_64.setBit(0); - rc_num |= l_data_buffer_64.setBit(1); - rc_num |= l_data_buffer_64.setBit(5); - if (rc_num) - { - FAPI_ERR("Buffer error in function setup_mcbist"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, 0x03010449, l_data_buffer_64); - if (rc) return rc; - //# MBS_ECC01_MBSECCQ - set EEC checking On but ECC correction OFF - rc = fapiGetScom(i_target_centaur, 0x0201144a, l_data_buffer_64); - if (rc) return rc; - rc_num = l_data_buffer_64.clearBit(0); - rc_num |= l_data_buffer_64.setBit(1); - if (rc_num) - { - FAPI_ERR("Buffer error in function setup_mcbist"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_centaur, 0x0201144a, l_data_buffer_64); - if (rc) return rc; - - rc = fapiGetScom(i_target_centaur, 0x0201148a, l_data_buffer_64); - if (rc) return rc; - rc_num = l_data_buffer_64.clearBit(0); - rc_num |= l_data_buffer_64.setBit(1); - if (rc_num) - { - FAPI_ERR("Buffer error in function setup_mcbist"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_centaur, 0x0201148a, l_data_buffer_64); - if (rc) return rc; - - rc = fapiGetScom(i_target_mba, MBA01_CCS_MODEQ_0x030106a7, l_data_buffer_64); - if (rc) return rc; - rc_num = l_data_buffer_64.clearBit(29); - if (rc_num) - { - FAPI_ERR("Buffer error in function setup_mcbist"); - rc.setEcmdError(rc_num); - return rc; - } - - rc = fapiPutScom(i_target_mba, MBA01_CCS_MODEQ_0x030106a7, l_data_buffer_64); - if (rc) return rc; - - for (l_index = 0; l_index < 8; l_index++) - { - rc = fapiGetScom(i_target_mba, scom_array[l_index], l_data_buffer_64); - if (rc) return rc; - l_flag = (l_data_buffer_64.getDoubleWord(0)) ? 1 : 0; - if (l_flag == 1) - { - break; - } - } - - for (l_index = 0; l_index < 16; l_index++) - { - rc = fapiGetScom(i_target_centaur, l_scom_array_MBS[l_index], l_data_buffer_64); - if (rc) return rc; - l_flag = (l_data_buffer_64.getDoubleWord(0)) ? 1 : 0; - if (l_flag == 1) - { - break; - } - } - - if (l_flag == 1) - { - FAPI_DBG("%s:WARNING: Bit Steering is enabled !!!", i_target_mba.toEcmdString()); - } - else - { - FAPI_DBG("%s:steer mode is not enabled", i_target_mba.toEcmdString()); - } - - rc = cfg_mcb_test_mem(i_target_mba, i_mcbtest1, l_sub_info); - if (rc) return rc; - rc = cfg_mcb_dgen(i_target_mba, i_mcbpatt1, i_mcbrotate, i_mcbrotdata); - if (rc) return rc; - uint8_t i_port = 0; - uint8_t i_rank = 0; - - FAPI_DBG("%s:DEBUG-----Print----Address Gen ",i_target_mba.toEcmdString()); - rc = FAPI_ATTR_GET(ATTR_MCBIST_ADDR_MODES, &i_target_mba, l_new_addr); - if (rc) return rc; - FAPI_DBG("DEBUG----- l_new_addr = %d ",l_new_addr); - - if (l_new_addr != 0) - { - rc = address_generation(i_target_mba, i_port, SF, BANK_RANK, i_rank, - io_start_address, io_end_address, l_str_cust_addr); - if (rc) - { - FAPI_DBG("%s:BAD - RC ADDR Generation\n", i_target_mba.toEcmdString()); - return rc; - } - } - - FAPI_INF( "+++ Enabling Refresh +++"); - - rc = fapiGetScom(i_target_mba, 0x03010432, l_data_buffer_64); - if(rc) return rc; - //Bit 0 is enable - rc_num = rc_num | l_data_buffer_64.setBit(0); - if(rc_num) - { - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, 0x03010432, l_data_buffer_64); - if(rc)return rc; - - if (i_mcbbytemask != NONE) - { - rc = cfg_byte_mask(i_target_mba); - if (rc) return rc; - } - - return rc; -} - -//*****************************************************************/ -// Funtion name : mcb_reset_trap -// Description: Clears all the trap registers in MCBIST engine -//Input Parameters : -// const fapi::Target & centaur.mba -//*****************************************************************/ - -fapi::ReturnCode mcb_reset_trap(const fapi::Target & i_target_mba) -{ - ecmdDataBufferBase l_data_buffer_64(64); - fapi::ReturnCode rc; - uint32_t rc_num = 0; - uint8_t l_mbaPosition = 0; - rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target_mba, l_mbaPosition); - - Target i_target_centaur; - rc = fapiGetParentChip(i_target_mba, i_target_centaur); - if (rc) return rc; - FAPI_DBG("%s:Function - mcb_reset_trap", i_target_mba.toEcmdString()); - //FAPI_DBG("%s:Using MCB Reset Trap Function -- This automatically resets error log RA, error counters, Status Reg and error map",i_target_mba.toEcmdString()); - //Reset the MCBIST runtime counter - FAPI_DBG("%s:Clearing the MCBIST Runtime Counter ", i_target_mba.toEcmdString()); - rc_num = l_data_buffer_64.flushTo0(); - if (rc_num) - { - FAPI_ERR("Error in function mcb_reset_trap:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiGetScom(i_target_mba, MBA01_MCBIST_RUNTIMECTRQ_0x030106b0, l_data_buffer_64); - if (rc) return rc; - rc_num = l_data_buffer_64.clearBit(0, 37); - if (rc_num) - { - FAPI_ERR("Error in function mcb_reset_trap:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, MBA01_MCBIST_RUNTIMECTRQ_0x030106b0, l_data_buffer_64); - if (rc) return rc; - - //FAPI_DBG("%s:To clear Port error map registers ",i_target_mba.toEcmdString()); - rc_num = l_data_buffer_64.flushTo0(); - if (rc_num) - { - FAPI_ERR("Error in function mcb_reset_trap:"); - rc.setEcmdError(rc_num); - return rc; - } - - rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MCBCMA1Q_0x02011672, l_data_buffer_64); - if (rc) return (rc); - rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MCBCMB1Q_0x02011673, l_data_buffer_64); - if (rc) return (rc); - rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MCBCMABQ_0x02011674, l_data_buffer_64); - if (rc) return (rc); - rc = fapiPutScom(i_target_centaur, 0x02011772, l_data_buffer_64); - if (rc) return (rc); - rc = fapiPutScom(i_target_centaur, 0x02011773, l_data_buffer_64); - if (rc) return (rc); - rc = fapiPutScom(i_target_centaur, 0x02011774, l_data_buffer_64); - if (rc) return (rc); - - return rc; -} - -//*****************************************************************/ -// Funtion name : start_mcb -// Description: Checks for dimms drop in the particular port & starts MCBIST -//Input Parameters : -// const fapi::Target & Centaur.mba -//*****************************************************************/ - -fapi::ReturnCode start_mcb(const fapi::Target & i_target_mba) -{ - ecmdDataBufferBase l_data_buffer_64(64); - ecmdDataBufferBase l_data_buffer_trap_64(64); - uint8_t l_num_ranks_per_dimm[2][2]; - fapi::ReturnCode rc; - uint32_t rc_num = 0; - FAPI_DBG("%s:Function - start_mcb", i_target_mba.toEcmdString()); - - rc = fapiGetScom(i_target_mba, MBA01_MCBIST_MCBAGRAQ_0x030106d6, l_data_buffer_64); - if (rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target_mba, l_num_ranks_per_dimm); - if (rc) return rc; - - if (l_num_ranks_per_dimm[0][0] > 0) - { - FAPI_DBG("%s: Socket 0 Configured", i_target_mba.toEcmdString()); - rc_num = l_data_buffer_64.setBit(24); - rc_num |= l_data_buffer_64.clearBit(25); - if (rc_num) - { - FAPI_ERR("Buffer error in function start_mcb"); - rc.setEcmdError(rc_num); - return rc; - } - } - else if (l_num_ranks_per_dimm[0][1] > 0) - { - FAPI_DBG("%s: Socket 1 Configured", i_target_mba.toEcmdString()); - rc_num = l_data_buffer_64.clearBit(24); - rc_num |= l_data_buffer_64.setBit(25); - if (rc_num) - { - FAPI_ERR("Buffer error in function start_mcb"); - rc.setEcmdError(rc_num); - return rc; - } - } - else if ((l_num_ranks_per_dimm[0][0] > 0) && (l_num_ranks_per_dimm[0][1] > 0)) - { - FAPI_DBG("%s: Socket 0, 1 Configured", i_target_mba.toEcmdString()); - rc_num = l_data_buffer_64.setBit(24); - rc_num |= l_data_buffer_64.setBit(25); - if (rc_num) - { - FAPI_ERR("Buffer error in function start_mcb"); - rc.setEcmdError(rc_num); - return rc; - } - } - else - { - FAPI_DBG("%s:No Socket found", i_target_mba.toEcmdString()); - } - - //rc = fapiDelay(DELAY_100US, DELAY_2000SIMCYCLES);if(rc) return rc; // wait 2000 simcycles (in sim mode) OR 100 uS (in hw mode) - - rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBAGRAQ_0x030106d6, l_data_buffer_64); - if (rc) return rc; - FAPI_DBG("%s:STARTING MCBIST for Centaur Target", i_target_mba.toEcmdString()); - rc = fapiGetScom(i_target_mba, MBA01_MCBIST_MCB_CNTLSTATQ_0x030106dc, l_data_buffer_64); - if (rc) return rc; - - if (l_data_buffer_64.isBitSet(0)) - { - FAPI_DBG("%s:MCBIST already in progess, wait till MCBIST completes", - i_target_mba.toEcmdString()); - return rc; - } - - rc_num = l_data_buffer_64.flushTo0(); - rc_num |= l_data_buffer_64.setBit(0); - if (rc_num) - { - FAPI_ERR("Buffer error in function start_mcb"); - rc.setEcmdError(rc_num); - return rc; - } - - rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCB_CNTLQ_0x030106db, l_data_buffer_64); - if (rc) return rc; - - //rc = fapiDelay(DELAY_100US, DELAY_2000SIMCYCLES);if(rc) return rc; // wait 2000 simcycles (in sim mode) OR 100 uS (in hw mode) - - return rc; -} - -//*****************************************************************/ -// Funtion name : poll_mcb -// Description : Will check the MCBIST Configuration Register for mcb fail, in progress -// fail. It will print the corresponding centaur on which MCBIST has -// been completed, in progress or failed. -// Input Parameters : -// const fapi::Target & Centaur.mba -// bool l_mcb_stop_on_fail Whether MCBIST should stop on fail or not -// uint64_t i_time Sets the max Time out value -// Output Parameter : -// uint32 status = 1 MCBIST done with fail or MCBIST not complete (default value) -// = 0 MCBIST Done without fail -//****************************************************************/ -fapi::ReturnCode poll_mcb(const fapi::Target & i_target_mba, - uint8_t *o_mcb_status, - struct Subtest_info l_sub_info[30], - uint8_t i_flag) -{ - fapi::ReturnCode rc; // return value after each SCOM access/buffer modification - uint32_t rc_num = 0; - ecmdDataBufferBase l_data_buffer_64(64); - ecmdDataBufferBase l_data_buffer1_64(64); - ecmdDataBufferBase l_data_buffer_trap_64(64); - ecmdDataBufferBase l_stop_on_fail_buffer_64(64); - //Current status of the MCB (done, fail, in progress) - uint8_t l_mcb_done = 0; - uint8_t l_mcb_fail = 0; - uint8_t l_mcb_ip = 0; - //Time out variables - uint64_t l_mcb_timeout = 0; - uint32_t l_count = 0; - uint64_t l_time = 0; - uint32_t l_time_count = 0; - uint8_t l_index = 0; - uint8_t l_Subtest_no = 0; - uint64_t l_counter = 0x0ll; - uint32_t i_mcbtest = 0; - uint32_t l_st_ln = 0; - uint32_t l_len = 0; - uint32_t l_dts_0 = 0; - uint32_t l_dts_1 = 0; - uint8_t l_mcb_stop_on_fail = 0; - mcbist_test_mem i_mcbtest1; - Target i_target_centaur; - rc = fapiGetParentChip(i_target_mba, i_target_centaur); - if (rc) return rc; - // Clear to register to zero; - - //Should get the attributes l_time - uint8_t test_array_count[44] = { 0, 2, 2, 1, 1, 1, 6, 6, 30, 30, - 2, 7, 4, 2, 1, 5, 4, 2, 1, 1, - 3, 1, 1, 4, 2, 1, 1, 1, 1, 10, - 0, 5, 3, 3, 3, 3, 9, 4, 30, 1, - 2, 2, 3, 3 }; - - FAPI_DBG("%s:Function Poll_MCBIST", i_target_mba.toEcmdString()); - rc = FAPI_ATTR_GET(ATTR_MCBIST_MAX_TIMEOUT, &i_target_mba, l_time); - if (rc) return rc; - rc = FAPI_ATTR_GET(ATTR_MCBIST_STOP_ON_ERROR, &i_target_mba, l_mcb_stop_on_fail); - if (rc) return rc; - - if (l_time == 0x0000000000000000) - { - l_time = MCB_MAX_TIMEOUT; - } - FAPI_DBG("%s:Value of max time %016llX", i_target_mba.toEcmdString(), l_time); - - while ((l_mcb_done == 0) && (l_mcb_timeout <= l_time)) - { - rc = fapiDelay(DELAY_100US, DELAY_2000SIMCYCLES); - if (rc) return rc; // wait 2000 simcycles (in sim mode) OR 100 uS (in hw mode) - rc = fapiGetScom(i_target_mba, MBA01_MCBIST_MCB_CNTLSTATQ_0x030106dc, l_data_buffer_64); - if (rc) return rc; - if (l_data_buffer_64.isBitSet(0)) - { - l_time_count++; - if (l_time_count == 500) - { - l_time_count = 0; - FAPI_DBG("%s:POLLING STATUS:POLLING IN PROGRESS...........", - i_target_mba.toEcmdString()); - #ifdef FAPI_MSSLABONLY - rc = mss_cen_dimm_temp_sensor(i_target_centaur);if (rc) return rc; - #endif - rc = fapiGetScom(i_target_centaur, 0x02050000, l_data_buffer_64);if (rc) return rc; - rc_num = l_data_buffer_64.extractToRight(&l_dts_0, 0, 12); - rc_num = rc_num | l_data_buffer_64.extractToRight(&l_dts_1, 16, 12); - if (rc_num) - { - FAPI_ERR("Buffer error in function poll_mcb"); - rc.setEcmdError(rc_num); - return rc; - } - - FAPI_DBG("%s:DTS Thermal Sensor 0 Results %d", i_target_centaur.toEcmdString(), l_dts_0); - FAPI_DBG("%s:DTS Thermal Sensor 1 Results %d", i_target_centaur.toEcmdString(), l_dts_1); - - if (i_flag == 0) - { - // Read Counter Reg - - rc = fapiGetScom(i_target_mba, 0x030106b0, l_data_buffer_64); - if (rc) return rc; - l_counter = l_data_buffer_64.getDoubleWord (0); - - FAPI_DBG("%s:MCBCounter %016llX ", i_target_mba.toEcmdString(), l_counter); - - //Read Sub-Test number - rc = fapiGetScom(i_target_centaur, 0x02011670, l_data_buffer_64); - if (rc) return rc; - l_st_ln = 3; - l_len = 5; - rc_num = l_data_buffer_64.extract(&l_Subtest_no, l_st_ln, l_len); - if (rc_num) - { - FAPI_ERR("Buffer error in function poll_mcb"); - rc.setEcmdError(rc_num); - return rc; - } - - //FAPI_DBG("%s:SUBTEST No %08x ", i_target_mba.toEcmdString(), l_Subtest_no); - rc = FAPI_ATTR_GET(ATTR_MCBIST_TEST_TYPE, &i_target_mba, i_mcbtest); - if (rc) return rc;//---------i_mcbtest------->run - rc = mss_conversion_testtype(i_target_mba, i_mcbtest, i_mcbtest1); - if (rc) return rc; - - //l_Subtest_no = Extracted value from 3 to 7 - l_index = test_array_count[i_mcbtest]; - //FAPI_DBG("%s:INDEX No %d ",l_index); - - if (l_Subtest_no < l_index) - { - switch (l_sub_info[l_Subtest_no].l_operation_type) - { - case 0: - FAPI_DBG("%s:SUBTEST :WRITE", i_target_mba.toEcmdString()); - break; - case 1: - FAPI_DBG("%s:SUBTEST :READ", i_target_mba.toEcmdString()); - break; - case 2: - FAPI_DBG("%s:SUBTEST :READ - WRITE", i_target_mba.toEcmdString()); - break; - case 3: - FAPI_DBG("%s:SUBTEST :WRITE - READ", i_target_mba.toEcmdString()); - break; - case 4: - FAPI_DBG("%s:SUBTEST :READ - WRITE - READ", i_target_mba.toEcmdString()); - break; - case 5: - FAPI_DBG("%s:SUBTEST :READ - WRITE - WRITE", i_target_mba.toEcmdString()); - break; - case 6: - FAPI_DBG("%s:SUBTEST :RANDOM COMMAND SEQUENCE", i_target_mba.toEcmdString()); - break; - case 7: - FAPI_DBG("%s:SUBTEST :GOTO SUBTEST N OR REFRESH ONLY", i_target_mba.toEcmdString()); - break; - default: - FAPI_DBG("%s:Wrong Operation selected for Subtest", i_target_mba.toEcmdString()); - } - - switch (l_sub_info[l_Subtest_no].l_data_mode) - { - case 0: - FAPI_DBG("%s:DATA MODE :FIXED DATA", i_target_mba.toEcmdString()); - break; - case 1: - FAPI_DBG("%s:DATA MODE :DATA_RANDOM_FORWARD", i_target_mba.toEcmdString()); - break; - case 2: - FAPI_DBG("%s:DATA MODE :DATA_RANDOM_REVERSE", i_target_mba.toEcmdString()); - break; - case 3: - FAPI_DBG("%s:DATA MODE :RANDOM w/ECC FORWARD", i_target_mba.toEcmdString()); - break; - case 4: - FAPI_DBG("%s:DATA MODE :RANDOM w/ECC REVERSE", i_target_mba.toEcmdString()); - break; - case 5: - FAPI_DBG("%s:DATA MODE :DATA EQUAL ADDRESS", i_target_mba.toEcmdString()); - break; - case 6: - FAPI_DBG("%s:DATA MODE :DATA ROTATE LEFT", i_target_mba.toEcmdString()); - break; - case 7: - FAPI_DBG("%s:DATA MODE :DATA ROTATE RIGHT", i_target_mba.toEcmdString()); - break; - default: - FAPI_DBG("%s:Wrong Data Mode selected for Subtest", i_target_mba.toEcmdString()); - } - - switch (l_sub_info[l_Subtest_no].l_addr_mode) - { - case 0: - FAPI_DBG("%s:ADDRESS MODE :SEQUENTIAL FORWARD", i_target_mba.toEcmdString()); - break; - case 1: - FAPI_DBG("%s:ADDRESS MODE :SEQUENTIAL REVERSE", i_target_mba.toEcmdString()); - break; - case 2: - FAPI_DBG("%s:ADDRESS MODE :RANDOM FORWARD", i_target_mba.toEcmdString()); - break; - case 3: - FAPI_DBG("%s:ADDRESS MODE :RANDOM REVERSE", i_target_mba.toEcmdString()); - break; - default: - FAPI_DBG("%s:Wrong Address Mode selected for Subtest", i_target_mba.toEcmdString()); - } - } - } - } - l_mcb_ip = 1; - } - if (l_data_buffer_64.isBitSet(1)) - { - FAPI_DBG("%s:POLLING STATUS:MCBIST POLLING DONE", - i_target_mba.toEcmdString()); - FAPI_DBG("%s:MCBIST is done", i_target_mba.toEcmdString()); - l_mcb_ip = 0; - l_mcb_done = 1; - - rc = fapiGetScom(i_target_mba, MBA01_MCBIST_MCBCFGQ_0x030106e0, l_data_buffer_trap_64); - if (rc) return rc; - rc_num = l_data_buffer_64.clearBit(60); - if (rc_num) - { - FAPI_ERR("Error in function Poll_mcb:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBCFGQ_0x030106e0, l_data_buffer_trap_64); - if (rc) return rc; - - } - if (l_data_buffer_64.isBitSet(2)) - { - l_mcb_fail = 1; - FAPI_DBG("%s:POLLING STATUS:MCBIST FAILED", i_target_mba.toEcmdString()); - - if (l_mcb_stop_on_fail == 1) //if stop on error is 1, break after the current subtest completes - { - rc = fapiGetScom(i_target_mba, MBA01_MCBIST_MCBCFGQ_0x030106e0, l_stop_on_fail_buffer_64); - if (rc) return rc; - rc_num = l_stop_on_fail_buffer_64.setBit(62); - if (rc_num) - { - FAPI_ERR("Error in function poll_mcb:"); - rc.setEcmdError(rc_num); - return rc; - } // Set bit 61 to break after current subtest - rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBCFGQ_0x030106e0, - l_stop_on_fail_buffer_64); - if (rc) return rc; - FAPI_DBG("%s:MCBIST will break after Current Subtest", - i_target_mba.toEcmdString()); - - while (l_mcb_done == 0) // Poll till MCBIST is done - { - rc = fapiGetScom(i_target_mba, MBA01_MCBIST_MCB_CNTLSTATQ_0x030106dc, l_data_buffer_64); - if (rc) return rc; - if (l_data_buffer_64.isBitSet(1)) - { - l_mcb_ip = 0; - l_mcb_done = 1; - - rc = fapiGetScom(i_target_mba, MBA01_MCBIST_MCBCFGQ_0x030106e0, l_data_buffer_trap_64); - if (rc) return rc; - rc_num = l_data_buffer_64.clearBit(60); - if (rc_num) - { - FAPI_ERR("Error in function Poll_mcb:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBCFGQ_0x030106e0, l_data_buffer_trap_64); - if (rc) return rc; - - FAPI_DBG("%s:MCBIST Done", i_target_mba.toEcmdString()); - rc_num = l_stop_on_fail_buffer_64.clearBit(62); - if (rc_num) - { - FAPI_ERR("Error in function poll_mcb:"); - rc.setEcmdError(rc_num); - return rc; - } // Clearing bit 61 to avoid breaking after current subtest - rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBCFGQ_0x030106e0, l_stop_on_fail_buffer_64); - if (rc) return rc; - } - } - } - } - l_mcb_timeout++; - if (l_mcb_timeout >= l_time) - { - FAPI_ERR("poll_mcb:Maximun time out"); - const fapi::Target & MBA_CHIPLET = i_target_mba; - FAPI_SET_HWP_ERROR(rc, RC_MSS_MCBIST_TIMEOUT_ERROR); - return rc; - } - -#ifdef MCB_DEBUG_1 - //if((l_count%100 == 0)&&(l_print == 0))//Can be changed later - if(l_count%100 == 0) - { - FAPI_DBG("%s:MCB done bit : l_mcb_done",i_target_mba.toEcmdString()); - FAPI_DBG("%s:MCB fail bit : l_mcb_fail",i_target_mba.toEcmdString()); - FAPI_DBG("%s:MCB IP bit : l_mcb_ip",i_target_mba.toEcmdString()); - } -#endif - l_count++; - } - - if ((l_mcb_done == 1) && (l_mcb_fail == 1) && (l_mcb_stop_on_fail == true)) - { - *o_mcb_status = 1; /// MCB fail -#ifdef MCB_DEBUG_2 - FAPI_DBG("%s:*************************************************",i_target_mba.toEcmdString()); - FAPI_DBG("%s:MCB done bit : %d",i_target_mba.toEcmdString(),l_mcb_done); - FAPI_DBG("%s:MCB fail bit : %d",i_target_mba.toEcmdString(),l_mcb_fail); - FAPI_DBG("%s:MCB IP bit : %d",i_target_mba.toEcmdString(),l_mcb_ip); - FAPI_DBG("%s:*************************************************",i_target_mba.toEcmdString()); -#endif - } - else if ((l_mcb_done == 1) && (l_mcb_fail == 0)) - { - *o_mcb_status = 0;//pass; -#ifdef MCB_DEBUG2 - FAPI_DBG("%s:*************************************************", - i_target_mba.toEcmdString()); - FAPI_DBG("%s:MCB done bit : %d", i_target_mba.toEcmdString(), - l_mcb_done); - FAPI_DBG("%s:MCB fail bit : %d", i_target_mba.toEcmdString(), - l_mcb_fail); - FAPI_DBG("%s:MCB IP bit : %d", i_target_mba.toEcmdString(), l_mcb_ip); - FAPI_DBG("%s:*************************************************", - i_target_mba.toEcmdString()); -#endif - } - else if ((l_mcb_done == 0) && (l_mcb_ip == 1) && (l_mcb_timeout == l_time)) - { - *o_mcb_status = 1;//fail; -#ifdef MCB_DEBUG2 - FAPI_DBG("%s:****************************************", - i_target_mba.toEcmdString()); - FAPI_DBG("%s:MCB done bit : %d", i_target_mba.toEcmdString(), - l_mcb_done); - FAPI_DBG("%s:MCB fail bit : %d", i_target_mba.toEcmdString(), - l_mcb_fail); - FAPI_DBG("%s:MCB IP bit : %d", i_target_mba.toEcmdString(), l_mcb_ip); - FAPI_DBG("%s:****************************************", - i_target_mba.toEcmdString()); - -#endif - } - - if (*o_mcb_status == 1) - { - FAPI_DBG("poll_mcb:MCBIST failed"); - return rc; - } - - return rc; -} -fapi::ReturnCode mcb_error_map_print(const fapi::Target & i_target_mba, - ecmdDataBufferBase & i_mcb_fail_160, - uint8_t i_port, - uint8_t i_array[80], - uint8_t i_number, - ecmdDataBufferBase i_data_buf_port, - ecmdDataBufferBase i_data_buf_spare) -{ - ReturnCode rc; - uint32_t rc_num=0; - uint8_t l_num_ranks_per_dimm[MAX_PORT][MAX_PORT]; - uint8_t l_rankpair_table[MAX_RANK]; - uint8_t l_cur_rank = 0; - uint16_t l_index0, l_index1, l_byte, l_nibble; - uint8_t l_max_rank = 0; - uint8_t l_rank_pair = 0; - char l_str1[200] = ""; - ecmdDataBufferBase l_mcb(64); - uint8_t i_rank = 0; - uint8_t l_mbaPosition = 0; - rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target_mba, l_mbaPosition); - if (rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target_mba, - l_num_ranks_per_dimm); - if (rc) return rc; - l_max_rank = l_num_ranks_per_dimm[i_port][0] + l_num_ranks_per_dimm[i_port][1]; - - uint64_t l_generic_buffer; - uint32_t l_sbit, l_len; - uint16_t l_output; - - rc = mss_getrankpair(i_target_mba, i_port, 0, &l_rank_pair, l_rankpair_table); - if (rc) return rc; - if (l_max_rank == 0) - { - FAPI_DBG("%s: NO RANK FOUND ON PORT %d ", i_target_mba.toEcmdString(), i_port); - return rc; - } - else - { - for (l_cur_rank = 0; l_cur_rank < l_max_rank; l_cur_rank++) - { - i_rank = l_rankpair_table[l_cur_rank]; - //FAPI_DBG("%s:i am rank %d cur_index %d",i_target_mba.toEcmdString(),i_rank,l_cur_rank); - if (i_rank > MAX_RANK) - { - break; - } - } - } - - if (i_port == 0) - { - if (l_mbaPosition == 0) - { - l_sbit = 0; - l_len = 16; - l_generic_buffer = i_data_buf_port.getDoubleWord(0); - rc_num |= i_data_buf_spare.extractToRight(&l_output, l_sbit, l_len); - FAPI_DBG("%s:################# MBA01 ###########################\n", i_target_mba.toEcmdString()); - FAPI_DBG("%s:################# PORT0 ERROR MAP #################\n", i_target_mba.toEcmdString()); - FAPI_DBG("%s:Byte 00112233445566778899", i_target_mba.toEcmdString()); - FAPI_DBG("%s:Nibble 01010101010101010101", i_target_mba.toEcmdString()); - FAPI_DBG("%s:MASK %016llX%04X\n", i_target_mba.toEcmdString(), l_generic_buffer, l_output); - } - else - { - l_sbit = 0; - l_len = 16; - l_generic_buffer = i_data_buf_port.getDoubleWord(0); - rc_num |= i_data_buf_spare.extractToRight(&l_output, l_sbit, l_len); - FAPI_DBG("%s:################# MBA23 ###########################\n", i_target_mba.toEcmdString()); - FAPI_DBG("%s:################# PORT0 ERROR MAP #################\n", i_target_mba.toEcmdString()); - FAPI_DBG("%s:Byte 00112233445566778899", i_target_mba.toEcmdString()); - FAPI_DBG("%s:Nibble 01010101010101010101", i_target_mba.toEcmdString()); - FAPI_DBG("%s:MASK %016llX%04X\n", i_target_mba.toEcmdString(), l_generic_buffer, l_output); - } - } - else - { - if (l_mbaPosition == 0) - { - l_sbit = 16; - l_len = 16; - l_generic_buffer = i_data_buf_port.getDoubleWord(0); - rc_num |= i_data_buf_spare.extractToRight(&l_output, l_sbit, l_len); - FAPI_DBG("%s:################# MBA01 ###########################\n", i_target_mba.toEcmdString()); - FAPI_DBG("%s:################# PORT1 ERROR MAP #################\n", i_target_mba.toEcmdString()); - FAPI_DBG("%s:Byte 00112233445566778899", i_target_mba.toEcmdString()); - FAPI_DBG("%s:Nibble 01010101010101010101", i_target_mba.toEcmdString()); - FAPI_DBG("%s:MASK %016llX%04X\n", i_target_mba.toEcmdString(), l_generic_buffer, l_output); - } - else - { - l_sbit = 16; - l_len = 16; - l_generic_buffer = i_data_buf_port.getDoubleWord(0); - rc_num = rc_num | i_data_buf_spare.extractToRight(&l_output, - l_sbit, l_len); - FAPI_DBG("%s:################# MBA23 ###########################\n", i_target_mba.toEcmdString()); - FAPI_DBG("%s:################# PORT1 ERROR MAP #################\n", i_target_mba.toEcmdString()); - FAPI_DBG("%s:Byte 00112233445566778899", i_target_mba.toEcmdString()); - FAPI_DBG("%s:Nibble 01010101010101010101", i_target_mba.toEcmdString()); - FAPI_DBG("%s:MASK %016llX%04X\n", i_target_mba.toEcmdString(), l_generic_buffer, l_output); - } - } - - uint8_t l_index, l_value, l_value1; - uint8_t l_marray0[80] = { 0 }; - ecmdDataBufferBase l_data_buffer1_64(64), l_data_buffer3_64(64); - - rc_num |= l_data_buffer1_64.flushTo0(); - //FAPI_ERR("Buffer error in function mcb_error_map_print"); - - if (rc_num) //The check for if bad rc_num was misplaced - { - FAPI_ERR("Error in function mcb_error_map_print:"); - rc.setEcmdError(rc_num); - return rc; - } - - uint8_t l_num, io_num, l_inter, l_num2, l_index2; - l_num = 0; - //FAPI_INF("%s:l_max_rank%d",i_target_mba.toEcmdString(),l_max_rank); - //FAPI_INF("%s:rank:%d",i_target_mba.toEcmdString(),i_rank); - for (l_index = 0; l_index < i_number; l_index++) - { - l_value = i_array[l_index]; - l_inter = (l_value / 4); - l_num2 = l_num - 1; - if (l_inter == l_marray0[l_num2] && (l_num != 0)) - { - continue; - } - - l_value1 = l_inter; - l_marray0[l_num] = l_value1; - l_num++; - //FAPI_INF("%s:l_value,l_value1,l_num:%d,%d,%d",i_target_mba.toEcmdString(),l_value,l_value1,l_num); - } - - //FAPI_INF("%s:l_value,l_value1,l_num:%d,%d,%d",i_target_mba.toEcmdString(),l_value,l_value1,l_num); - io_num = l_num; - - //To be in error map print function - - //Debug Prints - /* - uint8_t l_i; - l_i = 0; - - - FAPI_INF("________________________________________________________________________________________________________"); - for(l_i = 0;l_i < i_number;l_i++) - { - FAPI_INF("%s:INITIAL ARRAY:%d",i_target_mba.toEcmdString(),i_array[l_i] ); - } - FAPI_INF("________________________________________________________________________________________________________"); - for(l_i = 0;l_i < io_num;l_i++) - { - FAPI_INF("%s:FINAL ARRAY:%d",i_target_mba.toEcmdString(),l_marray0[l_i] ); - } - FAPI_INF("________________________________________________________________________________________________________");*/ - - l_cur_rank = 0; - i_rank = 0; - l_num = 0; - l_value = 0; - - //FAPI_DBG("%s: --------------------",i_target_mba.toEcmdString()); - - rc = mss_getrankpair(i_target_mba, i_port, 0, &l_rank_pair, l_rankpair_table); - if (rc) return rc; - for (l_cur_rank = 0; l_cur_rank < l_max_rank; l_cur_rank++) - { - l_index2 = 0; - l_num = 0; - i_rank = l_rankpair_table[l_cur_rank]; - sprintf(l_str1, "%s:%-4s%d%5s", i_target_mba.toEcmdString(), "RANK", i_rank, ""); - for (l_byte = 0; l_byte < MAX_BYTE; l_byte++) - { - for (l_nibble = 0; l_nibble < MAX_NIBBLES; l_nibble++) - { - l_value = l_marray0[l_num]; - //FAPI_DBG("%s:l_value %d l_num %d",i_target_mba.toEcmdString(),l_value,l_num); - l_index0 = (i_rank * 20) + (l_byte * 2) + l_nibble; - l_index2 = (l_byte * 2) + l_nibble; - l_index1 = l_index0; - if ((l_value == l_index2) && (l_num < io_num)) - { - strcat(l_str1, "M"); - //FAPI_DBG("%s:l_value %d l_num %d",i_target_mba.toEcmdString(),l_value,l_num); - l_num++; - } - else - { - if (i_mcb_fail_160.isBitSet(l_index1)) - { - strcat(l_str1, "X"); - } - else - { - strcat(l_str1, "."); - } - } - } - } - FAPI_DBG("%s", l_str1); - } - - return rc; -} - -/*****************************************************************/ -// Funtion name : mcb_error_map -// Description : Reads the nibblewise Error map registers into o_error_map -// Input Parameters : -// const fapi::Target & Centaur.mba -// uint8_t i_port Current port -// uint8_t i_rank Current Rank -// Output Parameter : -// uint8_t o_error_map[][8][10][2] Contains the error map -//****************************************************************/ -fapi::ReturnCode mcb_error_map(const fapi::Target & i_target_mba, - uint8_t o_error_map[][8][10][2], - uint8_t i_CDarray0[80], - uint8_t i_CDarray1[80], - uint8_t count_bad_dq[2]) -{ - ecmdDataBufferBase l_mcbem1ab(64); - ecmdDataBufferBase l_mcbem2ab(64); - ecmdDataBufferBase l_mcbem3ab(64); - ecmdDataBufferBase l_data_buffer_64(64); - - ecmdDataBufferBase l_mcb_fail_320(320); - ecmdDataBufferBase l_mcb_fail_160(160); - ecmdDataBufferBase l_mcb_fail1_160(160); - ecmdDataBufferBase l_mcb(64); - ecmdDataBufferBase l_ISDIMM_BUF1(64), l_ISDIMM_BUF0(64); - ecmdDataBufferBase l_ISDIMM_spare1(8), l_ISDIMM_spare0(8); - uint8_t l_max_rank0, l_max_rank1; - - uint8_t i_rank, i_port; - fapi::Target i_target_centaur; - fapi::ReturnCode rc; - uint32_t rc_num = 0; - uint16_t l_index0 = 0; - uint32_t l_index1 = 0; - uint8_t l_port = 0; - uint8_t l_rank = 0; - uint8_t l_byte = 0; - uint8_t l_nibble = 0; - uint8_t l_num_ranks_per_dimm[MAX_PORT][MAX_PORT]; - uint8_t l_mbaPosition = 0; - uint8_t rank_pair, i_byte, i_nibble, i_input_index_u8, o_val, i_byte1, i_nibble1; - - uint8_t l_index, l_i, l_number, l_value, l_value1, l_number1;//l_cur_rank, - l_number1 = 0; //HB - uint8_t l_array[80] = { 0 }; - uint8_t l_marray11[80] = { 0 }; - uint8_t l_array0[80] = { 0 }; - uint8_t l_marray0[80] = { 0 }; - uint8_t l_array1[80] = { 0 }; - uint8_t l_marray1[80] = { 0 }; - uint8_t l_marray[80] = { 0 }; - uint8_t cdimm_dq0[72] = { 0 }; - uint8_t cdimm_dq1[72] = { 0 }; - uint8_t cdimm_dq[80] = { 0 }; - uint8_t l_ISarray1[80] = { 0 }; - uint8_t l_ISarray0[80] = { 0 }; - uint8_t l_ISarray[80] = { 0 }; - uint8_t l_rankpair_table[MAX_RANK]; - ecmdDataBufferBase l_data_buffer1_64(64), l_data_buffer3_64(64), - l_data_buf_port0(64), l_data_buf_port1(64), l_data_buf_spare(64); - uint64_t l_generic_buffer0, l_generic_buffer1, l_generic_buffer; - uint32_t l_sbit, l_len; - uint8_t l_output0, l_output1, l_output, l_j; - - input_type l_input_type_e = ISDIMM_DQ; - uint8_t valid_rank[MAX_RANK]; - char l_str[200] = ""; - uint8_t l_max_bytes = 9; - uint8_t l_max_rank; - uint8_t l_attr_eff_dimm_type_u8; - FAPI_DBG("%s:Function MCB_ERROR_MAP", i_target_mba.toEcmdString()); - - rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target_mba, l_mbaPosition); - if (rc) - { - FAPI_ERR("Error getting MBA position"); - return rc; - } - - rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target_mba, - l_num_ranks_per_dimm); - if (rc) return rc; - - l_max_rank0 = l_num_ranks_per_dimm[0][0] + l_num_ranks_per_dimm[0][1]; - l_max_rank1 = l_num_ranks_per_dimm[1][0] + l_num_ranks_per_dimm[1][1]; - - rc = fapiGetParentChip(i_target_mba, i_target_centaur); - if (rc) - { - FAPI_ERR("Error in getting Parent Chiplet"); - return rc; - } - - if (l_mbaPosition == 0) - { - rc = fapiGetScom(i_target_centaur, MBS_MCBIST01_MCBEMA1Q_0x0201166a, l_mcbem1ab); - if (rc) return rc; - rc_num = l_mcb_fail_160.insert(l_mcbem1ab, 0, 60, 0); - if (rc_num) - { - FAPI_ERR("Error in function mcb_error_map:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiGetScom(i_target_centaur, MBS_MCBIST01_MCBEMA2Q_0x0201166b, l_mcbem2ab); - if (rc) return rc; - rc_num = l_mcb_fail_160.insert(l_mcbem2ab, 60, 60, 0); - if (rc_num) - { - FAPI_ERR("Error in function mcb_error_map:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiGetScom(i_target_centaur, MBS_MCBIST01_MCBEMA3Q_0x0201166c, l_mcbem3ab); - if (rc) return rc; - rc_num = l_mcb_fail_160.insert(l_mcbem3ab, 120, 40, 0); - if (rc_num) - { - FAPI_ERR("Error in function mcb_error_map:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiGetScom(i_target_centaur, MBS_MCBIST01_MCBEMB1Q_0x0201166d, l_mcbem1ab); - if (rc) return rc; - rc_num = l_mcb_fail1_160.insert(l_mcbem1ab, 0, 60, 0); - if (rc_num) - { - FAPI_ERR("Error in function mcb_error_map:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiGetScom(i_target_centaur, MBS_MCBIST01_MCBEMB2Q_0x0201166e, l_mcbem2ab); - if (rc) return rc; - rc_num = l_mcb_fail1_160.insert(l_mcbem2ab, 60, 60, 0); - if (rc_num) - { - FAPI_ERR("Error in function mcb_error_map:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiGetScom(i_target_centaur, MBS_MCBIST01_MCBEMB3Q_0x0201166f, l_mcbem3ab); - if (rc) return rc; - rc_num = l_mcb_fail1_160.insert(l_mcbem3ab, 120, 40, 0); - if (rc_num) - { - FAPI_ERR("Error in function mcb_error_map:"); - rc.setEcmdError(rc_num); - return rc; - } - } - else if (l_mbaPosition == 1) - { - rc = fapiGetScom(i_target_centaur, 0x0201176a, l_mcbem1ab); - if (rc) return rc; - rc_num = l_mcb_fail_160.insert(l_mcbem1ab, 0, 60, 0); - if (rc_num) - { - FAPI_ERR("Error in function mcb_error_map:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiGetScom(i_target_centaur, 0x0201176b, l_mcbem2ab); - if (rc) return rc; - rc_num = l_mcb_fail_160.insert(l_mcbem2ab, 60, 60, 0); - if (rc_num) - { - FAPI_ERR("Error in function mcb_error_map:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiGetScom(i_target_centaur, 0x0201176c, l_mcbem3ab); - if (rc) return rc; - rc_num = l_mcb_fail_160.insert(l_mcbem3ab, 120, 40, 0); - if (rc_num) - { - FAPI_ERR("Error in function mcb_error_map:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiGetScom(i_target_centaur, 0x0201176d, l_mcbem1ab); - if (rc) return rc; - rc_num = l_mcb_fail1_160.insert(l_mcbem1ab, 0, 60, 0); - if (rc_num) - { - FAPI_ERR("Error in function mcb_error_map:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiGetScom(i_target_centaur, 0x0201176e, l_mcbem2ab); - if (rc) return rc; - rc_num = l_mcb_fail1_160.insert(l_mcbem2ab, 60, 60, 0); - if (rc_num) - { - FAPI_ERR("Error in function mcb_error_map:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiGetScom(i_target_centaur, 0x0201176f, l_mcbem3ab); - if (rc) return rc; - rc_num = l_mcb_fail1_160.insert(l_mcbem3ab, 120, 40, 0); - if (rc_num) - { - FAPI_ERR("Error in function mcb_error_map:"); - rc.setEcmdError(rc_num); - return rc; - } - } - - for (l_port = 0; l_port < MAX_PORT; l_port++) - { - rc = mss_getrankpair(i_target_mba, l_port, 0, &rank_pair, valid_rank); - if (rc) return rc; - - if (l_port == 0) - { - l_max_rank = l_max_rank0; - } - else - { - l_max_rank = l_max_rank1; - } - - for (l_rank = 0; l_rank < l_max_rank; l_rank++) - { - i_rank = valid_rank[l_rank]; - - for (l_byte = 0; l_byte < MAX_BYTE; l_byte++) - { - for (l_nibble = 0; l_nibble < MAX_NIBBLES; l_nibble++) - { - if (l_port == 0) - { - l_index0 = (i_rank * 20) + (l_byte * 2) + l_nibble; - l_index1 = l_index0; - - if ((l_mcb_fail_160.isBitSet(l_index1))) - { - o_error_map[l_port][i_rank][l_byte][l_nibble] = 1; - } - else - { - o_error_map[l_port][i_rank][l_byte][l_nibble] = 0; - } - } - else if (l_port == 1) - { - - l_index0 = (i_rank * 20) + (l_byte * 2) + l_nibble; - l_index1 = l_index0; - if ((l_mcb_fail1_160.isBitSet(l_index1))) - { - - o_error_map[l_port][i_rank][l_byte][l_nibble] = 1; - } - else - { - o_error_map[l_port][i_rank][l_byte][l_nibble] = 0; - } - } - } - } - } - } - - rc = FAPI_ATTR_GET(ATTR_EFF_CUSTOM_DIMM, &i_target_mba, l_attr_eff_dimm_type_u8); - if (rc) return rc; - - l_i = 0; - rc_num = l_data_buffer1_64.flushTo0(); - i_port = 0; - - while (i_port < 2) - { - rc_num = l_data_buffer1_64.flushTo0(); - rc_num = l_data_buffer3_64.flushTo0(); - if (l_mbaPosition == 0) - { - if (i_port == 0) - { - //FAPI_INF("l_array:%d",l_i); - l_i = 0; - rc = fapiGetScom(i_target_centaur, MBS_MCBIST01_MCBCMA1Q_0x02011672, l_data_buf_port0); - if (rc) - return rc; - rc = fapiGetScom(i_target_centaur, MBS_MCBIST01_MCBCMABQ_0x02011674, l_data_buf_spare); - if (rc) return rc; - for (l_index = 0; l_index < 64; l_index++) - { - if (l_data_buf_port0.isBitSet(l_index)) - { - l_array0[l_i] = l_index; - l_i++; - //FAPI_INF("l_array:%d",l_i); - } - } - for (l_index = 0; l_index < 16; l_index++) - { - if (l_data_buf_spare.isBitSet(l_index)) - { - l_array0[l_i] = l_index + 64; - l_i++; - //FAPI_INF("l_array:%d",l_i); - } - } - l_number1 = l_i; - } - - else - { - //FAPI_INF("l_array:%d",l_i); - l_i = 0; - rc = fapiGetScom(i_target_centaur, MBS_MCBIST01_MCBCMB1Q_0x02011673, l_data_buf_port1); - if (rc) return rc; - rc = fapiGetScom(i_target_centaur, MBS_MCBIST01_MCBCMABQ_0x02011674, l_data_buf_spare); - if (rc) return rc; - for (l_index = 0; l_index < 64; l_index++) - { - if (l_data_buf_port1.isBitSet(l_index)) - { - l_array1[l_i] = l_index; - l_i++;//FAPI_INF("l_array:%d",l_i); - } - } - for (l_index = 16; l_index < 32; l_index++) - { - if (l_data_buf_spare.isBitSet(l_index)) - { - l_array1[l_i] = l_index + 64 - 16; - l_i++;//FAPI_INF("l_array:%d",l_i); - } - } - l_number = l_i; - } - } - else - { - if (i_port == 0) - { - //FAPI_INF("l_array:%d",l_i); - l_i = 0; - rc = fapiGetScom(i_target_centaur, 0x02011774, l_data_buf_spare); - if (rc) return rc; - rc = fapiGetScom(i_target_centaur, 0x02011772, l_data_buf_port0); - if (rc) return rc; - for (l_index = 0; l_index < 64; l_index++) - { - if (l_data_buf_port0.isBitSet(l_index)) - { - l_array0[l_i] = l_index; - l_i++;//FAPI_INF("l_array:%d",l_i); - } - } - for (l_index = 0; l_index < 16; l_index++) - { - if (l_data_buf_spare.isBitSet(l_index)) - { - l_array0[l_i] = l_index + 64; - l_i++;//FAPI_INF("l_array:%d",l_i); - } - } - l_number1 = l_i; - } - else - { - l_i = 0; - //FAPI_INF("l_array:%d",l_i); - rc = fapiGetScom(i_target_centaur, 0x02011774, l_data_buf_spare); - if (rc) return rc; - rc = fapiGetScom(i_target_centaur, 0x02011773, l_data_buf_port1); - if (rc) return rc; - for (l_index = 0; l_index < 64; l_index++) - { - if (l_data_buf_port1.isBitSet(l_index)) - { - l_array1[l_i] = l_index; - l_i++;//FAPI_INF("l_array:%d",l_i); - } - } - for (l_index = 16; l_index < 32; l_index++) - { - if (l_data_buf_spare.isBitSet(l_index)) - { - l_array1[l_i] = l_index + 64 - 16; - l_i++;//FAPI_INF("l_array:%d",l_i); - } - } - l_number = l_i; - } - } - i_port++; - } - - //Conversion from CDIMM larray to ISDIMM larray - //port 0 - for (l_i = 0; l_i < MAX_ISDIMM_DQ; l_i++) - { - rc = rosetta_map(i_target_mba, 0, l_input_type_e, l_i, 0, o_val); - if (rc) return rc; - cdimm_dq0[o_val] = l_i; - } - - //port 1 - for (l_i = 0; l_i < MAX_ISDIMM_DQ; l_i++) - { - rc = rosetta_map(i_target_mba, 1, l_input_type_e, l_i, 0, o_val); - if (rc) return rc; - cdimm_dq1[o_val] = l_i; - } - - uint8_t l_num, io_num, io_num0, io_num1, l_inter, l_flag, l_n; - l_n = 0; - io_num0 = 0; - io_num1 = 0; - - //FAPI_INF("%s:l_max_rank%d",i_target_mba.toEcmdString(),l_max_rank); - l_port = 0; - while (l_port < 2) - { - l_num = 0; - if (l_port == 0) - { - for (l_index = 0; l_index < l_number1; l_index++) - { - l_array[l_index] = l_array0[l_index]; - } - l_n = l_number1; - rc = mss_getrankpair(i_target_mba, l_port, 0, &rank_pair, l_rankpair_table); - if (rc) return rc; - - for (l_i = 0; l_i < MAX_ISDIMM_DQ; l_i++) - { - cdimm_dq[l_i] = cdimm_dq0[l_i]; - } - } - else - { - for (l_index = 0; l_index < l_number; l_index++) - { - l_array[l_index] = l_array1[l_index]; - l_n = l_number; - } - rc = mss_getrankpair(i_target_mba, l_port, 0, &rank_pair, l_rankpair_table); - if (rc) return rc; - - for (l_i = 0; l_i < MAX_ISDIMM_DQ; l_i++) - { - cdimm_dq[l_i] = cdimm_dq1[l_i]; - } - } - //Getting array for converting CDIMM values as index and ISDIMM values as value of array for that index - for (l_index = 0; l_index < l_n; l_index++) - { - l_value = l_array[l_index]; - - l_value1 = cdimm_dq[l_value]; - if (l_value >= 72) - { - l_value1 = 255; - } - - l_ISarray[l_index] = l_value1; - //FAPI_INF("L_ISARRAY port %d index %d value %d ",l_port,l_index,l_ISarray[l_index]); - } - - if (l_attr_eff_dimm_type_u8 != ENUM_ATTR_EFF_CUSTOM_DIMM_YES) - { - //For ISDIMM marray - for (l_index = 0; l_index < l_n; l_index++) - { - l_value = l_ISarray[l_index]; - l_inter = (l_value / 4); - l_value1 = l_num - 1; - l_marray[l_num] = l_inter * 4; - l_num++; - //FAPI_INF("%s:l_value,l_value1,l_num:%d,%d,%d",i_target_mba.toEcmdString(),l_value,l_value1,l_num); - } - } - else - { - //For CDIMM marray - for (l_index = 0; l_index < l_n; l_index++) - { - l_value = l_array[l_index]; - l_inter = (l_value / 4); - l_value1 = l_num - 1; - l_marray[l_num] = l_inter * 4; - l_num++; - //FAPI_INF("%s:l_value,l_value1,l_num:%d,%d,%d",i_target_mba.toEcmdString(),l_value,l_value1,l_num); - } - } - - //Loop to sort Masked ISDIMM array - for (l_i = 0; l_i < l_num - 1; l_i++) - { - for (l_j = l_i + 1; l_j < l_num; l_j++) - { - if (l_marray[l_i] > l_marray[l_j]) - { - l_value = l_marray[l_j]; - l_marray[l_j] = l_marray[l_i]; - l_marray[l_i] = l_value; - //FAPI_INF("port %d value %d index %d",l_port,l_marray[l_i],l_i); - } - } - } - - //loop to remove repetition elements - l_j = 0; - for (l_i = 0; l_i < l_num; l_i++) - { - l_flag = 0; - - if ((l_marray[l_i] == l_marray[l_i + 1]) && (l_num != 0)) - { - l_flag = 1; - } - - if (l_flag == 0) - { - l_marray11[l_j] = l_marray[l_i]; - l_j++; - } - } - l_num = l_j; - - if (l_port == 0) - { - io_num0 = l_num; - if (io_num0 >= 21) - { - io_num0 = 21; - } - for (l_index = 0; l_index < io_num0; l_index++) - { - l_marray0[l_index] = l_marray11[l_index]; - } - - for (l_index = 0; l_index < l_number1; l_index++) - { - - l_ISarray0[l_index] = l_ISarray[l_index]; - } - } - else - { - io_num1 = l_num; - if (io_num1 >= 21) - { - io_num1 = 21; - } - for (l_index = 0; l_index < io_num1; l_index++) - { - l_marray1[l_index] = l_marray11[l_index]; - } - for (l_index = 0; l_index < l_number; l_index++) - { - - l_ISarray1[l_index] = l_ISarray[l_index]; - } - } - l_port++; - } - - count_bad_dq[0] = l_number1; - count_bad_dq[1] = l_number; - // FAPI_INF("\n abhijit's number is number=%d and %d \n",count_bad_dq[0],count_bad_dq[1]); - for (l_i = 0; l_i < l_number1; l_i++) - { - i_CDarray0[l_i] = l_array0[l_i]; - } - for (l_i = 0; l_i < l_number; l_i++) - { - i_CDarray1[l_i] = l_array1[l_i]; - } - - if(l_attr_eff_dimm_type_u8 != fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES) //Calling ISDIMM error mAP and LRDIMM - { - FAPI_DBG("%s:################# Error MAP for ISDIMM #################", - i_target_mba.toEcmdString()); - for (l_port = 0; l_port < 2; l_port++) - { - if (l_port == 0) - { - l_max_rank = l_max_rank0; - - io_num = io_num0; - for (l_index = 0; l_index < io_num; l_index++) - { - l_marray[l_index] = l_marray0[l_index]; - } - } - else - { - l_max_rank = l_max_rank1; - - io_num = io_num1; - for (l_index = 0; l_index < io_num; l_index++) - { - l_marray[l_index] = l_marray1[l_index]; - } - } - - if (l_max_rank == 0) - { - FAPI_DBG("%s: NO RANKS FOUND ON PORT %d", i_target_mba.toEcmdString(), l_port); - } - else - { - //To set the mask print in error map - l_value = 0; - if (l_port == 0) - { - //For Port 0 - for (l_index = 0; l_index < l_number1; l_index++) - { - l_flag = 0; - l_value = l_ISarray0[l_index]; - //FAPI_INF("Value is %d for index %d", l_value,l_index); - if (l_value >= 72) - { - l_flag = 1; - //FAPI_INF("Value (72)is here for index %d",l_index); - } - if ((l_value >= 64) && (l_value < 72)) - { - l_value1 = l_value - 64; - l_flag = 2; - //FAPI_INF("Value (64)is here for index %d,l_value1 %d",l_index,l_value1); - rc_num = l_ISDIMM_spare0.setBit(l_value1); - if (rc_num) - { - FAPI_ERR("Error in function Error Map:"); - rc.setEcmdError(rc_num); - return rc; - } - } - if (l_flag == 0) - { - rc_num = l_ISDIMM_BUF0.setBit(l_value); - if (rc_num) - { - FAPI_ERR("Error in function Error Map:"); - rc.setEcmdError(rc_num); - return rc; - } - } - //FAPI_INF("VALUE OF FLAG %d",l_flag); - } - - l_generic_buffer0 = 0; - l_output0 = 0; - l_generic_buffer0 = l_ISDIMM_BUF0.getDoubleWord(0); - l_sbit = 0; - l_len = 8; - rc_num |= l_ISDIMM_spare0.extractToRight(&l_output0, l_sbit, l_len); - //FAPI_DBG("%s:MASK %016llX%02X\n",i_target_mba.toEcmdString(),l_generic_buffer0,l_output0); - l_generic_buffer = l_generic_buffer0; - l_output = l_output0; - } - else - { - for (l_index = 0; l_index < l_number; l_index++) - { - l_flag = 0; - l_value = l_ISarray1[l_index]; - //FAPI_INF("Value is %d for index %d", l_value,l_index); - if (l_value >= 72) - { - l_flag = 1; - //FAPI_INF("Value (72)is here for index %d",l_index); - } - if ((l_value >= 64) && (l_value < 72)) - { - l_value1 = l_value - 64; - l_flag = 2; - //FAPI_INF("Value (64)is here for index %d,l_value1 %d",l_index,l_value1); - rc_num = l_ISDIMM_spare1.setBit(l_value1); - if (rc_num) - { - FAPI_ERR("Error in function Error Map:"); - rc.setEcmdError(rc_num); - return rc; - } - } - if (l_flag == 0) - { - rc_num = l_ISDIMM_BUF1.setBit(l_value); - if (rc_num) - { - FAPI_ERR("Error in function Error Map:"); - rc.setEcmdError(rc_num); - return rc; - } - } - //FAPI_INF("VALUE OF FLAG %d",l_flag); - } - - l_generic_buffer1 = 0; - l_output1 = 0; - l_generic_buffer1 = l_ISDIMM_BUF1.getDoubleWord(0); - l_sbit = 0; - l_len = 8; - rc_num |= l_ISDIMM_spare1.extractToRight(&l_output1, l_sbit, l_len); - //FAPI_DBG("%s:MASK %016llX%02X\n",i_target_mba.toEcmdString(),l_generic_buffer1,l_output1); - l_generic_buffer = l_generic_buffer1; - l_output = l_output1; - } - - //Mask calculation Ends - - if (l_mbaPosition == 0) - { - //FAPI_DBG("%s:MASK %016llX%02X\n",i_target_mba.toEcmdString(),l_generic_buffer0,l_output0); - FAPI_DBG("%s:################# MBA01 ###########################\n", i_target_mba.toEcmdString()); - FAPI_DBG("%s:################# PORT%d ERROR MAP #################\n", i_target_mba.toEcmdString(), l_port); - FAPI_DBG("%s:Byte 001122334455667788", i_target_mba.toEcmdString()); - FAPI_DBG("%s:Nibble 010101010101010101", i_target_mba.toEcmdString()); - FAPI_DBG("%s:MASK %016llX%02X\n", i_target_mba.toEcmdString(), l_generic_buffer, l_output); - } - else - { - //FAPI_DBG("%s:MASK %016llX%02X\n",i_target_mba.toEcmdString(),l_generic_buffer1,l_output1); - FAPI_DBG("%s:################# MBA23 ###########################\n", i_target_mba.toEcmdString()); - FAPI_DBG( - "%s:################# PORT%d ERROR MAP #################\n",i_target_mba.toEcmdString(), l_port); - FAPI_DBG("%s:Byte 001122334455667788", i_target_mba.toEcmdString()); - FAPI_DBG("%s:Nibble 010101010101010101", i_target_mba.toEcmdString()); - FAPI_DBG("%s:MASK %016llX%02X\n", i_target_mba.toEcmdString(), l_generic_buffer, l_output); - } - - for (l_rank = 0; l_rank < l_max_rank; l_rank++) - { - l_num = 0; - rc = mss_getrankpair(i_target_mba, l_port, 0, &rank_pair, valid_rank); - if (rc) return rc; - i_rank = valid_rank[l_rank]; - sprintf(l_str, "%s:%-4s%d%5s", i_target_mba.toEcmdString(), "RANK", i_rank, ""); - l_flag = 0; - for (i_byte = 0; i_byte < l_max_bytes; i_byte++) - { - for (i_nibble = 0; i_nibble < 2; i_nibble++) - { - l_flag = 0; - l_inter = l_marray[l_num]; - - i_input_index_u8 = (8 * i_byte) + (4 * i_nibble); - - if ((l_inter == i_input_index_u8) && (l_num < io_num)) - { - //FAPI_INF("l_flag %d,l_inter %d,i_input_index_u8 %d",l_flag,l_inter,i_input_index_u8); - l_num++; - l_flag = 1; - } - - //FAPI_INF("l_flag %d,l_inter %d,i_input_index_u8 %d",l_flag,l_inter,i_input_index_u8); - rc = rosetta_map(i_target_mba, l_port, - l_input_type_e, i_input_index_u8, - 0, o_val); - if (rc) return rc; - i_byte1 = o_val / 8; - i_nibble1 = o_val % 8; - if (i_nibble1 > 3) - { - i_nibble1 = 1; - } - else - { - i_nibble1 = 0; - } - if (l_flag == 1) - { - strcat(l_str, "M"); - } - else - { - if (o_error_map[l_port][i_rank][i_byte1][i_nibble1] == 1) - { - strcat(l_str, "X"); - } - else - { - strcat(l_str, "."); - } - } - } - } - FAPI_DBG("%s", l_str); - } - } - } - } - - else //Calling CDIMM error Map print - { - FAPI_DBG("%s:################# CDIMM ERROR MAP ###########################\n", i_target_mba.toEcmdString()); - i_port = 0; - mcb_error_map_print(i_target_mba, l_mcb_fail_160, i_port, l_array0, - l_number1, l_data_buf_port0, l_data_buf_spare); - - i_port = 1; - mcb_error_map_print(i_target_mba, l_mcb_fail1_160, i_port, l_array1, - l_number, l_data_buf_port1, l_data_buf_spare); - } - - return rc; -} - -/*****************************************************************/ -// Funtion name : mcb_write_test_mem -// Description : : Based on parameters passed we write data into Register being passed -// Input Parameters : -// const fapi::Target & Centaur.mba -// const uint64_t i_reg_addr Register address -// mcbist_oper_type i_operation_type Operation Type -// mcbist_addr_mode i_addr_mode Sequential or Random address modes -// mcbist_data_mode i_data_mode Data Mode -// uint8_t i_done Done Bit -// mcbist_data_select_mode i_data_select_mode Different BURST modes or DEFAULT -// mcbist_add_select_mode i_addr_select_mode Address Select mode -// uint8_t i_testnumber Subtest number -// uint8_t i_cfg_test_123_cmd Integer value - -//****************************************************************/ -fapi::ReturnCode mcb_write_test_mem(const fapi::Target & i_target_mba, - const uint64_t i_reg_addr, - mcbist_oper_type i_operation_type, - uint8_t i_cfg_test_123_cmd, - mcbist_addr_mode i_addr_mode, - mcbist_data_mode i_data_mode, - uint8_t i_done, - mcbist_data_select_mode i_data_select_mode, - mcbist_add_select_mode i_addr_select_mode, - uint8_t i_testnumber, - uint8_t i_testnumber1, - uint8_t total_subtest_no, - struct Subtest_info l_sub_info[30]) -{ - fapi::ReturnCode rc; - uint32_t rc_num = 0; - uint8_t l_index = 0; - uint8_t l_operation_type = i_operation_type; - uint8_t l_cfg_test_123_cmd = i_cfg_test_123_cmd; - uint8_t l_addr_mode = i_addr_mode; - uint8_t l_data_mode = i_data_mode; - uint8_t l_data_select_mode = i_data_select_mode; - uint8_t l_addr_select_mode = i_addr_select_mode; - ecmdDataBufferBase l_data_buffer_64(64); - - FAPI_DBG("%s:Function mcb_write_test_mem", i_target_mba.toEcmdString()); - rc = fapiGetScom(i_target_mba, i_reg_addr, l_data_buffer_64); - if (rc) return rc; - l_index = i_testnumber * (MCB_TEST_NUM); - - uint8_t l_done_bit; - rc = FAPI_ATTR_GET(ATTR_MCBIST_ADDR_BANK, &i_target_mba, l_done_bit); - if (rc) return rc; - if (l_done_bit == 1) - { - return rc; - } - - l_sub_info[i_testnumber1].l_operation_type = l_operation_type; - l_sub_info[i_testnumber1].l_data_mode = l_data_mode; - l_sub_info[i_testnumber1].l_addr_mode = l_addr_mode; - - // Operation type - rc_num |= l_data_buffer_64.insertFromRight(l_operation_type, l_index, 3); - rc_num |= l_data_buffer_64.insertFromRight(l_cfg_test_123_cmd, l_index + 3, 3); - // ADDR MODE - rc_num |= l_data_buffer_64.insertFromRight(l_addr_mode, l_index + 6, 2); - // DATA MODE - rc_num |= l_data_buffer_64.insertFromRight(l_data_mode, l_index + 8, 3); - // Done bit - rc_num |= l_data_buffer_64.insertFromRight(i_done, l_index + 11, 1); - // Data Select Mode - rc_num |= l_data_buffer_64.insertFromRight(l_data_select_mode, l_index + 12, 2); - - // Address Select mode - rc_num |= l_data_buffer_64.insertFromRight(l_addr_select_mode, l_index + 14, 2); - - if (rc_num) - { - FAPI_ERR("Error in function mcb_write_test_mem:"); - rc.setEcmdError(rc_num); - return rc; - } - - rc = fapiPutScom(i_target_mba, i_reg_addr, l_data_buffer_64); - if (rc) return rc; - rc = fapiGetScom(i_target_mba, i_reg_addr, l_data_buffer_64); - if (rc) return rc; - - FAPI_DBG("%s:SUBTEST %d of %d in Progress.................... ", - i_target_mba.toEcmdString(), i_testnumber1, total_subtest_no); - //FAPI_DBG("%s:SUBTEST %d in Progress.................... ",i_testnumber); - FAPI_DBG("%s:SUBTEST DETAILS", i_target_mba.toEcmdString()); - - switch (l_operation_type) - { - case 0: - FAPI_DBG("%s:SUBTEST :WRITE", i_target_mba.toEcmdString()); - break; - case 1: - FAPI_DBG("%s:SUBTEST :READ", i_target_mba.toEcmdString()); - break; - case 2: - FAPI_DBG("%s:SUBTEST :READ - WRITE", i_target_mba.toEcmdString()); - break; - case 3: - FAPI_DBG("%s:SUBTEST :WRITE - READ", i_target_mba.toEcmdString()); - break; - case 4: - FAPI_DBG("%s:SUBTEST :READ - WRITE - READ", i_target_mba.toEcmdString()); - break; - case 5: - FAPI_DBG("%s:SUBTEST :READ - WRITE - WRITE", i_target_mba.toEcmdString()); - break; - case 6: - FAPI_DBG("%s:SUBTEST :RANDOM COMMAND SEQUENCE", i_target_mba.toEcmdString()); - break; - case 7: - FAPI_DBG("%s:SUBTEST :GOTO SUBTEST N OR REFRESH ONLY", i_target_mba.toEcmdString()); - break; - default: - FAPI_DBG("%s:Wrong Operation selected for Subtest", i_target_mba.toEcmdString()); - } - - switch (l_data_mode) - { - case 0: - FAPI_DBG("%s:DATA MODE :FIXED DATA", i_target_mba.toEcmdString()); - break; - case 1: - FAPI_DBG("%s:DATA MODE :DATA_RANDOM_FORWARD", i_target_mba.toEcmdString()); - break; - case 2: - FAPI_DBG("%s:DATA MODE :DATA_RANDOM_REVERSE", i_target_mba.toEcmdString()); - break; - case 3: - FAPI_DBG("%s:DATA MODE :RANDOM w/ECC FORWARD", i_target_mba.toEcmdString()); - break; - case 4: - FAPI_DBG("%s:DATA MODE :RANDOM w/ECC REVERSE", i_target_mba.toEcmdString()); - break; - case 5: - FAPI_DBG("%s:DATA MODE :DATA EQUAL ADDRESS", i_target_mba.toEcmdString()); - break; - case 6: - FAPI_DBG("%s:DATA MODE :DATA ROTATE LEFT", i_target_mba.toEcmdString()); - break; - case 7: - FAPI_DBG("%s:DATA MODE :DATA ROTATE RIGHT", i_target_mba.toEcmdString()); - break; - default: - FAPI_DBG("%s:Wrong Data Mode selected for Subtest", i_target_mba.toEcmdString()); - } - - switch (l_addr_mode) - { - case 0: - FAPI_DBG("%s:ADDRESS MODE :SEQUENTIAL FORWARD", i_target_mba.toEcmdString()); - break; - case 1: - FAPI_DBG("%s:ADDRESS MODE :SEQUENTIAL REVERSE", i_target_mba.toEcmdString()); - break; - case 2: - FAPI_DBG("%s:ADDRESS MODE :RANDOM FORWARD", i_target_mba.toEcmdString()); - break; - case 3: - FAPI_DBG("%s:ADDRESS MODE :RANDOM REVERSE", i_target_mba.toEcmdString()); - break; - default: - FAPI_DBG("%s:Wrong Address Mode selected for Subtest", i_target_mba.toEcmdString()); - } - - FAPI_DBG("%s:SUBTEST %d of %d done ", i_target_mba.toEcmdString(), - i_testnumber1, total_subtest_no); - - if (i_done == 1) - { - FAPI_DBG("%s:DONE BIT IS SET FOR CURRENT SUBTEST %d", - i_target_mba.toEcmdString(), i_testnumber1); - //FAPI_DBG("%s:DONE BIT IS SET FOR CURRENT SUBTEST %d",i_testnumber); - } - if ((l_data_mode == 0) || (l_data_mode == 6) || (l_data_mode == 7)|| (l_data_mode == 5)) - { - //FAPI_DBG("%s:fixed set and value of datamode is %d",l_data_mode); - l_sub_info[i_testnumber1].l_fixed_data_enable = 1; - } - else if ((l_data_mode == 1) || (l_data_mode == 2) || (l_data_mode == 3) || (l_data_mode == 4)) - { - l_sub_info[i_testnumber1].l_random_data_enable = 1; - //FAPI_DBG("%s:random set and value of datamode is %d",l_data_mode); - } - - if ((l_addr_mode == 0) || (l_addr_mode == 1)) - { - //FAPI_DBG("fixed addr and value of addrmode is %d",l_addr_mode); - l_sub_info[i_testnumber1].l_fixed_addr_enable = 1; - } - else if ((l_addr_mode == 2) || (l_addr_mode == 3)) - { - l_sub_info[i_testnumber1].l_random_addr_enable = 1; - //FAPI_DBG("random addr and value of addrmode is %d",l_addr_mode); - } - return rc; -} - -/*****************************************************************/ -// Funtion name : cfg_byte_mask -// Description : -// Input Parameters : It is used to mask bad bits read from SPD -// const fapi::Target & Centaur.mba -// uint8_t i_rank Current Rank -// uint8_t i_port Current Port -//****************************************************************/ - -fapi::ReturnCode cfg_byte_mask(const fapi::Target & i_target_mba) -{ - uint32_t rc_num; - uint8_t l_port = 0; - uint8_t l_dimm = 0; - uint8_t l_rank = 0; - uint8_t l_max_0 = 0; - uint8_t l_max_1 = 0; - fapi::ReturnCode rc; - uint8_t l_rnk = 0; - uint8_t num_ranks_per_dimm[2][2]; - uint8_t l_MAX_RANKS = 8; - uint8_t rank_pair = 0; - uint64_t l_var = 0xFFFFFFFFFFFFFFFFull; - uint16_t l_spare = 0xFFFF; - ecmdDataBufferBase l_data_buffer1_64(64); - Target i_target_centaur; - rc = fapiGetParentChip(i_target_mba, i_target_centaur); - if (rc) return rc; - uint8_t valid_rank[l_MAX_RANKS]; - rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target_mba, num_ranks_per_dimm); - if (rc) return rc; - uint8_t l_mbaPosition = 0; - uint8_t l_attr_eff_dimm_type_u8 = 0; - rc = FAPI_ATTR_GET(ATTR_EFF_CUSTOM_DIMM, &i_target_mba, l_attr_eff_dimm_type_u8); - if (rc) return rc; - rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target_mba, l_mbaPosition); - if (rc) return rc; - - for (l_port = 0; l_port < 2; l_port++) - { - l_MAX_RANKS = num_ranks_per_dimm[l_port][0] + num_ranks_per_dimm[l_port][1]; - rc = mss_getrankpair(i_target_mba, l_port, 0, &rank_pair, valid_rank); - if (rc) return rc; - - for (l_rank = 0; l_rank < l_MAX_RANKS; l_rank++) - { - l_rnk = valid_rank[l_rank]; - if (l_rnk == 255) - { - continue; - } - - ecmdDataBufferBase l_data_buffer2_64(64); - ecmdDataBufferBase l_data_buffer3_64(64); - ecmdDataBufferBase l_data_buffer4_64(64); - ecmdDataBufferBase l_data_buffer5_64(64); - - l_max_0 = num_ranks_per_dimm[0][0] + num_ranks_per_dimm[0][1]; - l_max_1 = num_ranks_per_dimm[1][0] + num_ranks_per_dimm[1][1]; - - rc_num = l_data_buffer3_64.flushTo0(); - if (rc_num) - { - FAPI_ERR("Error in function cfg_byte_mask:"); - rc.setEcmdError(rc_num); - return rc; - } - - uint8_t l_dqBitmap[DIMM_DQ_RANK_BITMAP_SIZE]; - uint8_t l_dq[8] = { 0 }; - uint8_t l_sp[2] = { 0 }; - uint16_t l_index0 = 0; - uint8_t l_index_sp = 0; - uint16_t l_sp_isdimm = 0xff; - - FAPI_DBG("%s:Function cfg_byte_mask", i_target_mba.toEcmdString()); - if (l_rnk > 3) - { - l_dimm = 1; - l_rnk = l_rnk - 4; - } - else - { - l_dimm = 0; - } - rc = dimmGetBadDqBitmap(i_target_mba, l_port, l_dimm, l_rnk, l_dqBitmap); - if (rc) return rc; - - for (l_index0 = 0; l_index0 < DIMM_DQ_RANK_BITMAP_SIZE; l_index0++) - { - if (l_index0 < 8) - { - l_dq[l_index0] = l_dqBitmap[l_index0]; - if (l_dqBitmap[l_index0]) - { - FAPI_DBG("%s:\n the port=%d bad dq=%x on dq=%d", - i_target_mba.toEcmdString(), l_port, - l_dqBitmap[l_index0], l_index0); - } - } - else - { - if (l_dqBitmap[l_index0]) - { - FAPI_DBG("%s:\n the port=%d bad dq=%x on dq=%d", - i_target_mba.toEcmdString(), l_port, - l_dqBitmap[l_index0], l_index0); - } - l_sp[l_index_sp] = l_dqBitmap[l_index0]; - l_index_sp++; - } - } - - rc_num = l_data_buffer1_64.insertFromRight(l_dq, 0, 64); - if (rc_num) - { - FAPI_ERR("Error in function cfg_byte_mask:"); - rc.setEcmdError(rc_num); - return rc; - } - - if (l_mbaPosition == 0) - { - if (l_port == 0) - { - if(l_attr_eff_dimm_type_u8 != fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES) - { - rc_num = l_data_buffer2_64.insertFromRight(l_sp_isdimm, 8, 8); - if (rc_num) - { - FAPI_ERR("Error in function cfg_byte_mask:"); - rc.setEcmdError(rc_num); - return rc; - } - rc_num = l_data_buffer2_64.insertFromRight(l_sp, 0, 8); - if (rc_num) - { - FAPI_ERR("Error in function cfg_byte_mask:"); - rc.setEcmdError(rc_num); - return rc; - } - } - else - { - rc_num = l_data_buffer2_64.insertFromRight(l_sp, 0, 16); - if (rc_num) - { - FAPI_ERR("Error in function cfg_byte_mask:"); - rc.setEcmdError(rc_num); - return rc; - } - } - rc = fapiGetScom(i_target_centaur, MBS_MCBIST01_MCBCMA1Q_0x02011672, l_data_buffer4_64); - if (rc) return rc; - rc_num = l_data_buffer1_64.setOr(l_data_buffer4_64, 0, 64); - if (rc_num) - { - FAPI_ERR("Error in function cfg_byte_mask:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MCBCMA1Q_0x02011672, l_data_buffer1_64); - if (rc) return rc; - rc = fapiGetScom(i_target_centaur, MBS_MCBIST01_MCBCMABQ_0x02011674, l_data_buffer5_64); - if (rc) return rc; - rc_num = l_data_buffer2_64.setOr(l_data_buffer5_64, 0, 64); - if (rc_num) - { - FAPI_ERR("Error in function cfg_byte_mask:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MCBCMABQ_0x02011674, l_data_buffer2_64); - if (rc) return rc; - } - else - { - rc = fapiGetScom(i_target_centaur, MBS_MCBIST01_MCBCMABQ_0x02011674, l_data_buffer2_64); - if (rc) return rc; - if(l_attr_eff_dimm_type_u8 != fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES) - { - rc_num = l_data_buffer2_64.insertFromRight(l_sp_isdimm, 24, 8); - rc_num |= l_data_buffer2_64.insertFromRight(l_sp, 16, 8); - if (rc_num) - { - FAPI_ERR("Error in function cfg_byte_mask:"); - rc.setEcmdError(rc_num); - return rc; - } - } - else - { - rc_num = l_data_buffer2_64.insertFromRight(l_sp, 16, 16); - if (rc_num) - { - FAPI_ERR("Error in function cfg_byte_mask:"); - rc.setEcmdError(rc_num); - return rc; - } - } - rc = fapiGetScom(i_target_centaur, MBS_MCBIST01_MCBCMB1Q_0x02011673, l_data_buffer4_64); - if (rc) return rc; - rc_num = l_data_buffer1_64.setOr(l_data_buffer4_64, 0, 64); - if (rc_num) - { - FAPI_ERR("Error in function cfg_byte_mask:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MCBCMB1Q_0x02011673, l_data_buffer1_64); - if (rc) return rc; - rc = fapiGetScom(i_target_centaur, MBS_MCBIST01_MCBCMABQ_0x02011674, l_data_buffer5_64); - if (rc) return rc; - rc_num = l_data_buffer2_64.setOr(l_data_buffer5_64, 0, 64); - if (rc_num) - { - FAPI_ERR("Error in function cfg_byte_mask:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MCBCMABQ_0x02011674, l_data_buffer2_64); - if (rc) return rc; - } - } - else - { - if (l_port == 0) - { - if(l_attr_eff_dimm_type_u8 != fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES) - { - rc_num = l_data_buffer2_64.insertFromRight(l_sp_isdimm, 8, 8); - rc_num |= l_data_buffer2_64.insertFromRight(l_sp, 0, 8); - if (rc_num) - { - FAPI_ERR("Error in function cfg_byte_mask:"); - rc.setEcmdError(rc_num); - return rc; - } - } - else - { - rc_num = l_data_buffer2_64.insertFromRight(l_sp, 0, 16); - if (rc_num) - { - FAPI_ERR("Error in function cfg_byte_mask:"); - rc.setEcmdError(rc_num); - return rc; - } - } - rc = fapiGetScom(i_target_centaur, 0x02011772, l_data_buffer4_64); - if (rc) return rc; - rc_num = l_data_buffer1_64.setOr(l_data_buffer4_64, 0, 64); - if (rc_num) - { - FAPI_ERR("Error in function cfg_byte_mask:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_centaur, 0x02011772, l_data_buffer1_64); - if (rc) return rc; - rc = fapiGetScom(i_target_centaur, 0x02011774, l_data_buffer5_64); - if (rc) return rc; - rc_num = l_data_buffer2_64.setOr(l_data_buffer5_64, 0, 64); - if (rc_num) - { - FAPI_ERR("Error in function cfg_byte_mask:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_centaur, 0x02011774, l_data_buffer2_64); - if (rc) return rc; - } - else - { - rc = fapiGetScom(i_target_centaur, 0x02011774, l_data_buffer2_64); - if (rc) return rc; - if(l_attr_eff_dimm_type_u8 != fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES) - { - rc_num = l_data_buffer2_64.insertFromRight(l_sp_isdimm, 24, 8); - rc_num |= l_data_buffer2_64.insertFromRight(l_sp, 16, 8); - if (rc_num) - { - FAPI_ERR("Error in function cfg_byte_mask:"); - rc.setEcmdError(rc_num); - return rc; - } - } - else - { - rc_num = l_data_buffer2_64.insertFromRight(l_sp, 16, 16); - if (rc_num) - { - FAPI_ERR("Error in function cfg_byte_mask:"); - rc.setEcmdError(rc_num); - return rc; - } - } - - rc = fapiGetScom(i_target_centaur, 0x02011773, l_data_buffer4_64); - if (rc) return rc; - rc_num = l_data_buffer1_64.setOr(l_data_buffer4_64, 0, 64); - if (rc_num) - { - FAPI_ERR("Error in function cfg_byte_mask:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_centaur, 0x02011773, - l_data_buffer1_64); - if (rc) return rc; - rc = fapiGetScom(i_target_centaur, 0x02011774, l_data_buffer5_64); - if (rc) return rc; - rc_num = l_data_buffer2_64.setOr(l_data_buffer5_64, 0, 64); - if (rc_num) - { - FAPI_ERR("Error in function cfg_byte_mask:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_centaur, 0x02011774, l_data_buffer2_64); - if (rc) return rc; - } - } - } - } - - if (l_max_0 == 0) - { - if (l_mbaPosition == 0) - { - rc = fapiGetScom(i_target_centaur, MBS_MCBIST01_MCBCMA1Q_0x02011672, l_data_buffer1_64); - if (rc) return rc; - rc_num = l_data_buffer1_64.setDoubleWord(0, l_var); - if (rc_num) - { - FAPI_ERR("Error in function cfg_byte_mask:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MCBCMA1Q_0x02011672, l_data_buffer1_64); - if (rc) return rc; - rc = fapiGetScom(i_target_centaur, MBS_MCBIST01_MCBCMABQ_0x02011674, l_data_buffer1_64); - if (rc) return rc; - rc_num = l_data_buffer1_64.insertFromRight(l_spare, 0, 16); - if (rc_num) - { - FAPI_ERR("Error in function cfg_byte_mask:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MCBCMABQ_0x02011674, l_data_buffer1_64); - if (rc) return rc; - } - else - { - rc = fapiGetScom(i_target_centaur, 0x02011772, l_data_buffer1_64); - if (rc) return rc; - rc_num = l_data_buffer1_64.setDoubleWord(0, l_var); - if (rc_num) - { - FAPI_ERR("Error in function cfg_byte_mask:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_centaur, 0x02011772, l_data_buffer1_64); - if (rc) return rc; - rc = fapiGetScom(i_target_centaur, 0x02011774, l_data_buffer1_64); - if (rc) return rc; - rc_num = l_data_buffer1_64.insertFromRight(l_spare, 0, 16); - if (rc_num) - { - FAPI_ERR("Error in function cfg_byte_mask:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_centaur, 0x02011774, l_data_buffer1_64); - if (rc) return rc; - } - } - - if (l_max_1 == 0) - { - if (l_mbaPosition == 0) - { - rc = fapiGetScom(i_target_centaur, MBS_MCBIST01_MCBCMB1Q_0x02011673, l_data_buffer1_64); - if (rc) return rc; - rc_num = l_data_buffer1_64.setDoubleWord(0, l_var); - if (rc_num) - { - FAPI_ERR("Error in function cfg_byte_mask:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MCBCMB1Q_0x02011673, l_data_buffer1_64); - if (rc) return rc; - rc = fapiGetScom(i_target_centaur, MBS_MCBIST01_MCBCMABQ_0x02011674, l_data_buffer1_64); - if (rc) return rc; - rc_num = l_data_buffer1_64.insertFromRight(l_spare, 16, 16); - if (rc_num) - { - FAPI_ERR("Error in function cfg_byte_mask:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MCBCMABQ_0x02011674, l_data_buffer1_64); - if (rc) return rc; - } - else - { - rc = fapiGetScom(i_target_centaur, 0x02011773, l_data_buffer1_64); - if (rc) return rc; - rc_num = l_data_buffer1_64.setDoubleWord(0, l_var); - if (rc_num) - { - FAPI_ERR("Error in function cfg_byte_mask:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_centaur, 0x02011773, l_data_buffer1_64); - if (rc) return rc; - rc = fapiGetScom(i_target_centaur, 0x02011774, l_data_buffer1_64); - if (rc) return rc; - rc_num = l_data_buffer1_64.insertFromRight(l_spare, 16, 16); - if (rc_num) - { - FAPI_ERR("Error in function cfg_byte_mask:"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_centaur, 0x02011774, l_data_buffer1_64); - if (rc) return rc; - } - } - - return rc; -} - -fapi::ReturnCode mss_conversion_testtype(const fapi::Target & i_target_mba, - uint8_t l_pattern, - mcbist_test_mem &i_mcbtest) -{ - ReturnCode rc; - - FAPI_INF("%s:value of testtype is %d", i_target_mba.toEcmdString(), l_pattern); - switch (l_pattern) - { - case 0: - i_mcbtest = USER_MODE; - FAPI_INF("%s:TESTTYPE :USER_MODE", i_target_mba.toEcmdString()); - break; - case 1: - i_mcbtest = CENSHMOO; - FAPI_INF("%s:TESTTYPE :CENSHMOO", i_target_mba.toEcmdString()); - break; - case 2: - i_mcbtest = SUREFAIL; - FAPI_INF("%s:TESTTYPE :SUREFAIL", i_target_mba.toEcmdString()); - break; - case 3: - i_mcbtest = MEMWRITE; - FAPI_INF("%s:TESTTYPE :MEMWRITE", i_target_mba.toEcmdString()); - break; - case 4: - i_mcbtest = MEMREAD; - FAPI_INF("%s:TESTTYPE :MEMREAD", i_target_mba.toEcmdString()); - break; - case 5: - i_mcbtest = CBR_REFRESH; - FAPI_INF("%s:TESTTYPE :CBR_REFRESH", i_target_mba.toEcmdString()); - break; - case 6: - i_mcbtest = MCBIST_SHORT; - FAPI_INF("%s:TESTTYPE :MCBIST_SHORT", i_target_mba.toEcmdString()); - break; - case 7: - i_mcbtest = SHORT_SEQ; - FAPI_INF("%s:TESTTYPE :SHORT_SEQ", i_target_mba.toEcmdString()); - break; - case 8: - i_mcbtest = DELTA_I; - FAPI_INF("%s:TESTTYPE :DELTA_I", i_target_mba.toEcmdString()); - break; - case 9: - i_mcbtest = DELTA_I_LOOP; - FAPI_INF("%s:TESTTYPE :DELTA_I_LOOP", i_target_mba.toEcmdString()); - break; - case 10: - i_mcbtest = SHORT_RAND; - FAPI_INF("%s:TESTTYPE :SHORT_RAND", i_target_mba.toEcmdString()); - break; - case 11: - i_mcbtest = LONG1; - FAPI_INF("%s:TESTTYPE :LONG1", i_target_mba.toEcmdString()); - break; - case 12: - i_mcbtest = BUS_TAT; - FAPI_INF("%s:TESTTYPE :BUS_TAT", i_target_mba.toEcmdString()); - break; - case 13: - i_mcbtest = SIMPLE_FIX; - FAPI_INF("%s:TESTTYPE :SIMPLE_FIX", i_target_mba.toEcmdString()); - break; - case 14: - i_mcbtest = SIMPLE_RAND; - FAPI_INF("%s:TESTTYPE :SIMPLE_RAND", i_target_mba.toEcmdString()); - break; - case 15: - i_mcbtest = SIMPLE_RAND_2W; - FAPI_INF("%s:TESTTYPE :SIMPLE_RAND_2W", i_target_mba.toEcmdString()); - break; - case 16: - i_mcbtest = SIMPLE_RAND_FIXD; - FAPI_INF("%s:TESTTYPE :SIMPLE_RAND_FIXD", i_target_mba.toEcmdString()); - break; - case 17: - i_mcbtest = SIMPLE_RA_RD_WR; - FAPI_INF("%s:TESTTYPE :SIMPLE_RA_RD_WR", i_target_mba.toEcmdString()); - break; - case 18: - i_mcbtest = SIMPLE_RA_RD_R; - FAPI_INF("%s:TESTTYPE :SIMPLE_RA_RD_R", i_target_mba.toEcmdString()); - break; - case 19: - i_mcbtest = SIMPLE_RA_FD_R; - FAPI_INF("%s:TESTTYPE :SIMPLE_RA_FD_R", i_target_mba.toEcmdString()); - break; - case 20: - i_mcbtest = SIMPLE_RA_FD_R_INF; - FAPI_INF("%s:TESTTYPE :SIMPLE_RA_FD_R_INF", i_target_mba.toEcmdString()); - break; - case 21: - i_mcbtest = SIMPLE_SA_FD_R; - FAPI_INF("%s:TESTTYPE :SIMPLE_SA_FD_R", i_target_mba.toEcmdString()); - break; - case 22: - i_mcbtest = SIMPLE_RA_FD_W; - FAPI_INF("%s:TESTTYPE :SIMPLE_RA_FD_W", i_target_mba.toEcmdString()); - break; - case 23: - i_mcbtest = INFINITE; - FAPI_INF("%s:TESTTYPE :INFINITE", i_target_mba.toEcmdString()); - break; - case 24: - i_mcbtest = WR_ONLY; - FAPI_INF("%s:TESTTYPE :WR_ONLY", i_target_mba.toEcmdString()); - break; - case 25: - i_mcbtest = W_ONLY; - FAPI_INF("%s:TESTTYPE :W_ONLY", i_target_mba.toEcmdString()); - break; - case 26: - i_mcbtest = R_ONLY; - FAPI_INF("%s:TESTTYPE :R_ONLY", i_target_mba.toEcmdString()); - break; - case 27: - i_mcbtest = W_ONLY_RAND; - FAPI_INF("%s:TESTTYPE :W_ONLY_RAND", i_target_mba.toEcmdString()); - break; - case 28: - i_mcbtest = R_ONLY_RAND; - FAPI_INF("%s:TESTTYPE :R_ONLY_RAND", i_target_mba.toEcmdString()); - break; - case 29: - i_mcbtest = R_ONLY_MULTI; - FAPI_INF("%s:TESTTYPE :R_ONLY_MULTI", i_target_mba.toEcmdString()); - break; - case 30: - i_mcbtest = SHORT; - FAPI_INF("%s:TESTTYPE :SHORT", i_target_mba.toEcmdString()); - break; - case 31: - i_mcbtest = SIMPLE_RAND_BARI; - FAPI_INF("%s:TESTTYPE :SIMPLE_RAND_BARI", i_target_mba.toEcmdString()); - break; - case 32: - i_mcbtest = W_R_INFINITE; - FAPI_INF("%s:TESTTYPE :W_R_INFINITE", i_target_mba.toEcmdString()); - break; - case 33: - i_mcbtest = W_R_RAND_INFINITE; - FAPI_INF("%s:TESTTYPE :W_R_RAND_INFINITE", i_target_mba.toEcmdString()); - break; - case 34: - i_mcbtest = R_INFINITE1; - FAPI_INF("%s:TESTTYPE :R_INFINITE1", i_target_mba.toEcmdString()); - break; - case 35: - i_mcbtest = R_INFINITE_RF; - FAPI_INF("%s:TESTTYPE :R_INFINITE_RF", i_target_mba.toEcmdString()); - break; - case 36: - i_mcbtest = MARCH; - FAPI_INF("%s:TESTTYPE :MARCH", i_target_mba.toEcmdString()); - break; - case 37: - i_mcbtest = SIMPLE_FIX_RF; - FAPI_INF("%s:TESTTYPE :SIMPLE_FIX_RF", i_target_mba.toEcmdString()); - break; - case 38: - i_mcbtest = SHMOO_STRESS; - FAPI_INF("%s:TESTTYPE :SHMOO_STRESS", i_target_mba.toEcmdString()); - break; - case 39: - i_mcbtest = SIMPLE_RAND_RA; - FAPI_INF("%s:TESTTYPE :SIMPLE_RAND_RA", i_target_mba.toEcmdString()); - break; - case 40: - i_mcbtest = SIMPLE_FIX_RA; - FAPI_INF("%s:TESTTYPE :SIMPLE_FIX_RA", i_target_mba.toEcmdString()); - break; - case 41: - i_mcbtest = SIMPLE_FIX_RF_RA; - FAPI_INF("%s:TESTTYPE :SIMPLE_FIX_RF_RA", i_target_mba.toEcmdString()); - break; - case 42: - i_mcbtest = TEST_RR; - FAPI_INF("%s:TESTTYPE :TEST_RR", i_target_mba.toEcmdString()); - break; - case 43: - i_mcbtest = TEST_RF; - FAPI_INF("%s:TESTTYPE :TEST_RF", i_target_mba.toEcmdString()); - break; - case 44: - i_mcbtest = W_ONLY_INFINITE_RAND; - FAPI_INF("%s:TESTTYPE :W_ONLY_INFINITE_RAND", i_target_mba.toEcmdString()); - break; - case 45: - i_mcbtest = MCB_2D_CUP_SEQ; - FAPI_INF("%s:TESTTYPE :MCB_2D_CUP_SEQ", i_target_mba.toEcmdString()); - break; - case 46: - i_mcbtest = MCB_2D_CUP_RAND; - FAPI_INF("%s:TESTTYPE :MCB_2D_CUP_RAND", i_target_mba.toEcmdString()); - break; - case 47: - i_mcbtest = SHMOO_STRESS_INFINITE; - FAPI_INF("%s:TESTTYPE :SHMOO_STRESS_INFINITE", i_target_mba.toEcmdString()); - break; - case 48: - i_mcbtest = HYNIX_1_COL; - FAPI_INF("%s:TESTTYPE :HYNIX_1_COL", i_target_mba.toEcmdString()); - break; - case 49: - i_mcbtest = RMWFIX; - FAPI_INF("%s:TESTTYPE :RMWFIX", i_target_mba.toEcmdString()); - break; - case 50: - i_mcbtest = RMWFIX_I; - FAPI_INF("%s:TESTTYPE :RMWFIX_I", i_target_mba.toEcmdString()); - break; - case 51: - i_mcbtest = W_INFINITE; - FAPI_INF("%s:TESTTYPE :W_INFINITE", i_target_mba.toEcmdString()); - break; - case 52: - i_mcbtest = R_INFINITE; - FAPI_INF("%s:TESTTYPE :R_INFINITE", i_target_mba.toEcmdString()); - break; - - - default: - FAPI_INF("%s:Wrong Test_type,so using default test_type", - i_target_mba.toEcmdString()); - } - - return rc; -} - -fapi::ReturnCode mss_conversion_data(const fapi::Target & i_target_mba, - uint8_t l_pattern, - mcbist_data_gen &i_mcbpatt) -{ - ReturnCode rc; - FAPI_INF("%s:value of pattern is %d", i_target_mba.toEcmdString(), l_pattern); - switch (l_pattern) - { - case 0: - i_mcbpatt = ABLE_FIVE; - FAPI_INF("%s:PATTERN :ABLE_FIVE", i_target_mba.toEcmdString()); - break; - case 1: - i_mcbpatt = USR_MODE; - FAPI_INF("%s:PATTERN :USER_MODE", i_target_mba.toEcmdString()); - break; - case 2: - i_mcbpatt = ONEHOT; - FAPI_INF("%s:PATTERN :ONEHOT", i_target_mba.toEcmdString()); - break; - case 3: - i_mcbpatt = DQ0_00011111_RESTALLONE; - FAPI_INF("%s:PATTERN :DQ0_00011111_RESTALLONE", i_target_mba.toEcmdString()); - break; - case 4: - i_mcbpatt = DQ0_11100000_RESTALLZERO; - FAPI_INF("%s:PATTERN :DQ0_11100000_RESTALLZERO", i_target_mba.toEcmdString()); - break; - case 5: - i_mcbpatt = ALLZERO; - FAPI_INF("%s:PATTERN :ALLZERO", i_target_mba.toEcmdString()); - break; - case 6: - i_mcbpatt = ALLONE; - FAPI_INF("%s:PATTERN :ALLONE", i_target_mba.toEcmdString()); - break; - case 7: - i_mcbpatt = BYTE_BURST_SIGNATURE; - FAPI_INF("%s:PATTERN :BYTE_BURST_SIGNATURE", i_target_mba.toEcmdString()); - break; - case 8: - i_mcbpatt = BYTE_BURST_SIGNATURE_V1; - FAPI_INF("%s:PATTERN :BYTE_BURST_SIGNATURE_V1", i_target_mba.toEcmdString()); - break; - case 9: - i_mcbpatt = BYTE_BURST_SIGNATURE_V2; - FAPI_INF("%s:PATTERN :BYTE_BURST_SIGNATURE_V2", i_target_mba.toEcmdString()); - break; - case 10: - i_mcbpatt = BYTE_BURST_SIGNATURE_V3; - FAPI_INF("%s:PATTERN :BYTE_BURST_SIGNATURE_V3", i_target_mba.toEcmdString()); - break; - case 11: - i_mcbpatt = DATA_GEN_DELTA_I; - FAPI_INF("%s:PATTERN :DATA_GEN_DELTA_I", i_target_mba.toEcmdString()); - break; - case 12: - i_mcbpatt = MCBIST_2D_CUP_PAT0; - FAPI_INF("%s:PATTERN :MCBIST_2D_CUP_PAT0", i_target_mba.toEcmdString()); - break; - case 13: - i_mcbpatt = MPR; - FAPI_INF("%s:PATTERN :MPR", i_target_mba.toEcmdString()); - break; - case 14: - i_mcbpatt = MPR03; - FAPI_INF("%s:PATTERN :MPR03", i_target_mba.toEcmdString()); - break; - case 15: - i_mcbpatt = MPR25; - FAPI_INF("%s:PATTERN :MPR25", i_target_mba.toEcmdString()); - break; - case 16: - i_mcbpatt = MPR47; - FAPI_INF("%s:PATTERN :MPR47", i_target_mba.toEcmdString()); - break; - case 17: - i_mcbpatt = DELTA_I1; - FAPI_INF("%s:PATTERN :DELTA_I1", i_target_mba.toEcmdString()); - break; - case 18: - i_mcbpatt = MCBIST_2D_CUP_PAT1; - FAPI_INF("%s:PATTERN :MCBIST_2D_CUP_PAT1", i_target_mba.toEcmdString()); - break; - case 19: - i_mcbpatt = MHC_55; - FAPI_INF("%s:PATTERN :MHC_55", i_target_mba.toEcmdString()); - break; - case 20: - i_mcbpatt = MHC_DQ_SIM; - FAPI_INF("%s:PATTERN :MHC_DQ_SIM", i_target_mba.toEcmdString()); - break; - case 21: - i_mcbpatt = MCBIST_2D_CUP_PAT2; - FAPI_INF("%s:PATTERN :MCBIST_2D_CUP_PAT2", i_target_mba.toEcmdString()); - break; - case 22: - i_mcbpatt = MCBIST_2D_CUP_PAT3; - FAPI_INF("%s:PATTERN :MCBIST_2D_CUP_PAT3", i_target_mba.toEcmdString()); - break; - case 23: - i_mcbpatt = MCBIST_2D_CUP_PAT4; - FAPI_INF("%s:PATTERN :MCBIST_2D_CUP_PAT4", i_target_mba.toEcmdString()); - break; - case 24: - i_mcbpatt = MCBIST_2D_CUP_PAT5; - FAPI_INF("%s:PATTERN :MCBIST_2D_CUP_PAT5", i_target_mba.toEcmdString()); - break; - case 25: - i_mcbpatt = MCBIST_2D_CUP_PAT6; - FAPI_INF("%s:PATTERN :MCBIST_2D_CUP_PAT6", i_target_mba.toEcmdString()); - break; - case 26: - i_mcbpatt = MCBIST_2D_CUP_PAT7; - FAPI_INF("%s:PATTERN :MCBIST_2D_CUP_PAT7", i_target_mba.toEcmdString()); - break; - case 27: - i_mcbpatt = MCBIST_2D_CUP_PAT8; - FAPI_INF("%s:PATTERN :MCBIST_2D_CUP_PAT8", i_target_mba.toEcmdString()); - break; - case 28: - i_mcbpatt = MCBIST_2D_CUP_PAT9; - FAPI_INF("%s:PATTERN :MCBIST_2D_CUP_PAT9", i_target_mba.toEcmdString()); - break; - case 29: - i_mcbpatt = CWLPATTERN; - FAPI_INF("%s:PATTERN :CWLPATTERN", i_target_mba.toEcmdString()); - break; - case 30: - i_mcbpatt = GREY1; - FAPI_INF("%s:PATTERN :GREY1", i_target_mba.toEcmdString()); - break; - case 31: - i_mcbpatt = DC_ONECHANGE; - FAPI_INF("%s:PATTERN :DC_ONECHANGE", i_target_mba.toEcmdString()); - break; - case 32: - i_mcbpatt = DC_ONECHANGEDIAG; - FAPI_INF("%s:PATTERN :DC_ONECHANGEDIAG", i_target_mba.toEcmdString()); - break; - case 33: - i_mcbpatt = GREY2; - FAPI_INF("%s:PATTERN :GREY2", i_target_mba.toEcmdString()); - break; - case 34: - i_mcbpatt = FIRST_XFER; - FAPI_INF("%s:PATTERN :FIRST_XFER", i_target_mba.toEcmdString()); - break; - case 35: - i_mcbpatt = MCBIST_222_XFER; - FAPI_INF("%s:PATTERN :MCBIST_222_XFER", i_target_mba.toEcmdString()); - break; - case 36: - i_mcbpatt = MCBIST_333_XFER; - FAPI_INF("%s:PATTERN :MCBIST_333_XFER", i_target_mba.toEcmdString()); - break; - case 37: - i_mcbpatt = MCBIST_444_XFER; - FAPI_INF("%s:PATTERN :MCBIST_444_XFER", i_target_mba.toEcmdString()); - break; - case 38: - i_mcbpatt = MCBIST_555_XFER; - FAPI_INF("%s:PATTERN :MCBIST_555_XFER", i_target_mba.toEcmdString()); - break; - case 39: - i_mcbpatt = MCBIST_666_XFER; - FAPI_INF("%s:PATTERN :MCBIST_666_XFER", i_target_mba.toEcmdString()); - break; - case 40: - i_mcbpatt = MCBIST_777_XFER; - FAPI_INF("%s:PATTERN :MCBIST_777_XFER", i_target_mba.toEcmdString()); - break; - case 41: - i_mcbpatt = MCBIST_888_XFER; - FAPI_INF("%s:PATTERN :MCBIST_888_XFER", i_target_mba.toEcmdString()); - break; - case 42: - i_mcbpatt = FIRST_XFER_X4MODE; - FAPI_INF("%s:PATTERN :FIRST_XFER_X4MODE", i_target_mba.toEcmdString()); - break; - case 43: - i_mcbpatt = MCBIST_LONG; - FAPI_INF("%s:PATTERN :MCBIST_LONG", i_target_mba.toEcmdString()); - break; - case 44: - i_mcbpatt = PSEUDORANDOM; - FAPI_INF("%s:PATTERN :PSEUDORANDOM", i_target_mba.toEcmdString()); - break; - case 45: - i_mcbpatt = CASTLE; - FAPI_INF("%s:PATTERN :CASTLE", i_target_mba.toEcmdString()); - break; - default: - FAPI_INF("%s:Wrong Data Pattern,so using default pattern", - i_target_mba.toEcmdString()); - } - - return rc; -} - -} - diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mrs6_DDR4.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mrs6_DDR4.C deleted file mode 100644 index 36892a768..000000000 --- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mrs6_DDR4.C +++ /dev/null @@ -1,626 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mrs6_DDR4.C $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2015 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: mss_mrs6_DDR4.C,v 1.6 2015/09/04 02:03:31 kmack Exp $ - - -//------------------------------------------------------------------------------ -// *! (C) Copyright International Business Machines Corp. 2007 -// *! All Rights Reserved -- Property of IBM - -//------------------------------------------------------------------------------ -// Don't forget to create CVS comments when you check in your changes! -//------------------------------------------------------------------------------ -// CHANGE HISTORY: -//------------------------------------------------------------------------------ -// Version:| Author: | Date: | Comment: -//---------|----------|---------|----------------------------------------------- -// 1.05 | 09/03/15 | kmack | RC updates -// 1.04 | 08/05/15 | sglancy | Fixed FW compile error -// 1.03 | 08/04/15 | sglancy | Changed to address FW comments -// 1.02 | 05/07/15 | sglancy | Fixed enable disable bug and added 3DS support -// 1.00 | 06/27/14 | abhijsau | Initial Draft - -//---------------------------------------------------------------------- -// Includes -//---------------------------------------------------------------------- - -#include <fapi.H> -#include <mss_funcs.H> -#include <cen_scom_addresses.H> -#include <mss_mrs6_DDR4.H> -using namespace fapi; - -extern "C" -{ - -// loads and runs MRS6 commands on a given MBA -ReturnCode mss_mrs6_DDR4( fapi::Target& i_target) -{ -ReturnCode rc; -uint32_t port_number; -uint32_t ccs_inst_cnt=0; - -for ( port_number = 0; port_number < 2; port_number++) - { - // Step four: Load MRS Setting - FAPI_INF("Loading MRS6 for port %d",port_number); - rc = mss_mr6_loader(i_target, port_number, ccs_inst_cnt); - if(rc) - { - FAPI_ERR(" mrs_load Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator()); - return rc; - } - - } - -// Execute the contents of CCS array - if (ccs_inst_cnt > 0) - { - // Set the End bit on the last CCS Instruction - rc = mss_ccs_set_end_bit( i_target, ccs_inst_cnt-1); - if(rc) - { - FAPI_ERR("CCS_SET_END_BIT FAILED rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator()); - return rc; - } - - rc = mss_execute_ccs_inst_array(i_target, 10, 10); - if(rc) - { - FAPI_ERR(" EXECUTE_CCS_INST_ARRAY FAILED rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator()); - return rc; - } - - ccs_inst_cnt = 0; - } - - return rc; - -} - -//Adds a NOP to CCS -fapi::ReturnCode add_nop_to_ccs(fapi::Target& i_target_mba, ecmdDataBufferBase &addr_16, uint32_t instruction_number,uint8_t rank,uint8_t bank,uint32_t delay,uint8_t port) { - fapi::ReturnCode l_rc = fapi::FAPI_RC_SUCCESS; - fapi::ReturnCode l_rc_buff = fapi::FAPI_RC_SUCCESS; - uint32_t l_ecmd_rc = 0; - - //CCS Array 0 buffers - ecmdDataBufferBase bank_3(3); - ecmdDataBufferBase ddr4_activate_1(1); - ecmdDataBufferBase rasn_1(1); - ecmdDataBufferBase casn_1(1); - ecmdDataBufferBase wen_1(1); - ecmdDataBufferBase cke_4(4); - ecmdDataBufferBase csn_8(8); - ecmdDataBufferBase odt_4(4); - ecmdDataBufferBase cal_type_4(4); - - //CCS Array 1 buffers - ecmdDataBufferBase idles_16(16); - ecmdDataBufferBase repeat_16(16); - ecmdDataBufferBase pattern_20(20); - ecmdDataBufferBase read_compare_1(1); - ecmdDataBufferBase rank_cal_4(4); - ecmdDataBufferBase cal_enable_1(1); - ecmdDataBufferBase ccs_end_1(1); - FAPI_INF("\n Running NO -OP command"); - - //CCS Array 0 Setup - - //Buffer conversions from inputs - l_ecmd_rc |= addr_16.reverse(); - l_ecmd_rc |= bank_3.insertFromRight(bank, 0, 3); - l_ecmd_rc |= bank_3.reverse(); //Banks are 0:2 - l_ecmd_rc |= csn_8.flushTo1(); - l_ecmd_rc |= csn_8.clearBit(rank); - - //Command structure setup - l_ecmd_rc |= cke_4.flushTo1(); - l_ecmd_rc |= rasn_1.setBit(0); - l_ecmd_rc |= casn_1.setBit(0); - l_ecmd_rc |= wen_1.setBit(0); - - l_ecmd_rc |= read_compare_1.clearBit(0); - - //Final setup - l_ecmd_rc |= odt_4.flushTo0(); - l_ecmd_rc |= cal_type_4.flushTo0(); - l_ecmd_rc |= ddr4_activate_1.setBit(0); - - if (l_ecmd_rc) { - FAPI_ERR( "add_activate_to_ccs: Error setting up buffers"); - l_rc_buff.setEcmdError(l_ecmd_rc); - return l_rc_buff; - } - - l_rc = mss_ccs_inst_arry_0(i_target_mba, instruction_number, addr_16, bank_3, ddr4_activate_1, rasn_1, casn_1, wen_1, cke_4, csn_8, odt_4, cal_type_4, port); - if (l_rc) return l_rc; - - - //CCS Array 1 Setup - l_ecmd_rc |= idles_16.insertFromRight(delay, 0, 16); - l_ecmd_rc |= repeat_16.flushTo0(); - l_ecmd_rc |= pattern_20.flushTo0(); - l_ecmd_rc |= read_compare_1.flushTo0(); - l_ecmd_rc |= rank_cal_4.flushTo0(); - l_ecmd_rc |= cal_enable_1.flushTo0(); - l_ecmd_rc |= ccs_end_1.flushTo0(); - - if (l_ecmd_rc) { - FAPI_ERR( "add_activate_to_ccs: Error setting up buffers"); - l_rc_buff.setEcmdError(l_ecmd_rc); - return l_rc_buff; - } - - l_rc = mss_ccs_inst_arry_1(i_target_mba, instruction_number, idles_16, repeat_16, pattern_20, read_compare_1, rank_cal_4, cal_enable_1, ccs_end_1); - if (l_rc) return l_rc; - - return l_rc; -} - -//Loads MRS6 commands for a given port into the CCS array -ReturnCode mss_mr6_loader( fapi::Target& i_target,uint32_t i_port_number,uint32_t& io_ccs_inst_cnt) -{ - - const uint8_t MRS6_BA = 6; - uint32_t dimm_number; - uint32_t rank_number; - ReturnCode rc; - ReturnCode rc_buff; - uint32_t rc_num = 0; - uint8_t tmod_delay = 12; - ecmdDataBufferBase data_buffer_64(64); - ecmdDataBufferBase address_16(16); - ecmdDataBufferBase bank_3(3); - ecmdDataBufferBase activate_1(1); - rc_num = rc_num | activate_1.setBit(0); - ecmdDataBufferBase rasn_1(1); - rc_num = rc_num | rasn_1.clearBit(0); - ecmdDataBufferBase casn_1(1); - rc_num = rc_num | casn_1.clearBit(0); - ecmdDataBufferBase wen_1(1); - rc_num = rc_num | wen_1.clearBit(0); - ecmdDataBufferBase cke_4(4); - rc_num = rc_num | cke_4.clearBit(0,4); - ecmdDataBufferBase csn_8(8); - rc_num = rc_num | csn_8.clearBit(0,8); - ecmdDataBufferBase odt_4(4); - rc_num = rc_num | odt_4.clearBit(0,4); - ecmdDataBufferBase ddr_cal_type_4(4); - - uint32_t instruction_number; - ecmdDataBufferBase num_idles_16(16); - ecmdDataBufferBase num_repeat_16(16); - ecmdDataBufferBase data_20(20); - ecmdDataBufferBase read_compare_1(1); - ecmdDataBufferBase rank_cal_4(4); - ecmdDataBufferBase ddr_cal_enable_1(1); - ecmdDataBufferBase ccs_end_1(1); - ecmdDataBufferBase mrs0(16); - ecmdDataBufferBase mrs1(16); - ecmdDataBufferBase mrs2(16); - ecmdDataBufferBase mrs3(16); - ecmdDataBufferBase mrs4(16); - ecmdDataBufferBase mrs5(16); - ecmdDataBufferBase mrs6(16); - - uint16_t MRS6 = 0; - - ecmdDataBufferBase data_buffer(64); - instruction_number = 0; - - uint16_t num_ranks = 0; - - FAPI_INF( "+++++++++++++++++++++ LOADING MRS SETTINGS FOR PORT %d +++++++++++++++++++++", i_port_number); - - uint8_t num_ranks_array[2][2]; //[port][dimm] - rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target, num_ranks_array); - if(rc) return rc; - - uint8_t dimm_type; - rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target, dimm_type); - if(rc) return rc; - - uint8_t is_sim = 0; - rc = FAPI_ATTR_GET(ATTR_IS_SIMULATION, NULL, is_sim); - if(rc) return rc; - - uint8_t address_mirror_map[2][2]; //address_mirror_map[port][dimm] - rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_ADDRESS_MIRRORING, &i_target, address_mirror_map); - if(rc) return rc; - - - // WORKAROUNDS - rc = fapiGetScom(i_target, CCS_MODEQ_AB_REG_0x030106A7, data_buffer); - if(rc) return rc; - //Setting up CCS mode - rc_num = rc_num | data_buffer.setBit(51); - if (rc_num) - { - FAPI_ERR( "mss_mr6_loader: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - rc = fapiPutScom(i_target, CCS_MODEQ_AB_REG_0x030106A7, data_buffer); - if(rc) return rc; - - if(i_port_number==0){ - rc = fapiGetScom(i_target,DPHY01_DDRPHY_WC_CONFIG3_P0_0x8000CC050301143F, data_buffer); - if(rc) return rc; - //Setting up CCS mode - rc_num = rc_num | data_buffer.clearBit(48); - if (rc_num) - { - FAPI_ERR( "mss_mr6_loader: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - rc = fapiPutScom(i_target,DPHY01_DDRPHY_WC_CONFIG3_P0_0x8000CC050301143F, data_buffer); - if(rc) return rc; - } - else{ - - rc = fapiGetScom(i_target,DPHY01_DDRPHY_WC_CONFIG3_P1_0x8001CC050301143F, data_buffer); - if(rc) return rc; - //Setting up CCS mode - rc_num = rc_num | data_buffer.clearBit(48); - if (rc_num) - { - FAPI_ERR( "mss_mr6_loader: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - rc = fapiPutScom(i_target,DPHY01_DDRPHY_WC_CONFIG3_P1_0x8001CC050301143F, data_buffer); - if(rc) return rc; - } - - //Lines commented out in the following section are waiting for xml attribute adds - - uint8_t dram_stack[2][2]; - rc = FAPI_ATTR_GET(ATTR_EFF_STACK_TYPE, &i_target, dram_stack); - if(rc) return rc; - - FAPI_INF( "Stack Type: %d\n", dram_stack[0][0]); - - - //MRS6 - uint8_t vrefdq_train_value[2][2][4]; //vrefdq_train value - NEW - rc = FAPI_ATTR_GET( ATTR_VREF_DQ_TRAIN_VALUE, &i_target, vrefdq_train_value); - if(rc) return rc; - uint8_t vrefdq_train_range[2][2][4]; //vrefdq_train range - NEW - rc = FAPI_ATTR_GET( ATTR_VREF_DQ_TRAIN_RANGE, &i_target, vrefdq_train_range); - if(rc) return rc; - uint8_t vrefdq_train_enable[2][2][4]; //vrefdq_train enable - NEW - rc = FAPI_ATTR_GET( ATTR_VREF_DQ_TRAIN_ENABLE, &i_target, vrefdq_train_enable); - if(rc) return rc; - - FAPI_INF("enable attribute %d",vrefdq_train_enable[0][0][0]); - - - - uint8_t tccd_l; //tccd_l - NEW - rc = FAPI_ATTR_GET( ATTR_TCCD_L, &i_target, tccd_l); - if(rc) return rc; - if (tccd_l == 4) - { - tccd_l = 0x00; - } - else if (tccd_l == 5) - { - tccd_l = 0x80; - } - else if (tccd_l == 6) - { - tccd_l = 0x40; - } - else if (tccd_l == 7) - { - tccd_l = 0xC0; - } - else if (tccd_l == 8) - { - tccd_l = 0x20; - } - - // Raise CKE high with NOPS, waiting min Reset CKE exit time (tXPR) - 400 cycles - rc_num = rc_num | cke_4.setBit(0,4); - rc_num = rc_num | csn_8.setBit(0,8); - rc_num = rc_num | address_16.clearBit(0, 16); - rc_num = rc_num | odt_4.clearBit(0,4); - rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 400, 0, 16); - - if (rc_num) - { - FAPI_ERR( "mss_mr6_loader: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - - rc = mss_ccs_inst_arry_0( i_target, - io_ccs_inst_cnt, - address_16, - bank_3, - activate_1, - rasn_1, - casn_1, - wen_1, - cke_4, - csn_8, - odt_4, - ddr_cal_type_4, - i_port_number); - if(rc) return rc; - rc = mss_ccs_inst_arry_1( i_target, - io_ccs_inst_cnt, - num_idles_16, - num_repeat_16, - data_20, - read_compare_1, - rank_cal_4, - ddr_cal_enable_1, - ccs_end_1); - if(rc) return rc; - io_ccs_inst_cnt ++; - - // Dimm 0-1 - for ( dimm_number = 0; dimm_number < 2; dimm_number++) - { - num_ranks = num_ranks_array[i_port_number][dimm_number]; - - if (num_ranks == 0) - { - FAPI_INF( "PORT%d DIMM%d not configured. Num_ranks: %d ", i_port_number, dimm_number, num_ranks); - } - else - { - // Rank 0-3 - for ( rank_number = 0; rank_number < num_ranks; rank_number++) - { - FAPI_INF( "MRS SETTINGS FOR PORT%d DIMM%d RANK%d", i_port_number, dimm_number, rank_number); - - rc_num = rc_num | csn_8.setBit(0,8); - rc_num = rc_num | address_16.clearBit(0, 16); - - //MRS6 - - vrefdq_train_value[i_port_number][dimm_number][rank_number] = mss_reverse_8bits(vrefdq_train_value[i_port_number][dimm_number][rank_number]); - - if (vrefdq_train_range[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VREF_DQ_TRAIN_RANGE_RANGE1) - { - vrefdq_train_range[i_port_number][dimm_number][rank_number] = 0x00; - } - else if (vrefdq_train_range[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VREF_DQ_TRAIN_RANGE_RANGE2) - { - vrefdq_train_range[i_port_number][dimm_number][rank_number] = 0xFF; - } - - if (vrefdq_train_enable[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE) - { - vrefdq_train_enable[i_port_number][dimm_number][rank_number] = 0xff;FAPI_INF("ENABLE is enabled"); - } - else if (vrefdq_train_enable[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_DISABLE) - { - vrefdq_train_enable[i_port_number][dimm_number][rank_number] = 0x00;FAPI_INF("DISABLE is enabled"); - } - - rc_num = rc_num | mrs6.insert((uint8_t) vrefdq_train_value[i_port_number][dimm_number][rank_number], 0, 6); - rc_num = rc_num | mrs6.insert((uint8_t) vrefdq_train_range[i_port_number][dimm_number][rank_number], 6, 1); - rc_num = rc_num | mrs6.insertFromRight((uint8_t) vrefdq_train_enable[i_port_number][dimm_number][rank_number], 7, 1); - - rc_num = rc_num | mrs6.insert((uint8_t) 0x00, 8, 2); - rc_num = rc_num | mrs6.insert((uint8_t) tccd_l, 10, 3); - rc_num = rc_num | mrs6.insert((uint8_t) 0x00, 13, 2); - - rc_num = rc_num | mrs6.extractPreserve(&MRS6, 0, 16, 0); - - FAPI_INF( "MRS 6: 0x%04X", MRS6); - - if (rc_num) - { - FAPI_ERR( "mss_mrs_load: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - - // Only corresponding CS to rank - rc_num = rc_num | csn_8.setBit(0,8); - rc_num = rc_num | csn_8.clearBit(rank_number+4*dimm_number); - - if (dram_stack[0][0] == ENUM_ATTR_EFF_STACK_TYPE_STACK_3DS) - { - FAPI_INF( "============= Got in the 3DS stack loop CKE !!!!=====================\n"); - rc_num = rc_num | csn_8.clearBit(2+4*dimm_number,2); - // I'm leaving this commented out - I need to double check it with Luke Mulkey to see which CS's are wired to which CKE's - // rc_num = rc_num | cke_4.clearBit(1); - } - - // Propogate through the 4 MRS cmds - // Copying the current MRS into address buffer matching the MRS_array order - // Setting the bank address - rc_num = rc_num | address_16.insert(mrs6, 0, 16, 0); - rc_num = rc_num | bank_3.insert((uint8_t) MRS6_BA, 0, 1, 7); - rc_num = rc_num | bank_3.insert((uint8_t) MRS6_BA, 1, 1, 6); - rc_num = rc_num | bank_3.insert((uint8_t) MRS6_BA, 2, 1, 5); - - if (rc_num) - { - FAPI_ERR( "mss_mrs_load: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - - if (( address_mirror_map[i_port_number][dimm_number] & (0x08 >> rank_number) ) && (is_sim == 0)) - { - rc = mss_address_mirror_swizzle(i_target, i_port_number, dimm_number, rank_number, address_16, bank_3); - if(rc) return rc; - } - - // Send out to the CCS array - rc = mss_ccs_inst_arry_0( i_target, - io_ccs_inst_cnt, - address_16, - bank_3, - activate_1, - rasn_1, - casn_1, - wen_1, - cke_4, - csn_8, - odt_4, - ddr_cal_type_4, - i_port_number); - if(rc) return rc; - rc = mss_ccs_inst_arry_1( i_target, - io_ccs_inst_cnt, - num_idles_16, - num_repeat_16, - data_20, - read_compare_1, - rank_cal_4, - ddr_cal_enable_1, - ccs_end_1); - if(rc) return rc; - io_ccs_inst_cnt ++; - - // Address inversion for RCD - if ( (dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_RDIMM) || (dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_RDIMM || dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) ) - { - FAPI_INF( "Sending out MRS with Address Inversion to B-side DRAMs\n"); - - - // Propogate through the 4 MRS cmds - // Copying the current MRS into address buffer matching the MRS_array order - // Setting the bank address - rc_num = rc_num | address_16.insert(mrs6, 0, 16, 0); - rc_num = rc_num | bank_3.insert((uint8_t) MRS6_BA, 0, 1, 7); - rc_num = rc_num | bank_3.insert((uint8_t) MRS6_BA, 1, 1, 6); - rc_num = rc_num | bank_3.insert((uint8_t) MRS6_BA, 2, 1, 5); - - // Indicate B-Side DRAMS BG1=1 - rc_num = rc_num | address_16.setBit(15); // Set BG1 = 1 - - rc_num = rc_num | address_16.flipBit(3,7); // Invert A3:A9 - rc_num = rc_num | address_16.flipBit(11); // Invert A11 - rc_num = rc_num | address_16.flipBit(13); // Invert A13 - rc_num = rc_num | address_16.flipBit(14); // Invert A17 - rc_num = rc_num | bank_3.flipBit(0,3); // Invert BA0,BA1,BG0 - - - if (rc_num) - { - FAPI_ERR( " Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - - if (( address_mirror_map[i_port_number][dimm_number] & (0x08 >> rank_number) ) && (is_sim == 0)) - { - rc = mss_address_mirror_swizzle(i_target, i_port_number, dimm_number, rank_number, address_16, bank_3); - if(rc) return rc; - } - - // Send out to the CCS array - rc = mss_ccs_inst_arry_0( i_target, - io_ccs_inst_cnt, - address_16, - bank_3, - activate_1, - rasn_1, - casn_1, - wen_1, - cke_4, - csn_8, - odt_4, - ddr_cal_type_4, - i_port_number); - if(rc) return rc; - rc = mss_ccs_inst_arry_1( i_target, - io_ccs_inst_cnt, - num_idles_16, - num_repeat_16, - data_20, - read_compare_1, - rank_cal_4, - ddr_cal_enable_1, - ccs_end_1); - if(rc) return rc; - io_ccs_inst_cnt ++; - - - } -instruction_number = io_ccs_inst_cnt; - -rc = add_nop_to_ccs (i_target, address_16,instruction_number,rank_number,MRS6_BA,tmod_delay,i_port_number); -io_ccs_inst_cnt = instruction_number; -io_ccs_inst_cnt++; -if (rc) return rc; - - } - } - } - - - - - - return rc; -} - - - - - -} - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mrs6_DDR4.H b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mrs6_DDR4.H deleted file mode 100644 index 5abc286d8..000000000 --- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mrs6_DDR4.H +++ /dev/null @@ -1,99 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mrs6_DDR4.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2015 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: mss_mrs6_DDR4.H,v 1.2 2015/08/04 18:47:26 sglancy Exp $ -// *!*************************************************************************** -// *! (C) Copyright International Business Machines Corp. 1997, 1998, 2013 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -// *!*************************************************************************** -// *! FILENAME : mss_mrs6_DDR4.H -// *! TITLE : -// *! DESCRIPTION : MRS6 setting procedures -// *! CONTEXT : -// *! -// *! OWNER NAME : -// *! BACKUP : -// *!*************************************************************************** -// CHANGE HISTORY: -//------------------------------------------------------------------------------- -// Version:|Author: | Date: | Comment: -// 1.2 | sglancy | 08/04/15| Changed to address FW comments -// 1.1 | abhijsau | 06/27/14| Initial Version -// --------|--------|---------|-------------------------------------------------- -//------------------------------------------------------------------------------ -#ifndef MSS_MR6_DDR4_H -#define MSS_MR6_DDR4_H - - -/****************************************************************************************/ -/* mss_mcbist_address.H */ -/****************************************************************************************/ -#include <fapi.H> - -typedef fapi::ReturnCode (*mss_mrs6_DDR4_FP_t)(const fapi::Target& i_target); - -extern "C" -{ - -using namespace fapi; -/** - * @sets up and runs Mode Register Set 6 on a centaur.mba level target - * - * @param[in] target: Reference to centaur.mba target, - * - * @return ReturnCode - */ - -fapi::ReturnCode mss_mrs6_DDR4(fapi::Target& i_target); -/** - * @Adds a no-op (NOP) command to the CCS array - * - * @param[in] target: Reference to centaur.mba target, - * @param[in] addr_16: 16 wide ecmdDataBufferBase to be used for the address bus - * @param[in] instruction_number: current location in the CCS array - * @param[in] rank: current rank - * @param[in] bank: current bank - * @param[in] delay: delay to add for the command - * @param[in] port: current port to execute the NOP on - * - * @return ReturnCode - */ -fapi::ReturnCode add_nop_to_ccs(fapi::Target& i_target_mba, ecmdDataBufferBase &addr_16, uint32_t instruction_number,uint8_t rank,uint8_t bank,uint32_t delay,uint8_t port); -/** - * @Loads in MRS6 for a given port number - * - * @param[in] target: Reference to centaur.mba target, - * @param[in] i_port: Current port to operate on - * @param[in/out] io_ccs_inst_cnt: Reference to current CCS array position - * - * @return ReturnCode - */ -fapi::ReturnCode mss_mr6_loader(fapi::Target& i_target,uint32_t i_port_number,uint32_t& io_ccs_inst_cnt); -} // extern "C" - -#endif // MSS_MR6_DDR4_H - - - diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_shmoo_common.H b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_shmoo_common.H deleted file mode 100644 index d535405ee..000000000 --- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_shmoo_common.H +++ /dev/null @@ -1,108 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_shmoo_common.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2012,2015 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: mss_shmoo_common.H,v 1.21 2015/08/07 11:29:09 sasethur Exp $ -// *!*************************************************************************** -// *! (C) Copyright International Business Machines Corp. 1997, 1998 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -// *!*************************************************************************** -// *! FILENAME : mss_shmoo_common.H -// *! TITLE : MSS Shmoo common defines -// *! DESCRIPTION : Memory Subsystem Shmoo common defines -// *! CONTEXT : To make all shmoos share a common defines -// *! -// *! OWNER NAME : Preetham Hosmane Email - preeragh@in.ibm.com -// *! BACKUP NAME : Saravanan Sethuraman Email: -// *! -// *!*************************************************************************** -// CHANGE HISTORY: -//------------------------------------------------------------------------------ -// Version:|Author: | Date: | Comment: -// 1.21 |preeragh| 30/07/15| Optimized for FW Linear/Composite/Bin -// 1.20 |preeragh| 22/06/15| DDR4 - Mods -// 1.18 |mjjones | 24/01/14| RAS Review Updates -// 1.15 |abhijit |8/8/12 | Updated Review Comments -// 1.9 |aditya |12/6/12 | Updated Review Comments -// 1.8 | abhijit| 15/11/12| made changes fw review comments -// 1.7 | abhijit| 22/10/12| made changes to variables -// 1.6 | abhijit| 22/10/12| made changes according to the new design -// --------|--------|-------- |-------------------------------------------------- -#ifndef MSS_SHMOO_COMMON_H -#define MSS_SHMOO_COMMON_H - -enum shmoo_type_t -{ - TEST_NONE = 0, - MCBIST = 1, - WR_EYE = 2, - WRT_DQS = 8, - RD_EYE = 4, - RD_GATE = 16 -}; - -enum shmoo_algorithm_t -{ - SEQ_LIN // Parallel bytes/ranks here .. no parallel targets in HB -}; - -const uint8_t NINE = 9; -const uint8_t MAX_SHMOO=2; -const uint8_t MAX_RANK_DIMM=4; -const uint8_t MAX_NIBBLES=2; -const uint8_t MAX_BITS=4; -const uint8_t MAX_DQ=80; -const uint8_t MAX_DQS=20; -const uint8_t SCHMOO_NIBBLES=20; -const uint8_t MAX_PORT = 2; -const uint8_t MAX_BYTE = 10; -const uint8_t MAX_RANK = 8; - -//! Defines the structure of a knob ..Holds static info regarding a knob -struct shmoo_knob_config_t -{ - //! These are const values that define a knob , will not change during - //! shmoo runtime - uint16_t min_val; //Minimum value that can be taken by the knob - uint16_t max_val; //Maximum value that can be taken by the knob -}; - -//! Defines the structure of a knob ..Holds dynamic runtime info of a knob -struct shmoo_knob_data_t -{ - // placeholder for the datastructure that will hold all the shmoo - // config data and results - bool done; - uint16_t lb_regval[MAX_DQ]; // Left Bound register/Hex value - uint16_t rb_regval[MAX_DQ];// Right Bound register/Hex value - uint16_t nom_val[MAX_DQ]; // nominal value of this instance of the knob - uint16_t last_pass[MAX_DQ]; - uint16_t total_margin[MAX_DQ]; - uint16_t curr_diff[MAX_DQ]; - uint16_t last_fail[MAX_DQ]; - uint16_t curr_val[MAX_DQ]; - uint16_t right_margin_val[MAX_DQ]; - uint16_t left_margin_val[MAX_DQ]; -}; -#endif diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C deleted file mode 100644 index 11905cba1..000000000 --- a/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C +++ /dev/null @@ -1,7513 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2012,2015 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: mss_draminit_training.C,v 1.103 2015/09/22 19:13:20 kmack Exp $ -//------------------------------------------------------------------------------ -// Don't forget to create CVS comments when you check in your changes! -//------------------------------------------------------------------------------ -// CHANGE HISTORY: -//------------------------------------------------------------------------------ -// Version:| Author: | Date: | Comment: -//---------|----------|---------|------------------------------------------------ -// 1.103 | kmack |16-SEP-15| Replaced sleep with fapiDelay -// 1.102 | kmack |16-SEP-15| DQS Alignment Workaround -// 1.101 | sglancy |14-JUL-15| Fixed compile issue -// 1.100 | sglancy |13-JUL-15| Fixed compile issue -// 1.99 | sglancy |13-JUL-15| Fixed LR DIMM order of operations and addressed FW comments -// 1.98 | sglancy |24-JUN-15| Added call to DQS offset function -// 1.97 | sglancy |10-JUN-15| Fixed BBM set code call - removed comment of code -// 1.96 | sglancy |27-MAY-15| Added changes for DDR4 3DS -// 1.95 | sglancy |12-MAY-15| Added DDR4 WR VREF set -// 1.94 | jdsloat |27-JAN-14| Addressed FW concerns from gerrit. -// 1.93 | jdsloat |22-JAN-14| Moved the initialization of rank_invalid within BYTE DISABLE WORKAROUND -// 1.92 | jdsloat |20-JAN-14| Added new workaround for BYTE DISABLE and for WR LVL DISABLE. This affects RAS/BBM work. -// 1.91 | jdsloat |24-SEP-14| Disabling spare CKE bit modify for SW275629. This bit will be modified via initfile. -// 1.90 | jdsloat |29-JUL-14| disable for delay reset call moved to system level -// 1.89 | jdsloat |29-JUL-14| Added a disable for delay reset call -// 1.88 | jdsloat |14-JUL-14| Fixed delay reset call -// 1.87 | jdsloat |09-JUN-14| Fixed log numbering... Added additonal error logs for more debug ability in a training error situation. -// 1.85 | jdsloat |23-APL-14| Fixed attribute variable l_disable1_rdclk_fixed unitialized error in SW25701/v1.83 -// 1.84 | jdsloat |23-APL-14| Fixed FAPI_ERR message within v1.83, mss_set_bbm_regs -// 1.83 | jdsloat |18-APL-14| SW25701 Workaround - mss_set_bbm_regs - x4s will not mask out RDCLKs on Bad Bits to avoid translation issues -// 1.82 | jdsloat |14-APL-14| Gerrit Review. Rc checks. -// 1.81 | jdsloat |11-APL-14| HW278227 BBM workaround: Masking out the same bits/bytes across all ranks. -// 1.80 | jdsloat |01-APL-14| RAS review edits/changes -// 1.79 | jdsloat |01-APL-14| RAS review edits/changes -// 1.78 | jdsloat |28-MAR-14| RAS review edits/changes -// 1.77 | jdsloat |28-MAR-14| Added ifdef around #include for mss_lrdimm_ddr4_funcs.H -// 1.76 | mwuu |14-MAR-14| Fixed CDIMM full spare case in getC4dq2reg (bbm) -// 1.75 | kcook |14-MAR-14| Fixed mss_mxd_training stub function definition -// 1.74 | kcook |14-MAR-14| Added calls to DDR4 LRDIMM training functions -// 1.73 | mwuu |25-FEB-14| Fixed ISDIMM spare case for bad bitmap -// 1.72 | mwuu |14-FEB-14| Fixed x4 spare case when mss_c4_phy returns bad -// | | | data with workaround -// 1.71 | mwuu |13-FEB-14| Updated get/setC4dq2reg, mss_set/get_bbm_regs FNs -// | | | to use access_delay_regs for dq/dqs pin mapping. -// | | | Added mss_get_dqs_lane helper FN. -// 1.70 | jdsloat | 11/11/13| Changed EFF attributes to VPD named attributes -// 1.69 | jdsloat |06-OCT-13| Removed Control Switch Attribute -// 1.68 | bellows |16-SEP-13| Hostboot compile update -// 1.67 | kcook |13-SEP-13| Updated define FAPI_LRDIMM token. -// 1.66 | kcook |27-AUG-13| Moved main LRDIMM sections into separate file. -// | | | Removed reference to ATTR_LAB_USE_JTAG_MODE. -// | mwuu | | Added ATTR_MSS_DISABLE1_REG_FIXED for bbm FN for DD2. -// 1.65 | kcook |16-AUG-13| Added LRDIMM support. Use with mss_funcs.C v1.32. -// 1.64 | jdsloat |01-AUG-13| Fixed dimm/rank conversion in address mirroring mode for a 4 rank dimm scenario -// 1.63 | jdsloat |29-JUN-13| Added JTAG mode and CONTROL SWITCH attribute checks to bad bit mask function calls. -// 1.62 | mwuu |17-JUN-13| Fixed set_bbm function to disable0,disable1,wr_clk registers -// | | | In x4 single bit fails disables entire nibble in set/get_bbm FN -// 1.61 | jdsloat |13-JUN-13| Added a single RC check -// 1.60 | jdsloat |11-JUN-13| Added a single RC check -// 1.59 | jdsloat |04-JUN-13| Added RC checks and port 1 to delay reset function -// 1.58 | jdsloat |20-MAY-13| Added a delay reset function for multiple training runs -// | | | changed mss_rtt_nom_rtt_wr_swap to use mirror mode function in mss_funcs -// | | | changed mss_rtt_nom_rtt_wr_swap to only execute on ddr3 -// | | | Mirror mode keyed off of mba level mirror_mode attribute. -// 1.57 | jdsloat |27-FEB-13| Added second workaround adjustment to waterfall problem in order to use 2 rank pairs. -// 1.56 | jdsloat |27-FEB-13| Fixed rtt_nom and rtt_wr swap bug during condition of rtt_nom = diabled and rtt_wr = non-disabled -// | | | Added workaround on a per quad resolution -// | | | Added workaround as a seperate sub -// | | | Added framework of binning workaround based on timing reference -// | | | Added putscom to enable spare cke mirroring -// 1.55 | jdsloat |25-FEB-13| Added MBA/Port info to debug messages. -// 1.54 | jdsloat |22-FEB-13| Edited WRITE_READ workaround to also edit DQSCLK PHASE -// 1.53 | jdsloat |14-FEB-13| Fixed WRITE_READ workaround so it will execute in a partial substep case -// | | | Edited mss_rtt_nom_rtt_wr_swap to only write rtt_nom with rtt_wr or supplied rtt_nom -// | | | Moved location of mss_rtt_nom_rtt_wr_swap around wr_lvl substep -// | | | Added Address Mirror Mode. -// 1.52 | jdsloat |07-FEB-13| Fixed address typo for RP3 in WRITE_READ workaround. -// 1.51 | gollub |31-JAN-13| Uncommenting mss_unmask_draminit_training_errors -// 1.50 | jdsloat |16-JAN-13| Fixed rank group enable within PC_INIT_CAL reg -// 1.49 | jdsloat |08-JAN-13| Added clearing RD PHASE SELECT values post Read Centering Workaround. -// 1.48 | jdsloat |08-JAN-13| Cleared Cal Config in PC_INIT_CAL on opposing port. -// 1.47 | jdsloat |08-JAN-13| Fixed port 1 cal setup RMW and fixed doing individual rank pairs. Both in PC_INIT_CAL_CONFIG0 regs. -// 1.46 | jdsloat |03-JAN-13| RM temp edits to CAL0q and CAL1q; Cleared INIT_CAL_STATUS and INIT_CAL_ERROR Regs before every subtest, edited debug messages -// 1.45 | gollub |21-DEC-12| Calling mss_unmask_draminit_training_errors after mss_draminit_training_cloned -// 1.43 | jdsloat |20-DEC-12| Temporarily disabled RTT_NOM swap -// 1.42 | bellows |06-DEC-12| Fixed up review comments -// 1.41 | jdsloat |02-DEC-12| Fixed RTT_NOM swap for Port 1 -// 1.40 | jdsloat |30-NOV-12| Temporarily comment Bad Bit Mask. - -// 1.39 | jdsloat |18-NOV-12| Fixed CAL_STEP to allow Zq Cal. -// 1.38 | jdsloat |16-NOV-12| Fixed Error Place holder and port addressing with BBM -// 1.37 | jdsloat |12-NOV-12| Fixed a bracket typo. -// 1.36 | jdsloat |07-NOV-12| Changed procedure to proceed through ALL rank_pair, Ports before reporting -// | | | error status for partial good support. Added Bad Bit Mask to disable regs function -// | | // 1.57 | jdsloat |27-FEB-13| | and disable regs to Bad Bit Mask function. -// 1.35 | jdsloat |08-OCT-12| Changed Write to Read,Modify,Write of Phy Init Cal Config Reg -// 1.34 | jdsloat |25-SEP-12| Bit 0 of Cal Step Attribute now offers an all at once option - bit 0 =1 if stepbystep -// 1.33 | jdsloat |07-SEP-12| Broke init_cal down to step by step keyed off of CAL_STEP_ENABLE attribute -// 1.32 | jdsloat |29-AUG-12| Fixed mss_rtt_nom_rtt_wr_swap and verified with regression -// 1.31 | bellows |28-AUG-12| Revert back to 1.29 until regression pass again -// 1.30 | jdsloat |23-AUG-12| Added mss_rtt_nom_rtt_wr_swap pre and post init_cal -// 1.29 | bellows |16-Jul-12| bellows | added in Id tag -// 1.28 | bellows |02-May-12| cal ranks are 4 bits, this needed to be adjusted -// 1.26 | asaetow |12-Apr-12| Added "if(rc) return rc;" at line 180. -// 1.25 | asaetow |06-Apr-12| Added "if(rc) return rc;" at line 165. -// 1.24 | asaetow |03-Apr-12| Changed FAPI_INF to FAPI_ERR where applicable from lines 275 to 324, per Mike Jones. -// 1.23 | asaetow |29-Mar-12| Fixed FAPI_SET_HWP_ERROR using temp error callout RC_MSS_PLACE_HOLDER_ERROR. -// | | | Changed uint32_t NUM_POLL to const. -// 1.22 | divyakum |29-Mar-12| Fixed rc assignment. Added comments for error handling. -// 1.21 | divyakum |06-Mar-12| Added cal status checking function. -// | | | Fixed init cal issue via CCS to account for both ports. -// 1.20 | divyakum | | Modified to execute CCS after every instruction. -// | | | Added error checking for calibration. Needs cen_scom_addresses.H v.1.15 or newer. -// 1.19 | divyakum |01-Mar-12| Fixed ddr_cal_enable_buffer_1 value for ZQ cal long -// 1.18 | divyakum |29-Feb-12| Removed call to ccs_mode function. writing to scom directly -// | | | Fixed wen_buffer value when re-issuing zqcal -// | | | Fixed test_buffer value when re-issuing zqcal -// | | | Added cen_scom_addresses.H in include -// 1.17 | divyakum |20-Feb-12| Adding comments to include i_target type -// 1.16 | divyakum |20-Feb-12| Replaced calls to insertFromBin with setHalfWord and setBit functions -// 1.15 | divyakum |14-Feb-12| Removed port field from mss_ccs_mode, mss_ccs_inst_arry_1, mss_execute_ccs_inst_array. -// | | | NOTE: compatible with mss_funcs.H v1.19 or newer -// 1.14 | divyakum |10-Feb-12| Added/Modified error codes, var names and declarations to meet coding guidlines -// 1.13 | divyakum |08-Feb-12| Modified Attributes to FAPI attributes -// | | | Added rc checking -// 1.12 | divyakum |31-Jan-12| Modified number of ports to work with Brent's userlevel. -// 1.11 | divyakum |20-Jan-12| Modified print messages. Fixed indentations -// 1.16 | divyakum |20-Jan-12| Fixed CCS func names to match mss_funcs.H ver 1.16 -// | divyakum | | Added resetn initialization. -// 1.15 | bellows |23-Dec-11| Set poll count to 100, set the end bit and when to execute the array time -// 1.14 | divyakum |21-Dec-11| Added more info prints. Fixed Execution of CCS -// 1.13 | bellows |20-Dec-11| Fixed up rank loop so that it goes over both DIMMs -// 1.12 | jdsloat |23-Nov-11| Incremented instruction number, added info messages -// 1.11 | jdsloat |21-Nov-11| Got rid of GOTO argument in CCS cmds. -// 1.10 | divyakum |18-Nov-11| Fixed function calls to match procedure name. -// 1.9 | divyakum |11-Oct-11| Fix to include mss_funcs instead of cen_funcs. -// | | | Changed usage of array attributes. -// | | | NOTE: Needs to be compiled with mss_funcs v1.3. -// 1.8 | divyakum |03-Oct-11| Removed primary_ranks_arrayvariable. Fixed rank loop for Socket1 -// 1.7 | divyakum |30-Sep-11| First drop for Centaur. This code compiles -// 1.6 | divyakum |28-Sep-11| Added Error path with cal fails. -// | | | Modified CCS_MODE, CCS_EXECUTE call -// 1.5 | divyakum |27-Sep-11| Updated code to match with cen_funcs.H v.1.5 -// 1.4 | divyakum |27-Sep-11| Added capability to issue CCS cmds to a port pair where possible. -// 1.3 | divyakum |26-Sep-11| Added calls to attributes and CCS array for ZQ and initial calibrations. -// | | | Added rank loopers. -// 1.2 | jdsloat |14-Jul-11| Proper call name fix -// 1.1 | jdsloat |22-Apr-11| Initial draft - - -//---------------------------------------------------------------------- -// FAPI function Includes -//---------------------------------------------------------------------- - -#include <fapi.H> -#include <fapiUtil.H> - -//---------------------------------------------------------------------- -// Centaur function Includes -//---------------------------------------------------------------------- -#include <cen_scom_addresses.H> -#include <mss_funcs.H> -#include <dimmBadDqBitmapFuncs.H> -#include <mss_unmask_errors.H> -#include <mss_lrdimm_funcs.H> -#include "mss_access_delay_reg.H" -#include <mss_mrs6_DDR4.H> -#ifdef FAPI_LRDIMM -#include <mss_lrdimm_ddr4_funcs.H> -#endif - -#ifndef FAPI_LRDIMM -using namespace fapi; -fapi::ReturnCode mss_execute_lrdimm_mb_dram_training(Target& i_target) -{ - ReturnCode rc; - - FAPI_ERR("Invalid exec of LRDIMM function on %s!", i_target.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); - return rc; - -} -fapi::ReturnCode mss_mrep_training(Target& i_target, uint32_t port) -{ - ReturnCode rc; - - FAPI_ERR("Invalid exec of LRDIMM function on %s!", i_target.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); - return rc; - -} -fapi::ReturnCode mss_mxd_training(Target& i_target, uint8_t port, uint8_t i_type) -{ - ReturnCode rc; - - FAPI_ERR("Invalid exec of LRDIMM function on %s!", i_target.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); - return rc; - -} -fapi::ReturnCode mss_dram_write_leveling(Target& i_target, uint32_t port) -{ - ReturnCode rc; - - FAPI_ERR("Invalid exec of LRDIMM function on %s!", i_target.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); - return rc; - -} -#endif - -//------------End My Includes------------------------------------------- - -//---------------------------------------------------------------------- -// Constants -//---------------------------------------------------------------------- -const uint8_t MRS1_BA = 1; -const uint8_t MRS2_BA = 2; - -#define MAX_PORTS 2 -#define MAX_DIMMS 2 -#define MAX_PRI_RANKS 4 -#define TOTAL_BYTES 10 -#define BITS_PER_REG 16 -#define DP18_INSTANCES 5 -#define BITS_PER_PORT (BITS_PER_REG*DP18_INSTANCES) - -//---------------------------------------------------------------------- -// Enums -//---------------------------------------------------------------------- - -enum mss_draminit_training_result -{ - MSS_INIT_CAL_COMPLETE = 1, - MSS_INIT_CAL_PASS = 2, - MSS_INIT_CAL_STALL = 3, - MSS_INIT_CAL_FAIL = 4 -}; - - -extern "C" { - - -//Sets the DQS offset to be 16 instead of 8, recommended training settings -fapi::ReturnCode mss_setup_dqs_offset(Target &i_target); - -using namespace fapi; - -ReturnCode mss_draminit_training(Target& i_target); -ReturnCode mss_draminit_training_cloned(Target& i_target); -ReturnCode mss_check_cal_status(Target& i_target, uint8_t i_mbaPosition, uint8_t i_port, uint8_t i_group, mss_draminit_training_result& io_status); -ReturnCode mss_check_error_status(Target& i_target, uint8_t i_mbaPosition, uint8_t i_port, uint8_t i_group, uint8_t cur_cal_step, mss_draminit_training_result& io_status, uint8_t i_max_cal_retry); -ReturnCode mss_rtt_nom_rtt_wr_swap( Target& i_target, uint8_t i_mbaPosition, uint32_t i_port_number, uint8_t i_rank, uint32_t i_rank_pair_group, uint32_t& io_ccs_inst_cnt, uint8_t& io_dram_rtt_nom_original); -ReturnCode mss_read_center_workaround(Target& i_target, uint8_t i_mbaPosition, uint32_t i_port, uint32_t i_rank_group); -ReturnCode mss_read_center_second_workaround(Target& i_target); -ReturnCode mss_disable_workaround( Target& i_target); -ReturnCode mss_wr_lvl_disable_workaround( Target& i_target); -ReturnCode mss_reset_delay_values(Target& i_target); - -ReturnCode getC4dq2reg(const Target &i_mba, const uint8_t i_port, const uint8_t i_dimm, const uint8_t i_rank, ecmdDataBufferBase &o_reg, uint8_t &is_clean); -ReturnCode setC4dq2reg(const Target &i_mba, const uint8_t i_port, const uint8_t i_dimm, const uint8_t i_rank, const ecmdDataBufferBase &i_reg); -ReturnCode mss_set_bbm_regs (const fapi::Target & mba_target); -ReturnCode mss_get_bbm_regs (const fapi::Target & mba_target, uint8_t i_training_success); -ReturnCode mss_get_dqs_lane (const fapi::Target & i_mba, const uint8_t i_port, const uint8_t i_block, const uint8_t i_quad, uint8_t &lane); - - -ReturnCode mss_draminit_training(Target& i_target) -{ - // Target is centaur.mba - - fapi::ReturnCode l_rc; - uint8_t reset_disable; - l_rc = FAPI_ATTR_GET(ATTR_MSS_DRAMINIT_RESET_DISABLE, NULL, reset_disable); - if(l_rc) return l_rc; - - - if (reset_disable != ENUM_ATTR_MSS_DRAMINIT_RESET_DISABLE_DISABLE) - { - - l_rc = mss_reset_delay_values(i_target); - if (l_rc) - { - return l_rc; - } - - } - - l_rc = mss_draminit_training_cloned(i_target); - if (l_rc) - { - return l_rc; - } - - // If mss_unmask_draminit_training_errors gets it's own bad rc, - // it will commit the passed in rc (if non-zero), and return it's own bad rc. - // Else if mss_unmask_draminit_training_errors runs clean, - // it will just return the passed in rc. - l_rc = mss_unmask_draminit_training_errors(i_target, l_rc); - if (l_rc) - { - return l_rc; - } - - return l_rc; -} - - - - -ReturnCode mss_draminit_training_cloned(Target& i_target) -{ - // Target is centaur.mba - //Enums and Constants - enum size - { - MAX_NUM_PORT = 2, - MAX_NUM_DIMM = 2, - MAX_NUM_GROUP = 4, - MAX_CAL_STEPS = 7, //read course and write course will occur at the sametime - MAX_DQS_RETRY = 10, //Used for the DQS Alignment workaround. Determines the number of DQS alignment retries. - INVALID = 255, - DELAY_0P5S = 500000000, - DELAY_LOOP = 6, - DELAY_SIM500 = 500 - }; - - const uint32_t NUM_POLL = 10000; - - ReturnCode rc; - uint32_t rc_num = 0; - - //Issue ZQ Cal first per rank - uint32_t instruction_number = 0; - ecmdDataBufferBase address_buffer_16(16); - rc_num = rc_num | address_buffer_16.flushTo0(); - ecmdDataBufferBase bank_buffer_8(8); - rc_num = rc_num | bank_buffer_8.flushTo0(); - ecmdDataBufferBase activate_buffer_1(1); - rc_num = rc_num | activate_buffer_1.flushTo0(); - ecmdDataBufferBase rasn_buffer_1(1); - ecmdDataBufferBase casn_buffer_1(1); - ecmdDataBufferBase wen_buffer_1(1); - ecmdDataBufferBase cke_buffer_8(8); - rc_num = rc_num | cke_buffer_8.flushTo1(); - ecmdDataBufferBase csn_buffer_8(8); - rc_num = rc_num | csn_buffer_8.flushTo1(); - ecmdDataBufferBase odt_buffer_8(8); - rc_num = rc_num | odt_buffer_8.flushTo0(); - ecmdDataBufferBase test_buffer_4(4); - - ecmdDataBufferBase num_idles_buffer_16(16); - rc_num = rc_num | num_idles_buffer_16.flushTo1(); - ecmdDataBufferBase num_repeat_buffer_16(16); - rc_num = rc_num | num_repeat_buffer_16.flushTo0(); - ecmdDataBufferBase data_buffer_20(20); - rc_num = rc_num | data_buffer_20.flushTo0(); - ecmdDataBufferBase read_compare_buffer_1(1); - rc_num = rc_num | read_compare_buffer_1.flushTo0(); - ecmdDataBufferBase rank_cal_buffer_4(4); - rc_num = rc_num | rank_cal_buffer_4.flushTo0(); - ecmdDataBufferBase ddr_cal_enable_buffer_1(1); - ecmdDataBufferBase ccs_end_buffer_1(1); - rc_num = rc_num | ccs_end_buffer_1.flushTo1(); - - - ecmdDataBufferBase stop_on_err_buffer_1(1); - rc_num = rc_num | stop_on_err_buffer_1.flushTo0(); - ecmdDataBufferBase cal_timeout_cnt_buffer_16(16); - rc_num = rc_num | cal_timeout_cnt_buffer_16.flushTo1(); - ecmdDataBufferBase resetn_buffer_1(1); - rc_num = rc_num | resetn_buffer_1.setBit(0); - ecmdDataBufferBase cal_timeout_cnt_mult_buffer_2(2); - rc_num = rc_num | cal_timeout_cnt_mult_buffer_2.flushTo1(); - - ecmdDataBufferBase data_buffer_64(64); - - if(rc_num) - { - rc.setEcmdError(rc_num); - return rc; - } - - uint8_t port = 0; - uint8_t group = 0; - uint8_t primary_ranks_array[4][2]; //primary_ranks_array[group][port] - uint8_t cal_steps = 0; - uint8_t delay_loop_cnt =0; - uint8_t dqs_try = 0; //part of DQS alignment workaround - uint8_t dqs_retry_num = 0; //part of DQS alignment workaround - uint8_t max_cal_retry = 0; //part of DQS alignment workaround added this to be a more generic var to pass into a proc. May be used if we need to add a retry to another cal step - uint8_t cur_cal_step = 0; - ecmdDataBufferBase cal_steps_8(8); - - uint8_t l_nwell_misplacement = 0; - uint8_t dram_rtt_nom_original = 0; - uint8_t training_success = 0; - - fapi::Target l_target_centaur; - rc = fapiGetParentChip(i_target, l_target_centaur); - if(rc) return rc; - - uint8_t dimm_type; - rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target, dimm_type); - if(rc) return rc; - - - uint8_t dram_gen = 0; - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_GEN, &i_target, dram_gen); - if(rc) return rc; - - uint8_t waterfall_broken = 0; - rc = FAPI_ATTR_GET(ATTR_MSS_BLUEWATERFALL_BROKEN, &l_target_centaur, waterfall_broken); - if(rc) return rc; - - enum mss_draminit_training_result cur_complete_status = MSS_INIT_CAL_COMPLETE; - enum mss_draminit_training_result cur_error_status = MSS_INIT_CAL_PASS; - - enum mss_draminit_training_result complete_status = MSS_INIT_CAL_COMPLETE; - enum mss_draminit_training_result error_status = MSS_INIT_CAL_PASS; - - //populate primary_ranks_arrays_array - rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP0, &i_target, primary_ranks_array[0]); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP1, &i_target, primary_ranks_array[1]); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP2, &i_target, primary_ranks_array[2]); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP3, &i_target, primary_ranks_array[3]); - if(rc) return rc; - - rc = FAPI_ATTR_GET(ATTR_MSS_NWELL_MISPLACEMENT, &l_target_centaur, l_nwell_misplacement); - if(rc) return rc; - - uint8_t mbaPosition; - // Get MBA position: 0 = mba01, 1 = mba23 - rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target, mbaPosition); - if(rc) - { - FAPI_ERR("Error getting MBA position"); - return rc; - } - - - - //Get which training steps we are to run - rc = FAPI_ATTR_GET(ATTR_MSS_CAL_STEP_ENABLE, &i_target, cal_steps); - if(rc) return rc; - rc_num = rc_num | cal_steps_8.insert(cal_steps, 0, 8, 0); - - /* - Disabling spare CKE bit modify for SW275629. This bit will be modified via initfile. - - - //Setup SPARE CKE enable bit - rc = fapiGetScom(i_target, MBA01_MBARPC0Q_0x03010434, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.setBit(42); - rc = fapiPutScom(i_target, MBA01_MBARPC0Q_0x03010434, data_buffer_64); - if(rc) return rc; - - */ - - //Set up CCS Mode Reg for Init cal - rc = fapiGetScom(i_target, MEM_MBA01_CCS_MODEQ_0x030106A7, data_buffer_64); - if(rc) return rc; - - rc_num = rc_num | data_buffer_64.insert(stop_on_err_buffer_1, 0, 1, 0); - rc_num = rc_num | data_buffer_64.insert(cal_timeout_cnt_buffer_16, 8, 16, 0); - rc_num = rc_num | data_buffer_64.insert(resetn_buffer_1, 24, 1, 0); - rc_num = rc_num | data_buffer_64.insert(cal_timeout_cnt_mult_buffer_2, 30, 2, 0); - if(rc_num) - { - rc.setEcmdError(rc_num); - return rc; - } - - rc = fapiPutScom(i_target, MEM_MBA01_CCS_MODEQ_0x030106A7, data_buffer_64); - if(rc) return rc; - - - rc = mss_set_bbm_regs (i_target); - if(rc) - { - FAPI_ERR( "Error Moving bad bit information to the Phy regs. Exiting."); - return rc; - } - - - - if ( ( cal_steps_8.isBitSet(0) ) || - ( (cal_steps_8.isBitClear(0)) && (cal_steps_8.isBitClear(1)) && - (cal_steps_8.isBitClear(2)) && (cal_steps_8.isBitClear(3)) && - (cal_steps_8.isBitClear(4)) && (cal_steps_8.isBitClear(5)) && - (cal_steps_8.isBitClear(6)) && (cal_steps_8.isBitClear(7)) )) - { - FAPI_INF( "Performing External ZQ Calibration on %s.", i_target.toEcmdString()); - - //Execute ZQ_CAL - for(port = 0; port < MAX_NUM_PORT; port++) - { - rc = mss_execute_zq_cal(i_target, port); - if(rc) return rc; - - } - - if ( (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR3) && - (dimm_type == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) ) - { - FAPI_INF("Performing LRDIMM MB-DRAM training"); - - // Execute MB-DRAM training - rc = mss_execute_lrdimm_mb_dram_training(i_target); - if (rc) return rc; - } - //executes the following to ensure that DRAMS have a good intial WR VREF DQ - //1) enter training mode w/ old value (nominal VREF DQ) - //2) set value in training mode (nominal VREF DQ) - //3) exit training mode (nominal VREF DQ) - else if(dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4) { - FAPI_INF("For DDR4, setting VREFDQ to have an initial value!!!!"); - uint8_t train_enable[2][2][4]; - uint8_t train_enable_override_on[2][2][4] ={{{ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE,ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE,ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE,ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE},{ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE,ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE,ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE,ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE}},{{ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE,ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE,ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE,ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE},{ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE,ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE,ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE,ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE}}}; - - rc = FAPI_ATTR_GET( ATTR_VREF_DQ_TRAIN_ENABLE, &i_target, train_enable); - if(rc) return rc; - - rc = FAPI_ATTR_SET(ATTR_VREF_DQ_TRAIN_ENABLE, &i_target, train_enable_override_on); - if(rc) return rc; - - //runs new values w/ train enable forces on - FAPI_INF("RUN MRS6 1ST"); - rc = mss_mrs6_DDR4( i_target); - if(rc) return rc; - FAPI_INF("RUN MRS6 2ND"); - rc = mss_mrs6_DDR4( i_target); - if(rc) return rc; - - //set old train enable value - rc = FAPI_ATTR_SET(ATTR_VREF_DQ_TRAIN_ENABLE, &i_target, train_enable); - if(rc) return rc; - - FAPI_INF("RUN MRS6 3RD"); - rc = mss_mrs6_DDR4( i_target); - if(rc) return rc; - - //sets up the DQS offset to be 16 instead of 8 - rc = mss_setup_dqs_offset(i_target); - if(rc) return rc; - } - //have to do ZQ cal, then DDR4 training mode for initial VREF setup, then do LR training - for(port = 0; port < MAX_NUM_PORT; port++) - { - - // Should only be called for DDR4 LRDIMMs, training code is in development. Does not effect any other configs - if ( (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4) && - (dimm_type == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) ) - { - rc = mss_mrep_training(i_target, port); - if(rc) return rc; - rc = mss_mxd_training(i_target,port,0); - if(rc) return rc; - } - } - } - - for(port = 0; port < MAX_NUM_PORT; port++) - { - - for(group = 0; group < MAX_NUM_GROUP; group++) - { - - //Check if rank group exists - if(primary_ranks_array[group][port] != INVALID) - { - - //Set up for Init Cal - Done per port pair - rc_num = rc_num | test_buffer_4.setBit(0, 2); //Init Cal test = 11XX - rc_num = rc_num | wen_buffer_1.flushTo1(); //Init Cal ras/cas/we = 1/1/1 - rc_num = rc_num | casn_buffer_1.flushTo1(); - rc_num = rc_num | rasn_buffer_1.flushTo1(); - rc_num = rc_num | ddr_cal_enable_buffer_1.flushTo1(); //Init cal - - FAPI_INF( "+++ Setting up Init Cal on %s Port: %d rank group: %d cal_steps: 0x%02X +++", i_target.toEcmdString(), port, group, cal_steps); - - for(cur_cal_step = 1; cur_cal_step < MAX_CAL_STEPS; cur_cal_step++) //Cycle through all possible cal steps - { - //DQS alignment workaround - max_cal_retry = 0; - - //Clearing any status or errors bits that may have occured in previous training subtest. - if(port == 0) - { - //clear status reg - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_STATUS_P0_0x8000C0190301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.clearBit(48, 4); - rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_STATUS_P0_0x8000C0190301143F, data_buffer_64); - if(rc) return rc; - - //clear error reg - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_ERROR_P0_0x8000C0180301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.clearBit(48, 11); - rc_num = rc_num | data_buffer_64.clearBit(60, 4); - rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_ERROR_P0_0x8000C0180301143F, data_buffer_64); - if(rc) return rc; - - //clear other port - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P1_0x8001C0160301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.clearBit(48); - rc_num = rc_num | data_buffer_64.clearBit(50); - rc_num = rc_num | data_buffer_64.clearBit(51); - rc_num = rc_num | data_buffer_64.clearBit(52); - rc_num = rc_num | data_buffer_64.clearBit(53); - rc_num = rc_num | data_buffer_64.clearBit(54); - rc_num = rc_num | data_buffer_64.clearBit(55); - rc_num = rc_num | data_buffer_64.clearBit(58); - rc_num = rc_num | data_buffer_64.clearBit(60); - rc_num = rc_num | data_buffer_64.clearBit(61); - rc_num = rc_num | data_buffer_64.clearBit(62); - rc_num = rc_num | data_buffer_64.clearBit(63); - rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P1_0x8001C0160301143F, data_buffer_64); - if(rc) return rc; - - //Setup the Config Reg bit for the only cal step we want - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P0_0x8000C0160301143F, data_buffer_64); - if(rc) return rc; - - } - else - { - //clear status reg - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_STATUS_P1_0x8001C0190301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.clearBit(48, 4); - rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_STATUS_P1_0x8001C0190301143F, data_buffer_64); - if(rc) return rc; - - //clear error reg - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_ERROR_P1_0x8001C0180301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.clearBit(48, 11); - rc_num = rc_num | data_buffer_64.clearBit(60, 4); - rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_ERROR_P1_0x8001C0180301143F, data_buffer_64); - if(rc) return rc; - - //clear other port - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P0_0x8000C0160301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.clearBit(48); - rc_num = rc_num | data_buffer_64.clearBit(50); - rc_num = rc_num | data_buffer_64.clearBit(51); - rc_num = rc_num | data_buffer_64.clearBit(52); - rc_num = rc_num | data_buffer_64.clearBit(53); - rc_num = rc_num | data_buffer_64.clearBit(54); - rc_num = rc_num | data_buffer_64.clearBit(55); - rc_num = rc_num | data_buffer_64.clearBit(58); - rc_num = rc_num | data_buffer_64.clearBit(60); - rc_num = rc_num | data_buffer_64.clearBit(61); - rc_num = rc_num | data_buffer_64.clearBit(62); - rc_num = rc_num | data_buffer_64.clearBit(63); - rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P0_0x8000C0160301143F, data_buffer_64); - if(rc) return rc; - - //Setup the Config Reg bit for the only cal step we want - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P1_0x8001C0160301143F, data_buffer_64); - if(rc) return rc; - - } - - //Clear training cnfg - rc_num = rc_num | data_buffer_64.clearBit(48); - rc_num = rc_num | data_buffer_64.clearBit(50); - rc_num = rc_num | data_buffer_64.clearBit(51); - rc_num = rc_num | data_buffer_64.clearBit(52); - rc_num = rc_num | data_buffer_64.clearBit(53); - rc_num = rc_num | data_buffer_64.clearBit(54); - rc_num = rc_num | data_buffer_64.clearBit(55); - rc_num = rc_num | data_buffer_64.clearBit(60); - rc_num = rc_num | data_buffer_64.clearBit(61); - rc_num = rc_num | data_buffer_64.clearBit(62); - rc_num = rc_num | data_buffer_64.clearBit(63); - - //Set stop on error - rc_num = rc_num | data_buffer_64.setBit(58); - - //cnfg rank groups - if(group == 0){ - rc_num = rc_num | data_buffer_64.setBit(60); - } - else if(group == 1){ - rc_num = rc_num | data_buffer_64.setBit(61); - } - else if(group == 2){ - rc_num = rc_num | data_buffer_64.setBit(62); - } - else if(group == 3){ - rc_num = rc_num | data_buffer_64.setBit(63); - } - - if ( (cur_cal_step == 1) && (cal_steps_8.isBitClear(0)) && (cal_steps_8.isBitClear(1)) && - (cal_steps_8.isBitClear(2)) && (cal_steps_8.isBitClear(3)) && - (cal_steps_8.isBitClear(4)) && (cal_steps_8.isBitClear(5)) && - (cal_steps_8.isBitClear(6)) && (cal_steps_8.isBitClear(7)) ) - { - FAPI_INF( "+++ Executing ALL Cal Steps at the same time on %s Port: %d rank group: %d +++", i_target.toEcmdString(), port, group); - rc_num = rc_num | data_buffer_64.setBit(48); - rc_num = rc_num | data_buffer_64.setBit(50); - rc_num = rc_num | data_buffer_64.setBit(51); - rc_num = rc_num | data_buffer_64.setBit(52); - rc_num = rc_num | data_buffer_64.setBit(53); - rc_num = rc_num | data_buffer_64.setBit(54); - rc_num = rc_num | data_buffer_64.setBit(55); - } - else if ( (cur_cal_step == 1) && (cal_steps_8.isBitSet(1)) ) - { - FAPI_INF( "+++ Write Leveling (WR_LVL) on %s Port %d rank group: %d +++", i_target.toEcmdString(), port, group); - rc_num = rc_num | data_buffer_64.setBit(48); - } - else if ( (cur_cal_step == 2) && (cal_steps_8.isBitSet(2)) ) - { - max_cal_retry = 0; - dqs_try = dqs_retry_num + 1; - FAPI_INF( "+++ DQS Align (DQS_ALIGN) attempt %d on %s Port: %d rank group: %d +++", dqs_try,i_target.toEcmdString(), port, group); - if (dqs_try == MAX_DQS_RETRY) - { - max_cal_retry = 1; - FAPI_INF( "+++ DQS Align (DQS_ALIGN) final attempt!"); - - } - rc_num = rc_num | data_buffer_64.setBit(50); - } - else if ( (cur_cal_step == 3) && (cal_steps_8.isBitSet(3)) ) - { - FAPI_INF( "+++ RD CLK Align (RDCLK_ALIGN) on %s Port: %d rank group: %d +++", i_target.toEcmdString(), port, group); - rc_num = rc_num | data_buffer_64.setBit(51); - } - else if ( (cur_cal_step == 4) && (cal_steps_8.isBitSet(4)) ) - { - FAPI_INF( "+++ Read Centering (READ_CTR) on %s Port: %d rank group: %d +++", i_target.toEcmdString(), port, group); - rc_num = rc_num | data_buffer_64.setBit(52); - } - else if ( (cur_cal_step == 5) && (cal_steps_8.isBitSet(5)) ) - { - FAPI_INF( "+++ Write Centering (WRITE_CTR) on %s Port: %d rank group: %d +++", i_target.toEcmdString(), port, group); - rc_num = rc_num | data_buffer_64.setBit(53); - } - else if ( (cur_cal_step == 6) && (cal_steps_8.isBitSet(6)) && (cal_steps_8.isBitClear(7)) ) - { - FAPI_INF( "+++ Initial Course Write (COURSE_WR) on %s Port: %d rank group: %d +++", i_target.toEcmdString(), port, group); - rc_num = rc_num | data_buffer_64.setBit(54); - } - else if ( (cur_cal_step == 6) && (cal_steps_8.isBitClear(6)) && (cal_steps_8.isBitSet(7)) ) - { - FAPI_INF( "+++ Course Read (COURSE_RD) on %s Port: %d rank group: %d +++", i_target.toEcmdString(), port, group); - rc_num = rc_num | data_buffer_64.setBit(55); - } - else if ( (cur_cal_step == 6) && (cal_steps_8.isBitSet(6)) && (cal_steps_8.isBitSet(7)) ) - { - FAPI_INF( "+++ Initial Course Write (COURSE_WR) and Course Read (COURSE_RD) simultaneously on %s Port: %d rank group: %d +++", i_target.toEcmdString(), port, group); - rc_num = rc_num | data_buffer_64.setBit(54); - rc_num = rc_num | data_buffer_64.setBit(55); - } - - if(rc_num) - { - rc.setEcmdError(rc_num); - return rc; - } - - if ( !( data_buffer_64.isBitClear(48, 8) ) ) // Only execute if we are doing a Cal Step - { - - // Before WR_LVL --- Change the RTT_NOM to RTT_WR pre-WR_LVL - if ( (cur_cal_step == 1) && (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR3)) - { - if ( dimm_type != fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM ) - { - - dram_rtt_nom_original = 0xFF; - rc = mss_rtt_nom_rtt_wr_swap(i_target, - mbaPosition, - port, - primary_ranks_array[group][port], - group, - instruction_number, - dram_rtt_nom_original); - if(rc) return rc; - } - } - // Should only be called for DDR4 LRDIMMs, training code is in development. Does not effect any other configs - else if ( (group == 0) && (cur_cal_step == 1) - && (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4) - && (dimm_type == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) ) - { - rc = mss_dram_write_leveling(i_target, port); - if(rc) return rc; - } - - //Set the config register - if(port == 0) - { - rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P0_0x8000C0160301143F, data_buffer_64); - if(rc) return rc; - } - else - { - rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P1_0x8001C0160301143F, data_buffer_64); - if(rc) return rc; - } - - rc = mss_ccs_inst_arry_0(i_target, - instruction_number, - address_buffer_16, - bank_buffer_8, - activate_buffer_1, - rasn_buffer_1, - casn_buffer_1, - wen_buffer_1, - cke_buffer_8, - csn_buffer_8, - odt_buffer_8, - test_buffer_4, - port); - - if(rc) return rc; //Error handling for mss_ccs_inst built into mss_funcs - - FAPI_INF( "primary_ranks_array[%d][0]: %d [%d][1]: %d", group, primary_ranks_array[group][0], group, primary_ranks_array[group][1]); - - - rc_num = rc_num | rank_cal_buffer_4.insert(primary_ranks_array[group][port], 0, 4, 4); // 8 bit storage, need last 4 bits - if(rc_num) - { - rc.setEcmdError(rc_num); - return rc; - } - - rc = mss_ccs_inst_arry_1(i_target, - instruction_number, - num_idles_buffer_16, - num_repeat_buffer_16, - data_buffer_20, - read_compare_buffer_1, - rank_cal_buffer_4, - ddr_cal_enable_buffer_1, - ccs_end_buffer_1); - - if(rc) return rc; //Error handling for mss_ccs_inst built into mss_funcs - - - rc = mss_execute_ccs_inst_array( i_target, NUM_POLL, 60); - if(rc) return rc; //Error handling for mss_ccs_inst built into mss_funcs - - //Check to see if the training completes - rc = mss_check_cal_status(i_target, mbaPosition, port, group, cur_complete_status); - if(rc) return rc; - - if (cur_complete_status == MSS_INIT_CAL_STALL) - { - complete_status = cur_complete_status; - } - - //Check to see if the training errored out - rc = mss_check_error_status(i_target, mbaPosition, port, group, cur_cal_step, cur_error_status, max_cal_retry); - if(rc) return rc; - - if (cur_error_status == MSS_INIT_CAL_FAIL) - { - error_status = cur_error_status; - - } - - // Following WR_LVL -- Restore RTT_NOM to orignal value post-wr_lvl - if ((cur_cal_step == 1) && (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR3)) - { - if ( dimm_type != fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM ) - { - - rc = mss_rtt_nom_rtt_wr_swap(i_target, - mbaPosition, - port, - primary_ranks_array[group][port], - group, - instruction_number, - dram_rtt_nom_original); - if(rc) return rc; - } - } - - // Following Read Centering -- Enter into READ CENTERING WORKAROUND - if ( (cur_cal_step == 4) && - ( waterfall_broken == fapi::ENUM_ATTR_MSS_BLUEWATERFALL_BROKEN_TRUE ) ) - { - rc = mss_read_center_workaround(i_target, mbaPosition, port, group); - if(rc) return rc; - } - - // DQS Alignment workaround - if (cur_cal_step == 2) - { - // Because the DQS cal step failed we need to rerun the step and clear out any bad bits - if (cur_error_status == MSS_INIT_CAL_FAIL) - { - - if (dqs_try < MAX_DQS_RETRY) - { - dqs_retry_num++; - cur_cal_step-- ; - for(delay_loop_cnt = 1; delay_loop_cnt <= DELAY_LOOP; delay_loop_cnt++) - { - rc = fapiDelay(DELAY_0P5S, DELAY_SIM500); - if(rc) return rc; - } - delay_loop_cnt = 0; - } - else if (dqs_try == MAX_DQS_RETRY) - { - dqs_retry_num = 0; - } - } - //If the DQS cal step passes on a retry, we need to reset the error status to a pass. - else if (cur_error_status == MSS_INIT_CAL_PASS) - { - if (dqs_try > 1) - { - error_status = MSS_INIT_CAL_PASS; - dqs_retry_num = 0; - } - - dqs_retry_num = 0; - - } - - } - - - } - }//end of step loop - } - }//end of group loop - }//end of port loop - - // Make sure the DQS_CLK values of each byte have matching nibble values, using the lowest - if ( waterfall_broken == fapi::ENUM_ATTR_MSS_BLUEWATERFALL_BROKEN_TRUE ) - { - rc = mss_read_center_second_workaround(i_target); - if(rc) return rc; - } - - if ((error_status != MSS_INIT_CAL_FAIL) && (error_status != MSS_INIT_CAL_STALL)) - { - training_success = 0xFF; - } - - rc = mss_get_bbm_regs(i_target, training_success); - if(rc) - { - FAPI_ERR( "Error Moving bad bit information from the Phy regs. Exiting."); - return rc; - } - - //Executes if we do "all at once" or on the last cal steps - //Must be a successful run. - if (error_status == MSS_INIT_CAL_PASS && - ((cal_steps_8.isBitSet(6) && cal_steps_8.isBitSet(7)) || - (cal_steps_8.isBitClear(0) && cal_steps_8.isBitClear(1) && - cal_steps_8.isBitClear(2) && cal_steps_8.isBitClear(3) && - cal_steps_8.isBitClear(4) && cal_steps_8.isBitClear(5) && - cal_steps_8.isBitClear(6) && cal_steps_8.isBitClear(7) ) ) ) - { - - FAPI_INF( "WR LVL DISABLE WORKAROUND: Running wr_lvl workaround on %s", i_target.toEcmdString()); - rc = mss_wr_lvl_disable_workaround(i_target); - if(rc) return rc; - } - - - // If we hit either of these States, the error callout originates from Mike Jones Bad Bit code. - if (complete_status == MSS_INIT_CAL_STALL) - { - FAPI_ERR( "+++ Partial/Full calibration stall. Check Debug trace. +++"); - } - else if (error_status == MSS_INIT_CAL_FAIL) - { - FAPI_ERR( "+++ Partial/Full calibration fail. Check Debug trace. +++"); - } - else - { - FAPI_INF( "+++ Full calibration successful. +++"); - } - - return rc; -} - -ReturnCode mss_check_cal_status( Target& i_target, - uint8_t i_mbaPosition, - uint8_t i_port, - uint8_t i_group, - mss_draminit_training_result& io_status - ) -{ - ecmdDataBufferBase cal_status_buffer_64(64); - - uint8_t poll_count = 1; - uint32_t cal_status_reg_offset; - - cal_status_reg_offset = 48 + i_group; - - ReturnCode rc; - - if(i_port == 0) - { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_STATUS_P0_0x8000C0190301143F, cal_status_buffer_64); - if(rc) return rc; - } - else - { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_STATUS_P1_0x8001C0190301143F, cal_status_buffer_64); - if(rc) return rc; - } - - while((!cal_status_buffer_64.isBitSet(cal_status_reg_offset)) && - (poll_count <= 20)) - { - FAPI_INF( "+++ Calibration on %s port: %d rank group: %d in progress. Poll count: %d +++", i_target.toEcmdString(), i_port, i_group, poll_count); - - poll_count++; - if(i_port == 0) - { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_STATUS_P0_0x8000C0190301143F, cal_status_buffer_64); - if(rc) return rc; - } - else - { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_STATUS_P1_0x8001C0190301143F, cal_status_buffer_64); - if(rc) return rc; - } - - } - - if(cal_status_buffer_64.isBitSet(cal_status_reg_offset)) - { - FAPI_INF( "+++ Calibration on %s port: %d rank group: %d finished. +++", i_target.toEcmdString(), i_port, i_group); - io_status = MSS_INIT_CAL_COMPLETE; - } - else - { - FAPI_ERR( "+++ Calibration on %s port: %d rank group: %d has stalled! +++", i_target.toEcmdString(), i_port, i_group); - io_status = MSS_INIT_CAL_STALL; - } - - return rc; -} - - - -ReturnCode mss_check_error_status( Target& i_target, - uint8_t i_mbaPosition, - uint8_t i_port, - uint8_t i_group, - uint8_t cur_cal_step, - mss_draminit_training_result& io_status, - uint8_t i_max_cal_retry - ) -{ - - ecmdDataBufferBase cal_error_buffer_64(64); - ReturnCode rc; - - uint8_t MBA_POSITION; - uint8_t PORT_POSITION; - uint8_t RANKGROUP_POSITION; - - if(i_port == 0) - { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_ERROR_P0_0x8000C0180301143F, cal_error_buffer_64); - if(rc) return rc; - } - else - { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_ERROR_P1_0x8001C0180301143F, cal_error_buffer_64); - if(rc) return rc; - } - - if((cal_error_buffer_64.isBitSet(60)) || (cal_error_buffer_64.isBitSet(61)) || (cal_error_buffer_64.isBitSet(62)) || (cal_error_buffer_64.isBitSet(63))) - { - io_status = MSS_INIT_CAL_FAIL; - - if(cal_error_buffer_64.isBitSet(48)) - { - FAPI_ERR( "+++ Write leveling error occured on %s port: %d rank group: %d! +++", i_target.toEcmdString(), i_port, i_group); - const fapi::Target & TARGET_MBA_ERROR = i_target; - MBA_POSITION = i_mbaPosition; - PORT_POSITION = i_port; - RANKGROUP_POSITION = i_group; - FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_WR_LVL_ERROR); - fapiLogError(rc, FAPI_ERRL_SEV_RECOVERED); - rc = FAPI_RC_SUCCESS; - } - if(cal_error_buffer_64.isBitSet(50)) - { - FAPI_ERR( "+++ DQS Alignment error occured on %s port: %d rank group: %d! +++", i_target.toEcmdString(), i_port, i_group); - const fapi::Target & TARGET_MBA_ERROR = i_target; - MBA_POSITION = i_mbaPosition; - PORT_POSITION = i_port; - RANKGROUP_POSITION = i_group; - - // Error Callout ByPass for Work Around: - //FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_DQS_ALIGNMENT_ERROR); - //fapiLogError(rc, FAPI_ERRL_SEV_RECOVERED); - //rc = FAPI_RC_SUCCESS; - - // DQS Alignment Work Around: - if (i_max_cal_retry == 0) - { - FAPI_INF( "+++ DQS Alignment recovery attempt on %s port: %d rank group: %d! +++", i_target.toEcmdString(), i_port, i_group); - uint64_t disable_bit_addr_for_dp18_0 = 0; - uint64_t disable_bit_addr_for_dp18_1 = 0; - uint64_t disable_bit_addr_for_dp18_2 = 0; - uint64_t disable_bit_addr_for_dp18_3 = 0; - uint64_t disable_bit_addr_for_dp18_4 = 0; - if (i_port == 0) { - if (i_group == 0) { - disable_bit_addr_for_dp18_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_0_0x8000007c0301143F; - disable_bit_addr_for_dp18_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_1_0x8000047c0301143F; - disable_bit_addr_for_dp18_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_2_0x8000087c0301143F; - disable_bit_addr_for_dp18_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_3_0x80000c7c0301143F; - disable_bit_addr_for_dp18_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_4_0x8000107c0301143F; - } else if (i_group == 1) { - disable_bit_addr_for_dp18_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_0_0x8000017c0301143F; - disable_bit_addr_for_dp18_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_1_0x8000057c0301143F; - disable_bit_addr_for_dp18_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_2_0x8000097c0301143F; - disable_bit_addr_for_dp18_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_3_0x80000d7c0301143F; - disable_bit_addr_for_dp18_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_4_0x8000117c0301143F; - } else if (i_group == 2) { - disable_bit_addr_for_dp18_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_0_0x8000027c0301143F; - disable_bit_addr_for_dp18_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_1_0x8000067c0301143F; - disable_bit_addr_for_dp18_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_2_0x80000a7c0301143F; - disable_bit_addr_for_dp18_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_3_0x80000e7c0301143F; - disable_bit_addr_for_dp18_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_4_0x8000127c0301143F; - } else if (i_group == 3) { - disable_bit_addr_for_dp18_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_0_0x8000037c0301143F; - disable_bit_addr_for_dp18_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_1_0x8000077c0301143F; - disable_bit_addr_for_dp18_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_2_0x80000b7c0301143F; - disable_bit_addr_for_dp18_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_3_0x80000f7c0301143F; - disable_bit_addr_for_dp18_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_4_0x8000137c0301143F; - } else { - FAPI_ERR( "+++ DQS Alignment Recovery error occured on %s port: %d rank group: %d! +++", i_target.toEcmdString(), i_port, i_group); - FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_DQS_ALIGNMENT_ERROR); - fapiLogError(rc, FAPI_ERRL_SEV_RECOVERED); - rc = FAPI_RC_SUCCESS; - } - } else if (i_port == 1) { - if (i_group == 0) { - disable_bit_addr_for_dp18_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_0_0x8001007c0301143F; disable_bit_addr_for_dp18_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_1_0x8001047c0301143F; - disable_bit_addr_for_dp18_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_2_0x8001087c0301143F; - disable_bit_addr_for_dp18_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_3_0x80010c7c0301143F; - disable_bit_addr_for_dp18_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_4_0x8001107c0301143F; - } else if (i_group == 1) { - disable_bit_addr_for_dp18_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_0_0x8001017c0301143F; - disable_bit_addr_for_dp18_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_1_0x8001057c0301143F; disable_bit_addr_for_dp18_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_2_0x8001097c0301143F; - disable_bit_addr_for_dp18_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_3_0x80010d7c0301143F; - disable_bit_addr_for_dp18_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_4_0x8001117c0301143F; - } else if (i_group == 2) { - disable_bit_addr_for_dp18_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_0_0x8001027c0301143F; - disable_bit_addr_for_dp18_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_1_0x8001067c0301143F; - disable_bit_addr_for_dp18_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_2_0x80010a7c0301143F; - disable_bit_addr_for_dp18_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_3_0x80010e7c0301143F; - disable_bit_addr_for_dp18_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_4_0x8001127c0301143F; - } else if (i_group == 3) { - disable_bit_addr_for_dp18_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_0_0x8001037c0301143F; - disable_bit_addr_for_dp18_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_1_0x8001077c0301143F; - disable_bit_addr_for_dp18_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_2_0x80010b7c0301143F; - disable_bit_addr_for_dp18_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_3_0x80010f7c0301143F; - disable_bit_addr_for_dp18_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_4_0x8001137c0301143F; - } else { - FAPI_ERR( "+++ DQS Alignment Recovery error occured on %s port: %d rank group: %d! +++", i_target.toEcmdString(), i_port, i_group); - FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_DQS_ALIGNMENT_ERROR); - fapiLogError(rc, FAPI_ERRL_SEV_RECOVERED); - rc = FAPI_RC_SUCCESS; - } - } else { - FAPI_ERR( "+++ DQS Alignment Recovery error occured on %s port: %d rank group: %d! +++", i_target.toEcmdString(), i_port, i_group); - FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_DQS_ALIGNMENT_ERROR); - fapiLogError(rc, FAPI_ERRL_SEV_RECOVERED); - rc = FAPI_RC_SUCCESS; - } - ecmdDataBufferBase disable_bit_data_for_dp18_buffer_64(64); - disable_bit_data_for_dp18_buffer_64.flushTo0(); - rc = fapiPutScom(i_target, disable_bit_addr_for_dp18_0, disable_bit_data_for_dp18_buffer_64); if(rc) return rc; - rc = fapiPutScom(i_target, disable_bit_addr_for_dp18_1, disable_bit_data_for_dp18_buffer_64); if(rc) return rc; - rc = fapiPutScom(i_target, disable_bit_addr_for_dp18_2, disable_bit_data_for_dp18_buffer_64); if(rc) return rc; - rc = fapiPutScom(i_target, disable_bit_addr_for_dp18_3, disable_bit_data_for_dp18_buffer_64); if(rc) return rc; - rc = fapiPutScom(i_target, disable_bit_addr_for_dp18_4, disable_bit_data_for_dp18_buffer_64); if(rc) return rc; - } else { - FAPI_ERR( "+++ DQS Alignment Recovery error occured on %s port: %d rank group: %d! +++", i_target.toEcmdString(), i_port, i_group); - FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_DQS_ALIGNMENT_ERROR); - fapiLogError(rc, FAPI_ERRL_SEV_RECOVERED); - rc = FAPI_RC_SUCCESS; - } - - } - if(cal_error_buffer_64.isBitSet(51)) - { - FAPI_ERR( "+++ RDCLK to SysClk alignment error occured on %s port: %d rank group: %d! +++", i_target.toEcmdString(), i_port, i_group); - const fapi::Target & TARGET_MBA_ERROR = i_target; - MBA_POSITION = i_mbaPosition; - PORT_POSITION = i_port; - RANKGROUP_POSITION = i_group; - FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_RD_CLK_SYS_CLK_ALIGNMENT_ERROR); - fapiLogError(rc, FAPI_ERRL_SEV_RECOVERED); - rc = FAPI_RC_SUCCESS; - } - if(cal_error_buffer_64.isBitSet(52)) - { - FAPI_ERR( "+++ Read centering error occured on %s port: %d rank group: %d! +++", i_target.toEcmdString(), i_port, i_group); - const fapi::Target & TARGET_MBA_ERROR = i_target; - MBA_POSITION = i_mbaPosition; - PORT_POSITION = i_port; - RANKGROUP_POSITION = i_group; - FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_RD_CENTERING_ERROR); - fapiLogError(rc, FAPI_ERRL_SEV_RECOVERED); - rc = FAPI_RC_SUCCESS; - } - if(cal_error_buffer_64.isBitSet(53)) - { - FAPI_ERR( "+++ Write centering error occured on %s port: %d rank group: %d! +++", i_target.toEcmdString(), i_port, i_group); - const fapi::Target & TARGET_MBA_ERROR = i_target; - MBA_POSITION = i_mbaPosition; - PORT_POSITION = i_port; - RANKGROUP_POSITION = i_group; - FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_WR_CENTERING_ERROR); - fapiLogError(rc, FAPI_ERRL_SEV_RECOVERED); - rc = FAPI_RC_SUCCESS; - } - if(cal_error_buffer_64.isBitSet(55)) - { - FAPI_ERR( "+++ Coarse read centering error occured on %s port: %d rank group: %d! +++", i_target.toEcmdString(), i_port, i_group); - const fapi::Target & TARGET_MBA_ERROR = i_target; - MBA_POSITION = i_mbaPosition; - PORT_POSITION = i_port; - RANKGROUP_POSITION = i_group; - FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_COURSE_RD_CENTERING_ERROR); - fapiLogError(rc, FAPI_ERRL_SEV_RECOVERED); - rc = FAPI_RC_SUCCESS; - } - if(cal_error_buffer_64.isBitSet(56)) - { - FAPI_ERR( "+++ Custom pattern read centering error occured on %s port: %d rank group: %d! +++", i_target.toEcmdString(), i_port, i_group); - const fapi::Target & TARGET_MBA_ERROR = i_target; - MBA_POSITION = i_mbaPosition; - PORT_POSITION = i_port; - RANKGROUP_POSITION = i_group; - FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_CUSTOM_PATTERN_RD_CENTERING_ERROR); - fapiLogError(rc, FAPI_ERRL_SEV_RECOVERED); - rc = FAPI_RC_SUCCESS; - } - if(cal_error_buffer_64.isBitSet(57)) - { - FAPI_ERR( "+++ Custom pattern write centering error occured on %s port: %d rank group: %d! +++", i_target.toEcmdString(), i_port, i_group); - const fapi::Target & TARGET_MBA_ERROR = i_target; - MBA_POSITION = i_mbaPosition; - PORT_POSITION = i_port; - RANKGROUP_POSITION = i_group; - FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_CUSTOM_PATTERN_WR_CENTERING_ERROR); - fapiLogError(rc, FAPI_ERRL_SEV_RECOVERED); - rc = FAPI_RC_SUCCESS; - } - if(cal_error_buffer_64.isBitSet(58)) - { - FAPI_ERR( "+++ Digital eye error occured on %s port: %d rank group: %d! +++", i_target.toEcmdString(), i_port, i_group); - const fapi::Target & TARGET_MBA_ERROR = i_target; - MBA_POSITION = i_mbaPosition; - PORT_POSITION = i_port; - RANKGROUP_POSITION = i_group; - FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_DIGITAL_EYE_ERROR); - fapiLogError(rc, FAPI_ERRL_SEV_RECOVERED); - rc = FAPI_RC_SUCCESS; - } - } - else - { - if (cur_cal_step == 1) - { - FAPI_INF( "+++ Write_leveling on %s port: %d rank group: %d was successful. +++", i_target.toEcmdString(), i_port, i_group); - } - else if (cur_cal_step == 2) - { - FAPI_INF( "+++ DQS Alignment on %s port: %d rank group: %d was successful. +++", i_target.toEcmdString(), i_port, i_group); - } - else if (cur_cal_step == 3) - { - FAPI_INF( "+++ RDCLK to SysClk alignment on %s port: %d rank group: %d was successful. +++", i_target.toEcmdString(), i_port, i_group); - } - else if (cur_cal_step == 4) - { - FAPI_INF( "+++ Read Centering on %s port: %d rank group: %d was successful. +++", i_target.toEcmdString(), i_port, i_group); - } - else if (cur_cal_step == 5) - { - FAPI_INF( "+++ Write Centering on %s port: %d rank group: %d was successful. +++", i_target.toEcmdString(), i_port, i_group); - } - else if (cur_cal_step == 6) - { - FAPI_INF( "+++ Course Read and/or Course Write on %s port: %d rank group: %d was successful. +++", i_target.toEcmdString(), i_port, i_group); - } - - io_status = MSS_INIT_CAL_PASS; - } - - return rc; -} - - - - - - - -ReturnCode mss_read_center_workaround( - Target& i_target, - uint8_t i_mbaPosition, - uint32_t i_port, - uint32_t i_rank_group - ) -{ - - ReturnCode rc; - uint32_t rc_num = 0; - ecmdDataBufferBase data_buffer_64(64); - - - uint64_t DQSCLK_RD_PHASE_ADDR_0 = 0; - uint64_t DQSCLK_RD_PHASE_ADDR_1 = 0; - uint64_t DQSCLK_RD_PHASE_ADDR_2 = 0; - uint64_t DQSCLK_RD_PHASE_ADDR_3 = 0; - uint64_t DQSCLK_RD_PHASE_ADDR_4 = 0; - uint64_t RD_TIMING_REF0_ADDR_0 = 0; - uint64_t RD_TIMING_REF0_ADDR_1 = 0; - uint64_t RD_TIMING_REF0_ADDR_2 = 0; - uint64_t RD_TIMING_REF0_ADDR_3 = 0; - uint64_t RD_TIMING_REF0_ADDR_4 = 0; - uint64_t RD_TIMING_REF1_ADDR_0 = 0; - uint64_t RD_TIMING_REF1_ADDR_1 = 0; - uint64_t RD_TIMING_REF1_ADDR_2 = 0; - uint64_t RD_TIMING_REF1_ADDR_3 = 0; - uint64_t RD_TIMING_REF1_ADDR_4 = 0; - uint8_t l_value_u8 = 0; - uint8_t l_new_value_u8 = 0; - uint8_t quad0_workaround_type = 2; - uint8_t quad1_workaround_type = 2; - uint8_t quad2_workaround_type = 2; - uint8_t quad3_workaround_type = 2; - uint8_t dqs_clk_increment_wa0 = 0; - uint8_t dqs_clk_increment_wa1 = 3; - uint8_t dqs_clk_increment_wa2 = 2; - uint8_t read_phase_value_wa0 = 0; - uint8_t read_phase_value_wa1 = 0; - uint8_t read_phase_value_wa2 = 0; - uint8_t dqs_clk_increment_quad0 = 2; - uint8_t dqs_clk_increment_quad1 = 2; - uint8_t dqs_clk_increment_quad2 = 2; - uint8_t dqs_clk_increment_quad3 = 2; - uint8_t read_phase_value_quad0 = 0; - uint8_t read_phase_value_quad1 = 0; - uint8_t read_phase_value_quad2 = 0; - uint8_t read_phase_value_quad3 = 0; - uint8_t l_timing_ref_quad0 = 0; - uint8_t l_timing_ref_quad1 = 0; - uint8_t l_timing_ref_quad2 = 0; - uint8_t l_timing_ref_quad3 = 0; - - FAPI_INF( "+++ Read Centering Workaround on %s Port: %d rank group: %d +++", i_target.toEcmdString(), i_port, i_rank_group); - FAPI_INF( "+++ Choosing New RD PHASE SELECT values based on timing values. +++"); - FAPI_INF( "+++ Incrementing DQS CLK PHASE SELECT regs based on timing values. +++"); - - if ( i_port == 0 ) - { - - RD_TIMING_REF0_ADDR_0 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE0_P0_0_0x800000700301143F; - RD_TIMING_REF0_ADDR_1 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE0_P0_1_0x800004700301143F; - RD_TIMING_REF0_ADDR_2 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE0_P0_2_0x800008700301143F; - RD_TIMING_REF0_ADDR_3 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE0_P0_3_0x80000C700301143F; - RD_TIMING_REF0_ADDR_4 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE0_P0_4_0x800010700301143F; - RD_TIMING_REF1_ADDR_0 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE1_P0_0_0x800000710301143F; - RD_TIMING_REF1_ADDR_1 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE1_P0_1_0x800004710301143F; - RD_TIMING_REF1_ADDR_2 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE1_P0_2_0x800008710301143F; - RD_TIMING_REF1_ADDR_3 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE1_P0_3_0x80000C710301143F; - RD_TIMING_REF1_ADDR_4 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE1_P0_4_0x800010710301143F; - - if ( i_rank_group == 0 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_0x800000090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_0x800004090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_0x800008090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_0x80000C090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_0x800010090301143F; - - } - else if ( i_rank_group == 1 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_0x800001090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_0x800005090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_0x800009090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_0x80000D090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_0x800011090301143F; - - } - else if ( i_rank_group == 2 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_0x800002090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_0x800006090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_0x80000A090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_0x80000E090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_0x800012090301143F; - - } - else if ( i_rank_group == 3 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_0x800003090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_0x800007090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_0x80000B090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_0x80000F090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_0x800013090301143F; - - } - } - else if (i_port == 1 ) - { - - RD_TIMING_REF0_ADDR_0 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE0_P1_0_0x800100700301143F; - RD_TIMING_REF0_ADDR_1 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE0_P1_1_0x800104700301143F; - RD_TIMING_REF0_ADDR_2 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE0_P1_2_0x800108700301143F; - RD_TIMING_REF0_ADDR_3 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE0_P1_3_0x80010C700301143F; - RD_TIMING_REF0_ADDR_4 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE0_P1_4_0x800110700301143F; - RD_TIMING_REF1_ADDR_0 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE1_P1_0_0x800100710301143F; - RD_TIMING_REF1_ADDR_1 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE1_P1_1_0x800104710301143F; - RD_TIMING_REF1_ADDR_2 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE1_P1_2_0x800108710301143F; - RD_TIMING_REF1_ADDR_3 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE1_P1_3_0x80010C710301143F; - RD_TIMING_REF1_ADDR_4 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE1_P1_4_0x800110710301143F; - - if ( i_rank_group == 0 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_0_0x800100090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_1_0x800104090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_2_0x800108090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_3_0x80010C090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_4_0x800110090301143F; - - } - else if ( i_rank_group == 1 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_0_0x800101090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_1_0x800105090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_2_0x800109090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_3_0x80010D090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_4_0x800111090301143F; - - - } - else if ( i_rank_group == 2 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_0_0x800102090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_1_0x800106090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_2_0x80010A090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_3_0x80010E090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_4_0x800112090301143F; - - } - else if ( i_rank_group == 3 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_0_0x800103090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_1_0x800107090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_2_0x80010B090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_3_0x80010F090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_4_0x800113090301143F; - - } - } - - //Block 0 - rc = fapiGetScom(i_target, RD_TIMING_REF0_ADDR_0, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.extractToRight(&l_timing_ref_quad0, 49, 7); - rc_num = rc_num | data_buffer_64.extractToRight(&l_timing_ref_quad1, 57, 7); - rc = fapiGetScom(i_target, RD_TIMING_REF1_ADDR_0, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.extractToRight(&l_timing_ref_quad2, 49, 7); - rc_num = rc_num | data_buffer_64.extractToRight(&l_timing_ref_quad3, 57, 7); - - if(rc_num) - { - rc.setEcmdError(rc_num); - return rc; - } - - if ( quad0_workaround_type == 0 ) - { - dqs_clk_increment_quad0 = dqs_clk_increment_wa0; - read_phase_value_quad0 = read_phase_value_wa0; - } - else if ( quad0_workaround_type == 1 ) - { - dqs_clk_increment_quad0 = dqs_clk_increment_wa1; - read_phase_value_quad0 = read_phase_value_wa1; - } - else if ( quad0_workaround_type == 2 ) - { - dqs_clk_increment_quad0 = dqs_clk_increment_wa2; - read_phase_value_quad0 = read_phase_value_wa2; - } - FAPI_INF( "+++ ALL Blocks ALL Quads using workaround number %d with dqs_clk_increment: %d read_phase_value: %d +++", quad0_workaround_type, dqs_clk_increment_quad0, read_phase_value_quad0); - - if ( quad1_workaround_type == 0 ) - { - dqs_clk_increment_quad1 = dqs_clk_increment_wa0; - read_phase_value_quad1 = read_phase_value_wa0; - } - else if ( quad1_workaround_type == 1 ) - { - dqs_clk_increment_quad1 = dqs_clk_increment_wa1; - read_phase_value_quad1 = read_phase_value_wa1; - } - else if ( quad1_workaround_type == 2 ) - { - dqs_clk_increment_quad1 = dqs_clk_increment_wa2; - read_phase_value_quad1 = read_phase_value_wa2; - } - - if ( quad2_workaround_type == 0 ) - { - dqs_clk_increment_quad2 = dqs_clk_increment_wa0; - read_phase_value_quad2 = read_phase_value_wa0; - } - else if ( quad2_workaround_type == 1 ) - { - dqs_clk_increment_quad2 = dqs_clk_increment_wa1; - read_phase_value_quad2 = read_phase_value_wa1; - } - else if ( quad2_workaround_type == 2 ) - { - dqs_clk_increment_quad2 = dqs_clk_increment_wa2; - read_phase_value_quad2 = read_phase_value_wa2; - } - - if ( quad3_workaround_type == 0 ) - { - dqs_clk_increment_quad3 = dqs_clk_increment_wa0; - read_phase_value_quad3 = read_phase_value_wa0; - } - else if ( quad3_workaround_type == 1 ) - { - dqs_clk_increment_quad3 = dqs_clk_increment_wa1; - read_phase_value_quad3 = read_phase_value_wa1; - } - else if ( quad3_workaround_type == 2 ) - { - dqs_clk_increment_quad3 = dqs_clk_increment_wa2; - read_phase_value_quad3 = read_phase_value_wa2; - } - - rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_0, data_buffer_64); - if (rc) return rc; - - // Set Read Phase. - rc_num = rc_num | data_buffer_64.insertFromRight(read_phase_value_quad0, 50, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(read_phase_value_quad1, 54, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(read_phase_value_quad2, 58, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(read_phase_value_quad3, 62, 2); - - //Increment dqs clk. 4 is the limit, wrap around (IE 5 = 1, 6 = 2) - l_value_u8 = 0; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_u8, 48, 2); - l_new_value_u8 = (l_value_u8 + dqs_clk_increment_quad0) % 4; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_new_value_u8, 48, 2); - l_value_u8 = 0; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_u8, 52, 2); - l_new_value_u8 = (l_value_u8 + dqs_clk_increment_quad1) % 4; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_new_value_u8, 52, 2); - l_value_u8 = 0; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_u8, 56, 2); - l_new_value_u8 = (l_value_u8 + dqs_clk_increment_quad2) % 4; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_new_value_u8, 56, 2); - l_value_u8 = 0; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_u8, 60, 2); - l_new_value_u8 = (l_value_u8 + dqs_clk_increment_quad3) % 4; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_new_value_u8, 60, 2); - - rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_0, data_buffer_64); - if (rc) return rc; - - //Block 1 - rc = fapiGetScom(i_target, RD_TIMING_REF0_ADDR_1, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.extractToRight(&l_timing_ref_quad0, 49, 7); - rc_num = rc_num | data_buffer_64.extractToRight(&l_timing_ref_quad1, 57, 7); - rc = fapiGetScom(i_target, RD_TIMING_REF1_ADDR_1, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.extractToRight(&l_timing_ref_quad2, 49, 7); - rc_num = rc_num | data_buffer_64.extractToRight(&l_timing_ref_quad3, 57, 7); - - if(rc_num) - { - rc.setEcmdError(rc_num); - return rc; - } - - if ( quad0_workaround_type == 0 ) - { - dqs_clk_increment_quad0 = dqs_clk_increment_wa0; - read_phase_value_quad0 = read_phase_value_wa0; - } - else if ( quad0_workaround_type == 1 ) - { - dqs_clk_increment_quad0 = dqs_clk_increment_wa1; - read_phase_value_quad0 = read_phase_value_wa1; - } - else if ( quad0_workaround_type == 2 ) - { - dqs_clk_increment_quad0 = dqs_clk_increment_wa2; - read_phase_value_quad0 = read_phase_value_wa2; - } - - if ( quad1_workaround_type == 0 ) - { - dqs_clk_increment_quad1 = dqs_clk_increment_wa0; - read_phase_value_quad1 = read_phase_value_wa0; - } - else if ( quad1_workaround_type == 1 ) - { - dqs_clk_increment_quad1 = dqs_clk_increment_wa1; - read_phase_value_quad1 = read_phase_value_wa1; - } - else if ( quad1_workaround_type == 2 ) - { - dqs_clk_increment_quad1 = dqs_clk_increment_wa2; - read_phase_value_quad1 = read_phase_value_wa2; - } - - if ( quad2_workaround_type == 0 ) - { - dqs_clk_increment_quad2 = dqs_clk_increment_wa0; - read_phase_value_quad2 = read_phase_value_wa0; - } - else if ( quad2_workaround_type == 1 ) - { - dqs_clk_increment_quad2 = dqs_clk_increment_wa1; - read_phase_value_quad2 = read_phase_value_wa1; - } - else if ( quad2_workaround_type == 2 ) - { - dqs_clk_increment_quad2 = dqs_clk_increment_wa2; - read_phase_value_quad2 = read_phase_value_wa2; - } - - if ( quad3_workaround_type == 0 ) - { - dqs_clk_increment_quad3 = dqs_clk_increment_wa0; - read_phase_value_quad3 = read_phase_value_wa0; - } - else if ( quad3_workaround_type == 1 ) - { - dqs_clk_increment_quad3 = dqs_clk_increment_wa1; - read_phase_value_quad3 = read_phase_value_wa1; - } - else if ( quad3_workaround_type == 2 ) - { - dqs_clk_increment_quad3 = dqs_clk_increment_wa2; - read_phase_value_quad3 = read_phase_value_wa2; - } - - - rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_1, data_buffer_64); - if (rc) return rc; - - // Set Read Phase. - rc_num = rc_num | data_buffer_64.insertFromRight(read_phase_value_quad0, 50, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(read_phase_value_quad1, 54, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(read_phase_value_quad2, 58, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(read_phase_value_quad3, 62, 2); - - //Increment dqs clk. 4 is the limit, wrap around (IE 5 = 1, 6 = 2) - l_value_u8 = 0; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_u8, 48, 2); - l_new_value_u8 = (l_value_u8 + dqs_clk_increment_quad0) % 4; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_new_value_u8, 48, 2); - l_value_u8 = 0; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_u8, 52, 2); - l_new_value_u8 = (l_value_u8 + dqs_clk_increment_quad1) % 4; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_new_value_u8, 52, 2); - l_value_u8 = 0; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_u8, 56, 2); - l_new_value_u8 = (l_value_u8 + dqs_clk_increment_quad2) % 4; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_new_value_u8, 56, 2); - l_value_u8 = 0; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_u8, 60, 2); - l_new_value_u8 = (l_value_u8 + dqs_clk_increment_quad3) % 4; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_new_value_u8, 60, 2); - - rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_1, data_buffer_64); - if (rc) return rc; - - //Block 2 - rc = fapiGetScom(i_target, RD_TIMING_REF0_ADDR_2, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.extractToRight(&l_timing_ref_quad0, 49, 7); - rc_num = rc_num | data_buffer_64.extractToRight(&l_timing_ref_quad1, 57, 7); - rc = fapiGetScom(i_target, RD_TIMING_REF1_ADDR_2, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.extractToRight(&l_timing_ref_quad2, 49, 7); - rc_num = rc_num | data_buffer_64.extractToRight(&l_timing_ref_quad3, 57, 7); - - if(rc_num) - { - rc.setEcmdError(rc_num); - return rc; - } - - if ( quad0_workaround_type == 0 ) - { - dqs_clk_increment_quad0 = dqs_clk_increment_wa0; - read_phase_value_quad0 = read_phase_value_wa0; - } - else if ( quad0_workaround_type == 1 ) - { - dqs_clk_increment_quad0 = dqs_clk_increment_wa1; - read_phase_value_quad0 = read_phase_value_wa1; - } - else if ( quad0_workaround_type == 2 ) - { - dqs_clk_increment_quad0 = dqs_clk_increment_wa2; - read_phase_value_quad0 = read_phase_value_wa2; - } - - if ( quad1_workaround_type == 0 ) - { - dqs_clk_increment_quad1 = dqs_clk_increment_wa0; - read_phase_value_quad1 = read_phase_value_wa0; - } - else if ( quad1_workaround_type == 1 ) - { - dqs_clk_increment_quad1 = dqs_clk_increment_wa1; - read_phase_value_quad1 = read_phase_value_wa1; - } - else if ( quad1_workaround_type == 2 ) - { - dqs_clk_increment_quad1 = dqs_clk_increment_wa2; - read_phase_value_quad1 = read_phase_value_wa2; - } - - if ( quad2_workaround_type == 0 ) - { - dqs_clk_increment_quad2 = dqs_clk_increment_wa0; - read_phase_value_quad2 = read_phase_value_wa0; - } - else if ( quad2_workaround_type == 1 ) - { - dqs_clk_increment_quad2 = dqs_clk_increment_wa1; - read_phase_value_quad2 = read_phase_value_wa1; - } - else if ( quad2_workaround_type == 2 ) - { - dqs_clk_increment_quad2 = dqs_clk_increment_wa2; - read_phase_value_quad2 = read_phase_value_wa2; - } - - if ( quad3_workaround_type == 0 ) - { - dqs_clk_increment_quad3 = dqs_clk_increment_wa0; - read_phase_value_quad3 = read_phase_value_wa0; - } - else if ( quad3_workaround_type == 1 ) - { - dqs_clk_increment_quad3 = dqs_clk_increment_wa1; - read_phase_value_quad3 = read_phase_value_wa1; - } - else if ( quad3_workaround_type == 2 ) - { - dqs_clk_increment_quad3 = dqs_clk_increment_wa2; - read_phase_value_quad3 = read_phase_value_wa2; - } - - - rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_2, data_buffer_64); - if (rc) return rc; - - // Set Read Phase. - rc_num = rc_num | data_buffer_64.insertFromRight(read_phase_value_quad0, 50, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(read_phase_value_quad1, 54, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(read_phase_value_quad2, 58, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(read_phase_value_quad3, 62, 2); - - //Increment dqs clk. 4 is the limit, wrap around (IE 5 = 1, 6 = 2) - l_value_u8 = 0; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_u8, 48, 2); - l_new_value_u8 = (l_value_u8 + dqs_clk_increment_quad0) % 4; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_new_value_u8, 48, 2); - l_value_u8 = 0; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_u8, 52, 2); - l_new_value_u8 = (l_value_u8 + dqs_clk_increment_quad1) % 4; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_new_value_u8, 52, 2); - l_value_u8 = 0; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_u8, 56, 2); - l_new_value_u8 = (l_value_u8 + dqs_clk_increment_quad2) % 4; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_new_value_u8, 56, 2); - l_value_u8 = 0; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_u8, 60, 2); - l_new_value_u8 = (l_value_u8 + dqs_clk_increment_quad3) % 4; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_new_value_u8, 60, 2); - - rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_2, data_buffer_64); - if (rc) return rc; - - //Block 3 - rc = fapiGetScom(i_target, RD_TIMING_REF0_ADDR_3, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.extractToRight(&l_timing_ref_quad0, 49, 7); - rc_num = rc_num | data_buffer_64.extractToRight(&l_timing_ref_quad1, 57, 7); - rc = fapiGetScom(i_target, RD_TIMING_REF1_ADDR_3, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.extractToRight(&l_timing_ref_quad2, 49, 7); - rc_num = rc_num | data_buffer_64.extractToRight(&l_timing_ref_quad3, 57, 7); - - if(rc_num) - { - rc.setEcmdError(rc_num); - return rc; - } - - if ( quad0_workaround_type == 0 ) - { - dqs_clk_increment_quad0 = dqs_clk_increment_wa0; - read_phase_value_quad0 = read_phase_value_wa0; - } - else if ( quad0_workaround_type == 1 ) - { - dqs_clk_increment_quad0 = dqs_clk_increment_wa1; - read_phase_value_quad0 = read_phase_value_wa1; - } - else if ( quad0_workaround_type == 2 ) - { - dqs_clk_increment_quad0 = dqs_clk_increment_wa2; - read_phase_value_quad0 = read_phase_value_wa2; - } - - if ( quad1_workaround_type == 0 ) - { - dqs_clk_increment_quad1 = dqs_clk_increment_wa0; - read_phase_value_quad1 = read_phase_value_wa0; - } - else if ( quad1_workaround_type == 1 ) - { - dqs_clk_increment_quad1 = dqs_clk_increment_wa1; - read_phase_value_quad1 = read_phase_value_wa1; - } - else if ( quad1_workaround_type == 2 ) - { - dqs_clk_increment_quad1 = dqs_clk_increment_wa2; - read_phase_value_quad1 = read_phase_value_wa2; - } - - if ( quad2_workaround_type == 0 ) - { - dqs_clk_increment_quad2 = dqs_clk_increment_wa0; - read_phase_value_quad2 = read_phase_value_wa0; - } - else if ( quad2_workaround_type == 1 ) - { - dqs_clk_increment_quad2 = dqs_clk_increment_wa1; - read_phase_value_quad2 = read_phase_value_wa1; - } - else if ( quad2_workaround_type == 2 ) - { - dqs_clk_increment_quad2 = dqs_clk_increment_wa2; - read_phase_value_quad2 = read_phase_value_wa2; - } - - if ( quad3_workaround_type == 0 ) - { - dqs_clk_increment_quad3 = dqs_clk_increment_wa0; - read_phase_value_quad3 = read_phase_value_wa0; - } - else if ( quad3_workaround_type == 1 ) - { - dqs_clk_increment_quad3 = dqs_clk_increment_wa1; - read_phase_value_quad3 = read_phase_value_wa1; - } - else if ( quad3_workaround_type == 2 ) - { - dqs_clk_increment_quad3 = dqs_clk_increment_wa2; - read_phase_value_quad3 = read_phase_value_wa2; - } - - - rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_3, data_buffer_64); - if (rc) return rc; - - // Set Read Phase. - rc_num = rc_num | data_buffer_64.insertFromRight(read_phase_value_quad0, 50, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(read_phase_value_quad1, 54, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(read_phase_value_quad2, 58, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(read_phase_value_quad3, 62, 2); - - //Increment dqs clk. 4 is the limit, wrap around (IE 5 = 1, 6 = 2) - l_value_u8 = 0; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_u8, 48, 2); - l_new_value_u8 = (l_value_u8 + dqs_clk_increment_quad0) % 4; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_new_value_u8, 48, 2); - l_value_u8 = 0; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_u8, 52, 2); - l_new_value_u8 = (l_value_u8 + dqs_clk_increment_quad1) % 4; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_new_value_u8, 52, 2); - l_value_u8 = 0; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_u8, 56, 2); - l_new_value_u8 = (l_value_u8 + dqs_clk_increment_quad2) % 4; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_new_value_u8, 56, 2); - l_value_u8 = 0; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_u8, 60, 2); - l_new_value_u8 = (l_value_u8 + dqs_clk_increment_quad3) % 4; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_new_value_u8, 60, 2); - - rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_3, data_buffer_64); - if (rc) return rc; - - //Block 4 - rc = fapiGetScom(i_target, RD_TIMING_REF0_ADDR_4, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.extractToRight(&l_timing_ref_quad0, 49, 7); - rc_num = rc_num | data_buffer_64.extractToRight(&l_timing_ref_quad1, 57, 7); - rc = fapiGetScom(i_target, RD_TIMING_REF1_ADDR_4, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.extractToRight(&l_timing_ref_quad2, 49, 7); - rc_num = rc_num | data_buffer_64.extractToRight(&l_timing_ref_quad3, 57, 7); - - if(rc_num) - { - rc.setEcmdError(rc_num); - return rc; - } - - if ( quad0_workaround_type == 0 ) - { - dqs_clk_increment_quad0 = dqs_clk_increment_wa0; - read_phase_value_quad0 = read_phase_value_wa0; - } - else if ( quad0_workaround_type == 1 ) - { - dqs_clk_increment_quad0 = dqs_clk_increment_wa1; - read_phase_value_quad0 = read_phase_value_wa1; - } - else if ( quad0_workaround_type == 2 ) - { - dqs_clk_increment_quad0 = dqs_clk_increment_wa2; - read_phase_value_quad0 = read_phase_value_wa2; - } - - if ( quad1_workaround_type == 0 ) - { - dqs_clk_increment_quad1 = dqs_clk_increment_wa0; - read_phase_value_quad1 = read_phase_value_wa0; - } - else if ( quad1_workaround_type == 1 ) - { - dqs_clk_increment_quad1 = dqs_clk_increment_wa1; - read_phase_value_quad1 = read_phase_value_wa1; - } - else if ( quad1_workaround_type == 2 ) - { - dqs_clk_increment_quad1 = dqs_clk_increment_wa2; - read_phase_value_quad1 = read_phase_value_wa2; - } - - if ( quad2_workaround_type == 0 ) - { - dqs_clk_increment_quad2 = dqs_clk_increment_wa0; - read_phase_value_quad2 = read_phase_value_wa0; - } - else if ( quad2_workaround_type == 1 ) - { - dqs_clk_increment_quad2 = dqs_clk_increment_wa1; - read_phase_value_quad2 = read_phase_value_wa1; - } - else if ( quad2_workaround_type == 2 ) - { - dqs_clk_increment_quad2 = dqs_clk_increment_wa2; - read_phase_value_quad2 = read_phase_value_wa2; - } - - if ( quad3_workaround_type == 0 ) - { - dqs_clk_increment_quad3 = dqs_clk_increment_wa0; - read_phase_value_quad3 = read_phase_value_wa0; - } - else if ( quad3_workaround_type == 1 ) - { - dqs_clk_increment_quad3 = dqs_clk_increment_wa1; - read_phase_value_quad3 = read_phase_value_wa1; - } - else if ( quad3_workaround_type == 2 ) - { - dqs_clk_increment_quad3 = dqs_clk_increment_wa2; - read_phase_value_quad3 = read_phase_value_wa2; - } - - - rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_4, data_buffer_64); - if (rc) return rc; - - // Set Read Phase. - rc_num = rc_num | data_buffer_64.insertFromRight(read_phase_value_quad0, 50, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(read_phase_value_quad1, 54, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(read_phase_value_quad2, 58, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(read_phase_value_quad3, 62, 2); - - //Increment dqs clk. 4 is the limit, wrap around (IE 5 = 1, 6 = 2) - l_value_u8 = 0; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_u8, 48, 2); - l_new_value_u8 = (l_value_u8 + dqs_clk_increment_quad0) % 4; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_new_value_u8, 48, 2); - l_value_u8 = 0; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_u8, 52, 2); - l_new_value_u8 = (l_value_u8 + dqs_clk_increment_quad1) % 4; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_new_value_u8, 52, 2); - l_value_u8 = 0; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_u8, 56, 2); - l_new_value_u8 = (l_value_u8 + dqs_clk_increment_quad2) % 4; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_new_value_u8, 56, 2); - l_value_u8 = 0; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_u8, 60, 2); - l_new_value_u8 = (l_value_u8 + dqs_clk_increment_quad3) % 4; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_new_value_u8, 60, 2); - - rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_4, data_buffer_64); - if (rc) return rc; - - if(rc_num) - { - rc.setEcmdError(rc_num); - return rc; - } - - return rc; -} - -ReturnCode mss_read_center_second_workaround( - Target& i_target - ) -{ - //MBA target level - //DQS_CLK for each nibble of a byte is being adjusted to the lowest value for the given byte - //Across all byte lanes - - uint8_t primary_ranks_array[4][2]; //primary_ranks_array[group][port] - ecmdDataBufferBase data_buffer_64(64); - uint64_t DQSCLK_RD_PHASE_ADDR_0 = 0; - uint64_t DQSCLK_RD_PHASE_ADDR_1 = 0; - uint64_t DQSCLK_RD_PHASE_ADDR_2 = 0; - uint64_t DQSCLK_RD_PHASE_ADDR_3 = 0; - uint64_t DQSCLK_RD_PHASE_ADDR_4 = 0; - uint64_t GATE_DELAY_ADDR_0 = 0; - uint64_t GATE_DELAY_ADDR_1 = 0; - uint64_t GATE_DELAY_ADDR_2 = 0; - uint64_t GATE_DELAY_ADDR_3 = 0; - uint64_t GATE_DELAY_ADDR_4 = 0; - uint8_t port = 0; - uint8_t rank_group = 0; - uint8_t l_value_n0_u8 = 0; - uint8_t l_value_n1_u8 = 0; - //uint8_t l_lowest_value_u8 = 0; - ReturnCode rc; - uint32_t rc_num = 0; - - uint32_t block; - uint32_t maxblocks = 5; - uint32_t byte; - uint32_t maxbytes = 2; - uint32_t nibble; - uint32_t maxnibbles = 2; - - uint8_t l_lowest_value_u8[4][5][2][2]; // l_lowest_value_u8[group][block][byte_of_reg][nibble_of_byte] - uint8_t l_gate_delay_value_u8[4][5][2][2]; // l_lowest_value_u8[group][block][byte_of_reg][nibble_of_byte] - - - //populate primary_ranks_arrays_array - rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP0, &i_target, primary_ranks_array[0]); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP1, &i_target, primary_ranks_array[1]); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP2, &i_target, primary_ranks_array[2]); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP3, &i_target, primary_ranks_array[3]); - if(rc) return rc; - - - for(port = 0; port < MAX_PORTS; port++) - { - - - //FAPI_INF( "DQS_CLK Byte matching Workaround being applied on %s PORT: %d RP: %d", i_target.toEcmdString(), port, rank_group); - - //Gather all the byte information - for(rank_group = 0; rank_group < MAX_PRI_RANKS; rank_group++) - { - - //Initialize values - for(block = 0; block < maxblocks; block++) - { - for (byte = 0; byte < maxbytes; byte++) - { - for (nibble = 0; nibble < maxnibbles; nibble++) - { - l_lowest_value_u8[rank_group][block][byte][nibble] = 255; - l_gate_delay_value_u8[rank_group][block][byte][nibble] = 255; - } - } - } - - //Check if rank group exists - if(primary_ranks_array[rank_group][port] != 255) - { - FAPI_INF( "DQS_CLK Byte matching Workaround being applied on %s PORT: %d RP: %d", i_target.toEcmdString(), port, rank_group); - if ( port == 0 ) - { - - if ( rank_group == 0 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_0x800000090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_0x800004090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_0x800008090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_0x80000C090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_0x800010090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_0_0x800000130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_1_0x800004130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_2_0x800008130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_3_0x80000C130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_4_0x800010130301143F; - - } - else if ( rank_group == 1 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_0x800001090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_0x800005090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_0x800009090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_0x80000D090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_0x800011090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_0_0x800001130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_1_0x800005130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_2_0x800009130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_3_0x80000D130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_4_0x800011130301143F; - - } - else if ( rank_group == 2 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_0x800002090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_0x800006090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_0x80000A090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_0x80000E090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_0x800012090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_0_0x800002130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_1_0x800006130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_2_0x80000A130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_3_0x80000E130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_4_0x800012130301143F; - - } - else if ( rank_group == 3 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_0x800003090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_0x800007090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_0x80000B090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_0x80000F090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_0x800013090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_0_0x800003130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_1_0x800007130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_2_0x80000B130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_3_0x80000F130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_4_0x800013130301143F; - - } - } - else if (port == 1 ) - { - - if ( rank_group == 0 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_0_0x800100090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_1_0x800104090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_2_0x800108090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_3_0x80010C090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_4_0x800110090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_0_0x800100130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_1_0x800104130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_2_0x800108130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_3_0x80010C130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_4_0x800110130301143F; - - } - else if ( rank_group == 1 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_0_0x800101090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_1_0x800105090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_2_0x800109090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_3_0x80010D090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_4_0x800111090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_0_0x800101130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_1_0x800105130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_2_0x800109130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_3_0x80010D130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_4_0x800111130301143F; - - } - else if ( rank_group == 2 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_0_0x800102090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_1_0x800106090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_2_0x80010A090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_3_0x80010E090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_4_0x800112090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_0_0x800102130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_1_0x800106130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_2_0x80010A130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_3_0x80010E130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_4_0x800112130301143F; - - } - else if ( rank_group == 3 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_0_0x800103090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_1_0x800107090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_2_0x80010B090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_3_0x80010F090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_4_0x800113090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_0_0x800103130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_1_0x800107130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_2_0x80010B130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_3_0x80010F130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_4_0x800113130301143F; - - } - } - - - // PHY BLOCK 0 - rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_0, data_buffer_64); - if (rc) return rc; - // Grabbing 2 nibbles of the same byte and making them equal to the same lowest value - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 2); - l_lowest_value_u8[rank_group][0][0][0] = l_value_n0_u8; - l_lowest_value_u8[rank_group][0][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 2); - l_lowest_value_u8[rank_group][0][1][0] = l_value_n0_u8; - l_lowest_value_u8[rank_group][0][1][1] = l_value_n1_u8; - - rc = fapiGetScom(i_target, GATE_DELAY_ADDR_0, data_buffer_64); - if (rc) return rc; - // Grabbing 2 nibbles of the same byte and making them equal the same lowest value - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 49, 3); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 53, 3); - l_gate_delay_value_u8[rank_group][0][0][0] = l_value_n0_u8; - l_gate_delay_value_u8[rank_group][0][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 57, 3); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 61, 3); - l_gate_delay_value_u8[rank_group][0][1][0] = l_value_n0_u8; - l_gate_delay_value_u8[rank_group][0][1][1] = l_value_n1_u8; - - // PHY BLOCK 1 - rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_1, data_buffer_64); - if (rc) return rc; - // Grabbing 2 nibbles of the same byte and making them equal to the same lowest value - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 2); - l_lowest_value_u8[rank_group][1][0][0] = l_value_n0_u8; - l_lowest_value_u8[rank_group][1][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 2); - l_lowest_value_u8[rank_group][1][1][0] = l_value_n0_u8; - l_lowest_value_u8[rank_group][1][1][1] = l_value_n1_u8; - - rc = fapiGetScom(i_target, GATE_DELAY_ADDR_1, data_buffer_64); - if (rc) return rc; - // Grabbing 2 nibbles of the same byte and making them equal the same lowest value - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 49, 3); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 53, 3); - l_gate_delay_value_u8[rank_group][1][0][0] = l_value_n0_u8; - l_gate_delay_value_u8[rank_group][1][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 57, 3); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 61, 3); - l_gate_delay_value_u8[rank_group][1][1][0] = l_value_n0_u8; - l_gate_delay_value_u8[rank_group][1][1][1] = l_value_n1_u8; - - // PHY BLOCK 2 - rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_2, data_buffer_64); - if (rc) return rc; - // Grabbing 2 nibbles of the same byte and making them equal to the same lowest value - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 2); - l_lowest_value_u8[rank_group][2][0][0] = l_value_n0_u8; - l_lowest_value_u8[rank_group][2][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 2); - l_lowest_value_u8[rank_group][2][1][0] = l_value_n0_u8; - l_lowest_value_u8[rank_group][2][1][1] = l_value_n1_u8; - - rc = fapiGetScom(i_target, GATE_DELAY_ADDR_2, data_buffer_64); - if (rc) return rc; - // Grabbing 2 nibbles of the same byte and making them equal the same lowest value - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 49, 3); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 53, 3); - l_gate_delay_value_u8[rank_group][2][0][0] = l_value_n0_u8; - l_gate_delay_value_u8[rank_group][2][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 57, 3); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 61, 3); - l_gate_delay_value_u8[rank_group][2][1][0] = l_value_n0_u8; - l_gate_delay_value_u8[rank_group][2][1][1] = l_value_n1_u8; - - // PHY BLOCK 3 - rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_3, data_buffer_64); - if (rc) return rc; - // Grabbing 2 nibbles of the same byte and making them equal to the same lowest value - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 2); - l_lowest_value_u8[rank_group][3][0][0] = l_value_n0_u8; - l_lowest_value_u8[rank_group][3][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 2); - l_lowest_value_u8[rank_group][3][1][0] = l_value_n0_u8; - l_lowest_value_u8[rank_group][3][1][1] = l_value_n1_u8; - - rc = fapiGetScom(i_target, GATE_DELAY_ADDR_3, data_buffer_64); - if (rc) return rc; - // Grabbing 2 nibbles of the same byte and making them equal the same lowest value - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 49, 3); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 53, 3); - l_gate_delay_value_u8[rank_group][3][0][0] = l_value_n0_u8; - l_gate_delay_value_u8[rank_group][3][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 57, 3); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 61, 3); - l_gate_delay_value_u8[rank_group][3][1][0] = l_value_n0_u8; - l_gate_delay_value_u8[rank_group][3][1][1] = l_value_n1_u8; - - // PHY BLOCK 4 - rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_4, data_buffer_64); - if (rc) return rc; - // Grabbing 2 nibbles of the same byte and making them equal to the same lowest value - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 2); - l_lowest_value_u8[rank_group][4][0][0] = l_value_n0_u8; - l_lowest_value_u8[rank_group][4][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 2); - l_lowest_value_u8[rank_group][4][1][0] = l_value_n0_u8; - l_lowest_value_u8[rank_group][4][1][1] = l_value_n1_u8; - - rc = fapiGetScom(i_target, GATE_DELAY_ADDR_4, data_buffer_64); - if (rc) return rc; - // Grabbing 2 nibbles of the same byte and making them equal the same lowest value - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 49, 3); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 53, 3); - l_gate_delay_value_u8[rank_group][4][0][0] = l_value_n0_u8; - l_gate_delay_value_u8[rank_group][4][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 57, 3); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 61, 3); - l_gate_delay_value_u8[rank_group][4][1][0] = l_value_n0_u8; - l_gate_delay_value_u8[rank_group][4][1][1] = l_value_n1_u8; - - if(rc_num) - { - rc.setEcmdError(rc_num); - return rc; - } - - } - } - - //Finding the lowest Value - for(block = 0; block < maxblocks; block++) - { - for (byte = 0; byte < maxbytes; byte++) - { - - for (nibble = 0; nibble < maxnibbles; nibble++) - { - - if ( (l_lowest_value_u8[0][block][byte][nibble] == 0) || - (l_lowest_value_u8[1][block][byte][nibble] == 0) || - (l_lowest_value_u8[2][block][byte][nibble] == 0) || - (l_lowest_value_u8[3][block][byte][nibble] == 0) ) - { - if ( (l_lowest_value_u8[0][block][byte][nibble] == 3) || - (l_lowest_value_u8[1][block][byte][nibble] == 3) || - (l_lowest_value_u8[2][block][byte][nibble] == 3) || - (l_lowest_value_u8[3][block][byte][nibble] == 3) ) - { - - //In this case alone we make all gate values equal the gate of the lowest DQSCLK - if (l_lowest_value_u8[0][block][byte][nibble] == 3) - { - l_gate_delay_value_u8[1][block][byte][nibble] = l_gate_delay_value_u8[0][block][byte][nibble]; - l_gate_delay_value_u8[2][block][byte][nibble] = l_gate_delay_value_u8[0][block][byte][nibble]; - l_gate_delay_value_u8[3][block][byte][nibble] = l_gate_delay_value_u8[0][block][byte][nibble]; - } - else if (l_lowest_value_u8[1][block][byte][nibble] == 3) - { - l_gate_delay_value_u8[0][block][byte][nibble] = l_gate_delay_value_u8[1][block][byte][nibble]; - l_gate_delay_value_u8[2][block][byte][nibble] = l_gate_delay_value_u8[1][block][byte][nibble]; - l_gate_delay_value_u8[3][block][byte][nibble] = l_gate_delay_value_u8[1][block][byte][nibble]; - } - else if (l_lowest_value_u8[2][block][byte][nibble] == 3) - { - l_gate_delay_value_u8[0][block][byte][nibble] = l_gate_delay_value_u8[2][block][byte][nibble]; - l_gate_delay_value_u8[1][block][byte][nibble] = l_gate_delay_value_u8[2][block][byte][nibble]; - l_gate_delay_value_u8[3][block][byte][nibble] = l_gate_delay_value_u8[2][block][byte][nibble]; - } - else if (l_lowest_value_u8[3][block][byte][nibble] == 3) - { - l_gate_delay_value_u8[0][block][byte][nibble] = l_gate_delay_value_u8[3][block][byte][nibble]; - l_gate_delay_value_u8[1][block][byte][nibble] = l_gate_delay_value_u8[3][block][byte][nibble]; - l_gate_delay_value_u8[2][block][byte][nibble] = l_gate_delay_value_u8[3][block][byte][nibble]; - } - - l_lowest_value_u8[0][block][byte][nibble] = 3; - l_lowest_value_u8[1][block][byte][nibble] = 3; - l_lowest_value_u8[2][block][byte][nibble] = 3; - l_lowest_value_u8[3][block][byte][nibble] = 3; - } - else - { - l_lowest_value_u8[0][block][byte][nibble] = 0; - l_lowest_value_u8[1][block][byte][nibble] = 0; - l_lowest_value_u8[2][block][byte][nibble] = 0; - l_lowest_value_u8[3][block][byte][nibble] = 0; - - } - } - else if ( (l_lowest_value_u8[0][block][byte][nibble] == 2) || - (l_lowest_value_u8[1][block][byte][nibble] == 2) || - (l_lowest_value_u8[2][block][byte][nibble] == 2) || - (l_lowest_value_u8[3][block][byte][nibble] == 2) ) - { - if ( (l_lowest_value_u8[0][block][byte][nibble] == 1) || - (l_lowest_value_u8[1][block][byte][nibble] == 1) || - (l_lowest_value_u8[2][block][byte][nibble] == 1) || - (l_lowest_value_u8[3][block][byte][nibble] == 1) ) - { - l_lowest_value_u8[0][block][byte][nibble] = 1; - l_lowest_value_u8[1][block][byte][nibble] = 1; - l_lowest_value_u8[2][block][byte][nibble] = 1; - l_lowest_value_u8[3][block][byte][nibble] = 1; - - } - else - { - l_lowest_value_u8[0][block][byte][nibble] = 2; - l_lowest_value_u8[1][block][byte][nibble] = 2; - l_lowest_value_u8[2][block][byte][nibble] = 2; - l_lowest_value_u8[3][block][byte][nibble] = 2; - - } - } - - } - } - - } - - - //Scoming in the New Values - for(rank_group = 0; rank_group < MAX_PRI_RANKS; rank_group++) - { - - //Check if rank group exists - if(primary_ranks_array[rank_group][port] != 255) - { - - if ( port == 0 ) - { - - if ( rank_group == 0 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_0x800000090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_0x800004090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_0x800008090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_0x80000C090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_0x800010090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_0_0x800000130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_1_0x800004130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_2_0x800008130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_3_0x80000C130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_4_0x800010130301143F; - - } - else if ( rank_group == 1 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_0x800001090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_0x800005090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_0x800009090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_0x80000D090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_0x800011090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_0_0x800001130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_1_0x800005130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_2_0x800009130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_3_0x80000D130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_4_0x800011130301143F; - - } - else if ( rank_group == 2 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_0x800002090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_0x800006090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_0x80000A090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_0x80000E090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_0x800012090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_0_0x800002130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_1_0x800006130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_2_0x80000A130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_3_0x80000E130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_4_0x800012130301143F; - - } - else if ( rank_group == 3 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_0x800003090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_0x800007090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_0x80000B090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_0x80000F090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_0x800013090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_0_0x800003130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_1_0x800007130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_2_0x80000B130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_3_0x80000F130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_4_0x800013130301143F; - - } - } - else if (port == 1 ) - { - - if ( rank_group == 0 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_0_0x800100090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_1_0x800104090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_2_0x800108090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_3_0x80010C090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_4_0x800110090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_0_0x800100130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_1_0x800104130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_2_0x800108130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_3_0x80010C130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_4_0x800110130301143F; - - } - else if ( rank_group == 1 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_0_0x800101090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_1_0x800105090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_2_0x800109090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_3_0x80010D090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_4_0x800111090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_0_0x800101130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_1_0x800105130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_2_0x800109130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_3_0x80010D130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_4_0x800111130301143F; - - } - else if ( rank_group == 2 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_0_0x800102090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_1_0x800106090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_2_0x80010A090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_3_0x80010E090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_4_0x800112090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_0_0x800102130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_1_0x800106130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_2_0x80010A130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_3_0x80010E130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_4_0x800112130301143F; - - } - else if ( rank_group == 3 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_0_0x800103090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_1_0x800107090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_2_0x80010B090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_3_0x80010F090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_4_0x800113090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_0_0x800103130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_1_0x800107130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_2_0x80010B130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_3_0x80010F130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_4_0x800113130301143F; - - } - } - - //BLOCK 0 - rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_0, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][0][0][0], 48, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][0][0][1], 52, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][0][1][0], 56, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][0][1][1], 60, 2); - rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_0, data_buffer_64); - if (rc) return rc; - - rc = fapiGetScom(i_target, GATE_DELAY_ADDR_0, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][0][0][0], 49, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][0][0][1], 53, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][0][1][0], 57, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][0][1][1], 61, 3); - rc = fapiPutScom(i_target, GATE_DELAY_ADDR_0, data_buffer_64); - if (rc) return rc; - - //BLOCK 1 - rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_1, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][1][0][0], 48, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][1][0][1], 52, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][1][1][0], 56, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][1][1][1], 60, 2); - rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_1, data_buffer_64); - if (rc) return rc; - - rc = fapiGetScom(i_target, GATE_DELAY_ADDR_1, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][1][0][0], 49, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][1][0][1], 53, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][1][1][0], 57, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][1][1][1], 61, 3); - rc = fapiPutScom(i_target, GATE_DELAY_ADDR_1, data_buffer_64); - if (rc) return rc; - - //BLOCK 2 - rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_2, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][2][0][0], 48, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][2][0][1], 52, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][2][1][0], 56, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][2][1][1], 60, 2); - rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_2, data_buffer_64); - if (rc) return rc; - - rc = fapiGetScom(i_target, GATE_DELAY_ADDR_2, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][2][0][0], 49, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][2][0][1], 53, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][2][1][0], 57, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][2][1][1], 61, 3); - rc = fapiPutScom(i_target, GATE_DELAY_ADDR_2, data_buffer_64); - if (rc) return rc; - - //BLOCK 3 - rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_3, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][3][0][0], 48, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][3][0][1], 52, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][3][1][0], 56, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][3][1][1], 60, 2); - rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_3, data_buffer_64); - if (rc) return rc; - - rc = fapiGetScom(i_target, GATE_DELAY_ADDR_3, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][3][0][0], 49, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][3][0][1], 53, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][3][1][0], 57, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][3][1][1], 61, 3); - rc = fapiPutScom(i_target, GATE_DELAY_ADDR_3, data_buffer_64); - if (rc) return rc; - - //Block 4 - rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_4, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][4][0][0], 48, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][4][0][1], 52, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][4][1][0], 56, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][4][1][1], 60, 2); - rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_4, data_buffer_64); - if (rc) return rc; - - rc = fapiGetScom(i_target, GATE_DELAY_ADDR_4, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][4][0][0], 49, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][4][0][1], 53, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][4][1][0], 57, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][4][1][1], 61, 3); - - if(rc_num) - { - rc.setEcmdError(rc_num); - return rc; - } - - rc = fapiPutScom(i_target, GATE_DELAY_ADDR_4, data_buffer_64); - if (rc) return rc; - - } - } - } - - return rc; -} - - -ReturnCode mss_disable_workaround( - Target& i_target - ) -{ - //MBA target level - //DQS_CLK for each nibble of a byte is being adjusted to the lowest value for the given byte - //Across all byte lanes - - uint8_t primary_ranks_array[4][2]; //primary_ranks_array[group][port] - ecmdDataBufferBase data_buffer_64(64); - uint64_t DQSCLK_RD_PHASE_ADDR_0 = 0; - uint64_t DQSCLK_RD_PHASE_ADDR_1 = 0; - uint64_t DQSCLK_RD_PHASE_ADDR_2 = 0; - uint64_t DQSCLK_RD_PHASE_ADDR_3 = 0; - uint64_t DQSCLK_RD_PHASE_ADDR_4 = 0; - uint64_t DISABLE_ADDR_0 = 0; - uint64_t DISABLE_ADDR_1 = 0; - uint64_t DISABLE_ADDR_2 = 0; - uint64_t DISABLE_ADDR_3 = 0; - uint64_t DISABLE_ADDR_4 = 0; - uint64_t GATE_DELAY_ADDR_0 = 0; - uint64_t GATE_DELAY_ADDR_1 = 0; - uint64_t GATE_DELAY_ADDR_2 = 0; - uint64_t GATE_DELAY_ADDR_3 = 0; - uint64_t GATE_DELAY_ADDR_4 = 0; - uint8_t port = 0; - uint8_t rank_group = 0; - uint8_t l_value_n0_u8 = 0; - uint8_t l_value_n1_u8 = 0; - //uint8_t l_lowest_value_u8 = 0; - ReturnCode rc; - uint32_t rc_num = 0; - - uint32_t block; - uint32_t maxblocks = 5; - uint32_t byte; - uint32_t maxbytes = 2; - uint32_t nibble; - uint32_t maxnibbles = 2; - uint8_t l_min_gate_delay = 255; - uint8_t l_min_dqs_clk = 255; - - uint8_t l_lowest_value_u8[4][5][2][2]; // l_lowest_value_u8[group][block][byte_of_reg][nibble_of_byte] - uint8_t l_gate_delay_value_u8[4][5][2][2]; // l_lowest_value_u8[group][block][byte_of_reg][nibble_of_byte] - uint8_t l_disable_value_u8[4][5][2][2]; - - - //populate primary_ranks_arrays_array - rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP0, &i_target, primary_ranks_array[0]); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP1, &i_target, primary_ranks_array[1]); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP2, &i_target, primary_ranks_array[2]); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP3, &i_target, primary_ranks_array[3]); - if(rc) return rc; - - - for(port = 0; port < MAX_PORTS; port++) - { - - - //FAPI_INF( "DQS_CLK Byte matching Workaround being applied on %s PORT: %d RP: %d", i_target.toEcmdString(), port, rank_group); - - //Gather all the byte information - for(rank_group = 0; rank_group < MAX_PRI_RANKS; rank_group++) - { - - //Initialize values - for(block = 0; block < maxblocks; block++) - { - for (byte = 0; byte < maxbytes; byte++) - { - for (nibble = 0; nibble < maxnibbles; nibble++) - { - l_lowest_value_u8[rank_group][block][byte][nibble] = 255; - l_gate_delay_value_u8[rank_group][block][byte][nibble] = 255; - l_disable_value_u8[rank_group][block][byte][nibble] = 0; - } - } - } - - //Check if rank group exists - if(primary_ranks_array[rank_group][port] != 255) - { - FAPI_INF( "DISABLE Workaround being applied on %s PORT: %d RP: %d", i_target.toEcmdString(), port, rank_group); - if ( port == 0 ) - { - - if ( rank_group == 0 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_0x800000090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_0x800004090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_0x800008090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_0x80000C090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_0x800010090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_0_0x800000130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_1_0x800004130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_2_0x800008130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_3_0x80000C130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_4_0x800010130301143F; - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_0_0x8000007c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_1_0x8000047c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_2_0x8000087c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_3_0x80000c7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_4_0x8000107c0301143F; - - - } - else if ( rank_group == 1 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_0x800001090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_0x800005090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_0x800009090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_0x80000D090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_0x800011090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_0_0x800001130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_1_0x800005130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_2_0x800009130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_3_0x80000D130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_4_0x800011130301143F; - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_0_0x8000017c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_1_0x8000057c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_2_0x8000097c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_3_0x80000d7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_4_0x8000117c0301143F; - - } - else if ( rank_group == 2 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_0x800002090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_0x800006090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_0x80000A090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_0x80000E090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_0x800012090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_0_0x800002130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_1_0x800006130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_2_0x80000A130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_3_0x80000E130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_4_0x800012130301143F; - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_0_0x8000027c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_1_0x8000067c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_2_0x80000a7c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_3_0x80000e7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_4_0x8000127c0301143F; - - } - else if ( rank_group == 3 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_0x800003090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_0x800007090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_0x80000B090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_0x80000F090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_0x800013090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_0_0x800003130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_1_0x800007130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_2_0x80000B130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_3_0x80000F130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_4_0x800013130301143F; - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_0_0x8000037c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_1_0x8000077c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_2_0x80000b7c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_3_0x80000f7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_4_0x8000137c0301143F; - - } - } - else if (port == 1 ) - { - - if ( rank_group == 0 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_0_0x800100090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_1_0x800104090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_2_0x800108090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_3_0x80010C090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_4_0x800110090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_0_0x800100130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_1_0x800104130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_2_0x800108130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_3_0x80010C130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_4_0x800110130301143F; - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_0_0x8001007c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_1_0x8001047c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_2_0x8001087c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_3_0x80010c7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_4_0x8001107c0301143F; - - } - else if ( rank_group == 1 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_0_0x800101090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_1_0x800105090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_2_0x800109090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_3_0x80010D090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_4_0x800111090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_0_0x800101130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_1_0x800105130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_2_0x800109130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_3_0x80010D130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_4_0x800111130301143F; - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_0_0x8001017c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_1_0x8001057c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_2_0x8001097c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_3_0x80010d7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_4_0x8001117c0301143F; - - } - else if ( rank_group == 2 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_0_0x800102090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_1_0x800106090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_2_0x80010A090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_3_0x80010E090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_4_0x800112090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_0_0x800102130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_1_0x800106130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_2_0x80010A130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_3_0x80010E130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_4_0x800112130301143F; - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_0_0x8001027c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_1_0x8001067c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_2_0x80010a7c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_3_0x80010e7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_4_0x8001127c0301143F; - - } - else if ( rank_group == 3 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_0_0x800103090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_1_0x800107090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_2_0x80010B090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_3_0x80010F090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_4_0x800113090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_0_0x800103130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_1_0x800107130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_2_0x80010B130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_3_0x80010F130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_4_0x800113130301143F; - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_0_0x8001037c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_1_0x8001077c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_2_0x80010b7c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_3_0x80010f7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_4_0x8001137c0301143F; - - } - } - - - // PHY BLOCK 0 - rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_0, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 50, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 54, 2); - l_lowest_value_u8[rank_group][0][0][0] = l_value_n0_u8; - l_lowest_value_u8[rank_group][0][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 58, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 62, 2); - l_lowest_value_u8[rank_group][0][1][0] = l_value_n0_u8; - l_lowest_value_u8[rank_group][0][1][1] = l_value_n1_u8; - - rc = fapiGetScom(i_target, DISABLE_ADDR_0, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 4); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 4); - l_disable_value_u8[rank_group][0][0][0] = l_value_n0_u8; - l_disable_value_u8[rank_group][0][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 4); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 4); - l_disable_value_u8[rank_group][0][1][0] = l_value_n0_u8; - l_disable_value_u8[rank_group][0][1][1] = l_value_n1_u8; - - rc = fapiGetScom(i_target, GATE_DELAY_ADDR_0, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 49, 3); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 53, 3); - l_gate_delay_value_u8[rank_group][0][0][0] = l_value_n0_u8; - l_gate_delay_value_u8[rank_group][0][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 57, 3); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 61, 3); - l_gate_delay_value_u8[rank_group][0][1][0] = l_value_n0_u8; - l_gate_delay_value_u8[rank_group][0][1][1] = l_value_n1_u8; - - // PHY BLOCK 1 - rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_1, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 50, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 54, 2); - l_lowest_value_u8[rank_group][1][0][0] = l_value_n0_u8; - l_lowest_value_u8[rank_group][1][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 58, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 62, 2); - l_lowest_value_u8[rank_group][1][1][0] = l_value_n0_u8; - l_lowest_value_u8[rank_group][1][1][1] = l_value_n1_u8; - - rc = fapiGetScom(i_target, DISABLE_ADDR_1, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 4); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 4); - l_disable_value_u8[rank_group][1][0][0] = l_value_n0_u8; - l_disable_value_u8[rank_group][1][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 4); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 4); - l_disable_value_u8[rank_group][1][1][0] = l_value_n0_u8; - l_disable_value_u8[rank_group][1][1][1] = l_value_n1_u8; - - rc = fapiGetScom(i_target, GATE_DELAY_ADDR_1, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 49, 3); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 53, 3); - l_gate_delay_value_u8[rank_group][1][0][0] = l_value_n0_u8; - l_gate_delay_value_u8[rank_group][1][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 57, 3); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 61, 3); - l_gate_delay_value_u8[rank_group][1][1][0] = l_value_n0_u8; - l_gate_delay_value_u8[rank_group][1][1][1] = l_value_n1_u8; - - // PHY BLOCK 2 - rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_2, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 50, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 54, 2); - l_lowest_value_u8[rank_group][2][0][0] = l_value_n0_u8; - l_lowest_value_u8[rank_group][2][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 58, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 62, 2); - l_lowest_value_u8[rank_group][2][1][0] = l_value_n0_u8; - l_lowest_value_u8[rank_group][2][1][1] = l_value_n1_u8; - - rc = fapiGetScom(i_target, DISABLE_ADDR_2, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 4); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 4); - l_disable_value_u8[rank_group][2][0][0] = l_value_n0_u8; - l_disable_value_u8[rank_group][2][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 4); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 4); - l_disable_value_u8[rank_group][2][1][0] = l_value_n0_u8; - l_disable_value_u8[rank_group][2][1][1] = l_value_n1_u8; - - rc = fapiGetScom(i_target, GATE_DELAY_ADDR_2, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 49, 3); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 53, 3); - l_gate_delay_value_u8[rank_group][2][0][0] = l_value_n0_u8; - l_gate_delay_value_u8[rank_group][2][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 57, 3); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 61, 3); - l_gate_delay_value_u8[rank_group][2][1][0] = l_value_n0_u8; - l_gate_delay_value_u8[rank_group][2][1][1] = l_value_n1_u8; - - // PHY BLOCK 3 - rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_3, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 50, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 54, 2); - l_lowest_value_u8[rank_group][3][0][0] = l_value_n0_u8; - l_lowest_value_u8[rank_group][3][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 58, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 62, 2); - l_lowest_value_u8[rank_group][3][1][0] = l_value_n0_u8; - l_lowest_value_u8[rank_group][3][1][1] = l_value_n1_u8; - - rc = fapiGetScom(i_target, DISABLE_ADDR_3, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 4); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 4); - l_disable_value_u8[rank_group][3][0][0] = l_value_n0_u8; - l_disable_value_u8[rank_group][3][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 4); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 4); - l_disable_value_u8[rank_group][3][1][0] = l_value_n0_u8; - l_disable_value_u8[rank_group][3][1][1] = l_value_n1_u8; - - rc = fapiGetScom(i_target, GATE_DELAY_ADDR_3, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 49, 3); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 53, 3); - l_gate_delay_value_u8[rank_group][3][0][0] = l_value_n0_u8; - l_gate_delay_value_u8[rank_group][3][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 57, 3); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 61, 3); - l_gate_delay_value_u8[rank_group][3][1][0] = l_value_n0_u8; - l_gate_delay_value_u8[rank_group][3][1][1] = l_value_n1_u8; - - // PHY BLOCK 4 - rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_4, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 50, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 54, 2); - l_lowest_value_u8[rank_group][4][0][0] = l_value_n0_u8; - l_lowest_value_u8[rank_group][4][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 58, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 62, 2); - l_lowest_value_u8[rank_group][4][1][0] = l_value_n0_u8; - l_lowest_value_u8[rank_group][4][1][1] = l_value_n1_u8; - - rc = fapiGetScom(i_target, DISABLE_ADDR_4, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 4); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 4); - l_disable_value_u8[rank_group][4][0][0] = l_value_n0_u8; - l_disable_value_u8[rank_group][4][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 4); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 4); - l_disable_value_u8[rank_group][4][1][0] = l_value_n0_u8; - l_disable_value_u8[rank_group][4][1][1] = l_value_n1_u8; - - rc = fapiGetScom(i_target, GATE_DELAY_ADDR_4, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 49, 3); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 53, 3); - l_gate_delay_value_u8[rank_group][4][0][0] = l_value_n0_u8; - l_gate_delay_value_u8[rank_group][4][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 57, 3); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 61, 3); - l_gate_delay_value_u8[rank_group][4][1][0] = l_value_n0_u8; - l_gate_delay_value_u8[rank_group][4][1][1] = l_value_n1_u8; - - if(rc_num) - { - rc.setEcmdError(rc_num); - return rc; - } - - } - } - - - - - //Finding the lowest Values on disabled bytes, then resetting mask. - for(block = 0; block < maxblocks; block++) - { - for (byte = 0; byte < maxbytes; byte++) - { - - for (nibble = 0; nibble < maxnibbles; nibble++) - { - if ( (l_disable_value_u8[0][block][byte][nibble] != 0) || (l_disable_value_u8[1][block][byte][nibble] != 0) - || (l_disable_value_u8[2][block][byte][nibble] != 0) || (l_disable_value_u8[3][block][byte][nibble] != 0) ) - { - - FAPI_INF( "Located disabled block %d byte %d nibble %d", block, byte, nibble); - - l_min_gate_delay = 255; - for(rank_group = 0; rank_group < MAX_PRI_RANKS; rank_group++) - { - if ( (l_gate_delay_value_u8[rank_group][block][byte][nibble] < l_min_gate_delay) - && (l_disable_value_u8[rank_group][block][byte][nibble] == 0) ) - { - l_min_gate_delay = l_gate_delay_value_u8[rank_group][block][byte][nibble]; - } - } - - FAPI_INF( "Lowest gate_delay %d", l_min_gate_delay); - - l_min_dqs_clk = 255; - for(rank_group = 0; rank_group < MAX_PRI_RANKS; rank_group++) - { - if ( (l_lowest_value_u8[rank_group][block][byte][nibble] < l_min_dqs_clk) - && (l_disable_value_u8[rank_group][block][byte][nibble] == 0) ) - { - l_min_dqs_clk = l_lowest_value_u8[rank_group][block][byte][nibble]; - } - } - - - FAPI_INF( "Lowest rdclk phase %d", l_min_dqs_clk); - - for(rank_group = 0; rank_group < MAX_PRI_RANKS; rank_group++) - { - if (l_disable_value_u8[rank_group][block][byte][nibble] != 0) - { - l_gate_delay_value_u8[rank_group][block][byte][nibble] = l_min_gate_delay; - l_lowest_value_u8[rank_group][block][byte][nibble] = l_min_dqs_clk; - //l_disable_value_u8[rank_group][block][byte][nibble] = 0; - } - } - - } - } - } - - } - - - //Scoming in the New Values - for(rank_group = 0; rank_group < MAX_PRI_RANKS; rank_group++) - { - - //Check if rank group exists - if(primary_ranks_array[rank_group][port] != 255) - { - - if ( port == 0 ) - { - - if ( rank_group == 0 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_0x800000090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_0x800004090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_0x800008090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_0x80000C090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_0x800010090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_0_0x800000130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_1_0x800004130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_2_0x800008130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_3_0x80000C130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_4_0x800010130301143F; - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_0_0x8000007c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_1_0x8000047c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_2_0x8000087c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_3_0x80000c7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_4_0x8000107c0301143F; - - - } - else if ( rank_group == 1 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_0x800001090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_0x800005090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_0x800009090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_0x80000D090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_0x800011090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_0_0x800001130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_1_0x800005130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_2_0x800009130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_3_0x80000D130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_4_0x800011130301143F; - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_0_0x8000017c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_1_0x8000057c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_2_0x8000097c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_3_0x80000d7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_4_0x8000117c0301143F; - - } - else if ( rank_group == 2 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_0x800002090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_0x800006090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_0x80000A090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_0x80000E090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_0x800012090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_0_0x800002130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_1_0x800006130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_2_0x80000A130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_3_0x80000E130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_4_0x800012130301143F; - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_0_0x8000027c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_1_0x8000067c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_2_0x80000a7c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_3_0x80000e7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_4_0x8000127c0301143F; - - } - else if ( rank_group == 3 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_0x800003090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_0x800007090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_0x80000B090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_0x80000F090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_0x800013090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_0_0x800003130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_1_0x800007130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_2_0x80000B130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_3_0x80000F130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_4_0x800013130301143F; - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_0_0x8000037c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_1_0x8000077c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_2_0x80000b7c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_3_0x80000f7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_4_0x8000137c0301143F; - - } - } - else if (port == 1 ) - { - - if ( rank_group == 0 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_0_0x800100090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_1_0x800104090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_2_0x800108090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_3_0x80010C090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_4_0x800110090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_0_0x800100130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_1_0x800104130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_2_0x800108130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_3_0x80010C130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_4_0x800110130301143F; - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_0_0x8001007c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_1_0x8001047c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_2_0x8001087c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_3_0x80010c7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_4_0x8001107c0301143F; - - } - else if ( rank_group == 1 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_0_0x800101090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_1_0x800105090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_2_0x800109090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_3_0x80010D090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_4_0x800111090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_0_0x800101130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_1_0x800105130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_2_0x800109130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_3_0x80010D130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_4_0x800111130301143F; - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_0_0x8001017c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_1_0x8001057c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_2_0x8001097c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_3_0x80010d7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_4_0x8001117c0301143F; - - } - else if ( rank_group == 2 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_0_0x800102090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_1_0x800106090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_2_0x80010A090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_3_0x80010E090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_4_0x800112090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_0_0x800102130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_1_0x800106130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_2_0x80010A130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_3_0x80010E130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_4_0x800112130301143F; - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_0_0x8001027c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_1_0x8001067c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_2_0x80010a7c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_3_0x80010e7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_4_0x8001127c0301143F; - - } - else if ( rank_group == 3 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_0_0x800103090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_1_0x800107090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_2_0x80010B090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_3_0x80010F090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_4_0x800113090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_0_0x800103130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_1_0x800107130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_2_0x80010B130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_3_0x80010F130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_4_0x800113130301143F; - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_0_0x8001037c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_1_0x8001077c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_2_0x80010b7c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_3_0x80010f7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_4_0x8001137c0301143F; - - } - } - - //BLOCK 0 - rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_0, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][0][0][0], 50, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][0][0][1], 54, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][0][1][0], 58, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][0][1][1], 62, 2); - rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_0, data_buffer_64); - if (rc) return rc; - - rc = fapiGetScom(i_target, GATE_DELAY_ADDR_0, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][0][0][0], 49, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][0][0][1], 53, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][0][1][0], 57, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][0][1][1], 61, 3); - rc = fapiPutScom(i_target, GATE_DELAY_ADDR_0, data_buffer_64); - if (rc) return rc; - - //BLOCK 1 - rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_1, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][1][0][0], 50, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][1][0][1], 54, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][1][1][0], 58, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][1][1][1], 62, 2); - rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_1, data_buffer_64); - if (rc) return rc; - - rc = fapiGetScom(i_target, GATE_DELAY_ADDR_1, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][1][0][0], 49, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][1][0][1], 53, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][1][1][0], 57, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][1][1][1], 61, 3); - rc = fapiPutScom(i_target, GATE_DELAY_ADDR_1, data_buffer_64); - if (rc) return rc; - - //BLOCK 2 - rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_2, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][2][0][0], 50, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][2][0][1], 54, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][2][1][0], 58, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][2][1][1], 62, 2); - rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_2, data_buffer_64); - if (rc) return rc; - - rc = fapiGetScom(i_target, GATE_DELAY_ADDR_2, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][2][0][0], 49, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][2][0][1], 53, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][2][1][0], 57, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][2][1][1], 61, 3); - rc = fapiPutScom(i_target, GATE_DELAY_ADDR_2, data_buffer_64); - if (rc) return rc; - - //BLOCK 3 - rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_3, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][3][0][0], 50, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][3][0][1], 54, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][3][1][0], 58, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][3][1][1], 62, 2); - rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_3, data_buffer_64); - if (rc) return rc; - - rc = fapiGetScom(i_target, GATE_DELAY_ADDR_3, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][3][0][0], 49, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][3][0][1], 53, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][3][1][0], 57, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][3][1][1], 61, 3); - rc = fapiPutScom(i_target, GATE_DELAY_ADDR_3, data_buffer_64); - if (rc) return rc; - - //Block 4 - rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_4, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][4][0][0], 50, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][4][0][1], 54, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][4][1][0], 58, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][4][1][1], 62, 2); - rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_4, data_buffer_64); - if (rc) return rc; - - rc = fapiGetScom(i_target, GATE_DELAY_ADDR_4, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][4][0][0], 49, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][4][0][1], 53, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][4][1][0], 57, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][4][1][1], 61, 3); - rc = fapiPutScom(i_target, GATE_DELAY_ADDR_4, data_buffer_64); - if (rc) return rc; - - if(rc_num) - { - rc.setEcmdError(rc_num); - return rc; - } - - - } - } - } - - return rc; -} - -ReturnCode mss_wr_lvl_disable_workaround( - Target& i_target - ) -{ - //MBA target level - //DQS_CLK for each nibble of a byte is being adjusted to the lowest value for the given byte - //Across all byte lanes - - uint8_t primary_ranks_array[4][2]; //primary_ranks_array[group][port] - ecmdDataBufferBase data_buffer_64(64); - uint64_t DISABLE_ADDR_0 = 0; - uint64_t DISABLE_ADDR_1 = 0; - uint64_t DISABLE_ADDR_2 = 0; - uint64_t DISABLE_ADDR_3 = 0; - uint64_t DISABLE_ADDR_4 = 0; - - uint64_t DQSCLK_RD_PHASE_ADDR_0 = 0; - uint64_t DQSCLK_RD_PHASE_ADDR_1 = 0; - uint64_t DQSCLK_RD_PHASE_ADDR_2 = 0; - uint64_t DQSCLK_RD_PHASE_ADDR_3 = 0; - uint64_t DQSCLK_RD_PHASE_ADDR_4 = 0; - uint64_t GATE_DELAY_ADDR_0 = 0; - uint64_t GATE_DELAY_ADDR_1 = 0; - uint64_t GATE_DELAY_ADDR_2 = 0; - uint64_t GATE_DELAY_ADDR_3 = 0; - uint64_t GATE_DELAY_ADDR_4 = 0; - uint8_t port = 0; - uint8_t rank_group = 0; - uint8_t l_value_n0_u8 = 0; - uint8_t l_value_n1_u8 = 0; - - ReturnCode rc; - uint32_t rc_num = 0; - - uint8_t block; - uint32_t maxblocks = 5; - uint32_t byte; - uint32_t maxbytes = 2; - uint32_t nibble; - uint32_t maxnibbles = 2; - - - uint8_t l_dqsclk_phase_value_u8[4][5][2][2]; // l_lowest_value_u8[group][block][byte_of_reg][nibble_of_byte] - uint8_t l_disable_value_u8[4][5][2][2]; - uint8_t l_disable_old_value_u8[4][5][2][2]; - uint8_t l_gate_delay_value_u8[4][5][2][2]; - uint8_t l_rdclk_phase_value_u8[4][5][2][2]; - - - - //populate primary_ranks_arrays_array - rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP0, &i_target, primary_ranks_array[0]); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP1, &i_target, primary_ranks_array[1]); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP2, &i_target, primary_ranks_array[2]); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP3, &i_target, primary_ranks_array[3]); - if(rc) return rc; - - FAPI_DBG("WR LVL DISABLE WORKAROUND: Entered WR_LVL workaround"); - - for(port = 0; port < MAX_PORTS; port++) - { - //Gather all the byte information - for(rank_group = 0; rank_group < MAX_PRI_RANKS; rank_group++) - { - - //Initialize values - for(block = 0; block < maxblocks; block++) - { - for (byte = 0; byte < maxbytes; byte++) - { - for (nibble = 0; nibble < maxnibbles; nibble++) - { - l_dqsclk_phase_value_u8[rank_group][block][byte][nibble] = 255; - l_gate_delay_value_u8[rank_group][block][byte][nibble] = 255; - l_rdclk_phase_value_u8[rank_group][block][byte][nibble] = 255; - l_disable_value_u8[rank_group][block][byte][nibble] = 0; - l_disable_old_value_u8[rank_group][block][byte][nibble] = 0; - - } - } - } - - //Check if rank group exists - if(primary_ranks_array[rank_group][port] != 255) - { - FAPI_DBG("WR LVL DISABLE WORKAROUND: DISABLE Workaround being applied on %s PORT: %d RP: %d", i_target.toEcmdString(), port, rank_group); - - if ( port == 0 ) - { - - if ( rank_group == 0 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_0x800000090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_0x800004090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_0x800008090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_0x80000C090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_0x800010090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_0_0x800000130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_1_0x800004130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_2_0x800008130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_3_0x80000C130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_4_0x800010130301143F; - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_0_0x8000007c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_1_0x8000047c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_2_0x8000087c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_3_0x80000c7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_4_0x8000107c0301143F; - - - } - else if ( rank_group == 1 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_0x800001090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_0x800005090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_0x800009090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_0x80000D090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_0x800011090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_0_0x800001130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_1_0x800005130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_2_0x800009130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_3_0x80000D130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_4_0x800011130301143F; - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_0_0x8000017c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_1_0x8000057c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_2_0x8000097c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_3_0x80000d7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_4_0x8000117c0301143F; - - } - else if ( rank_group == 2 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_0x800002090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_0x800006090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_0x80000A090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_0x80000E090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_0x800012090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_0_0x800002130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_1_0x800006130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_2_0x80000A130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_3_0x80000E130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_4_0x800012130301143F; - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_0_0x8000027c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_1_0x8000067c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_2_0x80000a7c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_3_0x80000e7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_4_0x8000127c0301143F; - - } - else if ( rank_group == 3 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_0x800003090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_0x800007090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_0x80000B090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_0x80000F090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_0x800013090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_0_0x800003130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_1_0x800007130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_2_0x80000B130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_3_0x80000F130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_4_0x800013130301143F; - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_0_0x8000037c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_1_0x8000077c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_2_0x80000b7c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_3_0x80000f7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_4_0x8000137c0301143F; - - } - } - else if (port == 1 ) - { - - if ( rank_group == 0 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_0_0x800100090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_1_0x800104090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_2_0x800108090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_3_0x80010C090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_4_0x800110090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_0_0x800100130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_1_0x800104130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_2_0x800108130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_3_0x80010C130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_4_0x800110130301143F; - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_0_0x8001007c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_1_0x8001047c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_2_0x8001087c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_3_0x80010c7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_4_0x8001107c0301143F; - - } - else if ( rank_group == 1 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_0_0x800101090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_1_0x800105090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_2_0x800109090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_3_0x80010D090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_4_0x800111090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_0_0x800101130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_1_0x800105130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_2_0x800109130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_3_0x80010D130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_4_0x800111130301143F; - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_0_0x8001017c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_1_0x8001057c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_2_0x8001097c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_3_0x80010d7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_4_0x8001117c0301143F; - - } - else if ( rank_group == 2 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_0_0x800102090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_1_0x800106090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_2_0x80010A090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_3_0x80010E090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_4_0x800112090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_0_0x800102130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_1_0x800106130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_2_0x80010A130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_3_0x80010E130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_4_0x800112130301143F; - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_0_0x8001027c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_1_0x8001067c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_2_0x80010a7c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_3_0x80010e7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_4_0x8001127c0301143F; - - } - else if ( rank_group == 3 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_0_0x800103090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_1_0x800107090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_2_0x80010B090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_3_0x80010F090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_4_0x800113090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_0_0x800103130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_1_0x800107130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_2_0x80010B130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_3_0x80010F130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_4_0x800113130301143F; - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_0_0x8001037c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_1_0x8001077c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_2_0x80010b7c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_3_0x80010f7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_4_0x8001137c0301143F; - - } - } - - - // PHY BLOCK 0 - - rc = fapiGetScom(i_target, DISABLE_ADDR_0, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 4); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 4); - l_disable_value_u8[rank_group][0][0][0] = l_value_n0_u8; - l_disable_value_u8[rank_group][0][0][1] = l_value_n1_u8; - l_disable_old_value_u8[rank_group][0][0][0] = l_value_n0_u8; - l_disable_old_value_u8[rank_group][0][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 4); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 4); - l_disable_value_u8[rank_group][0][1][0] = l_value_n0_u8; - l_disable_value_u8[rank_group][0][1][1] = l_value_n1_u8; - l_disable_old_value_u8[rank_group][0][1][0] = l_value_n0_u8; - l_disable_old_value_u8[rank_group][0][1][1] = l_value_n1_u8; - - - rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_0, data_buffer_64); - if (rc) return rc; - // Grabbing 2 nibbles of the same byte and making them equal the same lowest value - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 2); - l_dqsclk_phase_value_u8[rank_group][0][0][0] = l_value_n0_u8; - l_dqsclk_phase_value_u8[rank_group][0][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 2); - l_dqsclk_phase_value_u8[rank_group][0][1][0] = l_value_n0_u8; - l_dqsclk_phase_value_u8[rank_group][0][1][1] = l_value_n1_u8; - - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 50, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 54, 2); - l_rdclk_phase_value_u8[rank_group][0][0][0] = l_value_n0_u8; - l_rdclk_phase_value_u8[rank_group][0][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 58, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 62, 2); - l_rdclk_phase_value_u8[rank_group][0][1][0] = l_value_n0_u8; - l_rdclk_phase_value_u8[rank_group][0][1][1] = l_value_n1_u8; - - - rc = fapiGetScom(i_target, GATE_DELAY_ADDR_0, data_buffer_64); - if (rc) return rc; - // Grabbing 2 nibbles of the same byte and making them equal the same lowest value - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 49, 3); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 53, 3); - l_gate_delay_value_u8[rank_group][0][0][0] = l_value_n0_u8; - l_gate_delay_value_u8[rank_group][0][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 57, 3); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 61, 3); - l_gate_delay_value_u8[rank_group][0][1][0] = l_value_n0_u8; - l_gate_delay_value_u8[rank_group][0][1][1] = l_value_n1_u8; - - - // PHY BLOCK 1 - - rc = fapiGetScom(i_target, DISABLE_ADDR_1, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 4); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 4); - l_disable_value_u8[rank_group][1][0][0] = l_value_n0_u8; - l_disable_value_u8[rank_group][1][0][1] = l_value_n1_u8; - l_disable_old_value_u8[rank_group][1][0][0] = l_value_n0_u8; - l_disable_old_value_u8[rank_group][1][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 4); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 4); - l_disable_value_u8[rank_group][1][1][0] = l_value_n0_u8; - l_disable_value_u8[rank_group][1][1][1] = l_value_n1_u8; - l_disable_old_value_u8[rank_group][1][1][0] = l_value_n0_u8; - l_disable_old_value_u8[rank_group][1][1][1] = l_value_n1_u8; - - - rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_1, data_buffer_64); - if (rc) return rc; - // Grabbing 2 nibbles of the same byte and making them equal the same lowest value - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 2); - l_dqsclk_phase_value_u8[rank_group][1][0][0] = l_value_n0_u8; - l_dqsclk_phase_value_u8[rank_group][1][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 2); - l_dqsclk_phase_value_u8[rank_group][1][1][0] = l_value_n0_u8; - l_dqsclk_phase_value_u8[rank_group][1][1][1] = l_value_n1_u8; - - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 50, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 54, 2); - l_rdclk_phase_value_u8[rank_group][1][0][0] = l_value_n0_u8; - l_rdclk_phase_value_u8[rank_group][1][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 58, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 62, 2); - l_rdclk_phase_value_u8[rank_group][1][1][0] = l_value_n0_u8; - l_rdclk_phase_value_u8[rank_group][1][1][1] = l_value_n1_u8; - - rc = fapiGetScom(i_target, GATE_DELAY_ADDR_1, data_buffer_64); - if (rc) return rc; - // Grabbing 2 nibbles of the same byte and making them equal the same lowest value - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 49, 3); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 53, 3); - l_gate_delay_value_u8[rank_group][1][0][0] = l_value_n0_u8; - l_gate_delay_value_u8[rank_group][1][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 57, 3); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 61, 3); - l_gate_delay_value_u8[rank_group][1][1][0] = l_value_n0_u8; - l_gate_delay_value_u8[rank_group][1][1][1] = l_value_n1_u8; - - // PHY BLOCK 2 - - rc = fapiGetScom(i_target, DISABLE_ADDR_2, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 4); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 4); - l_disable_value_u8[rank_group][2][0][0] = l_value_n0_u8; - l_disable_value_u8[rank_group][2][0][1] = l_value_n1_u8; - l_disable_old_value_u8[rank_group][2][0][0] = l_value_n0_u8; - l_disable_old_value_u8[rank_group][2][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 4); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 4); - l_disable_value_u8[rank_group][2][1][0] = l_value_n0_u8; - l_disable_value_u8[rank_group][2][1][1] = l_value_n1_u8; - l_disable_old_value_u8[rank_group][2][1][0] = l_value_n0_u8; - l_disable_old_value_u8[rank_group][2][1][1] = l_value_n1_u8; - - rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_2, data_buffer_64); - if (rc) return rc; - // Grabbing 2 nibbles of the same byte and making them equal the same lowest value - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 2); - l_dqsclk_phase_value_u8[rank_group][2][0][0] = l_value_n0_u8; - l_dqsclk_phase_value_u8[rank_group][2][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 2); - l_dqsclk_phase_value_u8[rank_group][2][1][0] = l_value_n0_u8; - l_dqsclk_phase_value_u8[rank_group][2][1][1] = l_value_n1_u8; - - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 50, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 54, 2); - l_rdclk_phase_value_u8[rank_group][2][0][0] = l_value_n0_u8; - l_rdclk_phase_value_u8[rank_group][2][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 58, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 62, 2); - l_rdclk_phase_value_u8[rank_group][2][1][0] = l_value_n0_u8; - l_rdclk_phase_value_u8[rank_group][2][1][1] = l_value_n1_u8; - - rc = fapiGetScom(i_target, GATE_DELAY_ADDR_2, data_buffer_64); - if (rc) return rc; - // Grabbing 2 nibbles of the same byte and making them equal the same lowest value - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 49, 3); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 53, 3); - l_gate_delay_value_u8[rank_group][2][0][0] = l_value_n0_u8; - l_gate_delay_value_u8[rank_group][2][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 57, 3); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 61, 3); - l_gate_delay_value_u8[rank_group][2][1][0] = l_value_n0_u8; - l_gate_delay_value_u8[rank_group][2][1][1] = l_value_n1_u8; - - // PHY BLOCK 3 - - rc = fapiGetScom(i_target, DISABLE_ADDR_3, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 4); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 4); - l_disable_value_u8[rank_group][3][0][0] = l_value_n0_u8; - l_disable_value_u8[rank_group][3][0][1] = l_value_n1_u8; - l_disable_old_value_u8[rank_group][3][0][0] = l_value_n0_u8; - l_disable_old_value_u8[rank_group][3][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 4); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 4); - l_disable_value_u8[rank_group][3][1][0] = l_value_n0_u8; - l_disable_value_u8[rank_group][3][1][1] = l_value_n1_u8; - l_disable_old_value_u8[rank_group][3][1][0] = l_value_n0_u8; - l_disable_old_value_u8[rank_group][3][1][1] = l_value_n1_u8; - - - rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_3, data_buffer_64); - if (rc) return rc; - // Grabbing 2 nibbles of the same byte and making them equal the same lowest value - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 2); - l_dqsclk_phase_value_u8[rank_group][3][0][0] = l_value_n0_u8; - l_dqsclk_phase_value_u8[rank_group][3][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 2); - l_dqsclk_phase_value_u8[rank_group][3][1][0] = l_value_n0_u8; - l_dqsclk_phase_value_u8[rank_group][3][1][1] = l_value_n1_u8; - - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 50, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 54, 2); - l_rdclk_phase_value_u8[rank_group][3][0][0] = l_value_n0_u8; - l_rdclk_phase_value_u8[rank_group][3][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 58, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 62, 2); - l_rdclk_phase_value_u8[rank_group][3][1][0] = l_value_n0_u8; - l_rdclk_phase_value_u8[rank_group][3][1][1] = l_value_n1_u8; - - rc = fapiGetScom(i_target, GATE_DELAY_ADDR_3, data_buffer_64); - if (rc) return rc; - // Grabbing 2 nibbles of the same byte and making them equal the same lowest value - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 49, 3); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 53, 3); - l_gate_delay_value_u8[rank_group][3][0][0] = l_value_n0_u8; - l_gate_delay_value_u8[rank_group][3][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 57, 3); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 61, 3); - l_gate_delay_value_u8[rank_group][3][1][0] = l_value_n0_u8; - l_gate_delay_value_u8[rank_group][3][1][1] = l_value_n1_u8; - - // PHY BLOCK 4 - - rc = fapiGetScom(i_target, DISABLE_ADDR_4, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 4); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 4); - l_disable_value_u8[rank_group][4][0][0] = l_value_n0_u8; - l_disable_value_u8[rank_group][4][0][1] = l_value_n1_u8; - l_disable_old_value_u8[rank_group][4][0][0] = l_value_n0_u8; - l_disable_old_value_u8[rank_group][4][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 4); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 4); - l_disable_value_u8[rank_group][4][1][0] = l_value_n0_u8; - l_disable_value_u8[rank_group][4][1][1] = l_value_n1_u8; - l_disable_old_value_u8[rank_group][4][1][0] = l_value_n0_u8; - l_disable_old_value_u8[rank_group][4][1][1] = l_value_n1_u8; - - rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_4, data_buffer_64); - if (rc) return rc; - // Grabbing 2 nibbles of the same byte and making them equal the same lowest value - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 2); - l_dqsclk_phase_value_u8[rank_group][4][0][0] = l_value_n0_u8; - l_dqsclk_phase_value_u8[rank_group][4][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 2); - l_dqsclk_phase_value_u8[rank_group][4][1][0] = l_value_n0_u8; - l_dqsclk_phase_value_u8[rank_group][4][1][1] = l_value_n1_u8; - - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 50, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 54, 2); - l_rdclk_phase_value_u8[rank_group][4][0][0] = l_value_n0_u8; - l_rdclk_phase_value_u8[rank_group][4][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 58, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 62, 2); - l_rdclk_phase_value_u8[rank_group][4][1][0] = l_value_n0_u8; - l_rdclk_phase_value_u8[rank_group][4][1][1] = l_value_n1_u8; - - rc = fapiGetScom(i_target, GATE_DELAY_ADDR_4, data_buffer_64); - if (rc) return rc; - // Grabbing 2 nibbles of the same byte and making them equal the same lowest value - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 49, 3); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 53, 3); - l_gate_delay_value_u8[rank_group][4][0][0] = l_value_n0_u8; - l_gate_delay_value_u8[rank_group][4][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 57, 3); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 61, 3); - l_gate_delay_value_u8[rank_group][4][1][0] = l_value_n0_u8; - l_gate_delay_value_u8[rank_group][4][1][1] = l_value_n1_u8; - - if(rc_num) - { - rc.setEcmdError(rc_num); - return rc; - } - - } - } - - uint8_t ranks_array[4][4][2]; //[group][rank_group position][port] - // Determine rank and rank group matching - rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP0, &i_target, ranks_array[0][0]); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP1, &i_target, ranks_array[1][0]); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP2, &i_target, ranks_array[2][0]); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP3, &i_target, ranks_array[3][0]); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_SECONDARY_RANK_GROUP0, &i_target, ranks_array[0][1]); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_SECONDARY_RANK_GROUP1, &i_target, ranks_array[1][1]); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_SECONDARY_RANK_GROUP2, &i_target, ranks_array[2][1]); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_SECONDARY_RANK_GROUP3, &i_target, ranks_array[3][1]); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_TERTIARY_RANK_GROUP0, &i_target, ranks_array[0][2]); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_TERTIARY_RANK_GROUP1, &i_target, ranks_array[1][2]); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_TERTIARY_RANK_GROUP2, &i_target, ranks_array[2][2]); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_TERTIARY_RANK_GROUP3, &i_target, ranks_array[3][2]); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_QUATERNARY_RANK_GROUP0, &i_target, ranks_array[0][3]); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_QUATERNARY_RANK_GROUP1, &i_target, ranks_array[1][3]); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_QUATERNARY_RANK_GROUP2, &i_target, ranks_array[2][3]); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_QUATERNARY_RANK_GROUP3, &i_target, ranks_array[3][3]); if(rc) return rc; - - - access_type_t l_access_type_e = READ; - //READ - //WRITE - input_type_t l_input_type_e = WR_DQS; - //WR_DQ_t, - //RAW_WR_DQ, - //WR_DQS_t, - //RAW_WR_DQS, - uint8_t l_flag = 0; - uint8_t l_verbose = 0; - uint8_t l_rank_u8; - uint32_t l_old_delay_value_u32 = 0; - uint32_t l_old_DQS_delay_value_u32 = 0; - uint32_t l_delay_value_u32 = 0; - uint32_t l_DQS_delay_value_u32 = 0; - uint8_t l_index_u8 = 0; - uint8_t mask; - uint8_t nibble_dq; - uint8_t lane; - uint8_t rg; - uint8_t rank_2; - uint8_t width; - uint8_t dqs_index; - - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target, width); - - uint32_t instruction_number = 0; - ecmdDataBufferBase address_buffer_16(16); - rc_num = rc_num | address_buffer_16.flushTo0(); - ecmdDataBufferBase bank_buffer_8(8); - rc_num = rc_num | bank_buffer_8.flushTo0(); - ecmdDataBufferBase activate_buffer_1(1); - rc_num = rc_num | activate_buffer_1.flushTo0(); - ecmdDataBufferBase rasn_buffer_1(1); - ecmdDataBufferBase casn_buffer_1(1); - ecmdDataBufferBase wen_buffer_1(1); - ecmdDataBufferBase cke_buffer_8(8); - rc_num = rc_num | cke_buffer_8.flushTo1(); - ecmdDataBufferBase csn_buffer_8(8); - rc_num = rc_num | csn_buffer_8.flushTo1(); - ecmdDataBufferBase odt_buffer_8(8); - rc_num = rc_num | odt_buffer_8.flushTo0(); - ecmdDataBufferBase test_buffer_4(4); - rc_num = rc_num | test_buffer_4.setBit(0,4); - - ecmdDataBufferBase num_idles_buffer_16(16); - rc_num = rc_num | num_idles_buffer_16.flushTo1(); - ecmdDataBufferBase num_repeat_buffer_16(16); - rc_num = rc_num | num_repeat_buffer_16.flushTo0(); - ecmdDataBufferBase data_buffer_20(20); - rc_num = rc_num | data_buffer_20.flushTo0(); - ecmdDataBufferBase read_compare_buffer_1(1); - rc_num = rc_num | read_compare_buffer_1.flushTo0(); - ecmdDataBufferBase rank_cal_buffer_4(4); - rc_num = rc_num | rank_cal_buffer_4.flushTo0(); - ecmdDataBufferBase ddr_cal_enable_buffer_1(1); - rc_num = rc_num | ddr_cal_enable_buffer_1.flushTo1(); - ecmdDataBufferBase ccs_end_buffer_1(1); - rc_num = rc_num | ccs_end_buffer_1.flushTo1(); - uint8_t group = 255; - const uint32_t NUM_POLL = 10000; - - - uint8_t cur_cal_step = 2; - enum mss_draminit_training_result cur_error_status = MSS_INIT_CAL_PASS; - uint8_t mbaPosition; - // Get MBA position: 0 = mba01, 1 = mba23 - rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target, mbaPosition); - if(rc) - { - FAPI_ERR("Error getting MBA position"); - return rc; - } - - - - //Resetting Disable mask. Avoid spares. - for(block = 0; block < maxblocks; block++) - { - for (byte = 0; byte < 2; byte++) - { - - for (nibble = 0; nibble < maxnibbles; nibble++) - { - - for(rank_group = 0; rank_group < MAX_PRI_RANKS; rank_group++) - { - - //Check if rank group exists - if(primary_ranks_array[rank_group][port] != 255) - { - - - if ( port == 0 ) - { - - if ( rank_group == 0 ) - { - - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_0_0x8000007c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_1_0x8000047c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_2_0x8000087c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_3_0x80000c7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_4_0x8000107c0301143F; - - } - else if ( rank_group == 1 ) - { - - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_0_0x8000017c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_1_0x8000057c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_2_0x8000097c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_3_0x80000d7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_4_0x8000117c0301143F; - - } - else if ( rank_group == 2 ) - { - - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_0_0x8000027c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_1_0x8000067c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_2_0x80000a7c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_3_0x80000e7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_4_0x8000127c0301143F; - - } - else if ( rank_group == 3 ) - { - - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_0_0x8000037c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_1_0x8000077c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_2_0x80000b7c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_3_0x80000f7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_4_0x8000137c0301143F; - - } - } - else if (port == 1 ) - { - - if ( rank_group == 0 ) - { - - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_0_0x8001007c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_1_0x8001047c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_2_0x8001087c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_3_0x80010c7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_4_0x8001107c0301143F; - - } - else if ( rank_group == 1 ) - { - - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_0_0x8001017c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_1_0x8001057c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_2_0x8001097c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_3_0x80010d7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_4_0x8001117c0301143F; - - - } - else if ( rank_group == 2 ) - { - - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_0_0x8001027c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_1_0x8001067c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_2_0x80010a7c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_3_0x80010e7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_4_0x8001127c0301143F; - - - } - else if ( rank_group == 3 ) - { - - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_0_0x8001037c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_1_0x8001077c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_2_0x80010b7c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_3_0x80010f7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_4_0x8001137c0301143F; - - } - } - - lane = byte * 8 + nibble*4; - l_input_type_e = WR_DQ; - l_flag = 1; - // C4 DQ to lane/block (flag = 0) in PHY or lane/block to C4 DQ (flag = 1) - // In this case moving from lane/block to C4 DQ to determine spare - rc = mss_c4_phy(i_target, port, rank_group, l_input_type_e, l_index_u8, l_verbose, lane, block, l_flag); - if (rc) return rc; - - dqs_index = l_index_u8 / 8; - - - if ( ((dqs_index % 9 == 0)&&(dqs_index/9 > 0)) && (l_disable_value_u8[rank_group][block][byte][nibble] != 0x0)) - { - //This is a spare. Unmark it in the old map for the rest of the workaround to not operate on a spare - FAPI_DBG("WR LVL DISABLE WORKAROUND: Denoting Spare that is disabled for block: %d byte: %d nibble: %d Previous Value: 0x%02X", block, byte, nibble, l_disable_value_u8[rank_group][block][byte][nibble]); - l_disable_old_value_u8[rank_group][block][byte][nibble] = 0x00; - - } - else if (l_disable_value_u8[rank_group][block][byte][nibble] != 0x00) - { - //This is not a spare. Unmark into what will be scommed back in; to be able to reset the disable mask. - FAPI_DBG("WR LVL DISABLE WORKAROUND: Unmasking disable for block: %d byte: %d nibble: %d Previous Value: 0x%02X", block, byte, nibble, l_disable_value_u8[rank_group][block][byte][nibble]); - l_disable_value_u8[rank_group][block][byte][nibble] = 0x00; - - } - - - //BLOCK 0 - rc = fapiGetScom(i_target, DISABLE_ADDR_0, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][0][0][0], 48, 4); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][0][0][1], 52, 4); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][0][1][0], 56, 4); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][0][1][1], 60, 4); - rc = fapiPutScom(i_target, DISABLE_ADDR_0, data_buffer_64); - if (rc) return rc; - - //BLOCK 1 - - rc = fapiGetScom(i_target, DISABLE_ADDR_1, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][1][0][0], 48, 4); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][1][0][1], 52, 4); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][1][1][0], 56, 4); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][1][1][1], 60, 4); - rc = fapiPutScom(i_target, DISABLE_ADDR_1, data_buffer_64); - if (rc) return rc; - - //BLOCK 2 - - rc = fapiGetScom(i_target, DISABLE_ADDR_2, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][2][0][0], 48, 4); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][2][0][1], 52, 4); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][2][1][0], 56, 4); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][2][1][1], 60, 4); - rc = fapiPutScom(i_target, DISABLE_ADDR_2, data_buffer_64); - if (rc) return rc; - - - //BLOCK 3 - - rc = fapiGetScom(i_target, DISABLE_ADDR_3, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][3][0][0], 48, 4); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][3][0][1], 52, 4); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][3][1][0], 56, 4); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][3][1][1], 60, 4); - rc = fapiPutScom(i_target, DISABLE_ADDR_3, data_buffer_64); - if (rc) return rc; - - - //Block 4 - rc = fapiGetScom(i_target, DISABLE_ADDR_4, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][4][0][0], 48, 4); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][4][0][1], 52, 4); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][4][1][0], 56, 4); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][4][1][1], 60, 4); - rc = fapiPutScom(i_target, DISABLE_ADDR_4, data_buffer_64); - if (rc) return rc; - - - } - } - } - } - } - - - //Re-run DQS ALIGN for only rank_group/ports that had a disable. - - for(rank_group = 0; rank_group < MAX_PRI_RANKS; rank_group++) - { - group = 255; - for(block = 0; block < maxblocks; block++) - { - for (byte = 0; byte < maxbytes; byte++) - { - - for (nibble = 0; nibble < maxnibbles; nibble++) - { - //Check if rank group exists - if(primary_ranks_array[rank_group][port] != 255) - { - if (l_disable_old_value_u8[rank_group][block][byte][nibble] != 0x0) - { - group = rank_group; - } - } - - } - } - } - FAPI_DBG("WR LVL DISABLE WORKAROUND: DQS ALIGN LOOP on group: %d rank_group: %d port: %d", group, rank_group, port); - if (group != 255) - { - - FAPI_DBG("WR LVL DISABLE WORKAROUND: Re-Running DQS ALIGN on rank_group: %d port: %d", group, port); - //Clearing any status or errors bits that may have occured in previous training subtest. - if(port == 0) - { - //clear status reg - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_STATUS_P0_0x8000C0190301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.clearBit(48, 4); - rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_STATUS_P0_0x8000C0190301143F, data_buffer_64); - if(rc) return rc; - - //clear error reg - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_ERROR_P0_0x8000C0180301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.clearBit(48, 11); - rc_num = rc_num | data_buffer_64.clearBit(60, 4); - rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_ERROR_P0_0x8000C0180301143F, data_buffer_64); - if(rc) return rc; - - //clear other port - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P1_0x8001C0160301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.clearBit(48); - rc_num = rc_num | data_buffer_64.clearBit(50); - rc_num = rc_num | data_buffer_64.clearBit(51); - rc_num = rc_num | data_buffer_64.clearBit(52); - rc_num = rc_num | data_buffer_64.clearBit(53); - rc_num = rc_num | data_buffer_64.clearBit(54); - rc_num = rc_num | data_buffer_64.clearBit(55); - rc_num = rc_num | data_buffer_64.clearBit(58); - rc_num = rc_num | data_buffer_64.clearBit(60); - rc_num = rc_num | data_buffer_64.clearBit(61); - rc_num = rc_num | data_buffer_64.clearBit(62); - rc_num = rc_num | data_buffer_64.clearBit(63); - rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P1_0x8001C0160301143F, data_buffer_64); - if(rc) return rc; - - //Setup the Config Reg bit for the only cal step we want - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P0_0x8000C0160301143F, data_buffer_64); - if(rc) return rc; - - } - else - { - //clear status reg - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_STATUS_P1_0x8001C0190301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.clearBit(48, 4); - rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_STATUS_P1_0x8001C0190301143F, data_buffer_64); - if(rc) return rc; - - //clear error reg - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_ERROR_P1_0x8001C0180301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.clearBit(48, 11); - rc_num = rc_num | data_buffer_64.clearBit(60, 4); - rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_ERROR_P1_0x8001C0180301143F, data_buffer_64); - if(rc) return rc; - - //clear other port - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P0_0x8000C0160301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.clearBit(48); - rc_num = rc_num | data_buffer_64.clearBit(50); - rc_num = rc_num | data_buffer_64.clearBit(51); - rc_num = rc_num | data_buffer_64.clearBit(52); - rc_num = rc_num | data_buffer_64.clearBit(53); - rc_num = rc_num | data_buffer_64.clearBit(54); - rc_num = rc_num | data_buffer_64.clearBit(55); - rc_num = rc_num | data_buffer_64.clearBit(58); - rc_num = rc_num | data_buffer_64.clearBit(60); - rc_num = rc_num | data_buffer_64.clearBit(61); - rc_num = rc_num | data_buffer_64.clearBit(62); - rc_num = rc_num | data_buffer_64.clearBit(63); - rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P0_0x8000C0160301143F, data_buffer_64); - if(rc) return rc; - - //Setup the Config Reg bit for the only cal step we want - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P1_0x8001C0160301143F, data_buffer_64); - if(rc) return rc; - - } - - //Clear training cnfg - rc_num = rc_num | data_buffer_64.clearBit(48); - rc_num = rc_num | data_buffer_64.setBit(50); - rc_num = rc_num | data_buffer_64.clearBit(51); - rc_num = rc_num | data_buffer_64.clearBit(52); - rc_num = rc_num | data_buffer_64.clearBit(53); - rc_num = rc_num | data_buffer_64.clearBit(54); - rc_num = rc_num | data_buffer_64.clearBit(55); - rc_num = rc_num | data_buffer_64.clearBit(60); - rc_num = rc_num | data_buffer_64.clearBit(61); - rc_num = rc_num | data_buffer_64.clearBit(62); - rc_num = rc_num | data_buffer_64.clearBit(63); - - if(group == 0){ - rc_num = rc_num | data_buffer_64.setBit(60); - } - else if(group == 1){ - rc_num = rc_num | data_buffer_64.setBit(61); - } - else if(group == 2){ - rc_num = rc_num | data_buffer_64.setBit(62); - } - else if(group == 3){ - rc_num = rc_num | data_buffer_64.setBit(63); - } - - //Set the config register - if(port == 0) - { - rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P0_0x8000C0160301143F, data_buffer_64); - if(rc) return rc; - } - else - { - rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P1_0x8001C0160301143F, data_buffer_64); - if(rc) return rc; - } - - rc = mss_ccs_inst_arry_0(i_target, - instruction_number, - address_buffer_16, - bank_buffer_8, - activate_buffer_1, - rasn_buffer_1, - casn_buffer_1, - wen_buffer_1, - cke_buffer_8, - csn_buffer_8, - odt_buffer_8, - test_buffer_4, - port); - - if(rc) return rc; - rc_num = rc_num | rank_cal_buffer_4.insert(primary_ranks_array[rank_group][port], 0, 4, 4); // 8 bit storage, need last 4 bits - if(rc_num) - { - rc.setEcmdError(rc_num); - return rc; - } - - rc = mss_ccs_inst_arry_1(i_target, - instruction_number, - num_idles_buffer_16, - num_repeat_buffer_16, - data_buffer_20, - read_compare_buffer_1, - rank_cal_buffer_4, - ddr_cal_enable_buffer_1, - ccs_end_buffer_1); - if(rc) return rc; //Error handling for mss_ccs_inst built into mss_funcs - - rc = mss_execute_ccs_inst_array( i_target, NUM_POLL, 60); - if(rc) return rc; //Error handling for mss_ccs_inst built into mss_funcs - - //Check to see if the training errored out - rc = mss_check_error_status(i_target, mbaPosition, port, group, cur_cal_step, cur_error_status, 1); - if(rc) return rc; - - if (cur_error_status == MSS_INIT_CAL_FAIL) - { - //RC/Log is generated in mss_check_error_status - FAPI_ERR("Error returned on workaround Re-run of DQS_ALIGN on %s PORT: %d RP: %d", i_target.toEcmdString(), port, group); - } - - } - } - - uint8_t curr_bit; - - //Finding the lowest Values on disabled bytes, then resetting mask. - for(block = 0; block < maxblocks; block++) - { - for (byte = 0; byte < maxbytes; byte++) - { - - for (nibble = 0; nibble < maxnibbles; nibble++) - { - - for(rank_group = 0; rank_group < MAX_PRI_RANKS; rank_group++) - { - for (nibble_dq = 0; nibble_dq < 4; nibble_dq++) - { - - - if (l_disable_old_value_u8[rank_group][block][byte][nibble] != 0x00) - { - - FAPI_DBG("WR LVL DISABLE WORKAROUND: DISABLED block: %d byte: %d nibble: %d disable value: 0x%02X", block, byte, nibble, l_disable_old_value_u8[rank_group][block][byte][nibble]); - FAPI_DBG("WR LVL DISABLE WORKAROUND: DQSCLK replacement: block: %d byte: %d nibble: %d current value: %d", block, byte, nibble, l_dqsclk_phase_value_u8[rank_group][block][byte][nibble]); - //SWAPPING DQSCLK PHASE SELECT - for (rg = 0; rg < MAX_PRI_RANKS; rg++) - { - FAPI_DBG("WR LVL DISABLE WORKAROUND: DQSCLK possible replacement value: %d", l_dqsclk_phase_value_u8[rg][block][byte][nibble]); - - if ( (l_disable_old_value_u8[rg][block][byte][nibble] == 0) && (l_dqsclk_phase_value_u8[rg][block][byte][nibble] < l_dqsclk_phase_value_u8[rank_group][block][byte][nibble]) ) - { - FAPI_DBG("WR LVL DISABLE WORKAROUND: DQSCLK replacement: block: %d byte: %d nibble: %d", block, byte, nibble); - FAPI_DBG("WR LVL DISABLE WORKAROUND: DQSCLK replacement value: %d", l_dqsclk_phase_value_u8[rg][block][byte][nibble]); - l_dqsclk_phase_value_u8[rank_group][block][byte][nibble] = l_dqsclk_phase_value_u8[rg][block][byte][nibble]; - } - } - - FAPI_DBG("WR LVL DISABLE WORKAROUND: RDCLK replacement: block: %d byte: %d nibble: %d current value: %d", block, byte, nibble, l_dqsclk_phase_value_u8[rank_group][block][byte][nibble]); - //SWAPPING RDCLK PHASE SELECT - for (rg = 0; rg < MAX_PRI_RANKS; rg++) - { - FAPI_DBG("WR LVL DISABLE WORKAROUND: RDCLK possible replacement value: %d", l_rdclk_phase_value_u8[rg][block][byte][nibble]); - - if ( (l_disable_old_value_u8[rg][block][byte][nibble] == 0) && (l_rdclk_phase_value_u8[rg][block][byte][nibble] < l_rdclk_phase_value_u8[rank_group][block][byte][nibble]) ) - { - FAPI_DBG("WR LVL DISABLE WORKAROUND: RDCLK replacement: block: %d byte: %d nibble: %d", block, byte, nibble); - FAPI_DBG("WR LVL DISABLE WORKAROUND: RDCLK replacement value: %d", l_rdclk_phase_value_u8[rg][block][byte][nibble]); - l_rdclk_phase_value_u8[rank_group][block][byte][nibble] = l_rdclk_phase_value_u8[rg][block][byte][nibble]; - } - } - - FAPI_DBG("WR LVL DISABLE WORKAROUND: GATE DELAY replacement: block: %d byte: %d nibble: %d current value: %d", block, byte, nibble, l_dqsclk_phase_value_u8[rank_group][block][byte][nibble]); - //SWAPPING RDCLK PHASE SELECT - for (rg = 0; rg < MAX_PRI_RANKS; rg++) - { - FAPI_DBG("WR LVL DISABLE WORKAROUND: GATE DELAY possible replacement value: %d", l_gate_delay_value_u8[rg][block][byte][nibble]); - - if ( (l_disable_old_value_u8[rg][block][byte][nibble] == 0) && (l_gate_delay_value_u8[rg][block][byte][nibble] < l_gate_delay_value_u8[rank_group][block][byte][nibble]) ) - { - FAPI_DBG("WR LVL DISABLE WORKAROUND: GATE DELAY replacement: block: %d byte: %d nibble: %d", block, byte, nibble); - FAPI_DBG("WR LVL DISABLE WORKAROUND: GATE DELAY replacement value: %d", l_gate_delay_value_u8[rg][block][byte][nibble]); - l_gate_delay_value_u8[rank_group][block][byte][nibble] = l_gate_delay_value_u8[rg][block][byte][nibble]; - } - } - - //SWAPPING DQ AND DQS - mask = 0x8 >> nibble_dq; - curr_bit = l_disable_old_value_u8[rank_group][block][byte][nibble] & mask; - FAPI_DBG("WR LVL DISABLE WORKAROUND: DQ/DQS SWAP MASK: 0x%02X DISABLE BIT: 0x%02X CURR BIT: 0x%02X", mask, l_disable_old_value_u8[rank_group][block][byte][nibble] & mask, curr_bit); - - if (curr_bit) - { - - FAPI_DBG("WR LVL DISABLE WORKAROUND: DQ/DQS SWAP RANK_GROUP: %d BLOCK: %d BYTE: %d NIBBLE: %d DISABLE VALUE: 0x%02X", rank_group, block, byte, nibble, l_disable_old_value_u8[rank_group][block][byte][nibble]); - - //Figure out which lane to investigate - l_index_u8 = nibble_dq + 4 * nibble + 8 * byte; - lane = l_index_u8; - - l_input_type_e = WR_DQ; - l_flag = 1; - // C4 DQ to lane/block (flag = 0) in PHY or lane/block to C4 DQ (flag = 1) - // In this case moving from lane/block to C4 DQ to use access_delay_reg - rc = mss_c4_phy(i_target, port, rank_group, l_input_type_e, l_index_u8, l_verbose, lane, block, l_flag); - - - l_access_type_e = READ; - l_rank_u8 = ranks_array[rank_group][0][0]; - if (l_rank_u8 == 255) - continue; - - // Getting old DQ Value - l_input_type_e = WR_DQ; - rc = mss_access_delay_reg(i_target, l_access_type_e, port, ranks_array[rank_group][0][0], l_input_type_e, l_index_u8, l_verbose, l_old_delay_value_u32); - if(rc) return rc; - - - if (width == fapi::ENUM_ATTR_EFF_DRAM_WIDTH_X8) - { - dqs_index = l_index_u8 / 8; - } - else - { - dqs_index = l_index_u8 / 4; - } - - // Getting old DQS Value - l_input_type_e = WR_DQS; - rc = mss_access_delay_reg(i_target, l_access_type_e, port, ranks_array[rank_group][0][0], l_input_type_e, dqs_index, l_verbose, l_old_DQS_delay_value_u32); - if(rc) return rc; - - FAPI_DBG("WR LVL DISABLE WORKAROUND: Value being replaced C4: %d C4 DQS: %d Rank:%d DQ DELAY VALUE: 0x%03X DQS DELAY VALUE: 0x%03X ", l_index_u8, dqs_index, ranks_array[rank_group][0][0], l_old_delay_value_u32, l_old_DQS_delay_value_u32); - - for (rg = 0; rg < MAX_PRI_RANKS; rg++) - { - l_access_type_e = READ; - rank_2 = ranks_array[rg][0][0]; - FAPI_DBG("WR LVL DISABLE WORKAROUND: RANK: %d DISABLE VALUE: 0x%02X MASKED: 0x%02X", rank_2, l_disable_old_value_u8[rg][block][byte][nibble], l_disable_old_value_u8[rg][block][byte][nibble] & mask); - if ( (rank_2 != 255) && (l_disable_old_value_u8[rg][block][byte][nibble] == 0 ) ) - { - // Getting New DQ Value - l_input_type_e = WR_DQ; - rc = mss_access_delay_reg(i_target, l_access_type_e, port, rank_2, l_input_type_e, l_index_u8, l_verbose, l_delay_value_u32); - if(rc) return rc; - - // Getting New DQS Value - l_input_type_e = WR_DQS; - rc = mss_access_delay_reg(i_target, l_access_type_e, port, rank_2, l_input_type_e, dqs_index, l_verbose, l_DQS_delay_value_u32); - if(rc) return rc; - - FAPI_DBG("WR LVL DISABLE WORKAROUND: Possible Replacement Value C4: %d C4 DQS: %d Rank:%d DQ DELAY VALUE: 0x%03X DQS DELAY VALUE: 0x%03X", l_index_u8, dqs_index, rank_2, l_delay_value_u32, l_DQS_delay_value_u32); - - if ( l_delay_value_u32 < l_old_delay_value_u32) - { - l_old_delay_value_u32 = l_delay_value_u32; - // Writing DQ Value - l_access_type_e = WRITE; - l_rank_u8 = ranks_array[rank_group][0][0]; - l_input_type_e = WR_DQ; - rc = mss_access_delay_reg(i_target, l_access_type_e, port, ranks_array[rank_group][0][0], l_input_type_e, l_index_u8, l_verbose, l_delay_value_u32); - if(rc) return rc; - - FAPI_DBG("WR LVL DISABLE WORKAROUND: Replacing DQ: Value C4: %d C4 DQS: %d Rank:%d DELAY VALUE: 0x%03X", l_index_u8, dqs_index, ranks_array[rank_group][0][0], l_delay_value_u32); - } - if ( l_DQS_delay_value_u32 < l_old_DQS_delay_value_u32) - { - l_old_DQS_delay_value_u32 = l_DQS_delay_value_u32; - // Writing DQS Value - l_access_type_e = WRITE; - l_rank_u8 = ranks_array[rank_group][0][0]; - l_input_type_e = WR_DQS; - rc = mss_access_delay_reg(i_target, l_access_type_e, port, ranks_array[rank_group][0][0], l_input_type_e, dqs_index, l_verbose, l_DQS_delay_value_u32); - if(rc) return rc; - - FAPI_DBG("WR LVL DISABLE WORKAROUND: Replacing DQS: Value C4: %d C4 DQS: %d Rank:%d DQS DELAY VALUE: 0x%03X", l_index_u8, dqs_index, ranks_array[rank_group][0][0], l_DQS_delay_value_u32); - } - - } - - } - - - } - } - } - - } - } - - } - } - - - //Scoming in the New Values - for(rank_group = 0; rank_group < MAX_PRI_RANKS; rank_group++) - { - - //Check if rank group exists - if(primary_ranks_array[rank_group][port] != 255) - { - - - if ( port == 0 ) - { - - if ( rank_group == 0 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_0x800000090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_0x800004090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_0x800008090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_0x80000C090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_0x800010090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_0_0x800000130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_1_0x800004130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_2_0x800008130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_3_0x80000C130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_4_0x800010130301143F; - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_0_0x8000007c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_1_0x8000047c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_2_0x8000087c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_3_0x80000c7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_4_0x8000107c0301143F; - - - } - else if ( rank_group == 1 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_0x800001090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_0x800005090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_0x800009090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_0x80000D090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_0x800011090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_0_0x800001130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_1_0x800005130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_2_0x800009130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_3_0x80000D130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_4_0x800011130301143F; - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_0_0x8000017c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_1_0x8000057c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_2_0x8000097c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_3_0x80000d7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_4_0x8000117c0301143F; - - } - else if ( rank_group == 2 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_0x800002090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_0x800006090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_0x80000A090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_0x80000E090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_0x800012090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_0_0x800002130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_1_0x800006130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_2_0x80000A130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_3_0x80000E130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_4_0x800012130301143F; - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_0_0x8000027c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_1_0x8000067c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_2_0x80000a7c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_3_0x80000e7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_4_0x8000127c0301143F; - - } - else if ( rank_group == 3 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_0x800003090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_0x800007090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_0x80000B090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_0x80000F090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_0x800013090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_0_0x800003130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_1_0x800007130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_2_0x80000B130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_3_0x80000F130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_4_0x800013130301143F; - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_0_0x8000037c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_1_0x8000077c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_2_0x80000b7c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_3_0x80000f7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_4_0x8000137c0301143F; - - } - } - else if (port == 1 ) - { - - if ( rank_group == 0 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_0_0x800100090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_1_0x800104090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_2_0x800108090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_3_0x80010C090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_4_0x800110090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_0_0x800100130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_1_0x800104130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_2_0x800108130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_3_0x80010C130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_4_0x800110130301143F; - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_0_0x8001007c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_1_0x8001047c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_2_0x8001087c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_3_0x80010c7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_4_0x8001107c0301143F; - - } - else if ( rank_group == 1 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_0_0x800101090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_1_0x800105090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_2_0x800109090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_3_0x80010D090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_4_0x800111090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_0_0x800101130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_1_0x800105130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_2_0x800109130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_3_0x80010D130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_4_0x800111130301143F; - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_0_0x8001017c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_1_0x8001057c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_2_0x8001097c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_3_0x80010d7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_4_0x8001117c0301143F; - - } - else if ( rank_group == 2 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_0_0x800102090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_1_0x800106090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_2_0x80010A090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_3_0x80010E090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_4_0x800112090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_0_0x800102130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_1_0x800106130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_2_0x80010A130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_3_0x80010E130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_4_0x800112130301143F; - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_0_0x8001027c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_1_0x8001067c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_2_0x80010a7c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_3_0x80010e7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_4_0x8001127c0301143F; - - } - else if ( rank_group == 3 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_0_0x800103090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_1_0x800107090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_2_0x80010B090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_3_0x80010F090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_4_0x800113090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_0_0x800103130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_1_0x800107130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_2_0x80010B130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_3_0x80010F130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_4_0x800113130301143F; - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_0_0x8001037c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_1_0x8001077c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_2_0x80010b7c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_3_0x80010f7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_4_0x8001137c0301143F; - - } - } - - //Block 0 - rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_0, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][0][0][0], 48, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][0][0][1], 52, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][0][1][0], 56, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][0][1][1], 60, 2); - - rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][0][0][0], 50, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][0][0][1], 54, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][0][1][0], 58, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][0][1][1], 62, 2); - rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_0, data_buffer_64); - if (rc) return rc; - - rc = fapiGetScom(i_target, GATE_DELAY_ADDR_0, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][0][0][0], 49, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][0][0][1], 53, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][0][1][0], 57, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][0][1][1], 61, 3); - rc = fapiPutScom(i_target, GATE_DELAY_ADDR_0, data_buffer_64); - if (rc) return rc; - - //Block 1 - rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_1, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][1][0][0], 48, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][1][0][1], 52, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][1][1][0], 56, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][1][1][1], 60, 2); - - rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][1][0][0], 50, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][1][0][1], 54, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][1][1][0], 58, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][1][1][1], 62, 2); - rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_1, data_buffer_64); - if (rc) return rc; - - rc = fapiGetScom(i_target, GATE_DELAY_ADDR_1, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][1][0][0], 49, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][1][0][1], 53, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][1][1][0], 57, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][1][1][1], 61, 3); - rc = fapiPutScom(i_target, GATE_DELAY_ADDR_1, data_buffer_64); - if (rc) return rc; - - //Block 2 - rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_2, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][2][0][0], 48, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][2][0][1], 52, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][2][1][0], 56, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][2][1][1], 60, 2); - - rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][2][0][0], 50, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][2][0][1], 54, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][2][1][0], 58, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][2][1][1], 62, 2); - rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_2, data_buffer_64); - if (rc) return rc; - - rc = fapiGetScom(i_target, GATE_DELAY_ADDR_2, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][2][0][0], 49, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][2][0][1], 53, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][2][1][0], 57, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][2][1][1], 61, 3); - rc = fapiPutScom(i_target, GATE_DELAY_ADDR_2, data_buffer_64); - if (rc) return rc; - - //Block 3 - rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_3, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][3][0][0], 48, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][3][0][1], 52, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][3][1][0], 56, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][3][1][1], 60, 2); - - rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][3][0][0], 50, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][3][0][1], 54, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][3][1][0], 58, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][3][1][1], 62, 2); - rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_3, data_buffer_64); - if (rc) return rc; - - rc = fapiGetScom(i_target, GATE_DELAY_ADDR_3, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][3][0][0], 49, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][3][0][1], 53, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][3][1][0], 57, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][3][1][1], 61, 3); - rc = fapiPutScom(i_target, GATE_DELAY_ADDR_3, data_buffer_64); - if (rc) return rc; - - - //Block 4 - rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_4, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][4][0][0], 48, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][4][0][1], 52, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][4][1][0], 56, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][4][1][1], 60, 2); - - rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][4][0][0], 50, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][4][0][1], 54, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][4][1][0], 58, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][4][1][1], 62, 2); - rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_4, data_buffer_64); - if (rc) return rc; - - rc = fapiGetScom(i_target, GATE_DELAY_ADDR_4, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][4][0][0], 49, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][4][0][1], 53, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][4][1][0], 57, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][4][1][1], 61, 3); - rc = fapiPutScom(i_target, GATE_DELAY_ADDR_4, data_buffer_64); - if (rc) return rc; - - if(rc_num) - { - rc.setEcmdError(rc_num); - return rc; - } - - - } - } - } - - return rc; -} - - - - -ReturnCode mss_reset_delay_values( - Target& i_target - ) -{ - //MBA target level - //Reset Wr_level delays and Gate Delays - //Across all configed rank pairs, in order - - uint8_t primary_ranks_array[4][2]; //primary_ranks_array[group][port] - ecmdDataBufferBase data_buffer_64(64); - uint64_t GATE_DELAY_ADDR_0 = 0; - uint64_t GATE_DELAY_ADDR_1 = 0; - uint64_t GATE_DELAY_ADDR_2 = 0; - uint64_t GATE_DELAY_ADDR_3 = 0; - uint64_t GATE_DELAY_ADDR_4 = 0; - uint8_t port = 0; - uint8_t rank_group = 0; - ReturnCode rc; - uint32_t rc_num = 0; - - - //populate primary_ranks_arrays_array - rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP0, &i_target, primary_ranks_array[0]); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP1, &i_target, primary_ranks_array[1]); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP2, &i_target, primary_ranks_array[2]); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP3, &i_target, primary_ranks_array[3]); - if(rc) return rc; - - //Hit the reset button for wr_lvl values - //These won't reset until the next run of wr_lvl - rc = fapiGetScom(i_target, DPHY01_DDRPHY_WC_CONFIG2_P0_0x8000CC020301143F, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.insertFromRight((uint8_t) 0xFF, 63, 1); - rc = fapiPutScom(i_target, DPHY01_DDRPHY_WC_CONFIG2_P0_0x8000CC020301143F, data_buffer_64); - if (rc) return rc; - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_WC_CONFIG2_P1_0x8001CC020301143F, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.insertFromRight((uint8_t) 0xFF, 63, 1); - rc = fapiPutScom(i_target, DPHY01_DDRPHY_WC_CONFIG2_P1_0x8001CC020301143F, data_buffer_64); - if (rc) return rc; - - if(rc_num) - { - rc.setEcmdError(rc_num); - return rc; - } - - //Scoming in zeros into the Gate delay registers. - for(port = 0; port < MAX_PORTS; port++) - { - - for(rank_group = 0; rank_group < MAX_PRI_RANKS; rank_group++) - { - - //Check if rank group exists - if(primary_ranks_array[rank_group][port] != 255) - { - - if ( port == 0 ) - { - - if ( rank_group == 0 ) - { - - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_0_0x800000130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_1_0x800004130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_2_0x800008130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_3_0x80000C130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_4_0x800010130301143F; - - } - else if ( rank_group == 1 ) - { - - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_0_0x800001130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_1_0x800005130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_2_0x800009130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_3_0x80000D130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_4_0x800011130301143F; - - } - else if ( rank_group == 2 ) - { - - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_0_0x800002130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_1_0x800006130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_2_0x80000A130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_3_0x80000E130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_4_0x800012130301143F; - - } - else if ( rank_group == 3 ) - { - - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_0_0x800003130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_1_0x800007130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_2_0x80000B130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_3_0x80000F130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_4_0x800013130301143F; - - } - } - else if (port == 1 ) - { - - if ( rank_group == 0 ) - { - - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_0_0x800100130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_1_0x800104130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_2_0x800108130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_3_0x80010C130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_4_0x800110130301143F; - - } - else if ( rank_group == 1 ) - { - - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_0_0x800101130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_1_0x800105130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_2_0x800109130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_3_0x80010D130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_4_0x800111130301143F; - - } - else if ( rank_group == 2 ) - { - - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_0_0x800102130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_1_0x800106130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_2_0x80010A130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_3_0x80010E130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_4_0x800112130301143F; - - } - else if ( rank_group == 3 ) - { - - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_0_0x800103130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_1_0x800107130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_2_0x80010B130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_3_0x80010F130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_4_0x800113130301143F; - - } - } - - rc_num = rc_num | data_buffer_64.flushTo0(); - if(rc_num) - { - rc.setEcmdError(rc_num); - return rc; - } - - //BLOCK 0 - rc = fapiPutScom(i_target, GATE_DELAY_ADDR_0, data_buffer_64); - if (rc) return rc; - //BLOCK 1 - rc = fapiPutScom(i_target, GATE_DELAY_ADDR_1, data_buffer_64); - if (rc) return rc; - //BLOCK 2 - rc = fapiPutScom(i_target, GATE_DELAY_ADDR_2, data_buffer_64); - if (rc) return rc; - //BLOCK 3 - rc = fapiPutScom(i_target, GATE_DELAY_ADDR_3, data_buffer_64); - if (rc) return rc; - //BLOCK 4 - rc = fapiPutScom(i_target, GATE_DELAY_ADDR_4, data_buffer_64); - if (rc) return rc; - - - } - } - - } - - - return rc; -} - -ReturnCode mss_rtt_nom_rtt_wr_swap( - Target& i_target, - uint8_t i_mbaPosition, - uint32_t i_port_number, - uint8_t i_rank, - uint32_t i_rank_pair_group, - uint32_t& io_ccs_inst_cnt, - uint8_t& io_dram_rtt_nom_original - ) -{ - // Target MBA level - // This is a function written specifically for mss_draminit_training - // Meant for placing RTT_WR into RTT_NOM within MR1 before wr_lvl - // If the function argument dram_rtt_nom_original has a value of 0xFF it will put the original rtt_nom there - // and write rtt_wr to the rtt_nom value - // If the function argument dram_rtt_nom_original has any value besides 0xFF it will try to write that value to rtt_nom. - - - ReturnCode rc; - ReturnCode rc_buff; - uint32_t rc_num = 0; - - ecmdDataBufferBase address_16(16); - ecmdDataBufferBase bank_3(3); - ecmdDataBufferBase activate_1(1); - ecmdDataBufferBase rasn_1(1); - rc_num = rc_num | rasn_1.clearBit(0); - ecmdDataBufferBase casn_1(1); - rc_num = rc_num | casn_1.clearBit(0); - ecmdDataBufferBase wen_1(1); - rc_num = rc_num | wen_1.clearBit(0); - ecmdDataBufferBase cke_4(4); - rc_num = rc_num | cke_4.setBit(0,4); - ecmdDataBufferBase csn_8(8); - rc_num = rc_num | csn_8.setBit(0,8); - ecmdDataBufferBase odt_4(4); - rc_num = rc_num | odt_4.setBit(0,4); - ecmdDataBufferBase ddr_cal_type_4(4); - - ecmdDataBufferBase num_idles_16(16); - ecmdDataBufferBase num_repeat_16(16); - ecmdDataBufferBase data_20(20); - ecmdDataBufferBase read_compare_1(1); - ecmdDataBufferBase rank_cal_4(4); - ecmdDataBufferBase ddr_cal_enable_1(1); - ecmdDataBufferBase ccs_end_1(1); - - ecmdDataBufferBase mrs1_16(16); - ecmdDataBufferBase mrs2_16(16); - - ecmdDataBufferBase data_buffer_64(64); - - uint16_t MRS1 = 0; - uint16_t MRS2 = 0; - uint8_t dimm = 0; - uint8_t dimm_rank = 0; - - // dimm 0, dimm_rank 0-3 = ranks 0-3; dimm 1, dimm_rank 0-3 = ranks 4-7 - dimm = (i_rank) / 4; - dimm_rank = i_rank - 4*dimm; - - - uint8_t dimm_type; - rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target, dimm_type); - if(rc) return rc; - - uint8_t is_sim = 0; - rc = FAPI_ATTR_GET(ATTR_IS_SIMULATION, NULL, is_sim); - if(rc) return rc; - - uint8_t address_mirror_map[2][2]; //address_mirror_map[port][dimm] - rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_ADDRESS_MIRRORING, &i_target, address_mirror_map); - if(rc) return rc; - - - // Raise CKE high with NOPS, waiting min Reset CKE exit time (tXPR) - 400 cycles - rc_num = rc_num | csn_8.setBit(0,8); - rc_num = rc_num | address_16.clearBit(0, 16); - rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 400, 0, 16); - if(rc_num) - { - rc.setEcmdError(rc_num); - return rc; - } - rc = mss_ccs_inst_arry_0( i_target, - io_ccs_inst_cnt, - address_16, - bank_3, - activate_1, - rasn_1, - casn_1, - wen_1, - cke_4, - csn_8, - odt_4, - ddr_cal_type_4, - i_port_number); - if(rc) return rc; - rc = mss_ccs_inst_arry_1( i_target, - io_ccs_inst_cnt, - num_idles_16, - num_repeat_16, - data_20, - read_compare_1, - rank_cal_4, - ddr_cal_enable_1, - ccs_end_1); - if(rc) return rc; - io_ccs_inst_cnt ++; - - rc_num = rc_num | csn_8.setBit(0,8); - if (i_rank == 0) - { - rc_num = rc_num | csn_8.clearBit(0); - } - else if (i_rank == 1) - { - rc_num = rc_num | csn_8.clearBit(1); - } - else if (i_rank == 2) - { - rc_num = rc_num | csn_8.clearBit(2); - } - else if (i_rank == 3) - { - rc_num = rc_num | csn_8.clearBit(3); - } - else if (i_rank == 4) - { - rc_num = rc_num | csn_8.clearBit(4); - } - else if (i_rank == 5) - { - rc_num = rc_num | csn_8.clearBit(5); - } - else if (i_rank == 6) - { - rc_num = rc_num | csn_8.clearBit(6); - } - else if (i_rank == 7) - { - rc_num = rc_num | csn_8.clearBit(7); - } - - // MRS CMD to CMD spacing = 12 cycles - rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 12, 0, 16); - if(rc_num) - { - rc.setEcmdError(rc_num); - return rc; - } - - FAPI_INF( "Editing RTT_NOM during wr_lvl for %s PORT: %d RP: %d", i_target.toEcmdString(), i_port_number, i_rank_pair_group); - - //MRS1 - // Get contents of MRS 1 Shadow Reg - - if (i_port_number == 0){ - if (i_rank_pair_group == 0) - { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP0_P0_0x8000C01D0301143F, data_buffer_64); - if(rc) return rc; - } - else if (i_rank_pair_group == 1) - { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP1_P0_0x8000C11D0301143F, data_buffer_64); - if(rc) return rc; - } - else if (i_rank_pair_group == 2) - { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP2_P0_0x8000C21D0301143F, data_buffer_64); - if(rc) return rc; - } - else if (i_rank_pair_group == 3) - { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP3_P0_0x8000C31D0301143F, data_buffer_64); - if(rc) return rc; - } - } - else if (i_port_number == 1){ - if (i_rank_pair_group == 0) - { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP0_P1_0x8001C01D0301143F, data_buffer_64); - if(rc) return rc; - } - else if (i_rank_pair_group == 1) - { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP1_P1_0x8001C11D0301143F, data_buffer_64); - if(rc) return rc; - } - else if (i_rank_pair_group == 2) - { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP2_P1_0x8001C21D0301143F, data_buffer_64); - if(rc) return rc; - } - else if (i_rank_pair_group == 3) - { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP3_P1_0x8001C31D0301143F, data_buffer_64); - if(rc) return rc; - } - } - - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs1_16.insert(data_buffer_64, 0, 16, 0); - rc_num = rc_num | mrs1_16.extractPreserve(&MRS1, 0, 16, 0); - if(rc_num) - { - rc.setEcmdError(rc_num); - return rc; - } - FAPI_INF( "CURRENT MRS 1: 0x%04X", MRS1); - - uint8_t dll_enable = 0x00; //DLL Enable - if (mrs1_16.isBitSet(0)) - { - // DLL disabled - dll_enable = 0xFF; - } - else if (mrs1_16.isBitClear(0)) - { - // DLL enabled - dll_enable = 0x00; - } - - uint8_t out_drv_imp_cntl = 0x00; - if ( (mrs1_16.isBitClear(1)) && (mrs1_16.isBitClear(5)) ) - { - // out_drv_imp_ctrl set to 40 (Rzq/6) - out_drv_imp_cntl = 0x00; - } - else if ( (mrs1_16.isBitSet(1)) && (mrs1_16.isBitClear(5)) ) - { - // out_drv_imp_ctrl set to 34 (Rzq/7) - out_drv_imp_cntl = 0x80; - } - - uint8_t dram_rtt_nom = 0x00; - if ( (mrs1_16.isBitClear(2)) && (mrs1_16.isBitClear(6)) && (mrs1_16.isBitClear(9)) ) - { - // RTT_NOM set to disabled - FAPI_INF( "DRAM_RTT_NOM orignally set to Disabled."); - dram_rtt_nom = 0x00; - - } - else if ( (mrs1_16.isBitClear(2)) && (mrs1_16.isBitClear(6)) && (mrs1_16.isBitSet(9)) ) - { - // RTT_NOM set to 20 - FAPI_INF( "DRAM_RTT_NOM orignally set to 20 Ohm."); - dram_rtt_nom = 0x20; - } - else if ( (mrs1_16.isBitSet(2)) && (mrs1_16.isBitClear(6)) && (mrs1_16.isBitSet(9)) ) - { - // RTT_NOM set to 30 - FAPI_INF( "DRAM_RTT_NOM orignally set to 30 Ohm."); - dram_rtt_nom = 0xA0; - } - else if ( (mrs1_16.isBitSet(2)) && (mrs1_16.isBitSet(6)) && (mrs1_16.isBitClear(9)) ) - { - // RTT_NOM set to 40 - FAPI_INF( "DRAM_RTT_NOM orignally set to 40 Ohm."); - dram_rtt_nom = 0xC0; - } - else if ( (mrs1_16.isBitSet(2)) && (mrs1_16.isBitSet(6)) && (mrs1_16.isBitClear(9)) ) - { - // RTT_NOM set to 60 - FAPI_INF( "DRAM_RTT_NOM orignally set to 60 Ohm."); - dram_rtt_nom = 0x80; - } - else if ( (mrs1_16.isBitClear(2)) && (mrs1_16.isBitSet(6)) && (mrs1_16.isBitClear(9)) ) - { - // RTT_NOM set to 120 - FAPI_INF( "DRAM_RTT_NOM orignally set to 120 Ohm."); - dram_rtt_nom = 0x40; - } - - uint8_t dram_al = 0x00; - if ( (mrs1_16.isBitClear(3)) && (mrs1_16.isBitClear(4)) ) - { - //AL DISABLED - dram_al = 0x00; - } - else if ( (mrs1_16.isBitSet(3)) && (mrs1_16.isBitClear(4)) ) - { - // AL = CL -1 - dram_al = 0x80; - } - else if ( (mrs1_16.isBitClear(3)) && (mrs1_16.isBitSet(4)) ) - { - // AL = CL -2 - dram_al = 0x40; - } - - uint8_t wr_lvl = 0x00; //write leveling enable - if (mrs1_16.isBitClear(7)) - { - // WR_LVL DISABLED - wr_lvl = 0x00; - } - else if (mrs1_16.isBitSet(7)) - { - // WR_LVL ENABLED - wr_lvl = 0xFF; - } - - uint8_t tdqs_enable = 0x00; //TDQS Enable - if (mrs1_16.isBitClear(11)) - { - //TDQS DISABLED - tdqs_enable = 0x00; - } - else if (mrs1_16.isBitSet(11)) - { - //TDQS ENABLED - tdqs_enable = 0xFF; - } - - uint8_t q_off = 0x00; //Qoff - Output buffer Enable - if (mrs1_16.isBitSet(12)) - { - //Output Buffer Disabled - q_off = 0xFF; - } - else if (mrs1_16.isBitClear(12)) - { - //Output Buffer Enabled - q_off = 0x00; - } - - - // Get contents of MRS 2 Shadow Reg - if (i_port_number == 0){ - if (i_rank_pair_group == 0) - { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP0_P0_0x8000C01E0301143F, data_buffer_64); - if(rc) return rc; - } - else if (i_rank_pair_group == 1) - { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP1_P0_0x8000C11E0301143F, data_buffer_64); - if(rc) return rc; - } - else if (i_rank_pair_group == 2) - { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP2_P0_0x8000C21E0301143F, data_buffer_64); - if(rc) return rc; - } - else if (i_rank_pair_group == 3) - { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP3_P0_0x8000C31E0301143F, data_buffer_64); - if(rc) return rc; - } - } - else if (i_port_number == 1){ - if (i_rank_pair_group == 0) - { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP0_P1_0x8001C01E0301143F, data_buffer_64); - if(rc) return rc; - } - else if (i_rank_pair_group == 1) - { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP1_P1_0x8001C11E0301143F, data_buffer_64); - if(rc) return rc; - } - else if (i_rank_pair_group == 2) - { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP2_P1_0x8001C21E0301143F, data_buffer_64); - if(rc) return rc; - } - else if (i_rank_pair_group == 3) - { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP3_P1_0x8001C31E0301143F, data_buffer_64); - if(rc) return rc; - } - } - - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs2_16.insert(data_buffer_64, 0, 16, 0); - rc_num = rc_num | mrs2_16.extractPreserve(&MRS2, 0, 16, 0); - if(rc_num) - { - rc.setEcmdError(rc_num); - return rc; - } - FAPI_INF( "MRS 2: 0x%04X", MRS2); - - uint8_t dram_rtt_wr = 0x00; - if ( (mrs2_16.isBitClear(9)) && (mrs2_16.isBitClear(10)) ) - { - //RTT WR DISABLE - FAPI_INF( "DRAM_RTT_WR currently set to Disable."); - dram_rtt_wr = 0x00; - - //RTT NOM CODE FOR THIS VALUE IS - // dram_rtt_nom = 0x00 - - } - else if ( (mrs2_16.isBitSet(9)) && (mrs2_16.isBitClear(10)) ) - { - //RTT WR 60 OHM - FAPI_INF( "DRAM_RTT_WR currently set to 60 Ohm."); - dram_rtt_wr = 0x80; - - //RTT NOM CODE FOR THIS VALUE IS - // dram_rtt_nom = 0x80 - - } - else if ( (mrs2_16.isBitClear(9)) && (mrs2_16.isBitSet(10)) ) - { - //RTT WR 120 OHM - FAPI_INF( "DRAM_RTT_WR currently set to 120 Ohm."); - dram_rtt_wr = 0x40; - - //RTT NOM CODE FOR THIS VALUE IS - // dram_rtt_nom = 0x40 - - } - - - // If you have a 0 value in dram_rtt_nom_orignal - // you will use dram_rtt_nom_original to save the original value - if (io_dram_rtt_nom_original == 0xFF) - { - io_dram_rtt_nom_original = dram_rtt_nom; - dram_rtt_nom = dram_rtt_wr; - - if (dram_rtt_wr == 0x00) - { - FAPI_INF( "DRAM_RTT_NOM to be set to DRAM_RTT_WR which is Disable."); - } - else if (dram_rtt_wr == 0x80) - { - FAPI_INF( "DRAM_RTT_NOM to be set to DRAM_RTT_WR which is 60 Ohm."); - } - else if (dram_rtt_wr == 0x40) - { - FAPI_INF( "DRAM_RTT_NOM to be set to DRAM_RTT_WR which is 120 Ohm."); - } - } - else if (io_dram_rtt_nom_original != 0xFF) - { - dram_rtt_nom = io_dram_rtt_nom_original; - - if ( dram_rtt_nom == 0x00 ) - { - // RTT_NOM set to disabled - FAPI_INF( "DRAM_RTT_NOM being set back to Disabled."); - - } - else if ( dram_rtt_nom == 0x20 ) - { - // RTT_NOM set to 20 - FAPI_INF( "DRAM_RTT_NOM being set back to 20 Ohm."); - } - else if ( dram_rtt_nom == 0xA0 ) - { - // RTT_NOM set to 30 - FAPI_INF( "DRAM_RTT_NOM being set back to 30 Ohm."); - } - else if ( dram_rtt_nom == 0xC0 ) - { - // RTT_NOM set to 40 - FAPI_INF( "DRAM_RTT_NOM being set back to 40 Ohm."); - } - else if ( dram_rtt_nom == 0x80 ) - { - // RTT_NOM set to 60 - FAPI_INF( "DRAM_RTT_NOM being set back to 60 Ohm."); - } - else if ( dram_rtt_nom == 0x40 ) - { - // RTT_NOM set to 120 - FAPI_INF( "DRAM_RTT_NOM being set back to 120 Ohm."); - } - else - { - FAPI_INF( "Proposed DRAM_RTT_NOM value is a non-supported. Using Disabled."); - dram_rtt_nom = 0x00; - } - } - - - rc_num = rc_num | mrs1_16.insert((uint8_t) dll_enable, 0, 1, 0); - rc_num = rc_num | mrs1_16.insert((uint8_t) out_drv_imp_cntl, 1, 1, 0); - rc_num = rc_num | mrs1_16.insert((uint8_t) dram_rtt_nom, 2, 1, 0); - rc_num = rc_num | mrs1_16.insert((uint8_t) dram_al, 3, 2, 0); - rc_num = rc_num | mrs1_16.insert((uint8_t) out_drv_imp_cntl, 5, 1, 1); - rc_num = rc_num | mrs1_16.insert((uint8_t) dram_rtt_nom, 6, 1, 1); - rc_num = rc_num | mrs1_16.insert((uint8_t) wr_lvl, 7, 1, 0); - rc_num = rc_num | mrs1_16.insert((uint8_t) 0x00, 8, 1); - rc_num = rc_num | mrs1_16.insert((uint8_t) dram_rtt_nom, 9, 1, 2); - rc_num = rc_num | mrs1_16.insert((uint8_t) 0x00, 10, 1); - rc_num = rc_num | mrs1_16.insert((uint8_t) tdqs_enable, 11, 1, 0); - rc_num = rc_num | mrs1_16.insert((uint8_t) q_off, 12, 1, 0); - rc_num = rc_num | mrs1_16.insert((uint8_t) 0x00, 13, 3); - - rc_num = rc_num | mrs1_16.extractPreserve(&MRS1, 0, 16, 0); - FAPI_INF( "NEW MRS 1: 0x%04X", MRS1); - - // Copying the current MRS into address buffer matching the MRS_array order - // Setting the bank address - - rc_num = rc_num | address_16.insert(mrs1_16, 0, 16, 0); - rc_num = rc_num | bank_3.insert((uint8_t) MRS1_BA, 0, 1, 7); - rc_num = rc_num | bank_3.insert((uint8_t) MRS1_BA, 1, 1, 6); - rc_num = rc_num | bank_3.insert((uint8_t) MRS1_BA, 2, 1, 5); - - - - if ( ( address_mirror_map[i_port_number][dimm] & (0x08 >> dimm_rank) ) && (is_sim == 0)) - { - //dimm and rank are only for print trace only, functionally not needed - rc = mss_address_mirror_swizzle(i_target, i_port_number, dimm, dimm_rank, address_16, bank_3); - if(rc) return rc; - - } - - if (rc_num) - { - FAPI_ERR( "mss_mrs_load: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - - ccs_end_1.setBit(0); - - // Send out to the CCS array - rc = mss_ccs_inst_arry_0( i_target, - io_ccs_inst_cnt, - address_16, - bank_3, - activate_1, - rasn_1, - casn_1, - wen_1, - cke_4, - csn_8, - odt_4, - ddr_cal_type_4, - i_port_number); - if(rc) return rc; - rc = mss_ccs_inst_arry_1( i_target, - io_ccs_inst_cnt, - num_idles_16, - num_repeat_16, - data_20, - read_compare_1, - rank_cal_4, - ddr_cal_enable_1, - ccs_end_1); - if(rc) return rc; - - uint32_t NUM_POLL = 100; - rc = mss_execute_ccs_inst_array( i_target, NUM_POLL, 60); - if(rc) return rc; //Error handling for mss_ccs_inst built into mss_funcs - - io_ccs_inst_cnt = 0; - - return rc; - -} - - - -fapi::ReturnCode mss_set_bbm_regs (const fapi::Target & mba_target) -{ - // Flash to registers. - // disable0=dq bits, disable1=dqs(+,-) - // wrclk_en=dqs follows quad, same as disable0 - - const uint64_t disable_reg[MAX_PORTS][MAX_PRI_RANKS][DP18_INSTANCES] = { - /* port 0 */ - { // primary rank pair 0 - {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_0_0x8000007c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_1_0x8000047c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_2_0x8000087c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_3_0x80000c7c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_4_0x8000107c0301143F}, - // primary rank pair 1 - {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_0_0x8000017c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_1_0x8000057c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_2_0x8000097c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_3_0x80000d7c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_4_0x8000117c0301143F}, - // primary rank pair 2 - {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_0_0x8000027c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_1_0x8000067c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_2_0x80000a7c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_3_0x80000e7c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_4_0x8000127c0301143F}, - // primary rank pair 3 - {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_0_0x8000037c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_1_0x8000077c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_2_0x80000b7c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_3_0x80000f7c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_4_0x8000137c0301143F} - }, - /* port 1 */ - { - // primary rank pair 0 - {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_0_0x8001007c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_1_0x8001047c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_2_0x8001087c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_3_0x80010c7c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_4_0x8001107c0301143F}, - // primary rank p1 - {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_0_0x8001017c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_1_0x8001057c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_2_0x8001097c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_3_0x80010d7c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_4_0x8001117c0301143F}, - // primary rank pair 2 - {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_0_0x8001027c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_1_0x8001067c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_2_0x80010a7c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_3_0x80010e7c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_4_0x8001127c0301143F}, - // primary rank pair 3 - {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_0_0x8001037c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_1_0x8001077c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_2_0x80010b7c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_3_0x80010f7c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_4_0x8001137c0301143F} - }}; - const uint8_t rg_invalid[] = { - ENUM_ATTR_EFF_PRIMARY_RANK_GROUP0_INVALID, - ENUM_ATTR_EFF_PRIMARY_RANK_GROUP1_INVALID, - ENUM_ATTR_EFF_PRIMARY_RANK_GROUP2_INVALID, - ENUM_ATTR_EFF_PRIMARY_RANK_GROUP3_INVALID, - }; - - const uint16_t wrclk_disable_mask[] = { // by quads - 0x8800, 0x4400, 0x2280, 0x1140 - }; - - uint8_t l_dram_width, l_disable1_fixed, l_disable1_rdclk_fixed; - uint64_t l_addr; - // 0x8000007d0301143f from disable0 register - const uint64_t l_disable1_addr_offset = 0x0000000100000000ull; - // 0x800000050301143f from disable1 register - const uint64_t l_wrclk_en_addr_mask = 0xFFFFFF07FFFFFFFFull; - - ReturnCode rc; - ecmdDataBufferBase data_buffer(64); - ecmdDataBufferBase db_reg(BITS_PER_PORT); - ecmdDataBufferBase db_reg_rank0(BITS_PER_PORT); - ecmdDataBufferBase db_reg_rank1(BITS_PER_PORT); - ecmdDataBufferBase db_reg_rank2(BITS_PER_PORT); - ecmdDataBufferBase db_reg_rank3(BITS_PER_PORT); - ecmdDataBufferBase db_reg_rank4(BITS_PER_PORT); - ecmdDataBufferBase db_reg_rank5(BITS_PER_PORT); - ecmdDataBufferBase db_reg_rank6(BITS_PER_PORT); - ecmdDataBufferBase db_reg_rank7(BITS_PER_PORT); - uint32_t l_ecmdRc = ECMD_DBUF_SUCCESS; - uint8_t prg[MAX_PRI_RANKS][MAX_PORTS]; // primary rank group values - - FAPI_INF("Running flash->registers(set)"); - - std::vector<Target> mba_dimms; - rc = fapiGetAssociatedDimms(mba_target, mba_dimms); // functional dimms - if(rc) return rc; - - // ATTR_EFF_PRIMARY_RANK_GROUP0[port], GROUP1[port], - // GROUP2[port], GROUP3[port] - rc=FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP0, &mba_target, prg[0]); - if(rc) return rc; - rc=FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP1, &mba_target, prg[1]); - if(rc) return rc; - rc=FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP2, &mba_target, prg[2]); - if(rc) return rc; - rc=FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP3, &mba_target, prg[3]); - if(rc) return rc; - - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &mba_target, l_dram_width); - if(rc) return rc; - - - - fapi::Target l_target_centaur; - rc = fapiGetParentChip(mba_target, l_target_centaur); - if(rc) return rc; - - rc = FAPI_ATTR_GET(ATTR_MSS_DISABLE1_REG_FIXED, &l_target_centaur, l_disable1_fixed); - if(rc) return rc; - - rc = FAPI_ATTR_GET(ATTR_MSS_DISABLE1_RDCLK_REG_FIXED, &l_target_centaur, l_disable1_rdclk_fixed); - if(rc) return rc; - - switch (l_dram_width) - { - case ENUM_ATTR_EFF_DRAM_WIDTH_X4: - l_dram_width = 4; - break; - case ENUM_ATTR_EFF_DRAM_WIDTH_X8: - l_dram_width = 8; - break; - case ENUM_ATTR_EFF_DRAM_WIDTH_X16: - l_dram_width = 16; - break; - case ENUM_ATTR_EFF_DRAM_WIDTH_X32: - l_dram_width = 32; - break; - default: - //DECONFIG and FFDC INFO - const fapi::Target & TARGET_MBA_ERROR = mba_target; - const uint8_t & WIDTH = l_dram_width; - - FAPI_ERR("ATTR_EFF_DRAM_WIDTH is invalid %u", l_dram_width); - FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_DRAM_WIDTH_INPUT_ERROR_SETBBM); - return rc; - } - - l_ecmdRc = data_buffer.flushTo0(); - if (l_ecmdRc != ECMD_DBUF_SUCCESS) - { - FAPI_ERR("Error from ecmdDataBuffer flushTo0() " - "- rc 0x%.8X", l_ecmdRc); - rc.setEcmdError(l_ecmdRc); - return rc; - } - for (uint8_t port = 0; port < MAX_PORTS; port++ ) // [0:1] - { - db_reg_rank0.flushTo0(); - db_reg_rank1.flushTo0(); - db_reg_rank2.flushTo0(); - db_reg_rank3.flushTo0(); - db_reg_rank4.flushTo0(); - db_reg_rank5.flushTo0(); - db_reg_rank6.flushTo0(); - db_reg_rank7.flushTo0(); - uint8_t is_clean = 1; - - uint8_t l_rank0_invalid = 1; //0 = valid, 1 = invalid - uint8_t l_rank1_invalid = 1; - uint8_t l_rank2_invalid = 1; - uint8_t l_rank3_invalid = 1; - uint8_t l_rank4_invalid = 1; - uint8_t l_rank5_invalid = 1; - uint8_t l_rank6_invalid = 1; - uint8_t l_rank7_invalid = 1; - - // Gather all ranks first - // loop through primary ranks [0:3] - for (uint8_t prank = 0; prank < MAX_PRI_RANKS; prank++ ) - { - - is_clean = 1; - if (prg[prank][port] == rg_invalid[prank]) // invalid rank - { - FAPI_DBG("BYTE DISABLE WORKAROUND Primary rank group (prank) %i port %d rank value: %d INVALID, Marking and continuing...", - prank, port, prg[prank][port]); - - continue; - } - - if ( prg[prank][port] == 0) - { - FAPI_DBG("BYTE DISABLE WORKAROUND Primary rank group (prank) %i port %d rank value: %d Not INVALID, Marking and continuing...", - prank, port, prg[prank][port]); - rc = getC4dq2reg(mba_target, port, 0, 0, db_reg_rank0, is_clean); - if (rc) - { - FAPI_ERR("Error from getting register bitmap port=%i: " - "dimm=%i, rank=%i rc=%i", port, 0, 0, - static_cast<uint32_t>(rc)); - return rc; - } - l_rank0_invalid = 0; - } - - if ( prg[prank][port] == 1) - { - FAPI_DBG("BYTE DISABLE WORKAROUND Primary rank group (prank) %i port %d rank value: %d Not INVALID, Marking and continuing...", - prank, port, prg[prank][port]); - rc = getC4dq2reg(mba_target, port, 0, 1, db_reg_rank1, is_clean); - if (rc) - { - FAPI_ERR("Error from getting register bitmap port=%i: " - "dimm=%i, rank=%i rc=%i", port, 0, 1, - static_cast<uint32_t>(rc)); - return rc; - } - l_rank1_invalid = 0; - } - - if ( prg[prank][port] == 2) - { - FAPI_DBG("BYTE DISABLE WORKAROUND Primary rank group (prank) %i port %d rank value: %d Not INVALID, Marking and continuing...", - prank, port, prg[prank][port]); - rc = getC4dq2reg(mba_target, port, 0, 2, db_reg_rank2, is_clean); - if (rc) - { - FAPI_ERR("Error from getting register bitmap port=%i: " - "dimm=%i, rank=%i rc=%i", port, 0, 2, - static_cast<uint32_t>(rc)); - return rc; - } - l_rank2_invalid = 0; - } - - - if ( prg[prank][port] == 3) - { - FAPI_DBG("BYTE DISABLE WORKAROUND Primary rank group (prank) %i port %d rank value: %d Not INVALID, Marking and continuing...", - prank, port, prg[prank][port]); - rc = getC4dq2reg(mba_target, port, 0, 3, db_reg_rank3, is_clean); - if (rc) - { - FAPI_ERR("Error from getting register bitmap port=%i: " - "dimm=%i, rank=%i rc=%i", port, 0, 3, - static_cast<uint32_t>(rc)); - return rc; - } - l_rank3_invalid = 0; - } - - - - if ( prg[prank][port] == 4) - { - FAPI_DBG("BYTE DISABLE WORKAROUND Primary rank group (prank) %i port %d rank value: %d Not INVALID, Marking and continuing...", - prank, port, prg[prank][port]); - rc = getC4dq2reg(mba_target, port, 1, 0, db_reg_rank4, is_clean); - if (rc) - { - FAPI_ERR("Error from getting register bitmap port=%i: " - "dimm=%i, rank=%i rc=%i", port, 1, 0, - static_cast<uint32_t>(rc)); - return rc; - } - l_rank4_invalid = 0; - } - - - if ( prg[prank][port] == 5) - { - FAPI_DBG("BYTE DISABLE WORKAROUND Primary rank group (prank) %i port %d rank value: %d Not INVALID, Marking and continuing...", - prank, port, prg[prank][port]); - rc = getC4dq2reg(mba_target, port, 1, 1, db_reg_rank5, is_clean); - if (rc) - { - FAPI_ERR("Error from getting register bitmap port=%i: " - "dimm=%i, rank=%i rc=%i", port, 1, 1, - static_cast<uint32_t>(rc)); - return rc; - } - l_rank5_invalid = 0; - } - - - if ( prg[prank][port] == 6) - { - FAPI_DBG("BYTE DISABLE WORKAROUND Primary rank group (prank) %i port %d rank value: %d Not INVALID, Marking and continuing...", - prank, port, prg[prank][port]); - rc = getC4dq2reg(mba_target, port, 1, 2, db_reg_rank6, is_clean); - if (rc) - { - FAPI_ERR("Error from getting register bitmap port=%i: " - "dimm=%i, rank=%i rc=%i", port, 1, 2, - static_cast<uint32_t>(rc)); - return rc; - } - l_rank6_invalid = 0; - } - - - if ( prg[prank][port] == 7) - { - FAPI_DBG("BYTE DISABLE WORKAROUND Primary rank group (prank) %i port %d rank value: %d Not INVALID, Marking and continuing...", - prank, port, prg[prank][port]); - rc = getC4dq2reg(mba_target, port, 1, 3, db_reg_rank7, is_clean); - if (rc) - { - FAPI_ERR("Error from getting register bitmap port=%i: " - "dimm=%i, rank=%i rc=%i", port, 1, 3, - static_cast<uint32_t>(rc)); - return rc; - } - l_rank7_invalid = 0; - } - - } - - // loop through primary ranks [0:3] - for (uint8_t prank = 0; prank < MAX_PRI_RANKS; prank++ ) - { - uint8_t dimm = prg[prank][port] >> 2; - uint8_t rank = prg[prank][port] & 0x03; - uint16_t l_data = 0; - uint16_t l_data_rank0 = 0; - uint16_t l_data_rank1 = 0; - uint16_t l_data_rank2 = 0; - uint16_t l_data_rank3 = 0; - uint16_t l_data_rank4 = 0; - uint16_t l_data_rank5 = 0; - uint16_t l_data_rank6 = 0; - uint16_t l_data_rank7 = 0; - is_clean = 1; - - if (prg[prank][port] == rg_invalid[prank]) // invalid rank - { - FAPI_DBG("Primary rank group %i: INVALID, continuing...", - prank); - continue; - } - - rc = getC4dq2reg(mba_target, port, dimm, rank, db_reg, is_clean); - if (rc) - { - FAPI_ERR("Error from getting register bitmap port=%i: " - "dimm=%i, rank=%i rc=%i", port, dimm, rank, - static_cast<uint32_t>(rc)); - return rc; - } - - - - // quick test to move on to next rank if no bits need to be set - if (is_clean == 1) // Note ignores spares that match attribute - { - FAPI_INF("Primary rank group %i: No bad bits found for " - "p%i:d%i:r%i:cs%i", prank, port, dimm, rank, - prg[prank][port]); - continue; - } - for ( uint8_t i=0; i < DP18_INSTANCES; i++ ) // dp18 [0:4] - { - uint8_t disable1_data = 0; - uint16_t wrclk_mask = 0; - - // check or not to check(always set register)? - l_data = db_reg.getHalfWord(i); - l_data_rank0 = db_reg_rank0.getHalfWord(i); - l_data_rank1 = db_reg_rank1.getHalfWord(i); - l_data_rank2 = db_reg_rank2.getHalfWord(i); - l_data_rank3 = db_reg_rank3.getHalfWord(i); - l_data_rank4 = db_reg_rank4.getHalfWord(i); - l_data_rank5 = db_reg_rank5.getHalfWord(i); - l_data_rank6 = db_reg_rank6.getHalfWord(i); - l_data_rank7 = db_reg_rank7.getHalfWord(i); - - if (l_data == 0) - { - FAPI_DBG("\tDP18_%i has no bad bits set, continuing...", i); - continue; - } - // clear bits 48:63 - l_ecmdRc = data_buffer.flushTo0(); - if (l_ecmdRc != ECMD_DBUF_SUCCESS) - { - FAPI_ERR("Error from ecmdDataBuffer flushTo0() " - "- rc 0x%.8X", l_ecmdRc); - - rc.setEcmdError(l_ecmdRc); - return rc; - } - - uint16_t mask = 0xF000; - // Temp 0xE removed. - //uint16_t emask = 0xE000; - uint8_t all_F_mask = 0; - for (uint8_t n=0; n < 4; n++) { // check each nibble - uint16_t nmask = mask >> (4*n); - // Temp 0xE removed. - //uint16_t e_nmask = emask >> (4*n); - - - if ((nmask & l_data) == nmask) { - FAPI_DBG("BYTE DISABLE WORKAROUND Found a 0XF on nibble=%i Port%i, dimm=%i, prg%i rank=%i data=0x%04X", n, port, dimm, prank, rank, l_data); - if ( ( ((nmask & l_data_rank0) == nmask) || (l_rank0_invalid) ) && - ( ((nmask & l_data_rank1) == nmask) || (l_rank1_invalid) ) && - ( ((nmask & l_data_rank2) == nmask) || (l_rank2_invalid) ) && - ( ((nmask & l_data_rank3) == nmask) || (l_rank3_invalid) ) && - ( ((nmask & l_data_rank4) == nmask) || (l_rank4_invalid) ) && - ( ((nmask & l_data_rank5) == nmask) || (l_rank5_invalid) ) && - ( ((nmask & l_data_rank6) == nmask) || (l_rank6_invalid) ) && - ( ((nmask & l_data_rank7) == nmask) || (l_rank7_invalid) ) ) - { - //Leave it an F. - FAPI_DBG("BYTE DISABLE WORKAROUND All ranks are a F so writing an 0xF to disable regs."); - FAPI_DBG("BYTE DISABLE WORKAROUND data rank 0 =0x%04X rank 1 =0x%04X rank 2 =0x%04X rank 3 =0x%04X rank 4 =0x%04X rank 5 =0x%04X rank 6 =0x%04X rank 7 =0x%04X", l_data_rank0,l_data_rank1,l_data_rank2,l_data_rank3,l_data_rank4,l_data_rank5,l_data_rank6,l_data_rank7 ); - all_F_mask = 1; - } - else - { - //Replacing F nibble with E nibble - FAPI_DBG("BYTE DISABLE WORKAROUND Single rank is a 0xF so writing an 0x0 to disable regs. PRE DATA: 0x%04X", l_data); - l_data = l_data & ~(nmask); - FAPI_DBG("BYTE DISABLE WORKAROUND POST DATA: 0x%04X", l_data); - } - } - - // Temporarily removing the 0xE case - /* - if ((nmask & l_data) == e_nmask) { - FAPI_DBG("BYTE DISABLE WORKAROUND Found a 0XE on nibble=%i Port%i, dimm=%i, prg%i rank=%i data=0x%04X", n, port, dimm, prank, rank, l_data); - - //Leave it an E. - FAPI_DBG("BYTE DISABLE WORKAROUND Found a 0xE so writing an 0xE to disable regs."); - - } - */ - - uint16_t wrclk_nmask = 0xF000 >> (4*n); - if (l_dram_width != 4) // x8 only disable the wrclk - { - - if (((wrclk_nmask & l_data)>>(4*(3-n))) == 0x0F) - { - wrclk_mask |= wrclk_disable_mask[n]; - } - } - - } - - - if (all_F_mask ==1) { - FAPI_INF("Entering into all F across all ranks case. Need to Disable WRCLK Enable as well."); - for (uint8_t n=0; n < 4; n++) // check each nibble - { - uint16_t nmask = 0xF000 >> (4*n); - if (l_dram_width == 4) - { - if ((nmask & l_data) == nmask) // bad bit(s) in nibble - { - // For Marc Gollub, since repair for x4 DRAM is in nibble - // granularity. Also due to higher chance of hitting dq0 of - // Micron causing write leveling to fail for entire x4 DRAM. - // Will also save a re-training loop. Complement in get_bbm_regs. - - - FAPI_INF("Disabling entire nibble %i",n); - rc = mss_get_dqs_lane(mba_target, port, i, n, - disable1_data); - if (rc) return rc; - wrclk_mask |= wrclk_disable_mask[n]; - } - } // end x4 - else // width == 8+? - { - if ((n % 2) == 0) - { - nmask = 0xFF00 >> (4*n); - if ((nmask & l_data) == nmask) // entire byte bad - { - disable1_data |= (0xF0 >> (n*2)); - } - } - if (((nmask & l_data)>>(4*(3-n))) == 0x0F) - { - wrclk_mask |= wrclk_disable_mask[n]; - } - } - } - - } - - - FAPI_DBG("\t\tdisable1_data=0x%04X", disable1_data); - - // set disable0(dq) reg - l_ecmdRc |= data_buffer.setHalfWord(3, l_data); - - if (l_ecmdRc != ECMD_DBUF_SUCCESS) - { - FAPI_ERR("Error from ecmdDataBuffer setHalfWord() " - "- rc 0x%.8X", l_ecmdRc); - - rc.setEcmdError(l_ecmdRc); - return rc; - } - - l_addr = disable_reg[port][prank][i]; - - FAPI_INF("+++ Setting Disable0 Bad Bit Mask p%i: DIMM%i PRG%i " - "Rank%i dp18_%i addr=0x%llx, data=0x%04X", port, - dimm, prank, prg[prank][port], i, l_addr , l_data); - - rc = fapiPutScomUnderMask(mba_target, l_addr, data_buffer, - data_buffer); - - if (rc) - { - FAPI_ERR("Error from fapiPutScom writing disable0 reg"); - return rc; - } - - if (all_F_mask ==1) { - FAPI_INF("Entering into all F across ranks case. Need to Disable DQS as well."); - // set address for disable1(dqs) register - l_addr += l_disable1_addr_offset; - if (disable1_data != 0) - { - l_ecmdRc = data_buffer.flushTo0(); // clear buffer - if (l_ecmdRc != ECMD_DBUF_SUCCESS) - { - FAPI_ERR("Error from ecmdDataBuffer flushTo0() " - "- rc 0x%.8X", l_ecmdRc); - - rc.setEcmdError(l_ecmdRc); - return rc; - } - - l_ecmdRc = data_buffer.setByte(6, disable1_data); - if (l_ecmdRc != ECMD_DBUF_SUCCESS) - { - FAPI_ERR("Error from ecmdDataBuffer setByte() " - "- rc 0x%.8X", l_ecmdRc); - - rc.setEcmdError(l_ecmdRc); - return rc; - } - - // write disable1(dqs) register - rc = fapiPutScomUnderMask(mba_target, l_addr, - data_buffer, data_buffer); - if (rc) - { - FAPI_ERR("Error from PutScom writing disable1 reg"); - return rc; - } - } // end disable1_data != 0 - - - // set address for wrclk_en register - l_addr &= l_wrclk_en_addr_mask; - - if (wrclk_mask != 0) - { - l_ecmdRc = data_buffer.flushTo0(); // clear buffer - if (l_ecmdRc != ECMD_DBUF_SUCCESS) - { - FAPI_ERR("Error from ecmdDataBuffer flushTo0() " - "- rc 0x%.8X", l_ecmdRc); - - rc.setEcmdError(l_ecmdRc); - return rc; - } - ecmdDataBufferBase put_mask(64); - l_ecmdRc = put_mask.setHalfWord(3, wrclk_mask); - if (l_ecmdRc != ECMD_DBUF_SUCCESS) - { - FAPI_ERR("Error from ecmdDataBuffer setHalfWord()" - " for wrclk_mask - rc 0x%.8X", l_ecmdRc); - - rc.setEcmdError(l_ecmdRc); - return rc; - } - - if (!l_disable1_fixed) - { - // clear(0) out the unused quads for wrclkdb_reg - rc = fapiPutScomUnderMask(mba_target, l_addr, - data_buffer, put_mask); - if (rc) - { - FAPI_ERR("Error from fapiPutScomUnderMask writing " - "wrclk_en reg"); - return rc; - } - } - // does disabling read clocks for unused bytes cause problems? - // SW25701 Workaround - x4s will not mask out RDCLKs on Bad Bits to avoid translation issues - else if ( (!l_disable1_rdclk_fixed) && (l_dram_width != 4) ) - { - uint64_t rdclk_addr = - disable_reg[port][prank][i] & 0xFFFFFF040FFFFFFFull; - // clear(0) out the unused quads for rdclk - rc = fapiPutScomUnderMask(mba_target, rdclk_addr, - data_buffer, put_mask); - if (rc) - { - FAPI_ERR("Error from fapiPutScomUnderMask writing " - "rdclk_en reg"); - return rc; - } - - FAPI_DBG("rdclk_addr=0x%llx, wrclk_addr=0x%llx, " - "wrclk_mask=0x%04X", rdclk_addr, l_addr, wrclk_mask); - } - } // end wrclk_mask != 0 - } - - - } // end DP18 instance loop - } // end primary rank loop - } // end port loop - return rc; -} // end mss_set_bbm_regs - - -fapi::ReturnCode mss_get_dqs_lane (const fapi::Target & i_mba, - const uint8_t i_port, const uint8_t i_block, const uint8_t i_quad, - uint8_t &o_lane) -{ -// input = mba, port, dp18 block, quad -// output = OR'd in lane of the dqs for the specified input - - ReturnCode rc; - uint8_t dq, dqs; - uint8_t phy_lane = i_quad * 4; - uint8_t l_block = i_block; - // returns dq - rc=mss_c4_phy(i_mba,i_port,0,RD_DQ,dq,1,phy_lane,l_block,1); - if (rc) return rc; - FAPI_INF("DQ returning mss_c4_phy inputs port: %d input index: %d phy_lane: %d block: %d",i_port,dq,phy_lane,l_block); - - dqs = dq / 4; - // returns phy_lane - rc=mss_c4_phy(i_mba,i_port,0,WR_DQS,dqs,1,phy_lane,l_block,0); - if (rc) return rc; - FAPI_INF("phy_lane returning mss_c4_phy inputs port: %d input index: %d phy_lane: %d block: %d",i_port,dqs,phy_lane,l_block); - - if (l_block != i_block) - { - FAPI_ERR("\t !!! blocks don't match from c4 to phy i_block=%i," - " o_block=%i", i_block, l_block); - } - - switch (phy_lane) - { - case 16: - case 17: - o_lane |= 0xC0; - break; - case 18: - case 19: - o_lane |= 0x30; - break; - case 20: - case 21: - o_lane |= 0x0C; - break; - case 22: - case 23: - o_lane |= 0x03; - break; - default: - //DECONFIG and FFDC INFO - const fapi::Target & TARGET_MBA_ERROR = i_mba; - const uint8_t & PORT = i_port; - const uint8_t & BLOCK = i_block; - const uint8_t & QUAD = i_quad; - const uint8_t & PHYLANE = phy_lane; - - FAPI_ERR("\t!!! (Port%i, dp18_%i, q=%i) phy_lane(%i)" - "returned from mss_c4_phy is invalid", - i_port, i_block, i_quad, phy_lane); - FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_C4_PHY_TRANSLATION_ERROR); - } - return rc; -} //end mss_get_dqs_lane - -fapi::ReturnCode mss_get_bbm_regs (const fapi::Target & mba_target, uint8_t i_training_success) -{ -// Registers to Flash. - - const uint64_t disable_reg[MAX_PORTS][MAX_PRI_RANKS][DP18_INSTANCES] = { - /* port 0 */ - { // primary rank pair 0 - {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_0_0x8000007c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_1_0x8000047c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_2_0x8000087c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_3_0x80000c7c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_4_0x8000107c0301143F}, - // primary rank pair 1 - {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_0_0x8000017c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_1_0x8000057c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_2_0x8000097c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_3_0x80000d7c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_4_0x8000117c0301143F}, - // primary rank pair 2 - {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_0_0x8000027c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_1_0x8000067c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_2_0x80000a7c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_3_0x80000e7c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_4_0x8000127c0301143F}, - // primary rank pair 3 - {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_0_0x8000037c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_1_0x8000077c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_2_0x80000b7c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_3_0x80000f7c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_4_0x8000137c0301143F} - }, - /* port 1 */ - { - // primary rank pair 0 - {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_0_0x8001007c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_1_0x8001047c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_2_0x8001087c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_3_0x80010c7c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_4_0x8001107c0301143F}, - // primary rank pair 1 - {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_0_0x8001017c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_1_0x8001057c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_2_0x8001097c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_3_0x80010d7c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_4_0x8001117c0301143F}, - // primary rank pair 2 - {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_0_0x8001027c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_1_0x8001067c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_2_0x80010a7c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_3_0x80010e7c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_4_0x8001127c0301143F}, - // primary rank pair 3 - {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_0_0x8001037c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_1_0x8001077c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_2_0x80010b7c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_3_0x80010f7c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_4_0x8001137c0301143F} - - }}; - - const uint8_t rg_invalid[] = { - ENUM_ATTR_EFF_PRIMARY_RANK_GROUP0_INVALID, - ENUM_ATTR_EFF_PRIMARY_RANK_GROUP1_INVALID, - ENUM_ATTR_EFF_PRIMARY_RANK_GROUP2_INVALID, - ENUM_ATTR_EFF_PRIMARY_RANK_GROUP3_INVALID, - }; - - ReturnCode rc; - ecmdDataBufferBase data_buffer(64); - ecmdDataBufferBase db_reg(BITS_PER_PORT); - ecmdDataBufferBase db_reg_vpd(BITS_PER_PORT); - uint32_t l_ecmdRc = ECMD_DBUF_SUCCESS; - uint8_t prg[MAX_PRI_RANKS][MAX_PORTS]; // primary rank group values - uint8_t l_dram_width; - uint8_t dimm; - uint8_t l_rank0_invalid = 1; //0 = valid, 1 = invalid - uint8_t l_rank1_invalid = 1; - uint8_t l_rank2_invalid = 1; - uint8_t l_rank3_invalid = 1; - uint8_t l_rank4_invalid = 1; - uint8_t l_rank5_invalid = 1; - uint8_t l_rank6_invalid = 1; - uint8_t l_rank7_invalid = 1; - - //Storing all the errors across rank/eff dimm - ecmdDataBufferBase db_reg_dimm0_rank0(BITS_PER_PORT); - ecmdDataBufferBase db_reg_dimm0_rank1(BITS_PER_PORT); - ecmdDataBufferBase db_reg_dimm0_rank2(BITS_PER_PORT); - ecmdDataBufferBase db_reg_dimm0_rank3(BITS_PER_PORT); - ecmdDataBufferBase db_reg_dimm1_rank0(BITS_PER_PORT); - ecmdDataBufferBase db_reg_dimm1_rank1(BITS_PER_PORT); - ecmdDataBufferBase db_reg_dimm1_rank2(BITS_PER_PORT); - ecmdDataBufferBase db_reg_dimm1_rank3(BITS_PER_PORT); - - - FAPI_INF("Running (get)registers->flash"); - - std::vector<Target> mba_dimms; - rc = fapiGetAssociatedDimms(mba_target, mba_dimms); // functional dimms - if(rc) return rc; - - // 4 dimms per MBA, 2 per port - // ATTR_EFF_PRIMARY_RANK_GROUP0[port], GROUP1[port], - // GROUP2[port], GROUP3[port] - rc=FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP0, &mba_target, prg[0]); - if(rc) return rc; - rc=FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP1, &mba_target, prg[1]); - if(rc) return rc; - rc=FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP2, &mba_target, prg[2]); - if(rc) return rc; - rc=FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP3, &mba_target, prg[3]); - if(rc) return rc; - - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &mba_target, l_dram_width); - if(rc) return rc; - - switch (l_dram_width) - { - case ENUM_ATTR_EFF_DRAM_WIDTH_X4: - l_dram_width = 4; - break; - case ENUM_ATTR_EFF_DRAM_WIDTH_X8: - l_dram_width = 8; - break; - case ENUM_ATTR_EFF_DRAM_WIDTH_X16: - l_dram_width = 16; - break; - case ENUM_ATTR_EFF_DRAM_WIDTH_X32: - l_dram_width = 32; - break; - default: - //DECONFIG and FFDC INFO - const fapi::Target & TARGET_MBA_ERROR = mba_target; - const uint8_t & WIDTH = l_dram_width; - - FAPI_ERR("ATTR_EFF_DRAM_WIDTH is invalid %u", l_dram_width); - FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_DRAM_WIDTH_INPUT_ERROR_GETBBM); - return rc; - } - - l_ecmdRc = data_buffer.flushTo0(); - if (l_ecmdRc != ECMD_DBUF_SUCCESS) - { - FAPI_ERR("Error from ecmdDataBuffer flushTo0() " - "- rc 0x%.8X", l_ecmdRc); - - rc.setEcmdError(l_ecmdRc); - return rc; - } - for (uint8_t port = 0; port < MAX_PORTS; port++ ) // [0:1] - { - // Initialize all the stored errors to 0. - l_ecmdRc |= db_reg_dimm0_rank0.flushTo0(); - l_ecmdRc |= db_reg_dimm0_rank1.flushTo0(); - l_ecmdRc |= db_reg_dimm0_rank2.flushTo0(); - l_ecmdRc |= db_reg_dimm0_rank3.flushTo0(); - l_ecmdRc |= db_reg_dimm1_rank0.flushTo0(); - l_ecmdRc |= db_reg_dimm1_rank1.flushTo0(); - l_ecmdRc |= db_reg_dimm1_rank2.flushTo0(); - l_ecmdRc |= db_reg_dimm1_rank3.flushTo0(); - l_rank0_invalid = 1; //0 = valid, 1 = invalid - l_rank1_invalid = 1; - l_rank2_invalid = 1; - l_rank3_invalid = 1; - l_rank4_invalid = 1; - l_rank5_invalid = 1; - l_rank6_invalid = 1; - l_rank7_invalid = 1; - - if (l_ecmdRc != ECMD_DBUF_SUCCESS) - { - FAPI_ERR("Error from ecmdDataBuffer setHalfWord()" - " for wrclk_mask - rc 0x%.8X", l_ecmdRc); - - rc.setEcmdError(l_ecmdRc); - return rc; - } - - // loop through primary ranks [0:3] - for (uint8_t prank = 0; prank < MAX_PRI_RANKS; prank++ ) - { - dimm = prg[prank][port] >> 2; - uint8_t rank = prg[prank][port] & 0x03; - uint16_t l_data = 0; - - if (prg[prank][port] == rg_invalid[prank]) // invalid rank - { - FAPI_DBG("Primary rank group %i is INVALID, continuing...", - prank); - if ( prg[prank][port] == 0) - { - l_ecmdRc |= db_reg_dimm0_rank0.flushTo1(); - if (l_ecmdRc != ECMD_DBUF_SUCCESS) - { - FAPI_ERR("Error from ecmdDataBuffer setHalfWord() " - "- rc 0x%.8X", l_ecmdRc); - - rc.setEcmdError(l_ecmdRc); - return rc; - } - } - - if ( prg[prank][port] == 1) - { - l_ecmdRc |= db_reg_dimm0_rank1.flushTo1(); - if (l_ecmdRc != ECMD_DBUF_SUCCESS) - { - FAPI_ERR("Error from ecmdDataBuffer setHalfWord() " - "- rc 0x%.8X", l_ecmdRc); - - rc.setEcmdError(l_ecmdRc); - return rc; - } - } - - if ( prg[prank][port] == 2) - { - l_ecmdRc |= db_reg_dimm0_rank2.flushTo1(); - if (l_ecmdRc != ECMD_DBUF_SUCCESS) - { - FAPI_ERR("Error from ecmdDataBuffer setHalfWord() " - "- rc 0x%.8X", l_ecmdRc); - - rc.setEcmdError(l_ecmdRc); - return rc; - } - } - - - if ( prg[prank][port] == 3) - { - l_ecmdRc |= db_reg_dimm0_rank3.flushTo1(); - if (l_ecmdRc != ECMD_DBUF_SUCCESS) - { - FAPI_ERR("Error from ecmdDataBuffer setHalfWord() " - "- rc 0x%.8X", l_ecmdRc); - - rc.setEcmdError(l_ecmdRc); - return rc; - } - } - - - - if ( prg[prank][port] == 4) - { - l_ecmdRc |= db_reg_dimm1_rank0.flushTo1(); - if (l_ecmdRc != ECMD_DBUF_SUCCESS) - { - FAPI_ERR("Error from ecmdDataBuffer setHalfWord() " - "- rc 0x%.8X", l_ecmdRc); - - rc.setEcmdError(l_ecmdRc); - return rc; - } - } - - - if ( prg[prank][port] == 5) - { - l_ecmdRc |= db_reg_dimm1_rank1.flushTo1(); - if (l_ecmdRc != ECMD_DBUF_SUCCESS) - { - FAPI_ERR("Error from ecmdDataBuffer setHalfWord() " - "- rc 0x%.8X", l_ecmdRc); - - rc.setEcmdError(l_ecmdRc); - return rc; - } - } - - - if ( prg[prank][port] == 6) - { - l_ecmdRc |= db_reg_dimm1_rank2.flushTo1(); - if (l_ecmdRc != ECMD_DBUF_SUCCESS) - { - FAPI_ERR("Error from ecmdDataBuffer setHalfWord() " - "- rc 0x%.8X", l_ecmdRc); - - rc.setEcmdError(l_ecmdRc); - return rc; - } - } - - - if ( prg[prank][port] == 7) - { - l_ecmdRc |= db_reg_dimm1_rank3.flushTo1(); - if (l_ecmdRc != ECMD_DBUF_SUCCESS) - { - FAPI_ERR("Error from ecmdDataBuffer setHalfWord() " - "- rc 0x%.8X", l_ecmdRc); - - rc.setEcmdError(l_ecmdRc); - return rc; - } - } - - continue; - } - - // create the db_reg (all the failed bits of the port) - l_ecmdRc = db_reg.flushTo0(); - if (l_ecmdRc != ECMD_DBUF_SUCCESS) - { - FAPI_ERR("Error from ecmdDataBuffer flushTo0() " - "- rc 0x%.8X", l_ecmdRc); - - rc.setEcmdError(l_ecmdRc); - return rc; - } - - FAPI_DBG("Port%i, dimm=%i, prg%i rank=%i", port, dimm, prank, rank); - for ( uint8_t i=0; i < DP18_INSTANCES; i++ ) // dp18 [0:4] - { - // clear bits 48:63 - l_ecmdRc = data_buffer.clearBit(48, BITS_PER_REG); - if (l_ecmdRc != ECMD_DBUF_SUCCESS) - { - FAPI_ERR("Error from ecmdDataBuffer setHalfWord() " - "- rc 0x%.8X", l_ecmdRc); - - rc.setEcmdError(l_ecmdRc); - return rc; - } - - rc = fapiGetScom(mba_target, disable_reg[port][prank][i], - data_buffer); - if (rc) - { - FAPI_ERR("Error from fapiPutScom writing disable reg"); - return rc; - } - - l_data = data_buffer.getHalfWord(3); - - FAPI_DBG("dp18_%i 0x%llx = 0x%x", i, - disable_reg[port][prank][i], l_data); - - if (l_data != 0) - { - - l_ecmdRc = db_reg.setHalfWord(i, l_data); - if (l_ecmdRc != ECMD_DBUF_SUCCESS) - { - FAPI_ERR("Error from ecmdDataBuffer setHalfWord() " - "- rc 0x%.8X", l_ecmdRc); - - rc.setEcmdError(l_ecmdRc); - return rc; - } - - FAPI_INF("+++ Setting Bad Bit Mask p%i: DIMM%i PRG%i " - "Rank%i \tdp18_%i addr=0x%llx, data=0x%04X", port, - dimm, prank, prg[prank][port], i, - disable_reg[port][prank][i], l_data); - } - } // end DP18 instance loop - - if (prg[prank][port] == rg_invalid[prank]) // invalid rank - { - FAPI_DBG("Primary rank group %i: INVALID, continuing...", - prank); - - continue; - } - - - if (dimm == 0) - { - if (rank == 0) - { - l_ecmdRc |= db_reg.copy(db_reg_dimm0_rank0); - l_rank0_invalid = 0; //0 = valid, 1 = invalid - } - else if (rank == 1) - { - l_ecmdRc |= db_reg.copy(db_reg_dimm0_rank1); - l_rank1_invalid = 0; //0 = valid, 1 = invalid - } - else if (rank == 2) - { - l_ecmdRc |= db_reg.copy(db_reg_dimm0_rank2); - l_rank2_invalid = 0; //0 = valid, 1 = invalid - } - else if (rank == 3) - { - l_ecmdRc |= db_reg.copy(db_reg_dimm0_rank3); - l_rank3_invalid = 0; //0 = valid, 1 = invalid - } - } - else if (dimm == 1) - { - if (rank == 0) - { - l_ecmdRc |= db_reg.copy(db_reg_dimm1_rank0); - l_rank4_invalid = 0; //0 = valid, 1 = invalid - } - else if (rank == 1) - { - l_ecmdRc |= db_reg.copy(db_reg_dimm1_rank1); - l_rank5_invalid = 0; //0 = valid, 1 = invalid - } - else if (rank == 2) - { - l_ecmdRc |= db_reg.copy(db_reg_dimm1_rank2); - l_rank6_invalid = 0; //0 = valid, 1 = invalid - } - else if (rank == 3) - { - l_ecmdRc |= db_reg.copy(db_reg_dimm1_rank3); - l_rank7_invalid = 0; //0 = valid, 1 = invalid - } - } - - if (l_ecmdRc != ECMD_DBUF_SUCCESS) - { - FAPI_ERR("Error from ecmdDataBuffer copy() " - "- rc 0x%.8X", l_ecmdRc); - - rc.setEcmdError(l_ecmdRc); - return rc; - } - - } // end primary rank loop - - - // loop through primary ranks [0:3] - for (uint8_t prank = 0; prank < MAX_PRI_RANKS; prank++ ) - { - - dimm = prg[prank][port] >> 2; - uint8_t rank = prg[prank][port] & 0x03; - uint16_t l_data = 0; - uint16_t l_data_rank0 = 0; - uint16_t l_data_rank1 = 0; - uint16_t l_data_rank2 = 0; - uint16_t l_data_rank3 = 0; - uint16_t l_data_rank4 = 0; - uint16_t l_data_rank5 = 0; - uint16_t l_data_rank6 = 0; - uint16_t l_data_rank7 = 0; - uint16_t l_data_curr_vpd = 0; - - if (prg[prank][port] == rg_invalid[prank]) // invalid rank - { - FAPI_DBG("Primary rank group %i is INVALID, continuing...", - prank); - continue; - } - - FAPI_DBG("Port%i, dimm=%i, prg%i rank=%i", port, dimm, prank, rank); - for ( uint8_t i=0; i < DP18_INSTANCES; i++ ) // dp18 [0:4] - { - - - l_data_rank0 = db_reg_dimm0_rank0.getHalfWord(i); - l_data_rank1 = db_reg_dimm0_rank1.getHalfWord(i); - l_data_rank2 = db_reg_dimm0_rank2.getHalfWord(i); - l_data_rank3 = db_reg_dimm0_rank3.getHalfWord(i); - l_data_rank4 = db_reg_dimm1_rank0.getHalfWord(i); - l_data_rank5 = db_reg_dimm1_rank1.getHalfWord(i); - l_data_rank6 = db_reg_dimm1_rank2.getHalfWord(i); - l_data_rank7 = db_reg_dimm1_rank3.getHalfWord(i); - - - - if (dimm == 0) - { - if (rank == 0) - { - l_data = l_data_rank0; - } - else if (rank == 1) - { - l_data = l_data_rank1; - } - else if (rank == 2) - { - l_data = l_data_rank2; - } - else if (rank == 3) - { - l_data = l_data_rank3; - } - } - else if (dimm == 1) - { - if (rank == 0) - { - l_data = l_data_rank4; - } - else if (rank == 1) - { - l_data = l_data_rank5; - } - else if (rank == 2) - { - l_data = l_data_rank6; - } - else if (rank == 3) - { - l_data = l_data_rank7; - } - } - - - uint8_t is_clean = 1; - rc = getC4dq2reg(mba_target, port, dimm, rank, db_reg_vpd, is_clean); - l_data_curr_vpd = db_reg_vpd.getHalfWord(i); - - uint16_t mask = 0xF000; - // Temp remove of 0xE case - //uint16_t emask = 0xE000; - for (uint8_t n=0; n < 4; n++) { // check each nibble - uint16_t nmask = mask >> (4*n); - // Temp remove of 0xE case - //uint16_t e_nmask = emask >> (4*n); - - - if ((nmask & l_data_curr_vpd) == nmask) { - FAPI_DBG("BYTE DISABLE WORKAROUND: Found a 0XF on nibble=%i Port%i, dimm=%i, prg%i rank=%i data= 0x%04X", n, port, dimm, prank, rank, l_data); - FAPI_DBG("BYTE DISABLE WORKAROUND: data rank 0 =0x%04X rank 1 =0x%04X rank 2 =0x%04X rank 3 =0x%04X rank 4 =0x%04X rank 5 =0x%04X rank 6 =0x%04X rank 7 =0x%04X", l_data_rank0,l_data_rank1,l_data_rank2,l_data_rank3,l_data_rank4,l_data_rank5,l_data_rank6,l_data_rank7 ); - if (i_training_success) - { //Leave it an F. - FAPI_DBG("BYTE DISABLE WORKAROUND: Training was successful so writing an 0xF to VPD. PRE data: 0x%04X", l_data); - l_data = l_data | nmask; - FAPI_DBG("BYTE DISABLE WORKAROUND: POST DATA: 0x%04X", l_data); - } - else - { - if ( ( ((nmask & l_data_rank0) == nmask) || (l_rank0_invalid) ) && - ( ((nmask & l_data_rank1) == nmask) || (l_rank1_invalid) ) && - ( ((nmask & l_data_rank2) == nmask) || (l_rank2_invalid) ) && - ( ((nmask & l_data_rank3) == nmask) || (l_rank3_invalid) ) && - ( ((nmask & l_data_rank4) == nmask) || (l_rank4_invalid) ) && - ( ((nmask & l_data_rank5) == nmask) || (l_rank5_invalid) ) && - ( ((nmask & l_data_rank6) == nmask) || (l_rank6_invalid) ) && - ( ((nmask & l_data_rank7) == nmask) || (l_rank7_invalid) ) ) - { - FAPI_DBG("BYTE DISABLE WORKAROUND: All ranks were F's and training was not successful. Uncool."); - continue; - } - else - { - - //Temprorarily removing 0xE version. Skipping Straight to 0xFs to all ranks. - /* - //Replacing F nibble with E nibble - FAPI_DBG("BYTE DISABLE WORKAROUND: Training was not successful so writing an 0xE to VPD. PRE DATA: 0x%04X", l_data); - l_data = (l_data & ~(nmask)) | e_nmask; - FAPI_DBG("BYTE DISABLE WORKAROUND: POST DATA: 0x%04X", l_data); - */ - - //Replacing E nibble with F nibble - FAPI_DBG("BYTE DISABLE WORKAROUND: Training failed so writing an 0xF to VPD for all ranks."); - l_data = l_data | nmask; - l_data_rank0 = l_data_rank0 | nmask; - l_data_rank1 = l_data_rank1 | nmask; - l_data_rank2 = l_data_rank2 | nmask; - l_data_rank3 = l_data_rank3 | nmask; - l_data_rank4 = l_data_rank4 | nmask; - l_data_rank5 = l_data_rank5 | nmask; - l_data_rank6 = l_data_rank6 | nmask; - l_data_rank7 = l_data_rank7 | nmask; - - } - } - } - else if ( ((nmask & l_data_curr_vpd) != nmask) && ((nmask & l_data_curr_vpd) > 0)) { - FAPI_DBG("BYTE DISABLE WORKAROUND: Found a non-zero, non-F nibble. Applying to all ranks."); - - if (l_dram_width == 4) - { - FAPI_DBG("BYTE DISABLE WORKAROUND: Its a x4 so turning it to a 0xF. PRE DATA: 0x%04X", l_data); - l_data = l_data | nmask; - FAPI_DBG("BYTE DISABLE WORKAROUND: POST DATA: 0x%04X", l_data); - - FAPI_DBG("BYTE DISABLE WORKAROUND: PRE data rank 0 =0x%04X rank 1 =0x%04X rank 2 =0x%04X rank 3 =0x%04X rank 4 =0x%04X rank 5 =0x%04X rank 6 =0x%04X rank 7 =0x%04X", l_data_rank0,l_data_rank1,l_data_rank2,l_data_rank3,l_data_rank4,l_data_rank5,l_data_rank6,l_data_rank7 ); - l_data_rank0 = l_data_rank0 | nmask; - l_data_rank1 = l_data_rank1 | nmask; - l_data_rank2 = l_data_rank2 | nmask; - l_data_rank3 = l_data_rank3 | nmask; - l_data_rank4 = l_data_rank4 | nmask; - l_data_rank5 = l_data_rank5 | nmask; - l_data_rank6 = l_data_rank6 | nmask; - l_data_rank7 = l_data_rank7 | nmask; - FAPI_DBG("BYTE DISABLE WORKAROUND: POST data rank 0 =0x%04X rank 1 =0x%04X rank 2 =0x%04X rank 3 =0x%04X rank 4 =0x%04X rank 5 =0x%04X rank 6 =0x%04X rank 7 =0x%04X", l_data_rank0,l_data_rank1,l_data_rank2,l_data_rank3,l_data_rank4,l_data_rank5,l_data_rank6,l_data_rank7 ); - - } - else if (l_dram_width == 8) - { - FAPI_DBG("BYTE DISABLE WORKAROUND: Its a x8 so leaving it the same."); - - FAPI_DBG("BYTE DISABLE WORKAROUND: PRE data rank 0 =0x%04X rank 1 =0x%04X rank 2 =0x%04X rank 3 =0x%04X rank 4 =0x%04X rank 5 =0x%04X rank 6 =0x%04X rank 7 =0x%04X", l_data_rank0,l_data_rank1,l_data_rank2,l_data_rank3,l_data_rank4,l_data_rank5,l_data_rank6,l_data_rank7 ); - l_data_rank0 = (l_data_rank0) | ( l_data & nmask); - l_data_rank1 = (l_data_rank1) | ( l_data & nmask); - l_data_rank2 = (l_data_rank2) | ( l_data & nmask); - l_data_rank3 = (l_data_rank3) | ( l_data & nmask); - l_data_rank4 = (l_data_rank4) | ( l_data & nmask); - l_data_rank5 = (l_data_rank5) | ( l_data & nmask); - l_data_rank6 = (l_data_rank6) | ( l_data & nmask); - l_data_rank7 = (l_data_rank7) | ( l_data & nmask); - - FAPI_DBG("BYTE DISABLE WORKAROUND: POST data rank 0 =0x%04X rank 1 =0x%04X rank 2 =0x%04X rank 3 =0x%04X rank 4 =0x%04X rank 5 =0x%04X rank 6 =0x%04X rank 7 =0x%04X", l_data_rank0,l_data_rank1,l_data_rank2,l_data_rank3,l_data_rank4,l_data_rank5,l_data_rank6,l_data_rank7 ); - } - - - - - } - // Temporarily Removing the 0xE case with this workaround. - /* - else if ((nmask & l_data_curr_vpd) == e_nmask) { - FAPI_DBG("BYTE DISABLE WORKAROUND: Found a 0XE on nibble=%i Port%i, dimm=%i, prg%i rank=%i data= 0x%04X", n, port, dimm, prank, rank, l_data); - if (i_training_success) - { - //Leave it an E. - FAPI_DBG("BYTE DISABLE WORKAROUND: Training was successful so writing an 0xE to VPD."); - } - else - { - //Replacing E nibble with F nibble - FAPI_DBG("BYTE DISABLE WORKAROUND: Training failed so writing an 0xF to VPD for all ranks."); - l_data = l_data | nmask; - l_data_rank0 = l_data_rank0 | nmask; - l_data_rank1 = l_data_rank1 | nmask; - l_data_rank2 = l_data_rank2 | nmask; - l_data_rank3 = l_data_rank3 | nmask; - l_data_rank4 = l_data_rank4 | nmask; - l_data_rank5 = l_data_rank5 | nmask; - l_data_rank6 = l_data_rank6 | nmask; - l_data_rank7 = l_data_rank7 | nmask; - } - } - */ - } - - if (dimm == 0) - { - if (rank == 0) - { - l_data_rank0 = l_data; - } - else if (rank == 1) - { - l_data_rank1 = l_data; - } - else if (rank == 2) - { - l_data_rank2 = l_data; - } - else if (rank == 3) - { - l_data_rank3 = l_data; - } - } - else if (dimm == 1) - { - if (rank == 0) - { - l_data_rank4 = l_data; - } - else if (rank == 1) - { - l_data_rank5 = l_data; - } - else if (rank == 2) - { - l_data_rank6 = l_data; - } - else if (rank == 3) - { - l_data_rank7 = l_data; - } - } - - - l_ecmdRc |= db_reg_dimm0_rank0.setHalfWord(i, l_data_rank0); - l_ecmdRc |= db_reg_dimm0_rank1.setHalfWord(i, l_data_rank1); - l_ecmdRc |= db_reg_dimm0_rank2.setHalfWord(i, l_data_rank2); - l_ecmdRc |= db_reg_dimm0_rank3.setHalfWord(i, l_data_rank3); - - l_ecmdRc |= db_reg_dimm1_rank0.setHalfWord(i, l_data_rank4); - l_ecmdRc |= db_reg_dimm1_rank1.setHalfWord(i, l_data_rank5); - l_ecmdRc |= db_reg_dimm1_rank2.setHalfWord(i, l_data_rank6); - l_ecmdRc |= db_reg_dimm1_rank3.setHalfWord(i, l_data_rank7); - - if (l_ecmdRc != ECMD_DBUF_SUCCESS) - { - FAPI_ERR("Error from ecmdDataBuffer flushTo0() " - "- rc 0x%.8X", l_ecmdRc); - rc.setEcmdError(l_ecmdRc); - return rc; - } - - - } - - - }// end of primary rank loop - - - // loop through primary ranks [0:3] - for (uint8_t prank = 0; prank < MAX_PRI_RANKS; prank++ ) - { - dimm = prg[prank][port] >> 2; - uint8_t rank = prg[prank][port] & 0x03; - FAPI_DBG("BYTE DISABLE WORKAROUND: Looping through dimm: %d rank: %d ", dimm, rank); - - if (prg[prank][port] == rg_invalid[prank]) // invalid rank - { - FAPI_DBG("Primary rank group %i is INVALID, continuing...", - prank); - continue; - } - - if (dimm == 0) - { - if (rank == 0) - { - l_ecmdRc |= db_reg_dimm0_rank0.copy(db_reg); - } - else if (rank == 1) - { - l_ecmdRc |= db_reg_dimm0_rank1.copy(db_reg); - } - else if (rank == 2) - { - l_ecmdRc |= db_reg_dimm0_rank2.copy(db_reg); - } - else if (rank == 3) - { - - l_ecmdRc |= db_reg_dimm0_rank3.copy(db_reg); - } - } - else if (dimm == 1) - { - if (rank == 0) - { - l_ecmdRc |= db_reg_dimm1_rank0.copy(db_reg); - } - else if (rank == 1) - { - l_ecmdRc |= db_reg_dimm1_rank1.copy(db_reg); - } - else if (rank == 2) - { - l_ecmdRc |= db_reg_dimm1_rank2.copy(db_reg); - } - else if (rank == 3) - { - l_ecmdRc |= db_reg_dimm1_rank3.copy(db_reg); - } - } - - if (l_ecmdRc != ECMD_DBUF_SUCCESS) - { - FAPI_ERR("Error from ecmdDataBuffer flushTo0() " - "- rc 0x%.8X", l_ecmdRc); - rc.setEcmdError(l_ecmdRc); - return rc; - } - - FAPI_INF("Setting BBM across dimm: %d rank: %d", dimm, rank); - rc = setC4dq2reg(mba_target, port, dimm, rank, db_reg); - if (rc) - { - FAPI_ERR("Error from setting register bitmap p%i: " - "dimm=%i, rank=%i rc=%i", port, dimm, rank, - static_cast<uint32_t>(rc)); - return rc; - } - - }// end of primary rank loop - - - - } // end port loop - return rc; -} // end mss_get_bbm_regs - - -ReturnCode getC4dq2reg(const Target & i_mba, const uint8_t i_port, - const uint8_t i_dimm, const uint8_t i_rank, ecmdDataBufferBase &o_reg, uint8_t &is_clean) -{ -// used by set_bbm(flash to registers) -// calls dimmGetBadDqBitmap and converts the data to phy order in a databuffer -// output reg = in phy based order(lanes) - - uint8_t l_bbm[TOTAL_BYTES] = {0}; // bad bitmap from dimmGetBadDqBitmap - ReturnCode rc; - uint32_t ecmdrc = ECMD_DBUF_SUCCESS; - uint8_t dq; - uint8_t phy_lane, phy_block; - - ecmdrc = o_reg.flushTo0(); // clear output databuffer - if (ecmdrc != ECMD_DBUF_SUCCESS) - { - FAPI_ERR("Error from ecmdDataBuffer flushTo0() " - "- rc 0x%.8X", ecmdrc); - - rc.setEcmdError(ecmdrc); - return rc; - } - - // get Centaur dq bitmap (C4 signal) order=[0:79], array of bytes - rc = dimmGetBadDqBitmap(i_mba, i_port, i_dimm, i_rank, l_bbm); - if (rc) - { - FAPI_ERR("Error from dimmGetBadDqBitmap on port %i: " - "dimm=%i, rank=%i rc=%i", i_port, i_dimm, i_rank, - static_cast<uint32_t>(rc)); - return rc; - } - - uint8_t dimm_spare[MAX_PORTS][MAX_DIMMS][MAX_PRI_RANKS]; - rc = FAPI_ATTR_GET(ATTR_VPD_DIMM_SPARE, &i_mba, dimm_spare); - if(rc) return rc; - - for (uint8_t byte=0; byte < TOTAL_BYTES; byte++) - { - if (l_bbm[byte] != 0) - { - if (byte == (TOTAL_BYTES-1)) // spare byte - { - uint8_t spare_bitmap = 0; - - switch (dimm_spare[i_port][i_dimm][i_rank]) - { - case ENUM_ATTR_VPD_DIMM_SPARE_NO_SPARE: // 0xFF - continue; // ignore bbm data for nonexistent spare - break; - case ENUM_ATTR_VPD_DIMM_SPARE_LOW_NIBBLE: - spare_bitmap = 0x0F; - break; - case ENUM_ATTR_VPD_DIMM_SPARE_HIGH_NIBBLE: - spare_bitmap = 0xF0; - break; - case ENUM_ATTR_VPD_DIMM_SPARE_FULL_BYTE: - spare_bitmap = 0x00; - break; - default: - - //DECONFIG and FFDC INFO - const fapi::Target & TARGET_MBA_ERROR = i_mba; - const uint8_t & SPARE = dimm_spare[i_port][i_dimm][i_rank]; - const uint8_t & PORT = i_port; - const uint8_t & DIMM = i_dimm; - const uint8_t & RANK = i_rank; - - FAPI_ERR("ATTR_VPD_DIMM_SPARE is invalid %u", - dimm_spare[i_port][i_dimm][i_rank]); - FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_DIMM_SPARE_INPUT_ERROR); - return rc; - } - - if (l_bbm[byte] == spare_bitmap) // spare already set via initfile - continue; - } - - uint8_t bs=0; - uint8_t be=8; - uint8_t loc=0; - is_clean = 0; - - if ((l_bbm[byte] & 0xF0) == 0xF0) // 0xF? - { - dq = (byte * 8); // for first lane - // input=cen_c4_dq, output=phy block, lane - rc = mss_c4_phy(i_mba, i_port, 0, RD_DQ,dq, - 0, phy_lane,phy_block, 0); - if (rc) return rc; - - if (l_bbm[byte] == 0xFF) - { // block lanes + 1st lane{0,8} - loc = (phy_block * 16) + (phy_lane & 0x08); - o_reg.setBit(loc, 8); // set dq byte - FAPI_DBG("0xFF byte=%i, lbbm=0x%02x dp%i_%i dq=%i o=%i", - byte, l_bbm[byte], phy_block, phy_lane, dq, loc); - continue; - } - // block lanes + 1st lane{0,4,8,12} - loc = (phy_block * 16) + (phy_lane & 0x0C); - o_reg.setBit(loc, 4); // set dq nibble0 - FAPI_DBG("0xF0 byte=%i, lbbm=0x%02x dp%i_%i dq=%i o=%i", - byte, l_bbm[byte], phy_block, phy_lane, dq, loc); - - if (l_bbm[byte] == 0xF0) // done with byte - continue; - bs=4; // processed the first 4 bits already - } - else if ((l_bbm[byte] & 0x0F) == 0x0F) // 0x?F - { - dq = (byte * 8) + 4; // for first lane of dq - rc = mss_c4_phy(i_mba, i_port, 0, RD_DQ,dq, - 0, phy_lane, phy_block, 0); - if (rc) return rc; - // block lanes + 1st lane{0,4,8,12} - loc = (phy_block * 16) + (phy_lane & 0x0C); - FAPI_DBG("0x0F byte=%i, lbbm=0x%02x dp%i_%i dq=%i o=%i", - byte, l_bbm[byte], phy_block, phy_lane, dq, loc); - o_reg.setBit(loc, 4); // set dq nibble1 - if (l_bbm[byte] == 0x0F) // done with byte - continue; - be=4; // processed the last 4 bits already - } - else if ((l_bbm[byte] >> 4) == 0) // 0x0? - bs=4; - else if ((l_bbm[byte] & 0x0F) == 0) // 0x?0 - be=4; - - for (uint8_t b=bs; b < be; b++) // test each bit - { - if ((l_bbm[byte] & (0x80 >> b)) > 0) // bit is set, - { - dq = (byte * 8) + b; - rc=mss_c4_phy(i_mba, i_port, 0, RD_DQ,dq, - 0, phy_lane, phy_block, 0); - if (rc) return rc; - loc = (phy_block * 16) + phy_lane; - o_reg.setBit(loc); - FAPI_DBG("b=%i byte=%i, lbbm=0x%02x dp%i_%i dq=%i " - "loc=%i bs=%i be=%i", b, byte, l_bbm[byte], - phy_block, phy_lane, dq, loc, bs, be); - } - } - } // end if not clean - } // end byte - return rc; -} // end getC4dq2reg - - -ReturnCode setC4dq2reg(const Target &i_mba, const uint8_t i_port, - const uint8_t i_dimm, const uint8_t i_rank, const ecmdDataBufferBase &i_reg) -{ -// used by get_bbm(registers to flash) -// Converts the data from phy order (i_reg) to cen_c4_dq array -// for dimmSetBadDqBitmap to write flash with - - ReturnCode rc; - uint8_t l_bbm [TOTAL_BYTES] = {0}; - uint8_t dq=0; - uint8_t phy_lane; - uint8_t phy_block; - uint8_t data; - - - // get Centaur dq bitmap (C4 signal) order=[0:79], array of bytes - rc = dimmGetBadDqBitmap(i_mba, i_port, i_dimm, i_rank, l_bbm); - if (rc) - { - FAPI_ERR("Error from dimmGetBadDqBitmap on port %i: " - "dimm=%i, rank=%i rc=%i", i_port, i_dimm, i_rank, - static_cast<uint32_t>(rc)); - return rc; - } - - for (uint8_t byte=0; byte < TOTAL_BYTES; byte++) - { - data = i_reg.getByte(byte); - if (data != 0) // need to check bits - { - uint8_t bs=0; - uint8_t be=8; - - phy_block = (byte / 2); // byte=[0..9], block=[0..4] - FAPI_DBG("\n\t\t\t\t\t\tbyte=%i, data=0x%02x phy_block=%i ", - byte, data, phy_block); - if ((data & 0xF0) == 0xF0) // 0xF? - { - phy_lane = 8 * (byte % 2); // lane=[0,8] - // input=block, lane output=cen_dq - rc = mss_c4_phy(i_mba, i_port, 0, RD_DQ,dq, - 0, phy_lane, phy_block, 1); - if (rc) return rc; - - if (data == 0xFF) - { // set 8 consecutive bits of the cen_c4_dq - l_bbm[(dq/8)] = 0xFF; - FAPI_DBG("0xFF dp%i_%i dq=%i, lbbm=0x%02x", - phy_block, phy_lane, dq, l_bbm[dq/8]); - continue; - } - - l_bbm[(dq/8)] |= ((dq % 8) < 4) ? 0xF0 : 0x0F; - FAPI_DBG("0xF0 dp%i_%i dq=%i, lbbm=0x%02x", - phy_block, phy_lane, dq, l_bbm[dq/8]); - - if (data == 0xF0) // done with byte - continue; - bs=4; // need to work on other bits - } - else if ((data & 0x0F) == 0x0F) // 0x?F - { - phy_lane = (8 * (byte % 2)) + 4; // lane=[4,12] - rc = mss_c4_phy(i_mba, i_port, 0, RD_DQ, dq, - 0, phy_lane, phy_block, 1); - if (rc) return rc; - - l_bbm[(dq/8)] |= ((dq % 8) < 4) ? 0xF0 : 0x0F; - FAPI_DBG("0x0F dp%i_%i dq=%i, lbbm=0x%02x", - phy_block, phy_lane, dq, l_bbm[dq/8]); - - if (data == 0x0F) // done with byte - continue; - be=4; // need to work on other bits - } - else if ((data >> 4) == 0) // 0x0? - bs=4; - else if ((data & 0x0F) == 0) // 0x?0 - be=4; - - for (uint8_t b=bs; b < be; b++) // test each bit - { - if ((data & (0x80 >> b)) > 0) // bit is set, - { - phy_lane = (8 * (byte % 2)) + b; - rc = mss_c4_phy(i_mba, i_port, 0, RD_DQ, dq, - 0, phy_lane, phy_block, 1); - if (rc) return rc; - l_bbm[(dq/8)] |= (0x80 >> (dq % 8)); - - } - else // bit is not set, - { - phy_lane = (8 * (byte % 2)) + b; - rc = mss_c4_phy(i_mba, i_port, 0, RD_DQ, dq, - 0, phy_lane, phy_block, 1); - if (rc) return rc; - l_bbm[(dq/8)] &= (~(0x80 >> (dq % 8))); - - } - } - } //end if not clean - } //end byte - - // set Centaur dq bitmap (C4 signal) order=[0:79], array of bytes - rc = dimmSetBadDqBitmap(i_mba, i_port, i_dimm, i_rank, l_bbm); - if (rc) - { - - FAPI_ERR("Error from dimmSetBadDqBitmap on port %i: " - "dimm=%i, rank=%i rc=%i", i_port, i_dimm, i_rank, - static_cast<uint32_t>(rc)); - return rc; - } - - return rc; -} //end setC4dq2reg - - -//Sets the DQS offset to be 16 instead of 8, recommended training settings -fapi::ReturnCode mss_setup_dqs_offset(Target &i_target) { - fapi::ReturnCode rc; - uint32_t rc_num = 0; - ecmdDataBufferBase buffer(64); - uint64_t scom_addr_array[10] = {DPHY01_DDRPHY_DP18_DQSCLK_OFFSET_P0_0_0x800000370301143F , - DPHY01_DDRPHY_DP18_DQSCLK_OFFSET_P0_1_0x800004370301143F , - DPHY01_DDRPHY_DP18_DQSCLK_OFFSET_P0_2_0x800008370301143F , - DPHY01_DDRPHY_DP18_DQSCLK_OFFSET_P0_3_0x80000C370301143F , - DPHY01_DDRPHY_DP18_DQSCLK_OFFSET_P0_4_0x800010370301143F , - DPHY01_DDRPHY_DP18_DQSCLK_OFFSET_P1_0_0x800100370301143F , - DPHY01_DDRPHY_DP18_DQSCLK_OFFSET_P1_1_0x800104370301143F , - DPHY01_DDRPHY_DP18_DQSCLK_OFFSET_P1_2_0x800108370301143F , - DPHY01_DDRPHY_DP18_DQSCLK_OFFSET_P1_3_0x80010C370301143F , - DPHY01_DDRPHY_DP18_DQSCLK_OFFSET_P1_4_0x800110370301143F}; - - FAPI_INF("DDR4: setting up DQS offset to be 16"); - for(uint8_t scom_addr = 0; scom_addr < 10; ++scom_addr) { - rc = fapiGetScom(i_target, scom_addr_array[scom_addr], buffer); - if(rc) return rc; - //Setting up CCS mode - rc_num = rc_num | buffer.insertFromRight ((uint32_t)16, 49, 7); - if (rc_num) - { - FAPI_ERR( "mss_setup_dqs: Error setting up buffers"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target, scom_addr_array[scom_addr], buffer); - if(rc) return rc; - } - - return rc; -} - - -} //end extern C diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.H b/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.H deleted file mode 100644 index 7e64ce845..000000000 --- a/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.H +++ /dev/null @@ -1,56 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* COPYRIGHT International Business Machines Corp. 2012,2014 */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: mss_draminit_training.H,v 1.3 2012/07/17 13:22:42 bellows Exp $ -//------------------------------------------------------------------------------ -// Don't forget to create CVS comments when you check in your changes! -//------------------------------------------------------------------------------ -// CHANGE HISTORY: -//------------------------------------------------------------------------------ -// Version:| Date: | Author: | Comment: -//---------|----------|----------|----------------------------------------------- -// 1.3 | 07/16/12 | bellows | added in Id tag -// 1.1 | 02/20/12 | divyakum | Added target description -// 1.0 | 11/14/11 | divyakum | First draft. - -#ifndef mss_draminit_training_H_ -#define mss_draminit_training_H_ -#include <fapi.H> - -typedef fapi::ReturnCode (*mss_draminit_training_FP_t)(const fapi::Target target); - -extern "C" -{ - -/** - * @brief Draminit Training procedure. Calibrating DRAMs - * - * @param[in] target Reference to centaur.mba target - * - * @return ReturnCode - */ - -fapi::ReturnCode mss_draminit_training(const fapi::Target target); - -} // extern "C" - -#endif // mss_draminit_training_H_ diff --git a/src/usr/hwpf/hwp/dram_training/mss_funcs.C b/src/usr/hwpf/hwp/dram_training/mss_funcs.C deleted file mode 100644 index 2c1accbf6..000000000 --- a/src/usr/hwpf/hwp/dram_training/mss_funcs.C +++ /dev/null @@ -1,1020 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/dram_training/mss_funcs.C $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2012,2015 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: mss_funcs.C,v 1.43 2015/09/10 14:57:26 thi Exp $ -/* File mss_funcs.C created by SLOAT JACOB D. (JAKE),2D3970 on Fri Apr 22 2011. */ - -//------------------------------------------------------------------------------ -// *! (C) Copyright International Business Machines Corp. 2007 -// *! All Rights Reserved -- Property of IBM -//------------------------------------------------------------------------------ -// *! TITLE : mss_funcs.C -// *! DESCRIPTION : Tools for centaur procedures -// *! OWNER NAME : jdsloat@us.ibm.com -// *! BACKUP NAME : -// #! ADDITIONAL COMMENTS : -// -// General purpose funcs - -//------------------------------------------------------------------------------ -// Don't forget to create CVS comments when you check in your changes! -//------------------------------------------------------------------------------ -// CHANGE HISTORY: -//------------------------------------------------------------------------------ -// Version:| Author: | Date: | Comment: -//---------|----------|---------|----------------------------------------------- -// 1.43 | thi |10-SEP-15| Fixed more RC stuff -// 1.42 | kmack |03-SEP-15| Fixed up some RC stuff -// 1.41 | sglancy |21-AUG-15| Fixed ODT initialization bug - ODT must be held low through ZQ cal -// 1.40 | sglancy |09-JUL-15| Added fixes to ZQ cal bug -// 1.39 | sglancy |27-MAY-15| Added fixes to ZQ cal for 3DS DIMMs -// 1.38 | jdsloat |01-APL-14| RAS review edits/changes -// 1.37 | jdsloat |28-MAR-14| RAS review edits/changes -// 1.36 | kcook | 03/12/14| Added check for DDR3 LRDIMM during mss_execut_zq_cal. -// 1.35 | jdsloat | 02/21/14| Fixed an inf loop with edit 1.34 and 128GB DIMMs. -// 1.34 | jdsloat | 02/20/14| Edited set_end_bit to add a NOP to the end of every CCS execution per CCS defect -// 1.33 | kcook | 08/27/13| Removed LRDIMM functions to mss_lrdimm_funcs.C. Use with mss_funcs.H v1.16. -// 1.32 | kcook | 08/16/13| Added LRDIMM support. Use with mss_funcs.H v1.15. -// 1.31 | jdsloat | 05/20/13| Added ddr_gen determination in address mirror mode function -// 1.30 | jdsloat | 04/09/13| Moved Address mirror mode sub function in from mss_draminit -// 1.29 | jsabrow | 11/19/12| added CCS data loader: mss_ccs_load_data_pattern -// 1.28 | bellows | 07/16/12|added in Id tag -// 1.27 | divyakum | 3/22/12 | Fixed warnings from mss_execute_zq_cal function -// 1.26 | divyakum | 3/22/12 | Fixed mss_execute_zq_cal function variable name mismatch -// 1.25 | divyakum | 3/21/12 | Added mss_execute_zq_cal function -// 1.24 | jdsloat | 3/20/12 | ccs_inst_arry0 bank fields reverse function removed -// 1.23 | jdsloat | 3/05/12 | ccs_inst_arry0 address fields reversed - needed to delete commented code out -// 1.22 | jdsloat | 2/17/12 | ccs_inst_arry0 address fields reversed -// 1.21 | jdsloat | 2/17/12 | FAPI ERRORs uncommented -// 1.20 | jdsloat | 2/16/12 | Initialize rc_num -// 1.19 | 2/14/12 | jdsloat| MBA translation, elminate unnecesary RC returns, got rid of some port arguments -// 1.18 | 2/08/12 | jdsloat| Target to Target&, Added Error reporting -// 1.17 | 2/02/12 | jdsloat| Initialized reg_address to 0 -// 1.16 | 1/19/12 | jdsloat| tabs to 4 spaces - properly, cke fix in mss_ccs_inst_arry_0 -// 1.15 | 1/16/12 | jdsloat| tabs to 4 spaces -// 1.14 | 1/13/12 | jdsloat| Capatilization, curley brackets, "mss_" prefix, adding rc checks, argument prefixes, includes, RC checks -// 1.13 | 1/6/12 | jdsloat| Got rid of Globals -// 1.12 | 12/23/11 | bellows | Printout poll count -// 1.11 | 12/20/11 | bellows | Fixed up ODT default value of 00 for CCS -// 1.10 | 12/16/11 | bellows | Bit number correction for ras,cas,wen and cal_type -// 1.9 | 12/14/11 | bellows | Fixed Bank and Address bit reversals restored others -// 1.8 | 12/13/11 | jdsloat | Insert from right fix -// 1.7 | 12/13/11 | jdsloat | Bank Address shift for reserved bit - 3 bits long, invert several fields in CCS0 -// 1.6 | 10/31/11 | jdsloat | CCS Update - goto_inst now assumed to be +1, CCS_fail fix, CCS_status fix -// 1.5 | 10/18/11 | jdsloat | Debug Messages -// 1.4 | 10/13/11 | jdsloat | End of CCS array check fix -// 1.3 | 10/11/11 | jdsloat | Fix CS Lines, dataBuffer.insert functions -// 1.2 | 10/05/11 | jdsloat | Convert integers to ecmdDataBufferBase in CCS_INST_1, CCS_INST_2, CCS_MODE -// 1.1 | 10/04/11 | jdsloat | First drop of Centaur in FAPI dir -//---------|----------|---------|----------------------------------------------- -// 1.7 | 09/29/11 | jdsloat | Functional Changes: port flow, CCS changes, only configed CS, CCS overflow precaution etc. Compiles. -// 1.6 | 09/26/11 | jdsloat | Added port information. -// 1.5 | 09/22/11 | jdsloat | Full update to FAPI. Functional changes to match procedure. -// 1.4 | 09/13/11 | jdsloat | First attempt at FAPI upgrade - attributes still in ecmd. -// 1.1 | 06/27/11 | jdsloat | CCS function update -// 1.00 | 04/22/11 | jdsloat | First drop of Centaur - -//---------------------------------------------------------------------- -// Includes -//---------------------------------------------------------------------- - -#include <fapi.H> -#include <mss_funcs.H> -#include <cen_scom_addresses.H> -using namespace fapi; - -ReturnCode mss_ccs_set_end_bit( - Target& i_target, - uint32_t i_instruction_number - ) -{ - uint32_t rc_num = 0; - ReturnCode rc; - ecmdDataBufferBase data_buffer(64); - - ecmdDataBufferBase address_16(16); - ecmdDataBufferBase bank_3(3); - ecmdDataBufferBase activate_1(1); - ecmdDataBufferBase rasn_1(1); - ecmdDataBufferBase casn_1(1); - ecmdDataBufferBase wen_1(1); - ecmdDataBufferBase cke_4(4); - ecmdDataBufferBase csn_8(8); - ecmdDataBufferBase odt_4(4); - ecmdDataBufferBase ddr_cal_type_4(4); - ecmdDataBufferBase num_idles_16(16); - ecmdDataBufferBase num_repeat_16(16); - ecmdDataBufferBase data_20(20); - ecmdDataBufferBase read_compare_1(1); - ecmdDataBufferBase rank_cal_4(4); - ecmdDataBufferBase ddr_cal_enable_1(1); - ecmdDataBufferBase ccs_end_1(1); - - uint32_t l_port_number = 0xFFFFFFFF; - - i_instruction_number = i_instruction_number + 1; - - FAPI_INF( "Setting End Bit on instruction (NOP): %d.", i_instruction_number); - - // Single NOP with CKE raised high and the end bit set high - rc_num = rc_num | csn_8.setBit(0,8); - rc_num = rc_num | address_16.clearBit(0, 16); - rc_num = rc_num | num_idles_16.clearBit(0, 16); - rc_num = rc_num | odt_4.clearBit(0,4); - rc_num = rc_num | csn_8.setBit(0,8); - rc_num = rc_num | cke_4.setBit(0,4); - rc_num = rc_num | wen_1.clearBit(0); - rc_num = rc_num | casn_1.clearBit(0); - rc_num = rc_num | rasn_1.clearBit(0); - rc_num = rc_num | ccs_end_1.setBit(0); - - if (rc_num) - { - FAPI_ERR( "Error setting up buffers"); - rc.setEcmdError(rc_num); - return rc; - } - - rc = mss_ccs_inst_arry_0( i_target, - i_instruction_number, - address_16, - bank_3, - activate_1, - rasn_1, - casn_1, - wen_1, - cke_4, - csn_8, - odt_4, - ddr_cal_type_4, - l_port_number); - if(rc) return rc; - rc = mss_ccs_inst_arry_1( i_target, - i_instruction_number, - num_idles_16, - num_repeat_16, - data_20, - read_compare_1, - rank_cal_4, - ddr_cal_enable_1, - ccs_end_1); - if(rc) return rc; - - return rc; -} - - -ReturnCode mss_address_mirror_swizzle( - Target& i_target, - uint32_t i_port, - uint32_t i_dimm, - uint32_t i_rank, - ecmdDataBufferBase& io_address, - ecmdDataBufferBase& io_bank - ) -{ - ReturnCode rc; - ReturnCode rc_buff; - uint32_t rc_num = 0; - ecmdDataBufferBase address_post_swizzle_16(16); - ecmdDataBufferBase bank_post_swizzle_3(3); - uint16_t mirror_mode_ba = 0; - uint16_t mirror_mode_ad = 0; - uint8_t dram_gen = 0; - - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_GEN, &i_target, dram_gen); - if(rc) return rc; - - FAPI_INF( "ADDRESS MIRRORING ON %s PORT%d DIMM%d RANK%d", i_target.toEcmdString(), i_port, i_dimm, i_rank); - - rc_num = rc_num | io_address.extractPreserve(&mirror_mode_ad, 0, 16, 0); - FAPI_INF( "PRE - MIRROR MODE ADDRESS: 0x%04X", mirror_mode_ad); - rc_num = rc_num | io_bank.extractPreserve(&mirror_mode_ba, 0, 3, 0); - FAPI_INF( "PRE - MIRROR MODE BANK ADDRESS: 0x%04X", mirror_mode_ba); - - //Initialize address and bank address as the same pre mirror mode swizzle - rc_num = rc_num | address_post_swizzle_16.insert(io_address, 0, 16, 0); - rc_num = rc_num | bank_post_swizzle_3.insert(io_bank, 0, 3, 0); - - if (rc_num) - { - FAPI_ERR( "mss_address_mirror_swizzle: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - if (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR3) - { - //Swap A3 and A4 - rc_num = rc_num | address_post_swizzle_16.insert(io_address, 4, 1, 3); - rc_num = rc_num | address_post_swizzle_16.insert(io_address, 3, 1, 4); - - //Swap A5 and A6 - rc_num = rc_num | address_post_swizzle_16.insert(io_address, 6, 1, 5); - rc_num = rc_num | address_post_swizzle_16.insert(io_address, 5, 1, 6); - - //Swap A7 and A8 - rc_num = rc_num | address_post_swizzle_16.insert(io_address, 8, 1, 7); - rc_num = rc_num | address_post_swizzle_16.insert(io_address, 7, 1, 8); - - //Swap BA0 and BA1 - rc_num = rc_num | bank_post_swizzle_3.insert(io_bank, 1, 1, 0); - rc_num = rc_num | bank_post_swizzle_3.insert(io_bank, 0, 1, 1); - - if (rc_num) - { - FAPI_ERR( "mss_address_mirror_swizzle: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - } - else if (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4) - { - //Swap A3 and A4 - rc_num = rc_num | address_post_swizzle_16.insert(io_address, 4, 1, 3); - rc_num = rc_num | address_post_swizzle_16.insert(io_address, 3, 1, 4); - - //Swap A5 and A6 - rc_num = rc_num | address_post_swizzle_16.insert(io_address, 6, 1, 5); - rc_num = rc_num | address_post_swizzle_16.insert(io_address, 5, 1, 6); - - //Swap A7 and A8 - rc_num = rc_num | address_post_swizzle_16.insert(io_address, 8, 1, 7); - rc_num = rc_num | address_post_swizzle_16.insert(io_address, 7, 1, 8); - - //Swap A11 and A13 - rc_num = rc_num | address_post_swizzle_16.insert(io_address, 13, 1, 11); - rc_num = rc_num | address_post_swizzle_16.insert(io_address, 11, 1, 13); - - //Swap BA0 and BA1 - rc_num = rc_num | bank_post_swizzle_3.insert(io_bank, 1, 1, 0); - rc_num = rc_num | bank_post_swizzle_3.insert(io_bank, 0, 1, 1); - - //Swap BG0 and BG1 (BA2 and ADDR 15) - rc_num = rc_num | bank_post_swizzle_3.insert(io_address, 2, 1, 15); - rc_num = rc_num | address_post_swizzle_16.insert(io_bank, 15, 1, 2); - - if (rc_num) - { - FAPI_ERR( "mss_address_mirror_swizzle: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - } - - rc_num = rc_num | address_post_swizzle_16.extractPreserve(&mirror_mode_ad, 0, 16, 0); - FAPI_INF( "POST - MIRROR MODE ADDRESS: 0x%04X", mirror_mode_ad); - rc_num = rc_num | bank_post_swizzle_3.extractPreserve(&mirror_mode_ba, 0, 3, 0); - FAPI_INF( "POST - MIRROR MODE BANK ADDRESS: 0x%04X", mirror_mode_ba); - - //copy address and bank address back to the IO variables - rc_num = rc_num | io_address.insert(address_post_swizzle_16, 0, 16, 0); - rc_num = rc_num | io_bank.insert(bank_post_swizzle_3, 0, 3, 0); - - if (rc_num) - { - FAPI_ERR( "mss_address_mirror_swizzle: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - - return rc; -} - -ReturnCode mss_ccs_inst_arry_0( - Target& i_target, - uint32_t& io_instruction_number, - ecmdDataBufferBase i_address, - ecmdDataBufferBase i_bank, - ecmdDataBufferBase i_activate, - ecmdDataBufferBase i_rasn, - ecmdDataBufferBase i_casn, - ecmdDataBufferBase i_wen, - ecmdDataBufferBase i_cke, - ecmdDataBufferBase i_csn, - ecmdDataBufferBase i_odt, - ecmdDataBufferBase i_ddr_cal_type, - uint32_t i_port - ) -{ - //Example Use: - //CCS_INST_ARRY_0( i_target, io_instruction_number, i_address, i_bank, i_activate, i_rasn, i_casn, i_wen, i_cke, i_csn, i_odt, i_ddr_cal_type, i_port); - ReturnCode rc; - ReturnCode rc_buff; - uint32_t rc_num = 0; - uint32_t reg_address = 0; - ecmdDataBufferBase data_buffer(64); - - if ((io_instruction_number >= 30)&&(i_port != 0xFFFFFFFF)) - { - uint32_t num_retry = 10; - uint32_t timer = 10; - rc = mss_ccs_set_end_bit( i_target, 29); - if(rc) return rc; - rc = mss_execute_ccs_inst_array( i_target, num_retry, timer); - if(rc) return rc; - io_instruction_number = 0; - } - - if (i_port == 0xFFFFFFFF) - { - i_port = 0; - } - - reg_address = io_instruction_number + CCS_INST_ARRY0_AB_REG0_0x03010615; - - rc_num = rc_num | data_buffer.flushTo0(); - rc_num = rc_num | data_buffer.insert(i_cke, 24, 4, 0); - rc_num = rc_num | data_buffer.insert(i_cke, 28, 4, 0); - - if (i_port == 0) - { - rc_num = rc_num | data_buffer.insert(i_csn, 32, 8, 0); - rc_num = rc_num | data_buffer.insertFromRight((uint8_t)0xFF,40,8); - rc_num = rc_num | data_buffer.insert(i_odt, 48, 4, 0); - rc_num = rc_num | data_buffer.insertFromRight((uint8_t)0x00,52,4); - } - else - { - rc_num = rc_num | data_buffer.insert((uint8_t)0xFF,32,8); - rc_num = rc_num | data_buffer.insert(i_csn, 40, 8, 0); - rc_num = rc_num | data_buffer.insertFromRight((uint8_t)0x00,48,4); - rc_num = rc_num | data_buffer.insert(i_odt, 52, 4, 0); - } - - //Placing bits into the data buffer - rc_num = rc_num | data_buffer.insert( i_address, 0, 16, 0); - rc_num = rc_num | data_buffer.insert( i_bank, 17, 3, 0); - rc_num = rc_num | data_buffer.insert( i_activate, 20, 1, 0); - rc_num = rc_num | data_buffer.insert( i_rasn, 21, 1, 0); - rc_num = rc_num | data_buffer.insert( i_casn, 22, 1, 0); - rc_num = rc_num | data_buffer.insert( i_wen, 23, 1, 0); - rc_num = rc_num | data_buffer.insert( i_ddr_cal_type, 56, 4, 0); - - if (rc_num) - { - FAPI_ERR( "mss_ccs_inst_arry_0: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - - rc = fapiPutScom(i_target, reg_address, data_buffer); - - return rc; -} - -ReturnCode mss_ccs_inst_arry_1( - Target& i_target, - uint32_t& io_instruction_number, - ecmdDataBufferBase i_num_idles, - ecmdDataBufferBase i_num_repeat, - ecmdDataBufferBase i_data, - ecmdDataBufferBase i_read_compare, - ecmdDataBufferBase i_rank_cal, - ecmdDataBufferBase i_ddr_cal_enable, - ecmdDataBufferBase i_ccs_end - ) -{ - - //Example Use: - //CCS_INST_ARRY_1( i_target, io_instruction_number, i_num_idles, i_num_repeat, i_data, i_read_compare, i_rank_cal, i_ddr_cal_enable, i_ccs_end); - ReturnCode rc; - ReturnCode rc_buff; - uint32_t rc_num = 0; - uint32_t reg_address = 0; - ecmdDataBufferBase goto_inst(5); - - if ((io_instruction_number >= 30)&&(i_ccs_end.isBitClear(0))) - { - uint32_t num_retry = 10; - uint32_t timer = 10; - rc = mss_ccs_set_end_bit( i_target, 29); - if(rc) return rc; - rc = mss_execute_ccs_inst_array( i_target, num_retry, timer); - if(rc) return rc; - io_instruction_number = 0; - } - - reg_address = io_instruction_number + CCS_INST_ARRY1_AB_REG0_0x03010635; - - ecmdDataBufferBase data_buffer(64); - - rc_num = rc_num | goto_inst.insertFromRight(io_instruction_number + 1, 0, 5); - - //Setting up a CCS Instruction Array Type 1 - rc_num = rc_num | data_buffer.insert( i_num_idles, 0, 16, 0); - rc_num = rc_num | data_buffer.insert( i_num_repeat, 16, 16, 0); - rc_num = rc_num | data_buffer.insert( i_data, 32, 20, 0); - rc_num = rc_num | data_buffer.insert( i_read_compare, 52, 1, 0); - rc_num = rc_num | data_buffer.insert( i_rank_cal, 53, 4, 0); - rc_num = rc_num | data_buffer.insert( i_ddr_cal_enable, 57, 1, 0); - rc_num = rc_num | data_buffer.insert( i_ccs_end, 58, 1, 0); - rc_num = rc_num | data_buffer.insert( goto_inst, 59, 5, 0); - - if (rc_num) - { - FAPI_ERR( "mss_ccs_inst_arry_1: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - - rc = fapiPutScom(i_target, reg_address, data_buffer); - - return rc; -} - -//-------------- -ReturnCode mss_ccs_load_data_pattern( - Target& i_target, - uint32_t io_instruction_number, - mss_ccs_data_pattern data_pattern) -{ - //Example Use: - // - ReturnCode rc; - - if (data_pattern == MSS_CCS_DATA_PATTERN_00) - { - rc = mss_ccs_load_data_pattern(i_target, io_instruction_number, 0x00000000); - } - else if (data_pattern == MSS_CCS_DATA_PATTERN_0F) - { - rc = mss_ccs_load_data_pattern(i_target, io_instruction_number, 0x00055555); - } - else if (data_pattern == MSS_CCS_DATA_PATTERN_F0) - { - rc = mss_ccs_load_data_pattern(i_target, io_instruction_number, 0x000aaaaa); - } - else if (data_pattern == MSS_CCS_DATA_PATTERN_FF) - { - rc = mss_ccs_load_data_pattern(i_target, io_instruction_number, 0x000fffff); - } - - return rc; -} - - -ReturnCode mss_ccs_load_data_pattern( - Target& i_target, - uint32_t io_instruction_number, - uint32_t data_pattern) -{ - //Example Use: - // - ReturnCode rc; - ReturnCode rc_buff; - uint32_t rc_num = 0; - uint32_t reg_address = 0; - - if (io_instruction_number > 31) - { - FAPI_INF("mss_ccs_load_data_pattern: CCS Instruction Array index out of bounds"); - } - else - { - reg_address = io_instruction_number + CCS_INST_ARRY1_AB_REG0_0x03010635; - ecmdDataBufferBase data_buffer(64); - - //read current array1 reg - rc = fapiGetScom(i_target, reg_address, data_buffer); - if(rc) return rc; - - //modify data bits for specified pattern - rc_num = rc_num | data_buffer.insertFromRight(data_pattern, 32, 20); - if (rc_num) - { - FAPI_ERR( "mss_ccs_load_data_pattern: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - - //write array1 back out - rc = fapiPutScom(i_target, reg_address, data_buffer); - if(rc) return rc; - } - - return rc; -} -//-------------- - - - -ReturnCode mss_ccs_mode( - Target& i_target, - ecmdDataBufferBase i_stop_on_err, - ecmdDataBufferBase i_ue_disable, - ecmdDataBufferBase i_data_sel, - ecmdDataBufferBase i_pclk, - ecmdDataBufferBase i_nclk, - ecmdDataBufferBase i_cal_time_cnt, - ecmdDataBufferBase i_resetn, - ecmdDataBufferBase i_reset_recover, - ecmdDataBufferBase i_copy_spare_cke - ) -{ - ecmdDataBufferBase data_buffer(64); - ReturnCode rc; - ReturnCode rc_buff; - uint32_t rc_num = 0; - - - rc = fapiGetScom(i_target, CCS_MODEQ_AB_REG_0x030106A7, data_buffer); - if(rc) return rc; - - //Setting up CCS mode - rc_num = rc_num | data_buffer.insert( i_stop_on_err, 0, 1, 0); - rc_num = rc_num | data_buffer.insert( i_ue_disable, 1, 1, 0); - rc_num = rc_num | data_buffer.insert( i_data_sel, 2, 2, 0); - rc_num = rc_num | data_buffer.insert( i_nclk, 4, 2, 0); - rc_num = rc_num | data_buffer.insert( i_pclk, 6, 2, 0); - rc_num = rc_num | data_buffer.insert( i_cal_time_cnt, 8, 16, 0); - rc_num = rc_num | data_buffer.insert( i_resetn, 24, 1, 0); - rc_num = rc_num | data_buffer.insert( i_reset_recover, 25, 1, 0); - rc_num = rc_num | data_buffer.insert( i_copy_spare_cke, 26, 1, 0); - - if (rc_num) - { - FAPI_ERR( "mss_ccs_mode: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - - rc = fapiPutScom(i_target, CCS_MODEQ_AB_REG_0x030106A7, data_buffer); - if(rc) return rc; - - return rc; -} - -ReturnCode mss_ccs_start_stop( - Target& i_target, - bool i_start_stop - ) -{ - ReturnCode rc; - ReturnCode rc_buff; - uint32_t rc_num = 0; - ecmdDataBufferBase data_buffer(64); - - - rc = fapiGetScom(i_target, CCS_CNTLQ_AB_REG_0x030106A5, data_buffer); - if(rc) return rc; - - if (i_start_stop == MSS_CCS_START) - { - rc_num = rc_num | data_buffer.setBit(0,1); - FAPI_INF(" Executing contents of CCS." ); - } - else if (i_start_stop == MSS_CCS_STOP) - { - rc_num = rc_num | data_buffer.setBit(1,1); - FAPI_INF(" Halting execution of the CCS." ); - } - - if (rc_num) - { - FAPI_ERR( "mss_ccs_start_stop: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - - rc = fapiPutScom(i_target, CCS_CNTLQ_AB_REG_0x030106A5, data_buffer); - - return rc; -} - -ReturnCode mss_ccs_status_query( Target& i_target, mss_ccs_status_query_result& io_status) { - - ecmdDataBufferBase data_buffer(64); - ReturnCode rc; - - rc = fapiGetScom(i_target, CCS_STATQ_AB_REG_0x030106A6, data_buffer); - if(rc) return rc; - - if (data_buffer.getBit(2)) - { - io_status = MSS_STAT_QUERY_FAIL; - return rc; - } - else if (data_buffer.getBit(0)) - { - io_status = MSS_STAT_QUERY_IN_PROGRESS; - return rc; - } - else if (data_buffer.getBit(1)) - { - io_status = MSS_STAT_QUERY_PASS; - } - else - { - FAPI_INF("CCS Status Undetermined."); - } - return rc; -} - -ReturnCode mss_ccs_fail_type( - Target& i_target - ) -{ - ecmdDataBufferBase data_buffer(64); - ReturnCode rc; - - rc = fapiGetScom(i_target, CCS_STATQ_AB_REG_0x030106A6, data_buffer); - if(rc) return rc; - - if (data_buffer.getBit(3)) - { - //DECONFIG and FFDC INFO - const fapi::Target & TARGET_MBA_ERROR = i_target; - const ecmdDataBufferBase & REG_CONTENTS = data_buffer; - - FAPI_ERR("CCS returned a FAIL condtion of \"Read Miscompare\" "); - FAPI_SET_HWP_ERROR(rc, RC_MSS_CCS_READ_MISCOMPARE); - } - else if (data_buffer.getBit(4)) - { - //DECONFIG and FFDC INFO - const fapi::Target & TARGET_MBA_ERROR = i_target; - const ecmdDataBufferBase & REG_CONTENTS = data_buffer; - - FAPI_ERR("CCS returned a FAIL condition of \"UE or SUE Error\" "); - FAPI_SET_HWP_ERROR(rc, RC_MSS_CCS_UE_SUE); - } - else if (data_buffer.getBit(5)) - { - //DECONFIG and FFDC INFO - const fapi::Target & TARGET_MBA_ERROR = i_target; - const ecmdDataBufferBase & REG_CONTENTS = data_buffer; - - FAPI_ERR("CCS returned a FAIL condition of \"Calibration Operation Time Out\" "); - FAPI_SET_HWP_ERROR(rc, RC_MSS_CCS_CAL_TIMEOUT); - } - - return rc; -} - -ReturnCode mss_execute_ccs_inst_array( - Target& i_target, - uint32_t i_num_poll, - uint32_t i_wait_timer - ) -{ - enum mss_ccs_status_query_result status = MSS_STAT_QUERY_IN_PROGRESS; - uint32_t count = 0; - ReturnCode rc; - - rc = mss_ccs_start_stop( i_target, MSS_CCS_START); - if(rc) return rc; - - while ((count < i_num_poll) && (status == MSS_STAT_QUERY_IN_PROGRESS)) - { - rc = mss_ccs_status_query( i_target, status); - if(rc) return rc; - count++; - fapiDelay(i_wait_timer, i_wait_timer); - } - - FAPI_INF("CCS Executed Polling %d times.", count); - - if (status == MSS_STAT_QUERY_FAIL) - { - FAPI_ERR("CCS FAILED"); - rc = mss_ccs_fail_type(i_target); - if(rc) return rc; - FAPI_ERR("CCS has returned a fail."); - } - else if (status == MSS_STAT_QUERY_IN_PROGRESS) - { - FAPI_ERR("CCS Operation Hung"); - FAPI_ERR("CCS has returned a IN_PROGRESS status and considered Hung."); - rc = mss_ccs_fail_type(i_target); - if(rc) - { - return rc; - } - else - { - //DECONFIG and FFDC INFO - const fapi::Target & TARGET_MBA_ERROR = i_target; - - FAPI_ERR("Returning a CCS HUNG RC Value."); - FAPI_SET_HWP_ERROR(rc, RC_MSS_CCS_HUNG); - return rc; - } - } - else if (status == MSS_STAT_QUERY_PASS) - { - FAPI_INF("CCS Executed Successfully."); - } - else - { - FAPI_INF("CCS Status Undetermined."); - } - - return rc; -} - -uint32_t mss_reverse_32bits(uint32_t i_x) -{ - //reversing bit order of a 32 bit uint - i_x = (((i_x & 0xaaaaaaaa) >> 1) | ((i_x & 0x55555555) << 1)); - i_x = (((i_x & 0xcccccccc) >> 2) | ((i_x & 0x33333333) << 2)); - i_x = (((i_x & 0xf0f0f0f0) >> 4) | ((i_x & 0x0f0f0f0f) << 4)); - i_x = (((i_x & 0xff00ff00) >> 8) | ((i_x & 0x00ff00ff) << 8)); - return((i_x >> 16) | (i_x << 16)); -} - -uint8_t mss_reverse_8bits(uint8_t i_number){ - - //reversing bit order of a 8 bit uint - uint8_t temp = 0; - for (uint8_t loop = 0; loop < 8; loop++) - { - uint8_t bit = (i_number&(1<<loop))>>loop; - temp |= bit<<(7-loop); - } - return temp; -} - - - -ReturnCode mss_rcd_parity_check( - Target& i_target, - uint32_t i_port - ) -{ - //checks all ports for a parity error - ecmdDataBufferBase data_buffer(64); - ReturnCode rc; - ReturnCode rc_buff; - uint32_t rc_num = 0; - uint8_t port_0_error = 0; - uint8_t port_1_error = 0; - uint8_t rcd_parity_fail = 0; - - rc = fapiGetScom(i_target, MBA01_CALFIR_REG_0x03010402, data_buffer); - if(rc) return rc; - - rc_num = rc_num | data_buffer.extract(&port_0_error, 4, 1); - rc_num = rc_num | data_buffer.extract(&port_1_error, 7, 1); - rc_num = rc_num | data_buffer.extract(&rcd_parity_fail, 5, 1); - if (rc_num) - { - FAPI_ERR( "mss_rcd_parity_check: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - - FAPI_INF("Checking for RCD Parity Error."); - - if (rcd_parity_fail) - { - //DECONFIG and FFDC INFO - const fapi::Target & TARGET_MBA_ERROR = i_target; - - FAPI_ERR("Ports 0 and 1 has exceeded a maximum number of RCD Parity Errors."); - FAPI_SET_HWP_ERROR(rc, RC_MSS_RCD_PARITY_ERROR_LIMIT); - } - else if ((port_0_error) && (i_port == 0)) - { - //DECONFIG and FFDC INFO - const fapi::Target & TARGET_MBA_ERROR = i_target; - - FAPI_ERR("Port 0 has recorded an RCD Parity Error. "); - FAPI_SET_HWP_ERROR(rc, RC_MSS_RCD_PARITY_ERROR_PORT0); - } - else if ((port_1_error) && (i_port == 1)) - { - //DECONFIG and FFDC INFO - const fapi::Target & TARGET_MBA_ERROR = i_target; - - FAPI_ERR("Port 1 has recorded an RCD Parity Error. "); - FAPI_SET_HWP_ERROR(rc, RC_MSS_RCD_PARITY_ERROR_PORT1); - } - else - { - FAPI_INF("No RCD Parity Errors on Port %d.", i_port); - } - - return rc; -} - -//ZQ Cal -ReturnCode mss_execute_zq_cal( - Target& i_target, - uint8_t i_port - ) -{ - //Enums and Constants - enum size - { - MAX_NUM_DIMM = 2, - }; - - uint32_t NUM_POLL = 100; - - uint32_t instruction_number = 0; - ReturnCode rc; - ReturnCode rc_buff; - uint32_t rc_num = 0; - - //adds a NOP before ZQ cal - ecmdDataBufferBase address_buffer_16(16); - rc_num = rc_num | address_buffer_16.setHalfWord(0, 0x0000); //Set A10 bit for ZQCal Long - ecmdDataBufferBase bank_buffer_8(8); - rc_num = rc_num | bank_buffer_8.flushTo0(); - ecmdDataBufferBase activate_buffer_1(1); - rc_num = rc_num | activate_buffer_1.flushTo1(); - ecmdDataBufferBase rasn_buffer_1(1); - rc_num = rc_num | rasn_buffer_1.flushTo1(); //For NOP rasn = 1; casn = 1; wen = 1; - ecmdDataBufferBase casn_buffer_1(1); - rc_num = rc_num | casn_buffer_1.flushTo1(); - ecmdDataBufferBase wen_buffer_1(1); - rc_num = rc_num | wen_buffer_1.flushTo1(); - ecmdDataBufferBase cke_buffer_8(8); - rc_num = rc_num | cke_buffer_8.flushTo1(); - ecmdDataBufferBase csn_buffer_8(8); - rc_num = rc_num | csn_buffer_8.flushTo1();; - ecmdDataBufferBase odt_buffer_8(8); - rc_num = rc_num | odt_buffer_8.flushTo0(); - ecmdDataBufferBase test_buffer_4(4); - rc_num = rc_num | test_buffer_4.flushTo0(); // 01XX:External ZQ calibration - rc_num = rc_num | test_buffer_4.setBit(1); - ecmdDataBufferBase num_idles_buffer_16(16); - rc_num = rc_num | num_idles_buffer_16.setHalfWord(0, 0x0400); //1024 for ZQCal - ecmdDataBufferBase num_repeat_buffer_16(16); - rc_num = rc_num | num_repeat_buffer_16.flushTo0(); - ecmdDataBufferBase data_buffer_20(20); - rc_num = rc_num | data_buffer_20.flushTo0(); - ecmdDataBufferBase read_compare_buffer_1(1); - rc_num = rc_num | read_compare_buffer_1.flushTo0(); - ecmdDataBufferBase rank_cal_buffer_3(3); - rc_num = rc_num | rank_cal_buffer_3.flushTo0(); - ecmdDataBufferBase ddr_cal_enable_buffer_1(1); - rc_num = rc_num | ddr_cal_enable_buffer_1.flushTo0(); - ecmdDataBufferBase ccs_end_buffer_1(1); - rc_num = rc_num | ccs_end_buffer_1.flushTo0(); - - ecmdDataBufferBase stop_on_err_buffer_1(1); - rc_num = rc_num | stop_on_err_buffer_1.flushTo0(); - ecmdDataBufferBase resetn_buffer_1(1); - rc_num = rc_num | resetn_buffer_1.setBit(0); - ecmdDataBufferBase data_buffer_64(64); - rc_num = rc_num | data_buffer_64.flushTo0(); - - if (rc_num) - { - FAPI_ERR( "mss_execute_zq_cal: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - - rc = mss_ccs_inst_arry_0(i_target, instruction_number, address_buffer_16, bank_buffer_8, activate_buffer_1, rasn_buffer_1, casn_buffer_1, wen_buffer_1, cke_buffer_8, csn_buffer_8, odt_buffer_8, test_buffer_4, i_port); - if(rc) return rc; //Error handling for mss_ccs_inst built into mss_funcs - rc = mss_ccs_inst_arry_1(i_target, instruction_number, num_idles_buffer_16, num_repeat_buffer_16, data_buffer_20, read_compare_buffer_1, rank_cal_buffer_3, ddr_cal_enable_buffer_1, ccs_end_buffer_1); - if(rc) return rc; //Error handling for mss_ccs_inst built into mss_funcs - - rc = mss_ccs_inst_arry_0(i_target, instruction_number, address_buffer_16, bank_buffer_8, activate_buffer_1, rasn_buffer_1, casn_buffer_1, wen_buffer_1, cke_buffer_8, csn_buffer_8, odt_buffer_8, test_buffer_4, i_port); - if(rc) return rc; //Error handling for mss_ccs_inst built into mss_funcs - rc = mss_ccs_inst_arry_1(i_target, instruction_number, num_idles_buffer_16, num_repeat_buffer_16, data_buffer_20, read_compare_buffer_1, rank_cal_buffer_3, ddr_cal_enable_buffer_1, ccs_end_buffer_1); - if(rc) return rc; //Error handling for mss_ccs_inst built into mss_funcs - - rc = mss_ccs_inst_arry_0(i_target, instruction_number, address_buffer_16, bank_buffer_8, activate_buffer_1, rasn_buffer_1, casn_buffer_1, wen_buffer_1, cke_buffer_8, csn_buffer_8, odt_buffer_8, test_buffer_4, i_port); - if(rc) return rc; //Error handling for mss_ccs_inst built into mss_funcs - rc = mss_ccs_inst_arry_1(i_target, instruction_number, num_idles_buffer_16, num_repeat_buffer_16, data_buffer_20, read_compare_buffer_1, rank_cal_buffer_3, ddr_cal_enable_buffer_1, ccs_end_buffer_1); - if(rc) return rc; //Error handling for mss_ccs_inst built into mss_funcs - - instruction_number = 1; - - //now sets up for ZQ CAL - rc_num = rc_num | address_buffer_16.setHalfWord(0, 0x0020); //Set A10 bit for ZQCal Long - rc_num = rc_num | bank_buffer_8.flushTo0(); - rc_num = rc_num | activate_buffer_1.flushTo1(); - rc_num = rc_num | rasn_buffer_1.flushTo1(); //For ZQCal rasn = 1; casn = 1; wen = 0; - rc_num = rc_num | casn_buffer_1.flushTo1(); - rc_num = rc_num | wen_buffer_1.flushTo0(); - rc_num = rc_num | cke_buffer_8.flushTo1(); - rc_num = rc_num | odt_buffer_8.flushTo0(); - rc_num = rc_num | test_buffer_4.flushTo0(); // 01XX:External ZQ calibration - rc_num = rc_num | test_buffer_4.setBit(1); - rc_num = rc_num | num_idles_buffer_16.setHalfWord(0, 0x0400); //1024 for ZQCal - rc_num = rc_num | num_repeat_buffer_16.flushTo0(); - rc_num = rc_num | data_buffer_20.flushTo0(); - rc_num = rc_num | read_compare_buffer_1.flushTo0(); - rc_num = rc_num | rank_cal_buffer_3.flushTo0(); - rc_num = rc_num | ddr_cal_enable_buffer_1.flushTo0(); - rc_num = rc_num | ccs_end_buffer_1.flushTo0(); - rc_num = rc_num | stop_on_err_buffer_1.flushTo0(); - rc_num = rc_num | resetn_buffer_1.setBit(0); - rc_num = rc_num | data_buffer_64.flushTo0(); - - if (rc_num) - { - FAPI_ERR( "mss_execute_zq_cal: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - - - uint8_t current_rank = 0; - uint8_t start_rank = 0; - uint8_t num_master_ranks_array[2][2]; - uint8_t num_ranks_array[2][2]; //num_ranks_array[port][dimm] - uint8_t stack_type[2][2]; - uint8_t dimm_type; - uint8_t lrdimm_rank_mult_mode; - uint8_t dram_gen = 0; - uint8_t rank_end = 0; - - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_GEN, &i_target, dram_gen); - if(rc) return rc; - - rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target, num_ranks_array); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_STACK_TYPE, &i_target, stack_type); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM, &i_target, num_master_ranks_array); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target, dimm_type); - if(rc) return rc; - - //Set up CCS Mode Reg for ZQ cal long and Init cal - rc = fapiGetScom(i_target, MEM_MBA01_CCS_MODEQ_0x030106A7, data_buffer_64); - if(rc) return rc; - - rc_num = rc_num | data_buffer_64.insert(stop_on_err_buffer_1, 0, 1, 0); - rc_num = rc_num | data_buffer_64.insert(resetn_buffer_1, 24, 1, 0); - if(rc_num) - { - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target, MEM_MBA01_CCS_MODEQ_0x030106A7, data_buffer_64); - if(rc) return rc; - - for(uint8_t dimm = 0; dimm < MAX_NUM_DIMM; dimm++) - { - start_rank=(4 * dimm); - - if ( (dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) && (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR3) ) - { - rc = FAPI_ATTR_GET(ATTR_LRDIMM_RANK_MULT_MODE, &i_target, lrdimm_rank_mult_mode); - if(rc) return rc; - - if ( num_ranks_array[i_port][dimm] == 8 && lrdimm_rank_mult_mode == 4) - { // For LRDIMM 8 Rank, RM=4, CS0 and CS1 to execute ZQ cal - rank_end = 2; - } - } - else if(stack_type[i_port][dimm] == ENUM_ATTR_EFF_STACK_TYPE_STACK_3DS) { - rank_end = num_master_ranks_array[i_port][dimm]; - } - else { - rank_end = num_ranks_array[i_port][dimm]; - } - - for(current_rank = start_rank; current_rank < start_rank + rank_end; current_rank++) { - FAPI_INF( "+++++++++++++++ Sending zqcal to port: %d rank: %d +++++++++++++++", i_port, current_rank); - rc_num = rc_num | csn_buffer_8.flushTo1(); - rc_num = rc_num | csn_buffer_8.clearBit(current_rank); - if(rc_num) - { - rc.setEcmdError(rc_num); - return rc; - } - - //Issue execute. - FAPI_INF( "+++++++++++++++ Execute CCS array on port: %d +++++++++++++++", i_port); - rc = mss_ccs_inst_arry_0(i_target, instruction_number, address_buffer_16, bank_buffer_8, activate_buffer_1, rasn_buffer_1, casn_buffer_1, wen_buffer_1, cke_buffer_8, csn_buffer_8, odt_buffer_8, test_buffer_4, i_port); - if(rc) return rc; //Error handling for mss_ccs_inst built into mss_funcs - rc = mss_ccs_inst_arry_1(i_target, instruction_number, num_idles_buffer_16, num_repeat_buffer_16, data_buffer_20, read_compare_buffer_1, rank_cal_buffer_3, ddr_cal_enable_buffer_1, ccs_end_buffer_1); - if(rc) return rc; //Error handling for mss_ccs_inst built into mss_funcs - rc = mss_ccs_set_end_bit(i_target,instruction_number); - if(rc) return rc; - rc = mss_execute_ccs_inst_array(i_target, NUM_POLL, 60); - instruction_number = 1; - if(rc) return rc; //Error handling for mss_ccs_inst built into mss_funcs - } - } -return rc; -} - diff --git a/src/usr/hwpf/hwp/dram_training/mss_funcs.H b/src/usr/hwpf/hwp/dram_training/mss_funcs.H deleted file mode 100644 index 2ea52798d..000000000 --- a/src/usr/hwpf/hwp/dram_training/mss_funcs.H +++ /dev/null @@ -1,266 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/dram_training/mss_funcs.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2012,2014 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: mss_funcs.H,v 1.16 2013/08/27 22:23:53 kcook Exp $ -/* File mss_funcs.H created by SLOAT JACOB D. (JAKE),2D3970 on Fri Apr 22 2011. */ - -//------------------------------------------------------------------------------ -// *! (C) Copyright International Business Machines Corp. 2007 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -//------------------------------------------------------------------------------ -// *! TITLE : mss_funcs.H -// *! DESCRIPTION : Tools for centaur procedures -// *! OWNER NAME : -// *! BACKUP NAME : -// #! ADDITIONAL COMMENTS : -// -// CCS related and general utility functions. - -//------------------------------------------------------------------------------ -// Don't forget to create CVS comments when you check in your changes! -//------------------------------------------------------------------------------ -// CHANGE HISTORY: -//------------------------------------------------------------------------------ -// Version:| Author: | Date: | Comment: -//---------|----------|---------|----------------------------------------------- -// 1.16 | kcook | 08/27/13| Removed LRDIMM functions to mss_lrdimm_funcs.H. Use with mss_funcs.C v1.33. -// 1.15 | kcook | 08/16/13| Added LRDIMM support. Use with mss_funcs.C v1.32. -// 1.14 | jdsloat | 04/09/13| Moved Address mirror mode sub function in from mss_draminit -// 1.13 | jsabrow | 11/19/12| added CCS data loader: mss_ccs_load_data_pattern -// 1.12 | 07/16/12 | bellows | added in Id tag -// 1.11 | 3/21/12 | divyakum| Added mss_execute_zq_cal function -// 1.10 | 2/14/12 | jdsloat | Comment section filled in, elimated unnecessary constant, added enums -// 1.9 | 2/08/12 | jdsloat | Target to Target& -// 1.8 | 2/02/12 | jdsloat | Added fapi:: to arguments in function prototypes -// 1.7 | 1/13/12 | jdsloat | Capatilization, cleaned up includes, address names, "mss_" prefix, argument prefix -// 1.6 | 1/6/12 | jdsloat | Added a function call -// 1.5 | 1/5/12 | jdsloat | Got rid of Globals -// 1.4 | 10/31/11 | jdsloat | CCS Update - goto_inst now assumed to be +1, CCS_fail fix, CCS_status fix -// 1.3 | 10/06/11 | jdsloat | argument data type fix -// 1.2 | 10/05/11 | jdsloat | Convert integers to ecmdDataBufferBase in CCS_INST_1, CCS_INST_2, CCS_MODE -// 1.1 | 10/04/11 | jdsloat | First drop of Centaur in FAPI dir -//---------|----------|---------|----------------------------------------------- -// 1.6 | 09/29/11 | jdsloat | global CCS counts, port added to calls, temp dimms defined as # -// 1.5 | 09/27/11 | jdsloat | Added port information. -// 1.4 | 09/22/11 | jdsloat | Full update to FAPI. Functional changes to match procedure. -// 1.3 | 09/13/11 | jdsloat | First attempt at FAPI upgrade - attributes still in ecmd -// 1.00 | 04/22/11 | jdsloat | First drop of Centaur - -#ifndef _MSS_FUNCS_H -#define _MSS_FUNCS_H - -//---------------------------------------------------------------------- -// Constants for CCS Operations -//---------------------------------------------------------------------- -const uint64_t CCS_INST_ARRY0_AB_REG0_0x03010615 = 0x03010615; -const uint64_t CCS_INST_ARRY1_AB_REG0_0x03010635 = 0x03010635; - -const uint64_t CCS_CNTLQ_AB_REG_0x030106A5 = 0x030106A5; -const uint64_t CCS_MODEQ_AB_REG_0x030106A7 = 0x030106A7; -const uint64_t CCS_STATQ_AB_REG_0x030106A6 = 0x030106A6; -const uint64_t MBA01_CALFIR_REG_0x03010402 = 0x03010402; - - -//---------------------------------------------------------------------- -// Enums for CCS Operations -//---------------------------------------------------------------------- - -enum mss_ccs_status_query_result -{ - MSS_STAT_QUERY_PASS = 1, - MSS_STAT_QUERY_IN_PROGRESS = 2, - MSS_STAT_QUERY_FAIL = 3 -}; - - -enum mss_ccs_data_pattern -{ - MSS_CCS_DATA_PATTERN_00 = 1, - MSS_CCS_DATA_PATTERN_0F = 2, - MSS_CCS_DATA_PATTERN_F0 = 3, - MSS_CCS_DATA_PATTERN_FF = 4 -}; - - -const bool MSS_CCS_START = 0; -const bool MSS_CCS_STOP = 1; - - -//---------------------------------------------------------------------- -// CCS FUNCS -//---------------------------------------------------------------------- - -//-------------------------------------------------------------- -// mss_ccs_inst_arry_0 -// Adding information to the CCS - 0 instruction array by index -// Target = centaur.mba -//-------------------------------------------------------------- -fapi::ReturnCode mss_ccs_inst_arry_0( fapi::Target& i_target, - uint32_t& io_instruction_number, - ecmdDataBufferBase i_address, - ecmdDataBufferBase i_bank, - ecmdDataBufferBase i_activate, - ecmdDataBufferBase i_rasn, - ecmdDataBufferBase i_casn, - ecmdDataBufferBase i_wen, - ecmdDataBufferBase i_cke, - ecmdDataBufferBase i_csn, - ecmdDataBufferBase i_odt, - ecmdDataBufferBase i_ddr_cal_type, - uint32_t i_port); - -//-------------------------------------------------------------- -// mss_ccs_inst_arry_1 -// Adding information to the CCS - 1 instruction array by index -// Target = centaur.mba -//-------------------------------------------------------------- -fapi::ReturnCode mss_ccs_inst_arry_1( fapi::Target& i_target, - uint32_t& io_instruction_number, - ecmdDataBufferBase i_num_idles, - ecmdDataBufferBase i_num_repeat, - ecmdDataBufferBase i_data, - ecmdDataBufferBase i_read_compare, - ecmdDataBufferBase i_rank_cal, - ecmdDataBufferBase i_ddr_cal_enable, - ecmdDataBufferBase i_ccs_end); - - -//--------------------------------------------------------------- -// mss_ccs_load_data_pattern -// load predefined pattern (enum) into specified array1 index -// Target = centaur.mba -//--------------------------------------------------------------- -fapi::ReturnCode mss_ccs_load_data_pattern( fapi::Target& i_target, - uint32_t io_instruction_number, - mss_ccs_data_pattern data_pattern); - - -//--------------------------------------------------------------- -// mss_ccs_load_data_pattern -// load specified pattern (20 bits) into specified array1 index -// Target = centaur.mba -//--------------------------------------------------------------- -fapi::ReturnCode mss_ccs_load_data_pattern( fapi::Target& i_target, - uint32_t io_instruction_number, - uint32_t data_pattern); - - -//----------------------------------------- -// mss_ccs_status_query -// Querying the status of the CCS -// Target = centaur.mba -//----------------------------------------- -fapi::ReturnCode mss_ccs_status_query( fapi::Target& i_target, - mss_ccs_status_query_result& io_status); - - -//----------------------------------------- -// mss_ccs_start_stop -// Issuing a start or stop of the CCS -// Target = centaur.mba -//----------------------------------------- -fapi::ReturnCode mss_ccs_start_stop( fapi::Target& i_target, - uint32_t i_start_stop); - -//---------------------------------------------- -// mss_ccs_mode -// Adding info the the Mode Register of the CCS -// Target = centaur.mba -//---------------------------------------------- -fapi::ReturnCode mss_ccs_mode( fapi::Target& i_target, - ecmdDataBufferBase i_stop_on_err, - ecmdDataBufferBase i_ue_disable, - ecmdDataBufferBase i_data_sel, - ecmdDataBufferBase i_pclk, - ecmdDataBufferBase i_nclk, - ecmdDataBufferBase i_cal_time_cnt, - ecmdDataBufferBase i_resetn, - ecmdDataBufferBase i_reset_recover, - ecmdDataBufferBase i_copy_spare_cke); - -//----------------------------------------- -// mss_ccs_fail_type -// Extracting the type of ccs fail -// Target = centaur.mba -//----------------------------------------- -fapi::ReturnCode mss_ccs_fail_type( fapi::Target& i_target); - - -//----------------------------------- -// mss_execute_ccs_inst_array -// Execute the CCS intruction array -// Target = centaur.mba -//----------------------------------- -fapi::ReturnCode mss_execute_ccs_inst_array( fapi::Target& i_target, - uint32_t i_num_poll, - uint32_t i_wait_timer); - -//------------------------------------------- -// mss_ccs_set_end_bit -// Setting the End location of the CCS array -// Target = centaur.mba -//------------------------------------------- -fapi::ReturnCode mss_ccs_set_end_bit( fapi::Target& i_target, - uint32_t i_instruction_number); - -//-------------------------------------------------------- -// mss_rcd_parity_check -// Checking the Parity Error Bits associated with the RCD -// Target = centaur.mba -//-------------------------------------------------------- -fapi::ReturnCode mss_rcd_parity_check(fapi::Target& i_target, - uint32_t i_port); - -//----------------------------------------- -// mss_reverse_32bits, mss_reverse_8bits -// Reversing bit order of 8 or 32 bit uint -//----------------------------------------- -uint32_t mss_reverse_32bits( uint32_t i_x); -uint8_t mss_reverse_8bits(uint8_t i_number); - - -//----------------------------------------- -// mss_execute_zq_cal -// execute init ZQ Cal on given target and port -// Target = centaur.mba -//----------------------------------------- -fapi::ReturnCode mss_execute_zq_cal(fapi::Target& i_target, - uint8_t i_port); - - -//----------------------------------------- -// mss_address_mirror_swizzle -// swizzle the address bus and bank address bus for address mirror mode -// Target = centaur.mba -//----------------------------------------- -fapi::ReturnCode mss_address_mirror_swizzle(fapi::Target& i_target, - uint32_t i_port, - uint32_t i_dimm, - uint32_t i_rank, - ecmdDataBufferBase& io_address, - ecmdDataBufferBase& io_bank); - -#endif /* _MSS_FUNCS_H */ - diff --git a/src/usr/hwpf/hwp/dram_training/mss_lrdimm_funcs/mss_lrdimm_ddr4_funcs.H b/src/usr/hwpf/hwp/dram_training/mss_lrdimm_funcs/mss_lrdimm_ddr4_funcs.H deleted file mode 100644 index 8025af461..000000000 --- a/src/usr/hwpf/hwp/dram_training/mss_lrdimm_funcs/mss_lrdimm_ddr4_funcs.H +++ /dev/null @@ -1,218 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/dram_training/mss_lrdimm_funcs/mss_lrdimm_ddr4_funcs.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2014 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: mss_lrdimm_ddr4_funcs.H,v 1.1 2014/03/14 16:05:51 kcook Exp $ -//------------------------------------------------------------------------------ -// *! (C) Copyright International Business Machines Corp. 2013 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -//------------------------------------------------------------------------------ -// *! TITLE : mss_lrdimm_funcs.H -// *! DESCRIPTION : Tools for lrdimm centaur procedures -// *! OWNER NAME : KCOOK -// *! BACKUP NAME : MWUU -// #! ADDITIONAL COMMENTS : -// -// CCS related and general utility functions. -// Provides functions for mss_eff_conifg, mss_draminit, and mss_draminit_training -// for DDR4 LRDIMM. - -//------------------------------------------------------------------------------ -// Don't forget to create CVS comments when you check in your changes! -//------------------------------------------------------------------------------ -// CHANGE HISTORY: -//------------------------------------------------------------------------------ -// Version:| Author: | Date: | Comment: -//---------|----------|---------|----------------------------------------------- -// 1.1 | 03/14/14 | kcook | First drop of Centaur - -#ifndef _MSS_LRDIMM_DDR4_FUNCS_H -#define _MSS_LRDIMM_DDR4_FUNCS_H - -//#define LRDIMM 1 - -//---------------------------------------------------------------------- -// Constants -//---------------------------------------------------------------------- -const uint64_t MAINT0_MBA_MAINT_BUFF0_DATA_ECC0_0x0301065d = 0x0301065d; -const uint64_t DPHY23_DDRPHY_DP18_DATA_BIT_ENABLE1_P0_0_0x800000010301183F = 0x800000010301183Full; -const uint64_t DPHY23_DDRPHY_DP18_DATA_BIT_ENABLE1_P0_1_0x800004010301183F = 0x800004010301183Full; -const uint64_t DPHY23_DDRPHY_DP18_DATA_BIT_ENABLE1_P0_2_0x800008010301183F = 0x800008010301183Full; -const uint64_t DPHY23_DDRPHY_DP18_DATA_BIT_ENABLE1_P0_3_0x80000C010301183F = 0x80000C010301183Full; -const uint64_t DPHY23_DDRPHY_DP18_DATA_BIT_ENABLE1_P0_4_0x800010010301183F = 0x800010010301183Full; -const uint64_t DPHY23_DDRPHY_DP18_DATA_BIT_ENABLE1_P1_0_0x800100010301183F = 0x800100010301183Full; -const uint64_t DPHY23_DDRPHY_DP18_DATA_BIT_ENABLE1_P1_1_0x800104010301183F = 0x800104010301183Full; -const uint64_t DPHY23_DDRPHY_DP18_DATA_BIT_ENABLE1_P1_2_0x800108010301183F = 0x800108010301183Full; -const uint64_t DPHY23_DDRPHY_DP18_DATA_BIT_ENABLE1_P1_3_0x80010C010301183F = 0x80010C010301183Full; -const uint64_t DPHY23_DDRPHY_DP18_DATA_BIT_ENABLE1_P1_4_0x800110010301183F = 0x800110010301183Full; -//---------------------------------------------------------------------- -// Enums -//---------------------------------------------------------------------- -//---------------------------------------------------------------------- -// LRDIMM FUNCS -//---------------------------------------------------------------------- -//-------------------------------------------------------------- -// mss_create_db_ddr4 -// Determines DB control words and stores in attribute -// Target = centaur.mba -//-------------------------------------------------------------- -fapi::ReturnCode mss_create_db_ddr4( const fapi::Target& i_target_mba); - -//-------------------------------------------------------------- -// mss_lrdimm_ddr4_term_atts -// eff config termination rewrite odts -// Target = centaur.mba -//-------------------------------------------------------------- -fapi::ReturnCode mss_lrdimm_ddr4_term_atts( const fapi::Target& i_target_mba); - -//-------------------------------------------------------------- -// mss_lrdimm_ddr4_db_load -// Writes initial DB control words to DB from attributes -// Target = centaur.mba -//-------------------------------------------------------------- -fapi::ReturnCode mss_lrdimm_ddr4_db_load( fapi::Target& i_target, - uint32_t i_port_number, - uint32_t& io_ccs_inst_cnt); - -//-------------------------------------------------------------- -// mss_bcw_write -// Writes single BCW to DB -// Target = centaur.mba -//-------------------------------------------------------------- -fapi::ReturnCode mss_bcw_write( fapi::Target& i_target_mba, uint32_t i_port_number, - uint8_t bcw_width, uint8_t bcw, uint8_t bcw_value, - uint32_t& io_ccs_inst_cnt); - -//-------------------------------------------------------------- -// mss_dram_write_leveling -// Executes DB-DRAM write leveing -// Target = centaur.mba -//-------------------------------------------------------------- -fapi::ReturnCode mss_dram_write_leveling( fapi::Target& i_target_mba, uint32_t i_port_number); - -//-------------------------------------------------------------- -// mss_store_db_delay -// Used at end of training steps to write found delay values to DB control word registers -// Target = centaur.mba -//-------------------------------------------------------------- -fapi::ReturnCode mss_store_db_delay(fapi::Target& i_target_mba, uint8_t i_mbaPosition, uint32_t i_port_number, - uint32_t i_dimm_number, uint32_t i_rank_number, - uint8_t i_cw_reg, uint8_t i_nibble_delay[], - uint32_t& io_ccs_inst_cnt, uint8_t i_split_fine=0); -//-------------------------------------------------------------- -// mss_step_delay_cw0 -// Used in mxd training to step DB CW delay register and query data bus -// Target = centaur.mba -//-------------------------------------------------------------- -fapi::ReturnCode mss_step_delay_cw0(fapi::Target& i_target_mba, uint8_t i_port_number, uint8_t i_dimm_number, uint8_t i_rank_number, - uint8_t i_num_wr_rd, uint8_t o_nibble_delay[], uint8_t i_type, uint32_t& io_ccs_inst_cnt); - -//-------------------------------------------------------------- -// mss_step_delay_cw -// Used in dram_write_leveling and mrep_training to step DB CW delay registers and query data bus -// Target = centaur.mba -//-------------------------------------------------------------- -fapi::ReturnCode mss_step_delay_cw(fapi::Target& i_target_mba, uint32_t i_port_number, uint32_t i_dimm_number, uint32_t i_rank_number, - uint8_t i_cw_reg, uint8_t i_num_reads, uint8_t o_nibble_delay[], - uint32_t& io_ccs_inst_cnt); - -//-------------------------------------------------------------- -// mss_mr1_wr_lvl -// Send MR1 command to set DRAM to write leveling mode or normal mode -// Target = centaur.mba -//-------------------------------------------------------------- -fapi::ReturnCode mss_mr1_wr_lvl(fapi::Target& i_target_mba, uint32_t i_port_number, - uint8_t wr_lvl, uint32_t& io_ccs_inst_cnt); - - - -//-------------------------------------------------------------- -// mss_mrep_training -// Conducts MDQ Receive Enable Phase Training between DB and DRAM -// Target = centaur.mba -//-------------------------------------------------------------- -fapi::ReturnCode mss_mrep_training( fapi::Target& i_target_mba, uint32_t i_port_number); -//-------------------------------------------------------------- -// mss_mxd_training -// Conducts MRD or MWD coarse, normal, or find training. Still in development -// Target = centaur.mba -//-------------------------------------------------------------- -fapi::ReturnCode mss_mxd_training( fapi::Target& i_target_mba, uint8_t i_port_number, uint8_t i_type); -//-------------------------------------------------------------- -// mss_add_rdmpr -// Adds read command without activate to ccs -// Target = centaur.mba -//-------------------------------------------------------------- -fapi::ReturnCode mss_add_rdmpr( fapi::Target& i_target_mba, - uint32_t i_port_number, uint32_t dimm_number, uint32_t rank_number, - uint32_t& io_ccs_inst_cnt); - -//-------------------------------------------------------------- -// mss_mpr_operation -// Sets MR3 command to MPR data flow or normal data flow -// Target = centaur.mba -//-------------------------------------------------------------- -fapi::ReturnCode mss_mpr_operation( fapi::Target& i_target_mba, uint32_t i_port_number, - uint8_t mpr_op, - uint32_t& io_ccs_inst_cnt); - -//-------------------------------------------------------------- -// mss_force_fifo_capture -// Sets force_fifo_capture bit in rd_dia_config5 registers to Force DQ capture or normal operation -// Target = centaur.mba -//-------------------------------------------------------------- -fapi::ReturnCode mss_force_fifo_capture(fapi::Target& i_target_centaur, uint8_t i_mbaPosition, - uint32_t i_port_number, - uint32_t force_fifo); - -//-------------------------------------------------------------- -// mss_data_bit_set -// Sets single DQ byte or all DQ bytes to 0 or 1 through DATA_BIT_DIR registers. -// Used with DFT_FORCE_OUTPUT during PBA mode -// Target = centaur.mba -//-------------------------------------------------------------- -fapi::ReturnCode mss_data_bit_set(fapi::Target& i_target_mba, uint8_t i_mbaPosition, - uint32_t i_port_number, - uint8_t byte, uint8_t dq_value); - -//-------------------------------------------------------------- -// mss_dft_force_outputs -// Sets DFT_FORCE_OUTPUTS bit to 0 or 1 to control DQ bus during PBA mode -// Target = centaur.mba -//-------------------------------------------------------------- -fapi::ReturnCode mss_dft_force_outputs(fapi::Target& i_target_centaur, uint8_t i_mbaPosition, - uint32_t i_port_number, - uint32_t force_outputs); - -//-------------------------------------------------------------- - - - - - - - - -#endif /* _MSS_LRDIMM_DDR4_FUNCS_H */ - diff --git a/src/usr/hwpf/hwp/dram_training/mss_lrdimm_funcs/mss_lrdimm_funcs.C b/src/usr/hwpf/hwp/dram_training/mss_lrdimm_funcs/mss_lrdimm_funcs.C deleted file mode 100644 index 499b1e867..000000000 --- a/src/usr/hwpf/hwp/dram_training/mss_lrdimm_funcs/mss_lrdimm_funcs.C +++ /dev/null @@ -1,1995 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/dram_training/mss_lrdimm_funcs/mss_lrdimm_funcs.C $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2013,2015 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: mss_lrdimm_funcs.C,v 1.10 2015/03/16 21:37:44 jdsloat Exp $ -//------------------------------------------------------------------------------ -// *! (C) Copyright International Business Machines Corp. 2013 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -//------------------------------------------------------------------------------ -// *! TITLE : mss_lrdimm_funcs.C -// *! DESCRIPTION : Tools for LRDIMM centaur procedures -// *! OWNER NAME : kcook@us.ibm.com -// *! BACKUP NAME : mwuu@us.ibm.com -// #! ADDITIONAL COMMENTS : -// - -//------------------------------------------------------------------------------ -// Don't forget to create CVS comments when you check in your changes! -//------------------------------------------------------------------------------ -// CHANGE HISTORY: -//------------------------------------------------------------------------------ -// Version:| Author: | Date: | Comment: -//---------|----------|---------|----------------------------------------------- -// 1.10 | jdsloat |16-MAR-15| Fixed 2 declarations of ecmddatabuffer to ecmddatabufferbase -// 1.8 | kcook |13-FEB-14| More FW updates. -// 1.7 | kcook |12-FEB-14| Updated HWP_ERROR per RAS review to be used with memory_mss_lrdimm_funcs.xml -// 1.6 | bellows |02-JAN-14| VPD attribute removal -// 1.5 | kcook |12/03/13 | Updated VPD attributes. -// 1.4 | bellows |09/16/13 | Hostboot compile update -// 1.3 | bellows |09/16/13 | Added ID tag. -// 1.2 | kcook |09/13/13 | Updated define FAPI_LRDIMM token. -// 1.1 | kcook |08/27/13 | First drop of Centaur - -//---------------------------------------------------------------------- -// Includes -//---------------------------------------------------------------------- - -#include <fapi.H> -#include <mss_lrdimm_funcs.H> -#include <mss_funcs.H> - -#ifdef FAPI_LRDIMM -const uint8_t MAX_NUM_DIMMS = 2; -const uint8_t MAX_NUM_LR_RANKS = 8; -const uint8_t MRS1_BA = 1; -const uint8_t PORT_SIZE = 2; -const uint8_t DIMM_SIZE = 2; -const uint8_t RANK_SIZE = 4; -const uint32_t MSS_EFF_VALID = 255; - - -using namespace fapi; - -fapi::ReturnCode mss_lrdimm_rcd_load( fapi::Target& i_target, uint32_t port_number, uint32_t& ccs_inst_cnt) -{ - ReturnCode rc; - uint8_t num_drops_per_port; - // LRDIMM - uint8_t func1_rcd_number_array_u8[12] = {7,0,1,2,8,9,10,11,12,13,14,15}; - uint8_t func2_rcd_number_array_u8[8] = {7,0,1,2,3,4,5,6}; - uint8_t func3_rcd_number_array_u8[7] = {7,0,1,2,6,8,9}; - uint8_t funcODT_rcd_number_array_u8[3] = {7,10,11}; - uint8_t *p_func_num_arr; - ecmdDataBufferBase data_buff_rcd_word(64); - uint64_t func_rcd_control_word[2]; - uint8_t num_ranks_array[2][2]; //[port][dimm] - uint8_t dimm_number; - uint8_t rank_number; - uint64_t spd_func_words; - uint64_t att_spd_func_words[2][2]; - uint8_t num_rows; - uint8_t num_cols; - uint8_t dram_width; - uint64_t l_func1_mask = 0x00000000F00FFFFFLL; - uint8_t l_rcd_cntl_word_0; - uint8_t l_rcd_cntl_word_1; - uint8_t l_rcd_cntl_word_2; - uint8_t l_rcd_cntl_word_3; - uint8_t l_rcd_cntl_word_4; - uint8_t l_rcd_cntl_word_5; - uint8_t l_rcd_cntl_word_6; - uint8_t l_rcd_cntl_word_7; - uint8_t l_rcd_cntl_word_8; - uint8_t l_rcd_cntl_word_9; - uint8_t l_rcd_cntl_word_10; - uint8_t l_rcd_cntl_word_11; - uint8_t dimm_func_vec; - - rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target, num_ranks_array); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_LRDIMM_ADDITIONAL_CNTL_WORDS, &i_target, att_spd_func_words); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_ROWS, &i_target, num_rows); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_COLS, &i_target, num_cols); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target, dram_width); - if (rc) return rc; - rc=FAPI_ATTR_GET(ATTR_MSS_EFF_DIMM_FUNCTIONAL_VECTOR, &i_target, dimm_func_vec); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_NUM_DROPS_PER_PORT, &i_target, num_drops_per_port); - if(rc) return rc; - - - // Fucntion 1 - for (dimm_number = 0;dimm_number < MAX_NUM_DIMMS; dimm_number++) - { - - if ( num_ranks_array[port_number][dimm_number] != 0 ) - { - //F[1]RC0 IBT settings for DCS pins - l_rcd_cntl_word_0 = 0; // IBT DCS[1:0] 100 Ohm, DCS[3:2] IBT as defined DCS[1:0] - l_rcd_cntl_word_1 = 0; //IBT DCKE 100 Ohm - l_rcd_cntl_word_2 = 0; //IBT DODT[1:0] 100 Ohm - - l_rcd_cntl_word_7 = 1; //Function select - l_rcd_cntl_word_9 = 0; //Refresh stagger = 0clocks - l_rcd_cntl_word_10 = 0; //Refresh stagger limit = unimited - - data_buff_rcd_word.clearBit(0,64); - data_buff_rcd_word.insertFromRight(&l_rcd_cntl_word_0, 0,4); - data_buff_rcd_word.insertFromRight(&l_rcd_cntl_word_1, 4,4); - data_buff_rcd_word.insertFromRight(&l_rcd_cntl_word_2, 8,4); - data_buff_rcd_word.insertFromRight(&l_rcd_cntl_word_7, 28,4); - data_buff_rcd_word.insertFromRight(&l_rcd_cntl_word_9, 36,4); - data_buff_rcd_word.insertFromRight(&l_rcd_cntl_word_10, 40,4); - - func_rcd_control_word[dimm_number] = data_buff_rcd_word.getDoubleWord(0); - if(rc) return rc; - spd_func_words = att_spd_func_words[port_number][dimm_number] & l_func1_mask; // SPD for F[1]RC8,11-15 - func_rcd_control_word[dimm_number] = func_rcd_control_word[dimm_number] | spd_func_words; - } - } - - FAPI_INF("SELECTING FUNCTION %d", l_rcd_cntl_word_7); - p_func_num_arr = func1_rcd_number_array_u8; - rc = mss_spec_rcd_load(i_target, port_number, p_func_num_arr, - sizeof(func1_rcd_number_array_u8)/sizeof(func1_rcd_number_array_u8[0]), - func_rcd_control_word , ccs_inst_cnt,1); - if(rc) - { - FAPI_ERR(" spec_rcd_load Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator()); - return rc; - } - - // Function 2 - for (dimm_number = 0;dimm_number < MAX_NUM_DIMMS; dimm_number++) - { - if ( num_ranks_array[port_number][dimm_number] != 0 ) - { - l_rcd_cntl_word_0 = 0; // Transparent mode - l_rcd_cntl_word_1 = 0; // Reset control - l_rcd_cntl_word_2 = 0; // SMBus access control - l_rcd_cntl_word_3 = 8; // Training control & Errorout enable driven Low when Training - l_rcd_cntl_word_4 = 0; // MEMBIST Rank control - - //RC5 DRAM row & column addressing - if ( num_rows == 13 ) - { - if ( num_cols == 10 ) - { - l_rcd_cntl_word_5 = 0; - } - else if ( num_cols == 11 ) - { - l_rcd_cntl_word_5 = 1; - } - else if ( num_cols == 12 ) - { - l_rcd_cntl_word_5 = 2; - } - else if ( num_cols == 3 ) - { - l_rcd_cntl_word_5 = 3; - } - } - else if ( num_rows == 14 ) - { - if ( num_cols == 10 ) - { - l_rcd_cntl_word_5 = 4; - } - else if ( num_cols == 11 ) - { - l_rcd_cntl_word_5 = 5; - } - else if ( num_cols == 12 ) - { - l_rcd_cntl_word_5 = 6; - } - else if ( num_cols == 3 ) - { - l_rcd_cntl_word_5 = 7; - } - } - else if ( num_rows == 15 ) - { - if ( num_cols == 10 ) - { - l_rcd_cntl_word_5 = 8; - } - else if ( num_cols == 11 ) - { - l_rcd_cntl_word_5 = 9; - } - else if ( num_cols == 12 ) - { - l_rcd_cntl_word_5 = 10; - } - else if ( num_cols == 3 ) - { - l_rcd_cntl_word_5 = 11; - } - } - else if ( num_rows == 16 ) - { - if ( num_cols == 10 ) - { - l_rcd_cntl_word_5 = 12; - } - else if ( num_cols == 11 ) - { - l_rcd_cntl_word_5 = 13; - } - else if ( num_cols == 12 ) - { - l_rcd_cntl_word_5 = 14; - } - else if ( num_cols == 3 ) - { - l_rcd_cntl_word_5 = 15; - } - } - - l_rcd_cntl_word_6 = 0; // MEMBIST control - l_rcd_cntl_word_7 = 2; //Function select - - data_buff_rcd_word.clearBit(0,64); - data_buff_rcd_word.insertFromRight(&l_rcd_cntl_word_0, 0,4); - data_buff_rcd_word.insertFromRight(&l_rcd_cntl_word_1, 4,4); - data_buff_rcd_word.insertFromRight(&l_rcd_cntl_word_2, 8,4); - data_buff_rcd_word.insertFromRight(&l_rcd_cntl_word_3,12,4); - data_buff_rcd_word.insertFromRight(&l_rcd_cntl_word_4,16,4); - data_buff_rcd_word.insertFromRight(&l_rcd_cntl_word_5,20,4); - data_buff_rcd_word.insertFromRight(&l_rcd_cntl_word_6,24,4); - data_buff_rcd_word.insertFromRight(&l_rcd_cntl_word_7, 28,4); - - func_rcd_control_word[dimm_number] = data_buff_rcd_word.getDoubleWord(0); - - //check for rc but not seeing where rc is set in this loop/if statment - if(rc) return rc; - } - } - - - FAPI_INF("SELECTING FUNCTION %d", l_rcd_cntl_word_7); - p_func_num_arr = func2_rcd_number_array_u8; - rc = mss_spec_rcd_load(i_target, port_number, p_func_num_arr, - sizeof(func2_rcd_number_array_u8)/sizeof(func2_rcd_number_array_u8[0]), - func_rcd_control_word , ccs_inst_cnt,1); - if(rc) - { - FAPI_ERR(" spec_rcd_load Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator()); - return rc; - } - - // Function 3 - for (dimm_number = 0;dimm_number < MAX_NUM_DIMMS; dimm_number++) - { - if ( num_ranks_array[port_number][dimm_number] != 0 ) - { - data_buff_rcd_word.setDoubleWord(0, att_spd_func_words[port_number][dimm_number]); - data_buff_rcd_word.extractToRight(&l_rcd_cntl_word_8 , 40, 4); // f[3]RC8 is in space RCD10 - data_buff_rcd_word.extractToRight(&l_rcd_cntl_word_9 , 36, 4); - - //F[3]RC0 connector interface DQ RTT_Nom Termination, TDQS control - if ( num_drops_per_port == ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL ) - { // Single rank, dual drop - if ( dram_width == 8 ) - { - l_rcd_cntl_word_0 = 9; // RTT_Nom 60 Ohm, TDQS enabled - } - else - { - l_rcd_cntl_word_0 = 1; // RTT_NOM 60 Ohm, TDQS disabled - } - } - else - { // Single rank, Single drop - if ( dram_width == 8 ) - { - l_rcd_cntl_word_0 = 9; // RTT_Nom 60 Ohm, TDQS enabled - } - else - { - l_rcd_cntl_word_0 = 1; // RTT_NOM 60 Ohm, TDQS disabled - } - } - - //F[3]RC1 connector interface DQ RTT_WR termination & Reference voltage - if ( num_drops_per_port == ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL ) - { // Single rank, dual drop - l_rcd_cntl_word_1 = 2; // RTT_WR 120 Ohm , VrefDQ input pin - l_rcd_cntl_word_2 = 1; // Connecter interface DQ/DQS output driver imp 34 Ohm, DQ/DQS drivers enabled - } - else - { // Single rank, Single drop - l_rcd_cntl_word_1 = 0; // RTT_WR disabled, VrefDQ input pin - l_rcd_cntl_word_2 = 1; // Connecter interface DQ/DQS output driver imp 34 Ohm, DQ/DQS drivers enabled - } - - FAPI_INF("Using ATTR_EFF_SCHMOO_TEST_VALID for dq LRDIMM timing mode"); - rc=FAPI_ATTR_GET(ATTR_EFF_SCHMOO_TEST_VALID, &i_target, l_rcd_cntl_word_6); - - l_rcd_cntl_word_7 = 3; //Function select - - data_buff_rcd_word.clearBit(0,64); - data_buff_rcd_word.insertFromRight(&l_rcd_cntl_word_0, 0,4); - data_buff_rcd_word.insertFromRight(&l_rcd_cntl_word_1, 4,4); - data_buff_rcd_word.insertFromRight(&l_rcd_cntl_word_2, 8,4); - data_buff_rcd_word.insertFromRight(&l_rcd_cntl_word_6,24,4); - data_buff_rcd_word.insertFromRight(&l_rcd_cntl_word_7, 28,4); - data_buff_rcd_word.insertFromRight(&l_rcd_cntl_word_8,32,4); - data_buff_rcd_word.insertFromRight(&l_rcd_cntl_word_9, 36,4); - - func_rcd_control_word[dimm_number] = data_buff_rcd_word.getDoubleWord(0); - //why check rc here and not at the FAPI_ATTR_GET line - if(rc) return rc; - } - } - - FAPI_INF("SELECTING FUNCTION %d", l_rcd_cntl_word_7); - p_func_num_arr = func3_rcd_number_array_u8; - rc = mss_spec_rcd_load(i_target, port_number, p_func_num_arr, - sizeof(func3_rcd_number_array_u8)/sizeof(func3_rcd_number_array_u8[0]), - func_rcd_control_word , ccs_inst_cnt,1); - if(rc) - { - FAPI_ERR(" spec_rcd_load Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator()); - return rc; - } - - for ( rank_number = 0; rank_number < MAX_NUM_LR_RANKS; rank_number++ ) - { - for (dimm_number = 0;dimm_number < MAX_NUM_DIMMS; dimm_number++) - { - if ( num_ranks_array[port_number][dimm_number] != 0 ) - { - data_buff_rcd_word.setDoubleWord(0, att_spd_func_words[port_number][dimm_number]); - data_buff_rcd_word.extractToRight(&l_rcd_cntl_word_10 , rank_number/2*8, 4); // RC10 is in space RCD0/2/4/6 - data_buff_rcd_word.extractToRight(&l_rcd_cntl_word_11 , rank_number/2*8+4, 4); // RC11 is in space RCD1/3/5/7 - - l_rcd_cntl_word_7 = rank_number + 3; // Function word select 3:10 for Ranks 0-7 - - data_buff_rcd_word.clearBit(0,64); - data_buff_rcd_word.insertFromRight(&l_rcd_cntl_word_7, 28,4); - data_buff_rcd_word.insertFromRight(&l_rcd_cntl_word_10,40,4); - data_buff_rcd_word.insertFromRight(&l_rcd_cntl_word_11,44,4); - - func_rcd_control_word[dimm_number] = data_buff_rcd_word.getDoubleWord(0); - //not sure why the rc check is here since there are no rc calls - if(rc) return rc; - } - } - - FAPI_INF("SELECTING FUNCTION %d", l_rcd_cntl_word_7); - p_func_num_arr = funcODT_rcd_number_array_u8; - rc = mss_spec_rcd_load(i_target, port_number, p_func_num_arr, - sizeof(funcODT_rcd_number_array_u8)/sizeof(funcODT_rcd_number_array_u8[0]), - func_rcd_control_word , ccs_inst_cnt,1); - if(rc) - { - FAPI_ERR(" spec_rcd_load Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator()); - return rc; - } - } // end rank loop - - // Function 13 - l_rcd_cntl_word_7 = 13; - FAPI_INF("SELECTING FUNCTION %d", l_rcd_cntl_word_7); - - uint8_t Rx_MR1_2_DATA[2][2]; - rc=FAPI_ATTR_GET(ATTR_LRDIMM_MR12_REG, &i_target, Rx_MR1_2_DATA); - if(rc) return rc; - - uint8_t rcw = 7; - uint64_t rcd0_15[2] = { 0x0000000D00000000ll, // select FN 13 dimm0 - 0x0000000D00000000ll }; // " dimm1 - - // set FN 13 via RC 7 - rc = mss_spec_rcd_load( i_target, port_number, &rcw, 1, rcd0_15, ccs_inst_cnt,1); - if(rc) - { - FAPI_ERR(" spec_rcd_load Failed rc = 0x%08X (creator = %d)", - uint32_t(rc), rc.getCreator()); - return rc; - } - - uint8_t func13_rcd_number_array_size = 4; - uint8_t func13_rcd_number_array_u8[4] = { 10, 11, 14, 15 }; - p_func_num_arr = func13_rcd_number_array_u8; - - data_buff_rcd_word.clearBit(0,64); - data_buff_rcd_word.insertFromRight(&l_rcd_cntl_word_7, 28,4); // select F13 - - const uint8_t num_ecw = 11; // number of external funcs - uint8_t R2_7_MR1_2_DATA[2][2]; - R2_7_MR1_2_DATA[port_number][0] = Rx_MR1_2_DATA[port_number][0] & 0xE3; // disable RTT_NOM on ranks 2:7 - R2_7_MR1_2_DATA[port_number][1] = Rx_MR1_2_DATA[port_number][1] & 0xE3; // disable RTT_NOM on ranks 2:7 - - - // extended control word addr, data - uint8_t ext_funcs[MAX_NUM_DIMMS][num_ecw][2] = { - { - {0xAC, 0x00}, // MRS_CTRL = 0xAC; snoop/forward/store - // MRx_SNOOP = 0xC8-CF MR(0:3) MR to DRAM 0xC8/C9-CE/CF - {0xC8, 0x00}, // MR0_SNOOP(0:7) = 0xC8 MR0 to DRAM - {0xC9, 0x00}, // MR0_SNOOP(8:15) = 0xC9; MR0 to DRAM - // Rx_MR1_2 = 0xB8-BF; R(0:7) ranks, RTT_WR, RTT_NOM, D_IMP - {0xB8, Rx_MR1_2_DATA[port_number][0]}, // rank 0 - {0xB9, Rx_MR1_2_DATA[port_number][0]}, // rank 1 - {0xBA, R2_7_MR1_2_DATA[port_number][0]}, // rank 2 - {0xBB, R2_7_MR1_2_DATA[port_number][0]}, // rank 3 - {0xBC, R2_7_MR1_2_DATA[port_number][0]}, // rank 4 - {0xBD, R2_7_MR1_2_DATA[port_number][0]}, // rank 5 - {0xBE, R2_7_MR1_2_DATA[port_number][0]}, // rank 6 - {0xBF, R2_7_MR1_2_DATA[port_number][0]} // rank 7 - }, - { - {0xAC, 0x00}, // MRS_CTRL = 0xAC; snoop/forward/store - // MRx_SNOOP = 0xC8-CF MR(0:3) MR to DRAM 0xC8/C9-CE/CF - {0xC8, 0x00}, // MR0_SNOOP(0:7) = 0xC8 MR0 to DRAM - {0xC9, 0x00}, // MR0_SNOOP(8:15) = 0xC9; MR0 to DRAM - // Rx_MR1_2 = 0xB8-BF; R(0:7) ranks, RTT_WR, RTT_NOM, D_IMP - {0xB8, Rx_MR1_2_DATA[port_number][1]}, // rank 0 - {0xB9, Rx_MR1_2_DATA[port_number][1]}, // rank 1 - {0xBA, R2_7_MR1_2_DATA[port_number][1]}, // rank 2 - {0xBB, R2_7_MR1_2_DATA[port_number][1]}, // rank 3 - {0xBC, R2_7_MR1_2_DATA[port_number][1]}, // rank 4 - {0xBD, R2_7_MR1_2_DATA[port_number][1]}, // rank 5 - {0xBE, R2_7_MR1_2_DATA[port_number][1]}, // rank 6 - {0xBF, R2_7_MR1_2_DATA[port_number][1]} // rank 7 - } - }; - for (uint8_t i=0; i < num_ecw; i++) - { - // set func_rcd_control_word[dimm_number] - for (dimm_number = 0;dimm_number < MAX_NUM_DIMMS; dimm_number++) - { - if ( num_ranks_array[port_number][dimm_number] != 0 ) - { - // load address - data_buff_rcd_word.insertFromRight(ext_funcs[dimm_number][i][0],40,4); // lsb address - data_buff_rcd_word.insert(ext_funcs[dimm_number][i][0],44,4); // msb address - // load data - data_buff_rcd_word.insertFromRight(ext_funcs[dimm_number][i][1], 56,4); // lsb data - data_buff_rcd_word.insert(ext_funcs[dimm_number][i][1], 60,4); // msb data - - func_rcd_control_word[dimm_number] = data_buff_rcd_word.getDoubleWord(0); - - //not sure where the rc call is made - if(rc) return rc; - } // end if has ranks - } // end dimm loop - - - // load CCS with F13 RC 10:11, 14:15 - rc = mss_spec_rcd_load( i_target, port_number, p_func_num_arr, func13_rcd_number_array_size, - func_rcd_control_word , ccs_inst_cnt,1); - if(rc) - { - FAPI_ERR(" spec_rcd_load Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator()); - return rc; - } - } // end # extended control words to write - // end Function 13 - - // set FN 0 via RC 7 - rcd0_15[0] = 0; - rcd0_15[1] = 0; - rc = mss_spec_rcd_load( i_target, port_number, &rcw, 1, rcd0_15, ccs_inst_cnt,1); - if(rc) - { - FAPI_ERR(" spec_rcd_load Failed rc = 0x%08X (creator = %d)", - uint32_t(rc), rc.getCreator()); - return rc; - } - - // force execute of remaining rcd !! not necessary??? !! - // Execute the contents of CCS array - if (ccs_inst_cnt > 0) - { - // Set the End bit on the last CCS Instruction - rc = mss_ccs_set_end_bit( i_target, ccs_inst_cnt-1); - if(rc) - { - FAPI_ERR("CCS_SET_END_BIT FAILED rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator()); - return rc; - } - - rc = mss_execute_ccs_inst_array(i_target, 10, 10); - if(rc) - { - FAPI_ERR(" EXECUTE_CCS_INST_ARRAY FAILED rc = 0x%08X (creator = %d)", - uint32_t(rc), rc.getCreator()); - return rc; - } - - ccs_inst_cnt = 0; - } - // end force execute of rcd - - - return rc; - -} - -fapi::ReturnCode mss_lrdimm_mrs_load( fapi::Target& i_target , uint32_t i_port_number,uint32_t dimm_number, uint32_t& io_ccs_inst_cnt) -{ - // For LRDIMM Set Rtt_nom, rtt_wr, driver impedance for R0 and R1 - // turn off MRS broadcast - ReturnCode rc; - ReturnCode rc_buff; - uint32_t rc_num = 0; - ecmdDataBufferBase csn_8(8); - rc_num = rc_num | csn_8.setBit(0,8); - ecmdDataBufferBase address_16(16); - ecmdDataBufferBase bank_3(3); - ecmdDataBufferBase activate_1(1); - ecmdDataBufferBase rasn_1(1); - rc_num = rc_num | rasn_1.clearBit(0); - ecmdDataBufferBase casn_1(1); - rc_num = rc_num | casn_1.clearBit(0); - ecmdDataBufferBase wen_1(1); - rc_num = rc_num | wen_1.clearBit(0); - ecmdDataBufferBase cke_4(4); - rc_num = rc_num | cke_4.setBit(0,4); - ecmdDataBufferBase odt_4(4); - rc_num = rc_num | odt_4.setBit(0,4); - ecmdDataBufferBase ddr_cal_type_4(4); - ecmdDataBufferBase csn_setup_8(8); - rc_num = rc_num | csn_setup_8.setBit(0,8); - - ecmdDataBufferBase num_idles_16(16); - rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 400, 0, 16); - ecmdDataBufferBase num_idles_setup_16(16); - rc_num = rc_num | num_idles_setup_16.insertFromRight((uint32_t) 400, 0, 16); - ecmdDataBufferBase num_repeat_16(16); - ecmdDataBufferBase data_20(20); - ecmdDataBufferBase read_compare_1(1); - ecmdDataBufferBase rank_cal_4(4); - ecmdDataBufferBase ddr_cal_enable_1(1); - ecmdDataBufferBase ccs_end_1(1); - - ecmdDataBufferBase mrs1(16); - uint16_t MRS1 = 0; - //uint32_t mrs_number; - uint8_t address_mirror_map[2][2]; //address_mirror_map[port][dimm] - uint8_t is_sim = 0; - uint8_t dram_2n_mode = 0; - - uint32_t rank_number; - uint16_t num_ranks = 2; - uint8_t func13_rcd_number_array_size; - uint8_t func13_rcd_number_array_u8[4] = {10,11,14,15}; - ecmdDataBufferBase data_buff_rcd_word(64); - uint8_t l_rcd_cntl_word_7 = 0; - uint64_t func_rcd_control_word[2]; - uint8_t l_rcd_cntl_word_14; - uint64_t rcd_array[2][2]; //[port][dimm] - uint8_t num_ranks_array[2][2]; - - // cs 0:7 R0 R1 R2 R3 R4 R5 R6 R7 - uint8_t lrdimm_cs8n [] = { 0x4, 0x8, 0x6, 0xA, 0x5, 0x9, 0x7, 0xB }; - - rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target, num_ranks_array); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_RCD_CNTL_WORD_0_15, &i_target, rcd_array); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_ADDRESS_MIRRORING, &i_target, address_mirror_map); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_IS_SIMULATION, NULL, is_sim); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_2N_MODE_ENABLED, &i_target, dram_2n_mode); - if(rc) return rc; - - //MRS1 - uint8_t dll_enable; - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_DLL_ENABLE, &i_target, dll_enable); - if(rc) return rc; - uint8_t out_drv_imp_cntl[2][2]; - rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_RON, &i_target, out_drv_imp_cntl); - if(rc) return rc; - uint8_t dram_rtt_nom[2][2][4]; - rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_RTT_NOM, &i_target, dram_rtt_nom); - if(rc) return rc; - uint8_t dram_al; - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_AL, &i_target, dram_al); - if(rc) return rc; - uint8_t wr_lvl; //write leveling enable - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WR_LVL_ENABLE, &i_target, wr_lvl); - if(rc) return rc; - uint8_t tdqs_enable; //TDQS Enable - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_TDQS, &i_target, tdqs_enable); - if(rc) return rc; - uint8_t q_off; //Qoff - Output buffer Enable - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_OUTPUT_BUFFER, &i_target, q_off); - if(rc) return rc; - - - if (dll_enable == ENUM_ATTR_EFF_DRAM_DLL_ENABLE_ENABLE) - { - dll_enable = 0x00; - } - else if (dll_enable == ENUM_ATTR_EFF_DRAM_DLL_ENABLE_DISABLE) - { - dll_enable = 0xFF; - } - - if (dram_al == ENUM_ATTR_EFF_DRAM_AL_DISABLE) - { - dram_al = 0x00; - } - else if (dram_al == ENUM_ATTR_EFF_DRAM_AL_CL_MINUS_1) - { - dram_al = 0x80; - } - else if (dram_al == ENUM_ATTR_EFF_DRAM_AL_CL_MINUS_2) - { - dram_al = 0x40; - } - - if (wr_lvl == ENUM_ATTR_EFF_DRAM_WR_LVL_ENABLE_DISABLE) - { - wr_lvl = 0x00; - } - else if (wr_lvl == ENUM_ATTR_EFF_DRAM_WR_LVL_ENABLE_ENABLE) - { - wr_lvl = 0xFF; - } - - if (tdqs_enable == ENUM_ATTR_EFF_DRAM_TDQS_DISABLE) - { - tdqs_enable = 0x00; - } - else if (tdqs_enable == ENUM_ATTR_EFF_DRAM_TDQS_ENABLE) - { - tdqs_enable = 0xFF; - } - - if (q_off == ENUM_ATTR_EFF_DRAM_OUTPUT_BUFFER_DISABLE) - { - q_off = 0xFF; - } - else if (q_off == ENUM_ATTR_EFF_DRAM_OUTPUT_BUFFER_ENABLE) - { - q_off = 0x00; - } - - for (uint8_t dimm_num = 0;dimm_num < MAX_NUM_DIMMS; dimm_num++) - { - - if ( num_ranks_array[i_port_number][dimm_num] != 0 ) - { - l_rcd_cntl_word_14 = (rcd_array[i_port_number][dimm_num] & 0xF0) >> 4; // MRS broadcast - FAPI_INF("current F0RC14 = 0x%X",l_rcd_cntl_word_14); - l_rcd_cntl_word_14 = l_rcd_cntl_word_14 | 0x4; - FAPI_INF("setting F0RC14 = 0x%X",l_rcd_cntl_word_14); - data_buff_rcd_word.clearBit(0,64); - data_buff_rcd_word.insertFromRight(&l_rcd_cntl_word_14, 56,4); - func_rcd_control_word[dimm_num] = data_buff_rcd_word.getDoubleWord(0); - - //not sure need this rc check - if(rc) return rc; - } - } - - FAPI_INF("SELECTING FUNCTION %d", l_rcd_cntl_word_7); - - uint8_t *p_func_num_arr; - uint8_t func0_rcd_number_array_size = 2; - uint8_t func0_rcd_number_array_u8[] = { 7, 14 }; - p_func_num_arr = func0_rcd_number_array_u8; - rc = mss_spec_rcd_load(i_target, i_port_number, p_func_num_arr, func0_rcd_number_array_size, - func_rcd_control_word , io_ccs_inst_cnt,1); - if(rc) - { - FAPI_ERR(" spec_rcd_load Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator()); - return rc; - } - - - // set FN 0 via RC 7 - func_rcd_control_word[0]=0; - func_rcd_control_word[1]=0; - func0_rcd_number_array_u8 [0] = 7; - rc = mss_spec_rcd_load( i_target, i_port_number, p_func_num_arr, 1, - func_rcd_control_word, io_ccs_inst_cnt,1); - - if(rc) - { - FAPI_ERR(" spec_rcd_load Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator()); - return rc; - } - // end turn off MRS broadcast - - // Disable MRS snooping - l_rcd_cntl_word_7 = 13; - FAPI_INF("SELECTING FUNCTION %d", l_rcd_cntl_word_7); - - // extended control word addr, data - uint8_t ext_func[2] = { 0xAC, 0x04}; // MRS_CTRL = 0xAC; snoop/forward/store - uint8_t rcw = 7; - uint64_t rcd0_15[2] = { 0x0000000D00000000ll, // select FN 13 dimm0 - 0x0000000D00000000ll }; // " dimm1 - - // set FN 13 via RC 7 - rc = mss_spec_rcd_load( i_target, i_port_number, &rcw, 1, rcd0_15, io_ccs_inst_cnt,1); - if(rc) - { - FAPI_ERR(" spec_rcd_load Failed rc = 0x%08X (creator = %d)", - uint32_t(rc), rc.getCreator()); - return rc; - } - - func13_rcd_number_array_size = 4; - p_func_num_arr = func13_rcd_number_array_u8; - - data_buff_rcd_word.clearBit(0,64); - data_buff_rcd_word.insertFromRight(&l_rcd_cntl_word_7, 28,4); // select F13 - - // set func_rcd_control_word[dimm_number] - if ( num_ranks_array[i_port_number][dimm_number] != 0 ) { - // load address - data_buff_rcd_word.insertFromRight(ext_func[0],40,4); // lsb address - data_buff_rcd_word.insert(ext_func[0],44,4); // msb address - // load data - data_buff_rcd_word.insertFromRight(ext_func[1], 56,4); // lsb data - data_buff_rcd_word.insert(ext_func[1], 60,4); // msb data - - func_rcd_control_word[dimm_number] = data_buff_rcd_word.getDoubleWord(0); - //not sure need this rc check - if(rc) return rc; - } // end if has ranks - - // load CCS with F13 RC 10:11, 14:15 - rc = mss_spec_rcd_load( i_target, i_port_number, p_func_num_arr, func13_rcd_number_array_size, - func_rcd_control_word , io_ccs_inst_cnt,1); - if(rc) - { - FAPI_ERR(" spec_rcd_load Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator()); - return rc; - } - - // set FN 0 via RC 7 - rcd0_15[0] = 0; - rcd0_15[1] = 0; - rc = mss_spec_rcd_load( i_target, i_port_number, &rcw, 1, rcd0_15, io_ccs_inst_cnt,1); - if(rc) - { - FAPI_ERR(" spec_rcd_load Failed rc = 0x%08X (creator = %d)", - uint32_t(rc), rc.getCreator()); - return rc; - } - - // force execute of remaining rcd !! not necessary??? !! - // Execute the contents of CCS array - if (io_ccs_inst_cnt > 0) - { - // Set the End bit on the last CCS Instruction - rc = mss_ccs_set_end_bit( i_target, io_ccs_inst_cnt-1); - if(rc) - { - FAPI_ERR("CCS_SET_END_BIT FAILED rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator()); - return rc; - } - - rc = mss_execute_ccs_inst_array(i_target, 10, 10); - if(rc) - { - FAPI_ERR(" EXECUTE_CCS_INST_ARRAY FAILED rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator()); - return rc; - } - - io_ccs_inst_cnt = 0; - } - // end force execute of rcd - - // Set RTT_nom, rtt_wr, driver impdance through MR1 - for ( rank_number = 0; rank_number < num_ranks; rank_number++) - { - FAPI_INF( "MRS SETTINGS FOR PORT%d DIMM%d RANK%d", i_port_number, dimm_number, rank_number); - - rc_num = rc_num | csn_8.setBit(0,8); - rc_num = rc_num | address_16.clearBit(0, 16); - - if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE) - { - dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0x00; - } - else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM20) - { - dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0x20; - } - else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30) - { - dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0xA0; - } - else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40) - { - dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0xC0; - } - else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM60) - { - dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0x80; - } - else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM120) - { - dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0x40; - } - - if (out_drv_imp_cntl[i_port_number][dimm_number] == ENUM_ATTR_VPD_DRAM_RON_OHM40) - { - out_drv_imp_cntl[i_port_number][dimm_number] = 0x00; - } - else if (out_drv_imp_cntl[i_port_number][dimm_number] == ENUM_ATTR_VPD_DRAM_RON_OHM34) - { - out_drv_imp_cntl[i_port_number][dimm_number] = 0x80; - } - - - rc_num = rc_num | mrs1.insert((uint8_t) dll_enable, 0, 1, 0); - rc_num = rc_num | mrs1.insert((uint8_t) out_drv_imp_cntl[i_port_number][dimm_number], 1, 1, 0); - rc_num = rc_num | mrs1.insert((uint8_t) dram_rtt_nom[i_port_number][dimm_number][rank_number], 2, 1, 0); - rc_num = rc_num | mrs1.insert((uint8_t) dram_al, 3, 2, 0); - rc_num = rc_num | mrs1.insert((uint8_t) out_drv_imp_cntl[i_port_number][dimm_number], 5, 1, 1); - rc_num = rc_num | mrs1.insert((uint8_t) dram_rtt_nom[i_port_number][dimm_number][rank_number], 6, 1, 1); - rc_num = rc_num | mrs1.insert((uint8_t) wr_lvl, 7, 1, 0); - rc_num = rc_num | mrs1.insert((uint8_t) 0x00, 8, 1); - rc_num = rc_num | mrs1.insert((uint8_t) dram_rtt_nom[i_port_number][dimm_number][rank_number], 9, 1, 2); - rc_num = rc_num | mrs1.insert((uint8_t) 0x00, 10, 1); - rc_num = rc_num | mrs1.insert((uint8_t) tdqs_enable, 11, 1, 0); - rc_num = rc_num | mrs1.insert((uint8_t) q_off, 12, 1, 0); - rc_num = rc_num | mrs1.insert((uint8_t) 0x00, 13, 3); - - rc_num = rc_num | mrs1.extractPreserve(&MRS1, 0, 16, 0); - - FAPI_INF( "MRS 1: 0x%04X", MRS1); - - if (rc_num) - { - FAPI_ERR( "mss_mrs_load: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - - // Only corresponding CS to rank - rc_num = rc_num | csn_8.setBit(0,8); - rc_num = rc_num | csn_8.insert(lrdimm_cs8n[rank_number],(4*dimm_number),4,4); - //mrs_number = 2; - - // Copying the current MRS into address buffer matching the MRS_array order - // Setting the bank address - rc_num = rc_num | address_16.insert(mrs1, 0, 16, 0); - rc_num = rc_num | bank_3.insert((uint8_t) MRS1_BA, 0, 1, 7); - rc_num = rc_num | bank_3.insert((uint8_t) MRS1_BA, 1, 1, 6); - rc_num = rc_num | bank_3.insert((uint8_t) MRS1_BA, 2, 1, 5); - - - if (rc_num) - { - FAPI_ERR( "mss_mrs_load: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - - if (( address_mirror_map[i_port_number][dimm_number] & (0x08 >> rank_number) ) && (is_sim == 0)) - { - rc = mss_address_mirror_swizzle(i_target, i_port_number, dimm_number, rank_number, address_16, bank_3); - } - - - if (dram_2n_mode == ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_TRUE) - { - - // Send out to the CCS array - rc = mss_ccs_inst_arry_0( i_target, - io_ccs_inst_cnt, - address_16, - bank_3, - activate_1, - rasn_1, - casn_1, - wen_1, - cke_4, - csn_setup_8, - odt_4, - ddr_cal_type_4, - i_port_number); - if(rc) return rc; - rc = mss_ccs_inst_arry_1( i_target, - io_ccs_inst_cnt, - num_idles_setup_16, - num_repeat_16, - data_20, - read_compare_1, - rank_cal_4, - ddr_cal_enable_1, - ccs_end_1); - if(rc) return rc; - io_ccs_inst_cnt ++; - } - - // Send out to the CCS array - rc = mss_ccs_inst_arry_0( i_target, - io_ccs_inst_cnt, - address_16, - bank_3, - activate_1, - rasn_1, - casn_1, - wen_1, - cke_4, - csn_8, - odt_4, - ddr_cal_type_4, - i_port_number); - if(rc) return rc; - rc = mss_ccs_inst_arry_1( i_target, - io_ccs_inst_cnt, - num_idles_16, - num_repeat_16, - data_20, - read_compare_1, - rank_cal_4, - ddr_cal_enable_1, - ccs_end_1); - if(rc) return rc; - io_ccs_inst_cnt ++; - - } // end rank loop - - // turn on MRS broadcast - - l_rcd_cntl_word_7 = 0; - - for (uint8_t dimm_num = 0;dimm_num < MAX_NUM_DIMMS; dimm_num++) - { - - if ( num_ranks_array[i_port_number][dimm_num] != 0 ) - { - l_rcd_cntl_word_14 = (rcd_array[i_port_number][dimm_num] & 0xF0) >> 4; // MRS broadcast - FAPI_INF("current F0RC14 = 0x%X",l_rcd_cntl_word_14); - l_rcd_cntl_word_14 = l_rcd_cntl_word_14 & 0xB; - FAPI_INF("setting F0RC14 = 0x%X",l_rcd_cntl_word_14); - ecmdDataBufferBase data_buff_rcd_word(64); - data_buff_rcd_word.clearBit(0,64); - data_buff_rcd_word.insertFromRight(&l_rcd_cntl_word_14, 56,4); - func_rcd_control_word[dimm_num] = data_buff_rcd_word.getDoubleWord(0); - - //not sure if need the rc check - if(rc) return rc; - } - } - - FAPI_INF("SELECTING FUNCTION %d", l_rcd_cntl_word_7); - - func0_rcd_number_array_size = 2; - p_func_num_arr = func0_rcd_number_array_u8; - rc = mss_spec_rcd_load(i_target, i_port_number, p_func_num_arr, func0_rcd_number_array_size, - func_rcd_control_word , io_ccs_inst_cnt,1); - if(rc) - { - FAPI_ERR(" spec_rcd_load Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator()); - return rc; - } - - - // set FN 0 via RC 7 - func_rcd_control_word[0]=0; - func_rcd_control_word[1]=0; - func0_rcd_number_array_u8 [0] = 7; - rc = mss_spec_rcd_load( i_target, i_port_number, p_func_num_arr, 1, - func_rcd_control_word, io_ccs_inst_cnt,1); - - if(rc) - { - FAPI_ERR(" spec_rcd_load Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator()); - return rc; - } - // end turn on MRS broadcast - - // Enable MRS snooping - l_rcd_cntl_word_7 = 13; - FAPI_INF("SELECTING FUNCTION %d", l_rcd_cntl_word_7); - - // extended control word data - ext_func[1] = 0x00; // MRS_CTRL = 0xAC; snoop/forward/store - rcw = 7; - rcd0_15[0] = 0x0000000D00000000ll; // select FN 13 dimm0 - rcd0_15[1] = 0x0000000D00000000ll ; // " dimm1 - - // set FN 13 via RC 7 - rc = mss_spec_rcd_load( i_target, i_port_number, &rcw, 1, rcd0_15, io_ccs_inst_cnt,1); - if(rc) - { - FAPI_ERR(" spec_rcd_load Failed rc = 0x%08X (creator = %d)", - uint32_t(rc), rc.getCreator()); - return rc; - } - - func13_rcd_number_array_size = 4; - p_func_num_arr = func13_rcd_number_array_u8; - - data_buff_rcd_word.clearBit(0,64); - data_buff_rcd_word.insertFromRight(&l_rcd_cntl_word_7, 28,4); // select F13 - - // set func_rcd_control_word[dimm_number] - if ( num_ranks_array[i_port_number][dimm_number] != 0 ) { - // load address - data_buff_rcd_word.insertFromRight(ext_func[0],40,4); // lsb address - data_buff_rcd_word.insert(ext_func[0],44,4); // msb address - // load data - data_buff_rcd_word.insertFromRight(ext_func[1], 56,4); // lsb data - data_buff_rcd_word.insert(ext_func[1], 60,4); // msb data - - func_rcd_control_word[dimm_number] = data_buff_rcd_word.getDoubleWord(0); if(rc) return rc; - } // end if has ranks - - - // load CCS with F13 RC 10:11, 14:15 - rc = mss_spec_rcd_load( i_target, i_port_number, p_func_num_arr, func13_rcd_number_array_size, - func_rcd_control_word , io_ccs_inst_cnt,1); - if(rc) - { - FAPI_ERR(" spec_rcd_load Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator()); - return rc; - } - - // set FN 0 via RC 7 - rcd0_15[0] = 0; - rcd0_15[1] = 0; - rc = mss_spec_rcd_load( i_target, i_port_number, &rcw, 1, rcd0_15, io_ccs_inst_cnt,1); - if(rc) - { - FAPI_ERR(" spec_rcd_load Failed rc = 0x%08X (creator = %d)", - uint32_t(rc), rc.getCreator()); - return rc; - } - - // force execute of remaining rcd !! not necessary??? !! - // Execute the contents of CCS array - if (io_ccs_inst_cnt > 0) - { - // Set the End bit on the last CCS Instruction - rc = mss_ccs_set_end_bit( i_target, io_ccs_inst_cnt-1); - if(rc) - { - FAPI_ERR("CCS_SET_END_BIT FAILED rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator()); - return rc; - } - - rc = mss_execute_ccs_inst_array(i_target, 10, 10); - if(rc) - { - FAPI_ERR(" EXECUTE_CCS_INST_ARRAY FAILED rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator()); - return rc; - } - - io_ccs_inst_cnt = 0; - } - // end force execute of rcd - // End enable MRS snooping - - - return rc; -} - -fapi::ReturnCode mss_execute_lrdimm_mb_dram_training(fapi::Target &i_target) -{ - ReturnCode rc; - uint8_t l_rcd_cntl_word_7; - uint8_t l_rcd_cntl_word_12; - ecmdDataBufferBase data_buff_rcd_word(64); - uint32_t port; - uint8_t dimm_number; - const uint8_t MAX_NUM_DIMMS = 2; - const uint8_t MAX_NUM_PORT = 2; - uint8_t num_ranks_array[MAX_NUM_PORT][MAX_NUM_DIMMS]; - uint64_t func_rcd_control_word[2]; - uint8_t *p_func_num_arr; - uint8_t funcTRAIN_rcd_number_array_u8[2] = {7,12}; - - uint32_t ccs_inst_cnt = 0; - uint32_t rc_num = 0; - ecmdDataBufferBase address_16(16); - ecmdDataBufferBase bank_3(3); - ecmdDataBufferBase activate_1(1); - ecmdDataBufferBase rasn_1(1); - rc_num = rc_num | rasn_1.setBit(0); - ecmdDataBufferBase casn_1(1); - rc_num = rc_num | casn_1.setBit(0); - ecmdDataBufferBase wen_1(1); - rc_num = rc_num | wen_1.setBit(0); - ecmdDataBufferBase cke_4(4); - rc_num = rc_num | cke_4.setBit(0,4); - ecmdDataBufferBase csn_8(8); - rc_num = rc_num | csn_8.setBit(0,2); - rc_num = rc_num | csn_8.setBit(4,2); - ecmdDataBufferBase odt_4(4); - rc_num = rc_num | odt_4.setBit(0,4); - ecmdDataBufferBase ddr_cal_type_4(4); - - if(rc_num) - { - rc.setEcmdError(rc_num); - return rc; - } - ecmdDataBufferBase num_idles_16(16); - ecmdDataBufferBase num_repeat_16(16); - ecmdDataBufferBase data_20(20); - ecmdDataBufferBase read_compare_1(1); - ecmdDataBufferBase rank_cal_4(4); - ecmdDataBufferBase ddr_cal_enable_1(1); - ecmdDataBufferBase ccs_end_1(1); - - uint32_t l_mss_freq; - uint32_t l_num_idles_delay=20; - - fapi::Target l_target_centaur; - rc = fapiGetParentChip(i_target, l_target_centaur); - if(rc) return rc; - - rc = FAPI_ATTR_GET(ATTR_MSS_FREQ, &l_target_centaur, l_mss_freq); - if(rc) return rc; - - rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target, num_ranks_array); - if(rc) return rc; - - for ( port = 0; port < MAX_NUM_PORT; port++ ) - { - // MB-DRAM training - l_rcd_cntl_word_7 = 0; - l_rcd_cntl_word_12 = 2; // Training control, start DRAM interface training - - data_buff_rcd_word.clearBit(0,64); - data_buff_rcd_word.insertFromRight(&l_rcd_cntl_word_7, 28, 4); - data_buff_rcd_word.insertFromRight(&l_rcd_cntl_word_12, 48, 4); - - for ( dimm_number = 0; dimm_number < MAX_NUM_DIMMS; dimm_number++ ) - { - if ( num_ranks_array[port][dimm_number] != 0 ) - { - func_rcd_control_word[dimm_number] = data_buff_rcd_word.getDoubleWord(0); - if(rc) return rc; - } - } - - FAPI_INF("SELECTING FUNCTION %d", l_rcd_cntl_word_7); - p_func_num_arr = funcTRAIN_rcd_number_array_u8; - rc = mss_spec_rcd_load(i_target, port, p_func_num_arr, - (uint8_t) sizeof(funcTRAIN_rcd_number_array_u8)/(uint8_t)sizeof(funcTRAIN_rcd_number_array_u8[0]), - func_rcd_control_word , ccs_inst_cnt,1); - if(rc) - { - FAPI_ERR(" spec_rcd_load Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator()); - return rc; - } - - - rc_num = rc_num | address_16.clearBit(0, 16); - rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) l_num_idles_delay, 0, 16); - if(rc_num) - { - rc.setEcmdError(rc_num); - return rc; - } - - rc = mss_ccs_inst_arry_0( i_target, - ccs_inst_cnt, - address_16, - bank_3, - activate_1, - rasn_1, - casn_1, - wen_1, - cke_4, - csn_8, - odt_4, - ddr_cal_type_4, - port); - if(rc) return rc; - rc = mss_ccs_inst_arry_1( i_target, - ccs_inst_cnt, - num_idles_16, - num_repeat_16, - data_20, - read_compare_1, - rank_cal_4, - ddr_cal_enable_1, - ccs_end_1); - if(rc) return rc; - ccs_inst_cnt++; - } - - // Execute the contents of CCS array - if (ccs_inst_cnt > 0) - { - // Set the End bit on the last CCS Instruction - rc = mss_ccs_set_end_bit( i_target, ccs_inst_cnt-1); - if(rc) - { - FAPI_ERR("CCS_SET_END_BIT FAILED rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator()); - return rc; - } - - rc = mss_execute_ccs_inst_array(i_target, 10, 10); - if(rc) - { - FAPI_ERR(" EXECUTE_CCS_INST_ARRAY FAILED rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator()); - return rc; - } - - ccs_inst_cnt = 0; - }// end force execute of rcd - return rc; -} - -fapi::ReturnCode mss_lrdimm_eff_config(const fapi::Target &i_target_mba, - uint8_t cur_dimm_spd_valid_u8array[PORT_SIZE][DIMM_SIZE], - uint32_t mss_freq, uint8_t eff_num_ranks_per_dimm[PORT_SIZE][DIMM_SIZE]) -{ - ReturnCode rc; - - std::vector<fapi::Target> l_target_dimm_array; - uint8_t l_cur_mba_port = 0; - uint8_t l_cur_mba_dimm = 0; - - mss_lrdimm_spd_data *p_l_lr_spd_data = new mss_lrdimm_spd_data(); - memset( p_l_lr_spd_data, 0, sizeof(mss_lrdimm_spd_data) ); - - uint8_t lrdimm_mr12_reg[PORT_SIZE][DIMM_SIZE]; - uint64_t lrdimm_additional_cntl_words[PORT_SIZE][DIMM_SIZE]; - uint8_t lrdimm_rank_mult_mode; - uint8_t eff_ibm_type[PORT_SIZE][DIMM_SIZE]; - uint64_t eff_dimm_rcd_cntl_word_0_15[PORT_SIZE][DIMM_SIZE]; - - do - { - rc = fapiGetAssociatedDimms(i_target_mba, l_target_dimm_array); - if(rc) - { - FAPI_ERR("Error retrieving assodiated dimms"); - break; - } - - for (uint8_t l_dimm_index = 0; l_dimm_index < l_target_dimm_array.size(); l_dimm_index += 1) - { - rc = FAPI_ATTR_GET(ATTR_MBA_PORT, &l_target_dimm_array[l_dimm_index], - l_cur_mba_port); - if(rc) - { - FAPI_ERR("Error retrieving ATTR_MBA_PORT"); - break; - } - //------------------------------------------------------------------------ - rc = FAPI_ATTR_GET(ATTR_MBA_DIMM, &l_target_dimm_array[l_dimm_index], l_cur_mba_dimm); - if(rc) - { - FAPI_ERR("Error retrieving ATTR_MBA_DIMM"); - break; - } - - // Setup SPD attributes - rc = FAPI_ATTR_GET(ATTR_SPD_LR_ADDR_MIRRORING, &l_target_dimm_array[l_dimm_index], - p_l_lr_spd_data->lr_addr_mirroring[l_cur_mba_port][l_cur_mba_dimm]); - if(rc) break; - rc = FAPI_ATTR_GET(ATTR_SPD_LR_F0RC3_F0RC2, &l_target_dimm_array[l_dimm_index], - p_l_lr_spd_data->lr_f0rc3_f0rc2[l_cur_mba_port][l_cur_mba_dimm]); - if(rc) break; - rc = FAPI_ATTR_GET(ATTR_SPD_LR_F0RC5_F0RC4, &l_target_dimm_array[l_dimm_index], - p_l_lr_spd_data->lr_f0rc5_f0rc4[l_cur_mba_port][l_cur_mba_dimm]); - if(rc) break; - rc = FAPI_ATTR_GET(ATTR_SPD_LR_F1RC11_F1RC8, &l_target_dimm_array[l_dimm_index], - p_l_lr_spd_data->lr_f1rc11_f1rc8[l_cur_mba_port][l_cur_mba_dimm]); - if(rc) break; - rc = FAPI_ATTR_GET(ATTR_SPD_LR_F1RC13_F1RC12, &l_target_dimm_array[l_dimm_index], - p_l_lr_spd_data->lr_f1rc13_f1rc12[l_cur_mba_port][l_cur_mba_dimm]); - if(rc) break; - rc = FAPI_ATTR_GET(ATTR_SPD_LR_F1RC15_F1RC14, &l_target_dimm_array[l_dimm_index], - p_l_lr_spd_data->lr_f1rc15_f1rc14[l_cur_mba_port][l_cur_mba_dimm]); - if(rc) break; - rc = FAPI_ATTR_GET(ATTR_SPD_LR_F3RC9_F3RC8_FOR_800_1066, &l_target_dimm_array[l_dimm_index], - p_l_lr_spd_data->lr_f3rc9_f3rc8_for_800_1066[l_cur_mba_port][l_cur_mba_dimm]); - if(rc) break; - rc = FAPI_ATTR_GET(ATTR_SPD_LR_F34RC11_F34RC10_FOR_800_1066, &l_target_dimm_array[l_dimm_index], - p_l_lr_spd_data->lr_f34rc11_f34rc10_for_800_1066[l_cur_mba_port][l_cur_mba_dimm]); - if(rc) break; - rc = FAPI_ATTR_GET(ATTR_SPD_LR_F56RC11_F56RC10_FOR_800_1066, &l_target_dimm_array[l_dimm_index], - p_l_lr_spd_data->lr_f56rc11_f56rc10_for_800_1066[l_cur_mba_port][l_cur_mba_dimm]); - if(rc) break; - rc = FAPI_ATTR_GET(ATTR_SPD_LR_F78RC11_F78RC10_FOR_800_1066, &l_target_dimm_array[l_dimm_index], - p_l_lr_spd_data->lr_f78rc11_f78rc10_for_800_1066[l_cur_mba_port][l_cur_mba_dimm]); - if(rc) break; - rc = FAPI_ATTR_GET(ATTR_SPD_LR_F910RC11_F910RC10_FOR_800_1066, &l_target_dimm_array[l_dimm_index], - p_l_lr_spd_data->lr_f910rc11_f910rc10_for_800_1066[l_cur_mba_port][l_cur_mba_dimm]); - if(rc) break; - rc = FAPI_ATTR_GET(ATTR_SPD_LR_MR12_FOR_800_1066, &l_target_dimm_array[l_dimm_index], - p_l_lr_spd_data->lr_mr12_for_800_1066[l_cur_mba_port][l_cur_mba_dimm]); - if(rc) break; - rc = FAPI_ATTR_GET(ATTR_SPD_LR_F3RC9_F3RC8_FOR_1333_1600, &l_target_dimm_array[l_dimm_index], - p_l_lr_spd_data->lr_f3rc9_f3rc8_for_1333_1600[l_cur_mba_port][l_cur_mba_dimm]); - if(rc) break; - rc = FAPI_ATTR_GET(ATTR_SPD_LR_F34RC11_F34RC10_FOR_1333_1600, &l_target_dimm_array[l_dimm_index], - p_l_lr_spd_data->lr_f34rc11_f34rc10_for_1333_1600[l_cur_mba_port][l_cur_mba_dimm]); - if(rc) break; - rc = FAPI_ATTR_GET(ATTR_SPD_LR_F56RC11_F56RC10_FOR_1333_1600, &l_target_dimm_array[l_dimm_index], - p_l_lr_spd_data->lr_f56rc11_f56rc10_for_1333_1600[l_cur_mba_port][l_cur_mba_dimm]); - if(rc) break; - rc = FAPI_ATTR_GET(ATTR_SPD_LR_F78RC11_F78RC10_FOR_1333_1600, &l_target_dimm_array[l_dimm_index], - p_l_lr_spd_data->lr_f78rc11_f78rc10_for_1333_1600[l_cur_mba_port][l_cur_mba_dimm]); - if(rc) break; - rc = FAPI_ATTR_GET(ATTR_SPD_LR_F910RC11_F910RC10_FOR_1333_1600, &l_target_dimm_array[l_dimm_index], - p_l_lr_spd_data->lr_f910rc11_f910rc10_for_1333_1600[l_cur_mba_port][l_cur_mba_dimm]); - if(rc) break; - rc = FAPI_ATTR_GET(ATTR_SPD_LR_MR12_FOR_1333_1600, &l_target_dimm_array[l_dimm_index], - p_l_lr_spd_data->lr_mr12_for_1333_1600[l_cur_mba_port][l_cur_mba_dimm]); - if(rc) break; - rc = FAPI_ATTR_GET(ATTR_SPD_LR_F3RC9_F3RC8_FOR_1866_2133, &l_target_dimm_array[l_dimm_index], - p_l_lr_spd_data->lr_f3rc9_f3rc8_for_1866_2133[l_cur_mba_port][l_cur_mba_dimm]); - if(rc) break; - rc = FAPI_ATTR_GET(ATTR_SPD_LR_F34RC11_F34RC10_FOR_1866_2133, &l_target_dimm_array[l_dimm_index], - p_l_lr_spd_data->lr_f34rc11_f34rc10_for_1866_2133[l_cur_mba_port][l_cur_mba_dimm]); - if(rc) break; - rc = FAPI_ATTR_GET(ATTR_SPD_LR_F56RC11_F56RC10_FOR_1866_2133, &l_target_dimm_array[l_dimm_index], - p_l_lr_spd_data->lr_f56rc11_f56rc10_for_1866_2133[l_cur_mba_port][l_cur_mba_dimm]); - if(rc) break; - rc = FAPI_ATTR_GET(ATTR_SPD_LR_F78RC11_F78RC10_FOR_1866_2133, &l_target_dimm_array[l_dimm_index], - p_l_lr_spd_data->lr_f78rc11_f78rc10_for_1866_2133[l_cur_mba_port][l_cur_mba_dimm]); - if(rc) break; - rc = FAPI_ATTR_GET(ATTR_SPD_LR_F910RC11_F910RC10_FOR_1866_2133, &l_target_dimm_array[l_dimm_index], - p_l_lr_spd_data->lr_f910rc11_f910rc10_for_1866_2133[l_cur_mba_port][l_cur_mba_dimm]); - if(rc) break; - rc = FAPI_ATTR_GET(ATTR_SPD_LR_MR12_FOR_1866_2133, &l_target_dimm_array[l_dimm_index], - p_l_lr_spd_data->lr_mr12_for_1866_2133[l_cur_mba_port][l_cur_mba_dimm]); - if(rc) break; - } - - if(rc) - { - FAPI_ERR("Error reading spd data from caller"); - break; - } - - - // Setup attributes - for (int l_cur_mba_port = 0; l_cur_mba_port < PORT_SIZE; l_cur_mba_port += 1) - { - for (int l_cur_mba_dimm = 0; l_cur_mba_dimm < DIMM_SIZE; l_cur_mba_dimm += 1) - { - if (cur_dimm_spd_valid_u8array[l_cur_mba_port][l_cur_mba_dimm] == MSS_EFF_VALID) - { - FAPI_INF(" !! LRDIMM Detected -MW"); - - ecmdDataBufferBase rcd(64); - rcd.flushTo0(); - - rcd.setDoubleWord(0,eff_dimm_rcd_cntl_word_0_15[l_cur_mba_port][l_cur_mba_dimm]); - FAPI_INF("rcd0_15=0x%016llX",rcd.getDoubleWord(0)); - - rcd.insert(p_l_lr_spd_data->lr_f0rc3_f0rc2[l_cur_mba_port][l_cur_mba_dimm],12,4,0); //rcd3 - rcd.insert(p_l_lr_spd_data->lr_f0rc3_f0rc2[l_cur_mba_port][l_cur_mba_dimm],8,4,4); //rcd2 - - rcd.insert(p_l_lr_spd_data->lr_f0rc5_f0rc4[l_cur_mba_port][l_cur_mba_dimm],20,4,0); //rcd5 - rcd.insert(p_l_lr_spd_data->lr_f0rc5_f0rc4[l_cur_mba_port][l_cur_mba_dimm],16,4,4); //rcd4 - - rcd.insert(p_l_lr_spd_data->lr_addr_mirroring[l_cur_mba_port][l_cur_mba_dimm],59,1,7); // address mirroring - - eff_dimm_rcd_cntl_word_0_15[l_cur_mba_port][l_cur_mba_dimm]=rcd.getDoubleWord(0); - - ecmdDataBufferBase rcd_1(64); - rcd_1.flushTo0(); - // F[1]RC11,8 - rcd_1.insert(p_l_lr_spd_data->lr_f1rc11_f1rc8[l_cur_mba_port][l_cur_mba_dimm],44,4,0); //F[1]RC11 -> rcd11 - rcd_1.insert(p_l_lr_spd_data->lr_f1rc11_f1rc8[l_cur_mba_port][l_cur_mba_dimm],32,4,4); //F[1]RC8 -> rcd8 - - // F[1]RC13,12 - rcd_1.insert(p_l_lr_spd_data->lr_f1rc13_f1rc12[l_cur_mba_port][l_cur_mba_dimm],52,4,0); //F[1]RC13 -> rcd13 - rcd_1.insert(p_l_lr_spd_data->lr_f1rc13_f1rc12[l_cur_mba_port][l_cur_mba_dimm],48,4,4); //F[1]RC12 -> rcd12 - - // F[1]RC15,14 - rcd_1.insert(p_l_lr_spd_data->lr_f1rc15_f1rc14[l_cur_mba_port][l_cur_mba_dimm],60,4,0); //F[1]RC15 -> rcd15 - rcd_1.insert(p_l_lr_spd_data->lr_f1rc15_f1rc14[l_cur_mba_port][l_cur_mba_dimm],56,4,4); //F[1]RC14 -> rcd14 - - - if ( mss_freq > 1733 ) { - rcd_1.insert(p_l_lr_spd_data->lr_f3rc9_f3rc8_for_1866_2133[l_cur_mba_port][l_cur_mba_dimm],36,4,0); // F[3]RC9 -> rcd9 - rcd_1.insert(p_l_lr_spd_data->lr_f3rc9_f3rc8_for_1866_2133[l_cur_mba_port][l_cur_mba_dimm],40,4,4); // F[3]RC8 -> rcd10 - rcd_1.insert(p_l_lr_spd_data->lr_f34rc11_f34rc10_for_1866_2133[l_cur_mba_port][l_cur_mba_dimm],4,4,0); // F[3,4]RC11 -> rcd1 - rcd_1.insert(p_l_lr_spd_data->lr_f34rc11_f34rc10_for_1866_2133[l_cur_mba_port][l_cur_mba_dimm],0,4,4); // F[3,4]RC10 -> rcd0 - rcd_1.insert(p_l_lr_spd_data->lr_f56rc11_f56rc10_for_1866_2133[l_cur_mba_port][l_cur_mba_dimm],12,4,0); // F[6,6]RC11 -> rcd3 - rcd_1.insert(p_l_lr_spd_data->lr_f56rc11_f56rc10_for_1866_2133[l_cur_mba_port][l_cur_mba_dimm],8,4,4); // F[5,6]RC10 -> rcd2 - rcd_1.insert(p_l_lr_spd_data->lr_f78rc11_f78rc10_for_1866_2133[l_cur_mba_port][l_cur_mba_dimm],20,4,0); // F[7,8]RC11 -> rcd5 - rcd_1.insert(p_l_lr_spd_data->lr_f78rc11_f78rc10_for_1866_2133[l_cur_mba_port][l_cur_mba_dimm],16,4,4); // F[7,8]RC10 -> rcd4 - rcd_1.insert(p_l_lr_spd_data->lr_f910rc11_f910rc10_for_1866_2133[l_cur_mba_port][l_cur_mba_dimm],28,4,0); // F[9,10]RC11 -> rcd7 - rcd_1.insert(p_l_lr_spd_data->lr_f910rc11_f910rc10_for_1866_2133[l_cur_mba_port][l_cur_mba_dimm],24,4,4); // F[9,10]RC10 -> rcd6 - - lrdimm_mr12_reg[l_cur_mba_port][l_cur_mba_dimm] = p_l_lr_spd_data->lr_mr12_for_1866_2133[l_cur_mba_port][l_cur_mba_dimm]; - - } else if ( mss_freq > 1200 ) { - rcd_1.insert(p_l_lr_spd_data->lr_f3rc9_f3rc8_for_1333_1600[l_cur_mba_port][l_cur_mba_dimm],36,4,0); // F[3]RC9 -> rcd9 - rcd_1.insert(p_l_lr_spd_data->lr_f3rc9_f3rc8_for_1333_1600[l_cur_mba_port][l_cur_mba_dimm],40,4,4); // F[3]RC8 -> rcd10 - rcd_1.insert(p_l_lr_spd_data->lr_f34rc11_f34rc10_for_1333_1600[l_cur_mba_port][l_cur_mba_dimm],4,4,0); // F[3,4]RC11 -> rcd1 - rcd_1.insert(p_l_lr_spd_data->lr_f34rc11_f34rc10_for_1333_1600[l_cur_mba_port][l_cur_mba_dimm],0,4,4); // F[3,4]RC10 -> rcd0 - rcd_1.insert(p_l_lr_spd_data->lr_f56rc11_f56rc10_for_1333_1600[l_cur_mba_port][l_cur_mba_dimm],12,4,0); // F[6,6]RC11 -> rcd3 - rcd_1.insert(p_l_lr_spd_data->lr_f56rc11_f56rc10_for_1333_1600[l_cur_mba_port][l_cur_mba_dimm],8,4,4); // F[5,6]RC10 -> rcd2 - rcd_1.insert(p_l_lr_spd_data->lr_f78rc11_f78rc10_for_1333_1600[l_cur_mba_port][l_cur_mba_dimm],20,4,0); // F[7,8]RC11 -> rcd5 - rcd_1.insert(p_l_lr_spd_data->lr_f78rc11_f78rc10_for_1333_1600[l_cur_mba_port][l_cur_mba_dimm],16,4,4); // F[7,8]RC10 -> rcd4 - rcd_1.insert(p_l_lr_spd_data->lr_f910rc11_f910rc10_for_1333_1600[l_cur_mba_port][l_cur_mba_dimm],28,4,0); // F[9,10]RC11 -> rcd7 - rcd_1.insert(p_l_lr_spd_data->lr_f910rc11_f910rc10_for_1333_1600[l_cur_mba_port][l_cur_mba_dimm],24,4,4); // F[9,10]RC10 -> rcd6 - - lrdimm_mr12_reg[l_cur_mba_port][l_cur_mba_dimm] = p_l_lr_spd_data->lr_mr12_for_1333_1600[l_cur_mba_port][l_cur_mba_dimm]; - - } else { - rcd_1.insert(p_l_lr_spd_data->lr_f3rc9_f3rc8_for_800_1066[l_cur_mba_port][l_cur_mba_dimm],36,4,0); // F[3]RC9 -> rcd9 - rcd_1.insert(p_l_lr_spd_data->lr_f3rc9_f3rc8_for_800_1066[l_cur_mba_port][l_cur_mba_dimm],40,4,4); // F[3]RC8 -> rcd10 - rcd_1.insert(p_l_lr_spd_data->lr_f34rc11_f34rc10_for_800_1066[l_cur_mba_port][l_cur_mba_dimm],4,4,0); // F[3,4]RC11 -> rcd1 - rcd_1.insert(p_l_lr_spd_data->lr_f34rc11_f34rc10_for_800_1066[l_cur_mba_port][l_cur_mba_dimm],0,4,4); // F[3,4]RC10 -> rcd0 - rcd_1.insert(p_l_lr_spd_data->lr_f56rc11_f56rc10_for_800_1066[l_cur_mba_port][l_cur_mba_dimm],12,4,0); // F[6,6]RC11 -> rcd3 - rcd_1.insert(p_l_lr_spd_data->lr_f56rc11_f56rc10_for_800_1066[l_cur_mba_port][l_cur_mba_dimm],8,4,4); // F[5,6]RC10 -> rcd2 - rcd_1.insert(p_l_lr_spd_data->lr_f78rc11_f78rc10_for_800_1066[l_cur_mba_port][l_cur_mba_dimm],20,4,0); // F[7,8]RC11 -> rcd5 - rcd_1.insert(p_l_lr_spd_data->lr_f78rc11_f78rc10_for_800_1066[l_cur_mba_port][l_cur_mba_dimm],16,4,4); // F[7,8]RC10 -> rcd4 - rcd_1.insert(p_l_lr_spd_data->lr_f910rc11_f910rc10_for_800_1066[l_cur_mba_port][l_cur_mba_dimm],28,4,0); // F[9,10]RC11 -> rcd7 - rcd_1.insert(p_l_lr_spd_data->lr_f910rc11_f910rc10_for_800_1066[l_cur_mba_port][l_cur_mba_dimm],24,4,4); // F[9,10]RC10 -> rcd6 - - lrdimm_mr12_reg[l_cur_mba_port][l_cur_mba_dimm] = p_l_lr_spd_data->lr_mr12_for_800_1066[l_cur_mba_port][l_cur_mba_dimm]; - } - - uint64_t rcd1 = rcd_1.getDoubleWord(0); - lrdimm_additional_cntl_words[l_cur_mba_port][l_cur_mba_dimm] = rcd1; - - if ( eff_num_ranks_per_dimm[l_cur_mba_port][l_cur_mba_dimm] == 8 ) { - lrdimm_rank_mult_mode = 4; // Default for 8R is 4x mult mode - } - - // ======================================================================================== - - - // FIX finding stack type properly. - if ( eff_num_ranks_per_dimm[l_cur_mba_port][l_cur_mba_dimm] == 1 ) { - //p_o_atts->eff_stack_type[l_cur_mba_port][l_cur_mba_dimm] = fapi::ENUM_ATTR_EFF_STACK_TYPE_NONE; - eff_ibm_type[l_cur_mba_port][l_cur_mba_dimm] = fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_5A; - } else if ( eff_num_ranks_per_dimm[l_cur_mba_port][l_cur_mba_dimm] == 2 ) { - //p_o_atts->eff_stack_type[l_cur_mba_port][l_cur_mba_dimm] = fapi::ENUM_ATTR_EFF_STACK_TYPE_NONE; - eff_ibm_type[l_cur_mba_port][l_cur_mba_dimm] = fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_5B; - } else if ( eff_num_ranks_per_dimm[l_cur_mba_port][l_cur_mba_dimm] == 4 ) { - //p_o_atts->eff_stack_type[l_cur_mba_port][l_cur_mba_dimm] = fapi::ENUM_ATTR_EFF_STACK_TYPE_DDP_QDP; - eff_ibm_type[l_cur_mba_port][l_cur_mba_dimm] = fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_5C; - } else if ( eff_num_ranks_per_dimm[l_cur_mba_port][l_cur_mba_dimm] == 8 ) { - //p_o_atts->eff_stack_type[l_cur_mba_port][l_cur_mba_dimm] = fapi::ENUM_ATTR_EFF_STACK_TYPE_DDP_QDP; - eff_ibm_type[l_cur_mba_port][l_cur_mba_dimm] = fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_5D; - } else { - //p_o_atts->eff_stack_type[l_cur_mba_port][l_cur_mba_dimm] = fapi::ENUM_ATTR_EFF_STACK_TYPE_NONE; - eff_ibm_type[l_cur_mba_port][l_cur_mba_dimm] = fapi::ENUM_ATTR_EFF_IBM_TYPE_UNDEFINED; - FAPI_ERR("Currently unsupported IBM_TYPE on %s!", i_target_mba.toEcmdString()); - uint8_t IBM_TYPE = eff_num_ranks_per_dimm[l_cur_mba_port][l_cur_mba_dimm]; - const fapi::Target& TARGET = i_target_mba; - fapi::Target& DIMM = l_target_dimm_array[l_cur_mba_dimm]; - FAPI_SET_HWP_ERROR(rc, RC_MSS_LRDIMM_UNSUPPORTED_TYPE); - return rc; - } - } // end valid dimm - } // end dimm loop - } // end port loop - - rc = FAPI_ATTR_SET(ATTR_EFF_IBM_TYPE, &i_target_mba, - eff_ibm_type); - rc = FAPI_ATTR_SET(ATTR_LRDIMM_MR12_REG, &i_target_mba, - lrdimm_mr12_reg); - rc = FAPI_ATTR_SET(ATTR_LRDIMM_ADDITIONAL_CNTL_WORDS, &i_target_mba, - lrdimm_additional_cntl_words); - rc = FAPI_ATTR_SET(ATTR_LRDIMM_RANK_MULT_MODE, &i_target_mba, - lrdimm_rank_mult_mode); - rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_RCD_CNTL_WORD_0_15, &i_target_mba, - eff_dimm_rcd_cntl_word_0_15); - - if(rc) - { - FAPI_ERR("Error setting attributes"); - break; - } - } while(0); - - return rc; -} - -fapi::ReturnCode mss_lrdimm_rewrite_odt(const fapi::Target& i_target_mba, uint32_t * p_b_var_array, uint32_t *var_array_p_array[5]) -{ - ReturnCode rc; - uint8_t l_num_ranks_per_dimm_u8array[PORT_SIZE][DIMM_SIZE]; -// uint8_t l_arr_offset; - uint32_t l_mss_freq = 0; - uint8_t l_dram_width_u8; - - // uint32_t *odt_array; - - // For dual drop, Set ODT_RD as 2rank (8R LRDIMM) or 4rank (4R LRDIMM) - fapi::Target l_target_centaur; - rc = fapiGetParentChip(i_target_mba, l_target_centaur); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_MSS_FREQ, &l_target_centaur, l_mss_freq); if(rc) return rc; - - rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target_mba, l_num_ranks_per_dimm_u8array); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target_mba, l_dram_width_u8); if(rc) return rc; - -// uint8_t l_start=44, l_end=60; -// 8/4/2014 kahnevan - ifdefing this out to avoid 64 bit compiler warnings for unused odt_array variable. -// With the code at the bottom commented out, (comment from mdb) nothing was being done with the value. -#if 0 - if ( (l_num_ranks_per_dimm_u8array[0][1] == 4) || (l_num_ranks_per_dimm_u8array[1][1] == 4) ) { - odt_array = var_array_p_array[0]; - FAPI_INF("Setting LRDIMM ODT_RD as 4 rank dimm"); - } else if ( (l_num_ranks_per_dimm_u8array[0][1] == 8) || (l_num_ranks_per_dimm_u8array[1][1] == 8) ) { - if ( l_mss_freq <= 1466 ) { // 1333Mbps - if ( l_dram_width_u8 == 4 ) { - odt_array = var_array_p_array[1]; - } else if ( l_dram_width_u8 == 8 ) { - odt_array = var_array_p_array[2]; - } - } else if ( l_mss_freq <= 1733 ) { // 1600 Mbps - if ( l_dram_width_u8 == 4 ) { - odt_array = var_array_p_array[3]; - } else if ( l_dram_width_u8 == 8 ) { - odt_array = var_array_p_array[4]; - } - } - FAPI_INF("Setting LRDIMM ODT_RD as 2 logical rank dimm"); - } -#endif - -// mdb - we do not have eff config attributes, so we can't set this array. This function probably goes away -// for ( l_arr_offset = l_start; l_arr_offset < l_end; l_arr_offset++ ) { -// *(p_b_var_array + l_arr_offset) = *(odt_array + l_arr_offset); -// } - - return rc; -} - -fapi::ReturnCode mss_lrdimm_term_atts(const fapi::Target& i_target_mba) -{ - ReturnCode rc; - - uint8_t l_dram_ron[PORT_SIZE][DIMM_SIZE]; - uint8_t l_dram_rtt_wr[PORT_SIZE][DIMM_SIZE]; - uint8_t l_dram_rtt_nom[PORT_SIZE][DIMM_SIZE]; - - uint8_t attr_eff_dram_ron[PORT_SIZE][DIMM_SIZE]; - uint8_t attr_eff_dram_rtt_nom[PORT_SIZE][DIMM_SIZE][RANK_SIZE]; - uint8_t attr_eff_dram_rtt_wr[PORT_SIZE][DIMM_SIZE][RANK_SIZE]; - uint8_t attr_eff_odt_wr[PORT_SIZE][DIMM_SIZE][RANK_SIZE]; - - uint32_t l_mss_freq = 0; - uint32_t l_mss_volt = 0; - uint8_t l_num_ranks_per_dimm_u8array[PORT_SIZE][DIMM_SIZE]; - uint8_t l_num_drops_per_port; - uint8_t l_dram_density; - uint8_t l_dram_width_u8; - - uint8_t l_lrdimm_mr12_u8array[PORT_SIZE][DIMM_SIZE]; - uint8_t l_lrdimm_rank_mult_mode; - - uint8_t l_rcd_cntl_word_0_1; - uint8_t l_rcd_cntl_word_6_7; - uint8_t l_rcd_cntl_word_8_9; - uint8_t l_rcd_cntl_word_10; - uint8_t l_rcd_cntl_word_11; - uint8_t l_rcd_cntl_word_12; - uint8_t l_rcd_cntl_word_13; - uint8_t l_rcd_cntl_word_14; - uint8_t l_rcd_cntl_word_15; - uint64_t l_rcd_cntl_word_0_15; - uint64_t l_rcd_cntl_word_2_5_mask = 0x00FFFF0000000010LL; - ecmdDataBufferBase data_buffer_64(64); - ecmdDataBufferBase data_buffer_8(8); - - // Fetch impacted attributes - uint64_t l_attr_eff_dimm_rcd_cntl_word_0_15[PORT_SIZE][DIMM_SIZE]; - rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_RCD_CNTL_WORD_0_15, &i_target_mba, l_attr_eff_dimm_rcd_cntl_word_0_15); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_RON, &i_target_mba, attr_eff_dram_ron); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_RTT_NOM, &i_target_mba, attr_eff_dram_rtt_nom); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_RTT_WR, &i_target_mba, attr_eff_dram_rtt_wr); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_VPD_ODT_WR, &i_target_mba, attr_eff_odt_wr); if(rc) return rc; - - // Fetch impacted attributes - rc = FAPI_ATTR_GET(ATTR_EFF_NUM_DROPS_PER_PORT, &i_target_mba, l_num_drops_per_port); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target_mba, l_dram_width_u8); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target_mba, l_num_ranks_per_dimm_u8array); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_DENSITY, &i_target_mba, l_dram_density); if(rc) return rc; - - fapi::Target l_target_centaur; - rc = fapiGetParentChip(i_target_mba, l_target_centaur); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_MSS_FREQ, &l_target_centaur, l_mss_freq); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_MSS_VOLT, &l_target_centaur, l_mss_volt); if(rc) return rc; - - // Fetch SPD MR1,2 - rc = FAPI_ATTR_GET(ATTR_LRDIMM_MR12_REG, &i_target_mba, l_lrdimm_mr12_u8array); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_LRDIMM_RANK_MULT_MODE, &i_target_mba, l_lrdimm_rank_mult_mode); if(rc) return rc; - - for (uint8_t l_port = 0; l_port < PORT_SIZE; l_port++) { - for (uint8_t l_dimm = 0; l_dimm < DIMM_SIZE; l_dimm++) { - - // Set RCD control word - FAPI_INF("before setting: rcd control word 0-15 %.16llX", l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] ); - l_rcd_cntl_word_0_1 = 0x00; // Global features, Clock driver enable - FAPI_INF("rcd control word 0-1 %X", l_rcd_cntl_word_0_1 ); - - // RCD cntl words 2-5 from SPD - - l_rcd_cntl_word_6_7 = 0x00; // CKE & ODT management, Function select - FAPI_INF("rcd control word 6-7 %X", l_rcd_cntl_word_6_7 ); - - if ( l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL ) { - l_rcd_cntl_word_8_9 = 0x20; // IBT=200 Ohm & Vref settings for address, command, par_in, Power saving settings - } - else { - l_rcd_cntl_word_8_9 = 0x00; // IBT=100 Ohm & Vref settings for address, command, par_in, Power saving settings - } - FAPI_INF("rcd control word 8-9 %X", l_rcd_cntl_word_8_9 ); - - - const fapi::Target& TARGET = i_target_mba; - // RC10 LRDIMM operating speed - if ( l_mss_freq <= 933 ) { // 800Mbps - l_rcd_cntl_word_10 = 0; - } else if ( l_mss_freq <= 1200 ) { // 1066Mbps - l_rcd_cntl_word_10 = 1; - } else if ( l_mss_freq <= 1466 ) { // 1333Mbps - l_rcd_cntl_word_10 = 2; - } else if ( l_mss_freq <= 1733 ) { // 1600Mbps - l_rcd_cntl_word_10 = 3; - } else if ( l_mss_freq <= 2000 ) { // 1866Mbps - l_rcd_cntl_word_10 = 4; - } else { - FAPI_ERR("Invalid LRDIMM ATTR_MSS_FREQ = %d on %s!", l_mss_freq, i_target_mba.toEcmdString()); - uint32_t& L_MSS_FREQ = l_mss_freq; - FAPI_SET_HWP_ERROR(rc, RC_MSS_LRDIMM_INVALID_MSS_FREQ); return rc; - } - FAPI_INF("rcd control word 10 %X", l_rcd_cntl_word_10 ); - - // RC11 Operating voltage & parity calculation (buffer does not include A17:16) - if ( l_mss_volt >= 1420 ) { // 1.5V - l_rcd_cntl_word_11 = 4; - } else if ( l_mss_volt >= 1270 ) { // 1.35V - l_rcd_cntl_word_11 = 5; - } else if ( l_mss_volt >= 1170 ) { // 1.25V - l_rcd_cntl_word_11 = 6; - } else { - FAPI_ERR("Invalid LRDIMM ATTR_MSS_VOLT = %d on %s!", l_mss_volt, i_target_mba.toEcmdString()); - uint32_t& L_MSS_VOLT = l_mss_volt; - FAPI_SET_HWP_ERROR(rc, RC_MSS_LRDIMM_INVALID_MSS_VOLT); return rc; - } - FAPI_INF("rcd control word 11 %X", l_rcd_cntl_word_11 ); - - l_rcd_cntl_word_12 = 0; //Training - FAPI_INF("rcd control word 12 %X", l_rcd_cntl_word_12 ); - - // rC13 DIMM configuration - if ( l_num_ranks_per_dimm_u8array[l_port][l_dimm] == 8 ) { - l_rcd_cntl_word_13 = 4; // 8 physical ranks, 2 logical ranks, RM=4 - } else if ( l_num_ranks_per_dimm_u8array[l_port][l_dimm] == 4 ) { - l_rcd_cntl_word_13 = 9; // 4 physical ranks, 4 logical ranks, direct rank mapping - // } else if ( l_num_ranks_per_dimm_u8array[l_port][l_dimm] == 2 ) { - // l_rcd_cntl_word_13 = 6; // 2 physical ranks, 2 logical ranks, direct rank mapping - // } else if ( l_num_ranks_per_dimm_u8array[l_port][l_dimm] == 1 ) { - // l_rcd_cntl_word_13 = 3; // 1 physical rank, 1 logical rank, direct rank mapping - } else { - l_rcd_cntl_word_13 = 0; - } - FAPI_INF("rcd control word 13 %X", l_rcd_cntl_word_13 ); - - // RC14 DRAM configuration & DRAM command - if ( l_lrdimm_rank_mult_mode != 0 ) { - data_buffer_8.setBit(2); // turn off refresh broadcast - } - if ( l_dram_width_u8 == 8 ) { - data_buffer_8.setBit(0); - } - data_buffer_8.extractToRight( &l_rcd_cntl_word_14, 0, 4); - FAPI_INF("rcd control word 14 %X", l_rcd_cntl_word_14 ); - uint8_t& L_LRDIMM_RANK_MULT_MODE=l_lrdimm_rank_mult_mode; - uint8_t& L_DRAM_DENSITY=l_dram_density; - - // RC15 Rank multiplication - if ( l_lrdimm_rank_mult_mode == 4 ) { - if ( l_dram_density == 1 ) { - l_rcd_cntl_word_15 = 5; // A[15:14]; 4x multiplication, 1 Gbit DDR3 SDRAM - } else if ( l_dram_density == 2 ) { - l_rcd_cntl_word_15 = 6; // A[16:15]; 4x multiplication, 2 Gbit DDR3 SDRAM - } else if ( l_dram_density == 4 ) { - l_rcd_cntl_word_15 = 7; // A[17:16]; 4x multiplication, 4 Gbit DDR3 SDRAM - } else { - FAPI_ERR("Invalid LRDIMM Rank mult mode =%d, ATTR_EFF_DRAM_DENSITY = %d on %s!", l_lrdimm_rank_mult_mode, l_dram_density, i_target_mba.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_LRDIMM_INVALID_RANK_MULT_MODE); return rc; - } - } else if ( l_lrdimm_rank_mult_mode == 2 ) { - if ( l_dram_density == 1 ) { - l_rcd_cntl_word_15 = 1; // A[14]; 2x multiplication, 1 Gbit DDR3 SDRAM - } else if ( l_dram_density == 2 ) { - l_rcd_cntl_word_15 = 2; // A[15]; 2x multiplication, 2 Gbit DDR3 SDRAM - } else if ( l_dram_density == 4 ) { - l_rcd_cntl_word_15 = 3; // A[16]; 2x multiplication, 4 Gbit DDR3 SDRAM - } else { - FAPI_ERR("Invalid LRDIMM Rank Mult mode = %d, ATTR_EFF_DRAM_DENSITY = %d on %s!", l_lrdimm_rank_mult_mode, l_dram_density, i_target_mba.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_LRDIMM_INVALID_DRAM_DENSITY_MULT_2); return rc; - } - } else { - l_rcd_cntl_word_15 = 0; - } - FAPI_INF("rcd control word 15 %X", l_rcd_cntl_word_15 ); - - data_buffer_64.insertFromRight(&l_rcd_cntl_word_0_1, 0, 8); - data_buffer_64.clearBit( 8, 16); - data_buffer_64.insertFromRight(&l_rcd_cntl_word_6_7, 24, 8); - data_buffer_64.insertFromRight(&l_rcd_cntl_word_8_9, 32, 8); - data_buffer_64.insertFromRight(&l_rcd_cntl_word_10, 40, 4); - data_buffer_64.insertFromRight(&l_rcd_cntl_word_11, 44, 4); - data_buffer_64.insertFromRight(&l_rcd_cntl_word_12, 48, 4); - data_buffer_64.insertFromRight(&l_rcd_cntl_word_13, 52, 4); - data_buffer_64.insertFromRight(&l_rcd_cntl_word_14, 56, 4); - data_buffer_64.insertFromRight(&l_rcd_cntl_word_15, 60, 4); - l_rcd_cntl_word_0_15 = data_buffer_64.getDoubleWord(0); if(rc) return rc; - FAPI_INF("from data buffer: rcd control word 0-15 %llX", l_rcd_cntl_word_0_15 ); - l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] & l_rcd_cntl_word_2_5_mask; - l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] | l_rcd_cntl_word_0_15; - - FAPI_INF("after mask: rcd control word 0-15 %.16llX", l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] ); - - // Setup LRDIMM drive impedance, rtt nom, rtt wr, odt wr - l_dram_ron[l_port][l_dimm] = l_lrdimm_mr12_u8array[l_port][l_dimm] & 0x03; // Pulled from SPD LR MR1,2 DRAM DriverImpedance [1:0] - l_dram_rtt_nom[l_port][l_dimm] = (l_lrdimm_mr12_u8array[l_port][l_dimm] & 0x1C) >> 2; // Pulled from SPD LR MR1,2 DRAM RTT_nom for ranks 0/1 [4:2] - l_dram_rtt_wr[l_port][l_dimm] = (l_lrdimm_mr12_u8array[l_port][l_dimm] & 0xC0) >> 6; // Pulled from SPD LR MR1,2 DRAM RTT_WR [7:6] - - if ( l_dram_ron[l_port][l_dimm] == 0 ) { - l_dram_ron[l_port][l_dimm] = fapi::ENUM_ATTR_VPD_DRAM_RON_OHM40; - } else if ( l_dram_ron[l_port][l_dimm] == 1 ) { - l_dram_ron[l_port][l_dimm] = fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34; - } else { - uint8_t& L_DRAM_RON = l_dram_ron[l_port][l_dimm]; - FAPI_ERR("Invalid SPD LR MR1,2 DRAM drv imp on %s!", i_target_mba.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_LRDIMM_INVALID_SPD_DRV_IMP); return rc; - } - - attr_eff_dram_ron[l_port][l_dimm] = l_dram_ron[l_port][l_dimm]; - FAPI_INF("Set LRDIMM DRAM_RON to SPD LR MR1,2 DRAM drv imp"); - - switch (l_dram_rtt_nom[l_port][l_dimm]) { - case 0 : l_dram_rtt_nom[l_port][l_dimm] = fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE; - break; - case 1 : l_dram_rtt_nom[l_port][l_dimm] = fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM60; - break; - case 2 : l_dram_rtt_nom[l_port][l_dimm] = fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM120; - break; - case 3 : l_dram_rtt_nom[l_port][l_dimm] = fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40; - break; - case 4 : l_dram_rtt_nom[l_port][l_dimm] = fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM20; - break; - case 5 : l_dram_rtt_nom[l_port][l_dimm] = fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30; - break; - default: FAPI_ERR("Invalid SPD LR MR1,2 DRAM RTT_NOM on %s!", i_target_mba.toEcmdString()); - uint8_t& L_DRAM_RTT_NOM = l_dram_rtt_nom[l_port][l_dimm]; - FAPI_SET_HWP_ERROR(rc, RC_MSS_LRDIMM_INVALID_SPD_RTT_NOM); - return rc; - } - - switch (l_dram_rtt_wr[l_port][l_dimm]) { - case 0 : l_dram_rtt_wr[l_port][l_dimm] = fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE; - break; - case 1 : l_dram_rtt_wr[l_port][l_dimm] = fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60; - break; - case 2 : l_dram_rtt_wr[l_port][l_dimm] = fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120; - break; - default: FAPI_ERR("Invalid SPD LR MR1,2 DRAM RTT_WR on %s!", i_target_mba.toEcmdString()); - uint8_t& L_DRAM_RTT_WR = l_dram_rtt_wr[l_port][l_dimm]; - FAPI_SET_HWP_ERROR(rc, RC_MSS_LRDIMM_INVALID_SPD_RTT_WR); - return rc; - } - - uint8_t l_rank; - for ( l_rank = 0; l_rank < RANK_SIZE; l_rank++ ) { // clear RTT_NOM & RTT_WR - attr_eff_dram_rtt_nom[l_port][l_dimm][l_rank] = fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE; - attr_eff_dram_rtt_wr[l_port][l_dimm][l_rank] = fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE; - } - - if ( l_num_ranks_per_dimm_u8array[l_port][l_dimm] > 0 ) { // Set RTT_NOM Rank 0 for multi rank LRDIMM - attr_eff_dram_rtt_nom[l_port][l_dimm][0] = l_dram_rtt_nom[l_port][l_dimm]; // set attr_eff_dram_rtt_nom[0][0][0] - attr_eff_dram_rtt_wr[l_port][l_dimm][0] = l_dram_rtt_wr[l_port][l_dimm]; // set attr_eff_dram_rtt_wr[0][0][0] - - FAPI_INF("Setting Port0 Rank 0 LRDIMM RTT_NOM & RTT_WR from SPD LR MR1,2"); - - if ( l_num_ranks_per_dimm_u8array[l_port][l_dimm] > 1 ) { // Set RTT_NOM Rank 1 for 4rank or 8rank LRDIMM - attr_eff_dram_rtt_nom[l_port][l_dimm][1] = l_dram_rtt_nom[l_port][l_dimm]; // set attr_eff_dram_rtt_nom[0][0][1] - attr_eff_dram_rtt_wr[l_port][l_dimm][1] = l_dram_rtt_wr[l_port][l_dimm]; // set attr_eff_dram_rtt_wr[0][0][1] - - attr_eff_dram_rtt_wr[l_port][l_dimm][2] = l_dram_rtt_wr[l_port][l_dimm]; // set attr_eff_dram_rtt_wr[0][0][2] - attr_eff_dram_rtt_wr[l_port][l_dimm][3] = l_dram_rtt_wr[l_port][l_dimm]; // set attr_eff_dram_rtt_wr[0][0][3] - FAPI_INF("Setting Port0 Rank 1+ LRDIMM RTT_NOM & RTT_WR from SPD LR MR1,2"); - } - } - -//------------------------------------------------------------------------------------------------------------- - - // Set ODT_WR for each valid rank as single RDIMM rank value. - if ( l_num_ranks_per_dimm_u8array[l_port][l_dimm] > 1 ) { // SET ODT_WR Rank 1 for multi rank LRDIMM (8R or 4R) - attr_eff_odt_wr[l_port][l_dimm][1] = attr_eff_odt_wr[l_port][l_dimm][0]; // set attr_eff_odt_wr[0][0][1] to attr_eff_odt_wr[0][0][0] - if ( l_num_ranks_per_dimm_u8array[l_port][l_dimm] == 4 ) { // Set ODT_WR Rankd 2,3 for 4 rank LRDIMM - attr_eff_odt_wr[l_port][l_dimm][2] = attr_eff_odt_wr[l_port][l_dimm][0]; // set attr_eff_odt_wr[0][0][2] to attr_eff_odt_wr[0][0][0] - attr_eff_odt_wr[l_port][l_dimm][3] = attr_eff_odt_wr[l_port][l_dimm][0]; // set attr_eff_odt_wr[0][0][3] to attr_eff_odt_wr[0][0][0] - } - } - - } // end dimm loop - } // end port loop - - // Set adjusted attributes - rc = FAPI_ATTR_SET(ATTR_VPD_DRAM_RON, &i_target_mba, attr_eff_dram_ron); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_VPD_DRAM_RTT_NOM, &i_target_mba, attr_eff_dram_rtt_nom); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_VPD_DRAM_RTT_WR, &i_target_mba, attr_eff_dram_rtt_wr); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_VPD_ODT_WR, &i_target_mba, attr_eff_odt_wr); if(rc) return rc; - - rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_RCD_CNTL_WORD_0_15, &i_target_mba, l_attr_eff_dimm_rcd_cntl_word_0_15); if(rc) return rc; - - return rc; -} - -fapi::ReturnCode mss_spec_rcd_load( fapi::Target& i_target, uint32_t i_port_number, uint8_t *p_i_rcd_num_arr, uint8_t i_rcd_num_arr_length, uint64_t i_rcd_word[], uint32_t& io_ccs_inst_cnt,uint8_t i_keep_cke_high) -{ - const uint8_t MAX_NUM_PORTS=2; - const uint8_t MAX_NUM_DIMMS=2; - ReturnCode rc; - ReturnCode rc_buff; - uint32_t rc_num = 0; - uint32_t dimm_number; - uint8_t spec_rcd; - - ecmdDataBufferBase rcd_cntl_wrd_4(8); - ecmdDataBufferBase rcd_cntl_wrd_64(64); - uint16_t num_ranks; - - uint16_t num_idles_delay = 20; // default=12 klc - - ecmdDataBufferBase address_16(16); - ecmdDataBufferBase bank_3(3); - ecmdDataBufferBase activate_1(1); - ecmdDataBufferBase rasn_1(1); - rc_num = rc_num | rasn_1.setBit(0); - ecmdDataBufferBase casn_1(1); - rc_num = rc_num | casn_1.setBit(0); - ecmdDataBufferBase wen_1(1); - rc_num = rc_num | wen_1.setBit(0); - ecmdDataBufferBase cke_4(4); - if (i_keep_cke_high == 1) - rc_num = rc_num | cke_4.setBit(0,4); - else - rc_num = rc_num | cke_4.clearBit(0,4); - ecmdDataBufferBase csn_8(8); - rc_num = rc_num | csn_8.setBit(0,8); - ecmdDataBufferBase odt_4(4); - rc_num = rc_num | odt_4.setBit(0,4); - ecmdDataBufferBase ddr_cal_type_4(4); - - ecmdDataBufferBase num_idles_16(16); - ecmdDataBufferBase num_repeat_16(16); - ecmdDataBufferBase data_20(20); - ecmdDataBufferBase read_compare_1(1); - ecmdDataBufferBase rank_cal_4(4); - ecmdDataBufferBase ddr_cal_enable_1(1); - ecmdDataBufferBase ccs_end_1(1); - - uint8_t num_ranks_array[MAX_NUM_PORTS][MAX_NUM_DIMMS]; //[port][dimm] - - rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target, num_ranks_array); - if(rc) return rc; - - FAPI_INF( "+++++++++++++++++++++ LOADING RCD CONTROL WORD FOR PORT %d +++++++++++++++++++++", i_port_number); - - for ( dimm_number = 0; dimm_number < MAX_NUM_DIMMS; dimm_number++) - { - num_ranks = num_ranks_array[i_port_number][dimm_number]; - - if (num_ranks == 0) - { - FAPI_INF( "PORT%d DIMM%d not configured. Num_ranks: %d", i_port_number, dimm_number, num_ranks); - } - else - { - FAPI_INF( "RCD SETTINGS FOR PORT%d DIMM%d ", i_port_number, dimm_number); - FAPI_INF( "RCD Control Word: 0x%016llX", i_rcd_word[dimm_number]); - FAPI_INF( "Loading function specific RCD Control Words"); - - if (rc_num) - { - FAPI_ERR( "mss_spec_rcd_load: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - - rc_num = rc_num | csn_8.setBit(0,8); // reset CS lines - // for dimm0 use CS0,1 (active low); for dimm1 use CS4,5 (active low) - rc_num = rc_num | csn_8.clearBit( (dimm_number * 4), 2 ); - // set specific control words - for ( spec_rcd = 0; spec_rcd < i_rcd_num_arr_length; spec_rcd++ ) - { - rc_num = rc_num | bank_3.clearBit(0, 3); - rc_num = rc_num | address_16.clearBit(0, 16); - - rc_num = rc_num | rcd_cntl_wrd_64.setDoubleWord(0, i_rcd_word[dimm_number]); - rc_num = rc_num | rcd_cntl_wrd_64.extract(rcd_cntl_wrd_4, 4*p_i_rcd_num_arr[spec_rcd], 4); - - //control word number code bits A0, A1, A2, BA2 - rc_num = rc_num | bank_3.insert(p_i_rcd_num_arr[spec_rcd], 2, 1, 4); // BA2(MSB) from array bit 4 - rc_num = rc_num | address_16.insert(p_i_rcd_num_arr[spec_rcd], 2, 1, 5); // A2 - rc_num = rc_num | address_16.insert(p_i_rcd_num_arr[spec_rcd], 1, 1, 6); // A1 - rc_num = rc_num | address_16.insert(p_i_rcd_num_arr[spec_rcd], 0, 1, 7); // A0 - - //control word values RCD0 = A3, RCD1 = A4, RCD2 = BA0, RCD3 = BA1 - rc_num = rc_num | bank_3.insert(rcd_cntl_wrd_4, 1, 1, 0); // BA1 (MSB) - rc_num = rc_num | bank_3.insert(rcd_cntl_wrd_4, 0, 1, 1); // BA0 - rc_num = rc_num | address_16.insert(rcd_cntl_wrd_4, 4, 1, 2); // A4 - rc_num = rc_num | address_16.insert(rcd_cntl_wrd_4, 3, 1, 3); // A3 - - FAPI_INF("Loading RCD %d (0x%02x) = 0x%01X", p_i_rcd_num_arr[spec_rcd], - p_i_rcd_num_arr[spec_rcd], - (rcd_cntl_wrd_4.getByte(0)>>4)); - - // Send out to the CCS array - rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) num_idles_delay, 0, 16); - rc = mss_ccs_inst_arry_0( i_target, - io_ccs_inst_cnt, - address_16, - bank_3, - activate_1, - rasn_1, - casn_1, - wen_1, - cke_4, - csn_8, - odt_4, - ddr_cal_type_4, - i_port_number); - if(rc) return rc; - rc = mss_ccs_inst_arry_1( i_target, - io_ccs_inst_cnt, - num_idles_16, - num_repeat_16, - data_20, - read_compare_1, - rank_cal_4, - ddr_cal_enable_1, - ccs_end_1); - if(rc) return rc; - io_ccs_inst_cnt ++; - - if (rc_num) - { - FAPI_ERR( "mss_rcd_load: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - } //end control word loop - } // end valid rank - } // end dimm loop - return rc; -} - -#endif diff --git a/src/usr/hwpf/hwp/dram_training/mss_lrdimm_funcs/mss_lrdimm_funcs.H b/src/usr/hwpf/hwp/dram_training/mss_lrdimm_funcs/mss_lrdimm_funcs.H deleted file mode 100644 index f478d8aa3..000000000 --- a/src/usr/hwpf/hwp/dram_training/mss_lrdimm_funcs/mss_lrdimm_funcs.H +++ /dev/null @@ -1,167 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/dram_training/mss_lrdimm_funcs/mss_lrdimm_funcs.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2013,2014 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: mss_lrdimm_funcs.H,v 1.2 2013/09/16 13:28:55 bellows Exp $ -//------------------------------------------------------------------------------ -// *! (C) Copyright International Business Machines Corp. 2013 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -//------------------------------------------------------------------------------ -// *! TITLE : mss_lrdimm_funcs.H -// *! DESCRIPTION : Tools for lrdimm centaur procedures -// *! OWNER NAME : KCOOK -// *! BACKUP NAME : MWUU -// #! ADDITIONAL COMMENTS : -// -// CCS related and general utility functions. - -//------------------------------------------------------------------------------ -// Don't forget to create CVS comments when you check in your changes! -//------------------------------------------------------------------------------ -// CHANGE HISTORY: -//------------------------------------------------------------------------------ -// Version:| Author: | Date: | Comment: -//---------|----------|---------|----------------------------------------------- -// 1.2 | 09/16/13 | bellows | Added ID tag -// 1.1 | 08/27/13 | kcook | First drop of Centaur - -#ifndef _MSS_LRDIMM_FUNCS_H -#define _MSS_LRDIMM_FUNCS_H - -//#define LRDIMM 1 - -//---------------------------------------------------------------------- -// Constants -//---------------------------------------------------------------------- -const uint8_t PORT = 2; -const uint8_t DIMM = 2; -const uint8_t RANK = 4; -//---------------------------------------------------------------------- -// Enums -//---------------------------------------------------------------------- - -struct mss_lrdimm_spd_data -{ - uint8_t lr_addr_mirroring[PORT][DIMM]; - uint8_t lr_f0rc3_f0rc2[PORT][DIMM]; - uint8_t lr_f0rc5_f0rc4[PORT][DIMM]; - uint8_t lr_f1rc11_f1rc8[PORT][DIMM]; - uint8_t lr_f1rc13_f1rc12[PORT][DIMM]; - uint8_t lr_f1rc15_f1rc14[PORT][DIMM]; - uint8_t lr_f3rc9_f3rc8_for_800_1066[PORT][DIMM]; - uint8_t lr_f34rc11_f34rc10_for_800_1066[PORT][DIMM]; - uint8_t lr_f56rc11_f56rc10_for_800_1066[PORT][DIMM]; - uint8_t lr_f78rc11_f78rc10_for_800_1066[PORT][DIMM]; - uint8_t lr_f910rc11_f910rc10_for_800_1066[PORT][DIMM]; - uint8_t lr_mr12_for_800_1066[PORT][DIMM]; - uint8_t lr_f3rc9_f3rc8_for_1333_1600[PORT][DIMM]; - uint8_t lr_f34rc11_f34rc10_for_1333_1600[PORT][DIMM]; - uint8_t lr_f56rc11_f56rc10_for_1333_1600[PORT][DIMM]; - uint8_t lr_f78rc11_f78rc10_for_1333_1600[PORT][DIMM]; - uint8_t lr_f910rc11_f910rc10_for_1333_1600[PORT][DIMM]; - uint8_t lr_mr12_for_1333_1600[PORT][DIMM]; - uint8_t lr_f3rc9_f3rc8_for_1866_2133[PORT][DIMM]; - uint8_t lr_f34rc11_f34rc10_for_1866_2133[PORT][DIMM]; - uint8_t lr_f56rc11_f56rc10_for_1866_2133[PORT][DIMM]; - uint8_t lr_f78rc11_f78rc10_for_1866_2133[PORT][DIMM]; - uint8_t lr_f910rc11_f910rc10_for_1866_2133[PORT][DIMM]; - uint8_t lr_mr12_for_1866_2133[PORT][DIMM]; -}; - - -//---------------------------------------------------------------------- -// LRDIMM FUNCS -//---------------------------------------------------------------------- - -//-------------------------------------------------------------- -// mss_lrimm_rcd_load -// Set Function 1-13 RCD words -// Target = centaur.mba -//-------------------------------------------------------------- -fapi::ReturnCode mss_lrdimm_rcd_load( fapi::Target& i_target, - uint32_t port_number, - uint32_t& ccs_inst_cnt ); - -//-------------------------------------------------------------- -// mss_lrdimm_mrs_load -// Set MRS1 settings for Rank 0 and Rank 1 -// Target = centaur.mba -//-------------------------------------------------------------- -fapi::ReturnCode mss_lrdimm_mrs_load( fapi::Target& i_target, - uint32_t i_port_number, - uint32_t dimm_number, - uint32_t& io_ccs_inst_cnt); -//-------------------------------------------------------------- -// mss_execute_lrdimm_mb_dram_training -// run lrdimm memory buffer training -// Target = centaur.mba -//-------------------------------------------------------------- -fapi::ReturnCode mss_execute_lrdimm_mb_dram_training( fapi::Target& i_target); - -//-------------------------------------------------------------- -// mss_lrdimm_eff_config -// run lrdimm attribute set up -// Target = centaur.mba -//-------------------------------------------------------------- -fapi::ReturnCode mss_lrdimm_eff_config( const fapi::Target& i_target_mba, - uint8_t cur_dimm_spd_valid_u8array[PORT][DIMM], - uint32_t mss_freq, - uint8_t eff_num_ranks_per_dimm[PORT][DIMM]); - -//-------------------------------------------------------------- -// mss_lrdimm_rewrite_odt -// eff config termination rewrite odts for dual drop -// Target = centaur.mba -//-------------------------------------------------------------- -fapi::ReturnCode mss_lrdimm_rewrite_odt( const fapi::Target& i_target_mba, - uint32_t *p_b_var_array, - uint32_t *var_array_p_array[5]); - - -//-------------------------------------------------------------- -// mss_lrdimm_term_atts -// eff config termination rewrite odts for dual drop -// Target = centaur.mba -//-------------------------------------------------------------- -fapi::ReturnCode mss_lrdimm_term_atts( const fapi::Target& i_target_mba); - - - -//----------------------------------------- -// mss_spec_rcd_load -// execute RCD loads of specific control words. For LRDIMM. -// Target = centaur.mba -//----------------------------------------- -fapi::ReturnCode mss_spec_rcd_load(fapi::Target& i_target, - uint32_t i_port_number, - uint8_t * p_i_rcd_num_arr, - uint8_t i_rcd_num_arr_length, - uint64_t i_rcd_word[], - uint32_t& io_ccs_inst_cnt, - uint8_t i_keep_cke_high=0); - - - -#endif /* _MSS_LRDIMM_FUNCS_H */ - diff --git a/src/usr/hwpf/hwp/dram_training/mss_scominit/mss_scominit.C b/src/usr/hwpf/hwp/dram_training/mss_scominit/mss_scominit.C deleted file mode 100644 index c9ae89d86..000000000 --- a/src/usr/hwpf/hwp/dram_training/mss_scominit/mss_scominit.C +++ /dev/null @@ -1,244 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/dram_training/mss_scominit/mss_scominit.C $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2012,2014 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: mss_scominit.C,v 1.19 2014/08/05 15:06:52 kahnevan Exp $ -//------------------------------------------------------------------------------ -// *! (C) Copyright International Business Machines Corp. 2011 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -//------------------------------------------------------------------------------ -// *! TITLE : mss_scominit -// *! DESCRIPTION : see additional comments below -// *! OWNER NAME : Menlo Wuu Email: menlowuu@us.ibm.com -// *! BACKUP NAME : Mark Bellows Email: bellows@us.ibm.com -// *! ADDITIONAL COMMENTS : -// -// The purpose of this procedure execute memory initfiles in proper sequence. -// -//------------------------------------------------------------------------------ -// Don't forget to create CVS comments when you check in your changes! -//------------------------------------------------------------------------------ -// CHANGE HISTORY: -//------------------------------------------------------------------------------ -// Version:| Author: | Date: | Comment: -//---------|----------|---------|----------------------------------------------- -// 1.18 | menlowuu |14-NOV-13| Added Mike Jones changes for callouts -// 1.17 | menlowuu |02-JUL-13| Fixed vector insert for L4 targets -// 1.16 | menlowuu |02-JUL-13| Added L4 targets for MBS initfile -// 1.15 | menlowuu |11-NOV-12| Removed include of dimmBadDqBitmapFuncs.H> -// 1.14 | menlowuu |09-NOV-12| Removed mss_set_bbm_regs FN since now handled -// in draminit_training. -// 1.13 | menlowuu |26-SEP-12| Changed ORing of port to SCOM address -// 1.12 | menlowuu |19-SEP-12| Fixed some return codes. -// 1.11 | menlowuu |22-AUG-12| Added return code for mss_set_bbm_regs FN. -// 1.10 | menlowuu |21-AUG-12| Removed running *_mcbist files since it was -// moved into the *_def files. -// 1.9 | menlowuu |15-AUG-12| Added disable bit set FN, reused rc, added -// mbs/mba_mcbist.if to the scominit FN. -// 1.8 | bellows |16-JUL-12| added in Id tag -// 1.7 | menlowuu |14-JUN-12| Added fixes suggested by Mike, -// replace rc_num with ReturnCode, created RC for when -// MBAs != 2, and return on all errors -// 1.6 | menlowuu |08-JUN-12| Fixed inserting centaur vector & return code. -// 1.5 | menlowuu |06-JUN-12| Added code to use -// primary centaur target, secondary mba[0/1] for mbs.if; -// primary mba[0|1] target, secondary centaur for mba.if, phy.if -// 1.4 | menlowuu |05-JUN-12| Added vector target for fapiHwpExecInitFile -// 1.3 | menlowuu |15-MAY-12| Added fapi namespace to rc_num definition -// 0.1 | menlowuu |01-DEC-11| First Draft. - - -//---------------------------------------------------------------------- -// My Includes -//---------------------------------------------------------------------- -#include <mss_scominit.H> - -//---------------------------------------------------------------------- -// Includes -//---------------------------------------------------------------------- -#include <fapi.H> -#include <fapiHwpExecInitFile.H> - -//---------------------------------------------------------------------- -// Constants -//---------------------------------------------------------------------- -#define MAX_PORTS 2 -#define MAX_PRI_RANKS 4 -#define TOTAL_BYTES 10 - -extern "C" { - using namespace fapi; - -//****************************************************************************** -// -//****************************************************************************** -ReturnCode mss_scominit(const Target & i_target) { - - ReturnCode rc; - std::vector<Target> vector_targets, vector_l4_targets; - const char* mbs_if[] = { - "mbs_def.if", - /* "mbs_mcbist.if" // moved into mbs_def file */ - }; - const char* mba_if[] = { - "mba_def.if", - /* "mba_mcbist.if", // moved into mba_def file */ - "cen_ddrphy.if" - }; - - FAPI_INF("Performing HWP: mss_scominit"); - - // Print the ecmd string of the chip - FAPI_INF("Input Target: %s", i_target.toEcmdString()); - - // Get a vector of the present MBA targets - rc = fapiGetChildChiplets(i_target, TARGET_TYPE_MBA_CHIPLET, - vector_targets, TARGET_STATE_PRESENT); - - if (rc) - { - FAPI_ERR("Error from fapiGetChildChiplets getting present MBA's!"); - FAPI_ERR("RC = 0x%x", static_cast<uint32_t>(rc)); - return (rc); - } - else if (vector_targets.size() != 2) - { - FAPI_ERR("fapiGetChildChiplets returned %zd present MBAs, expected 2", - vector_targets.size()); - uint32_t NUM_MBAS = vector_targets.size(); - FAPI_SET_HWP_ERROR(rc, RC_MSS_SCOMINIT_NUM_MBA_ERROR); - return (rc); - } - else - { - // insert centaur target at beginning of vector - vector_targets.insert(vector_targets.begin(),i_target); - - FAPI_INF("Getting L4 targets"); - // Get L4 vectors - rc = fapiGetChildChiplets(i_target, TARGET_TYPE_L4, - vector_l4_targets, TARGET_STATE_PRESENT); - - if (rc) - { - FAPI_ERR("Error from fapiGetChildChiplets getting L4 targets!"); - FAPI_ERR("RC = 0x%x", static_cast<uint32_t>(rc)); - return (rc); - } - - if (vector_l4_targets.size() != 1) - { - FAPI_ERR("fapiGetChildChiplets returned %zd present L4s, expected 1", - vector_l4_targets.size()); - uint32_t NUM_L4S = vector_l4_targets.size(); - FAPI_SET_HWP_ERROR(rc, RC_MSS_SCOMINIT_NUM_L4_ERROR); - return (rc); - } - - // insert L4 targets at the end - vector_targets.insert(vector_targets.end(),vector_l4_targets.begin(), vector_l4_targets.end()); - - // run mbs initfile... - uint8_t num_mbs_files = sizeof(mbs_if)/sizeof(char*); - for (uint8_t itr=0; itr < num_mbs_files; itr++) - { - FAPI_EXEC_HWP(rc, fapiHwpExecInitFile, vector_targets, mbs_if[itr]); - - if (rc) - { - FAPI_ERR(" !!! Error running MBS %s, RC = 0x%x", - mbs_if[itr], static_cast<uint32_t>(rc)); - return (rc); - } - else - { - FAPI_INF("MBS scom initfile %s passed", mbs_if[itr]); - } - } - } - - // Clear vector targets - vector_targets.clear(); - - // Get a vector of the functional MBA targets - rc=fapiGetChildChiplets(i_target, TARGET_TYPE_MBA_CHIPLET, vector_targets); - - if (rc) - { - FAPI_ERR("Error from fapiGetChildChiplets getting functional MBA's!"); - return (rc); - } - else - { - uint8_t l_unitPos = 0; - - FAPI_INF("Found %zi functional MBA chiplets", vector_targets.size()); - - // Iterate through the returned chiplets - for (uint32_t i = 0; i < vector_targets.size(); i++) - { - // Find the position of the MBA chiplet - rc=FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &vector_targets[i], l_unitPos); - - if (rc) - { - FAPI_ERR("Error getting ATTR_CHIP_UNIT_POS for MBA"); - return (rc); - } - else - { - std::vector<Target> mba_cen_targets; - - FAPI_INF("MBA%i valid", l_unitPos); - - // push current mba target then centaur target - mba_cen_targets.push_back(vector_targets[i]); - mba_cen_targets.push_back(i_target); - - // run mba initfiles... - uint8_t num_mba_files = sizeof(mba_if)/sizeof(char*); - for (uint8_t itr=0; itr < num_mba_files; itr++) - { - FAPI_EXEC_HWP(rc, fapiHwpExecInitFile, mba_cen_targets, - mba_if[itr]); - - if (rc) - { - FAPI_ERR(" !!! Error running MBA %s, RC = 0x%x", - mba_if[itr], static_cast<uint32_t>(rc)); - return (rc); - } - else - { - FAPI_INF("MBA scom initfile %s passed", mba_if[itr]); - } - } // end for loop, running MBA/PHY initfiles - } // end else, MBA fapiHwpExecInitFile - } // end for loop, valid chip unit pos - } // found functional MBAs - - return (rc); -} // end mss_scominit - -} // extern "C" diff --git a/src/usr/hwpf/hwp/dram_training/mss_scominit/mss_scominit.H b/src/usr/hwpf/hwp/dram_training/mss_scominit/mss_scominit.H deleted file mode 100644 index 68946c1e8..000000000 --- a/src/usr/hwpf/hwp/dram_training/mss_scominit/mss_scominit.H +++ /dev/null @@ -1,85 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/dram_training/mss_scominit/mss_scominit.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2012,2014 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: mss_scominit.H,v 1.7 2012/11/10 02:53:17 mwuu Exp $ -//------------------------------------------------------------------------------ -// *! (C) Copyright International Business Machines Corp. 2011 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -//------------------------------------------------------------------------------ -// *! TITLE : mss_scominit.H -// *! DESCRIPTION : see additional comments below -// *! OWNER NAME : Menlo Wuu Email: menlowuu@us.ibm.com -// *! BACKUP NAME : Mark Bellows Email: bellows@us.ibm.com -// *! ADDITIONAL COMMENTS : -// -// Header file for mss_scominit. -// -//------------------------------------------------------------------------------ -// Don't forget to create CVS comments when you check in your changes! -//------------------------------------------------------------------------------ -// CHANGE HISTORY: -//------------------------------------------------------------------------------ -// Version:| Author: | Date: | Comment: -//---------|----------|---------|----------------------------------------------- -// 1.7 | menlowuu |09-NOV-12| Removed mss_set_bbm_regs since now done in -// draminit_training -// 1.6 | menlowuu |15-AUG-12| added bad bitmask function -// 1.5 |bellows |16-JUL-12| added in Id tag -// 1.4 | menlowuu |20-JUN-12| added type to the typedef -// 1.3 | menlowuu |13-JUN-12| added & to reference i_target in FP_t function -// added comment expecting centaur target -// 1.2 | menlowuu |06-JUN-12| Removed char* parameter for function -// 0.1 | menlowuu |01-DEC-11| First Draft. - - -#ifndef MSS_SCOMINIT_H_ -#define MSS_SCOMINIT_H_ - -//---------------------------------------------------------------------- -// My Includes -//---------------------------------------------------------------------- - - -//---------------------------------------------------------------------- -// Includes -//---------------------------------------------------------------------- -#include <fapi.H> - -typedef fapi::ReturnCode (*mss_scominit_FP_t)(const fapi::Target & i_target); - -extern "C" { - -//****************************************************************************** -// mss_scominit -//****************************************************************************** -// mss_scominit procedure [Calls the vaious memory initfiles] -// param[in] i_target [Reference to target, expecting centaur(MEMBUF) target] -// return ReturnCode - -fapi::ReturnCode mss_scominit(const fapi::Target & i_target); - -} // extern "C" - -#endif // MSS_SCOMINIT_H_ diff --git a/src/usr/hwpf/hwp/dram_training/mss_termination_control.C b/src/usr/hwpf/hwp/dram_training/mss_termination_control.C deleted file mode 100644 index c18bce0dd..000000000 --- a/src/usr/hwpf/hwp/dram_training/mss_termination_control.C +++ /dev/null @@ -1,1620 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/dram_training/mss_termination_control.C $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2012,2014 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: mss_termination_control.C,v 1.27 2014/02/25 21:08:15 mwuu Exp $ -/* File is created by SARAVANAN SETHURAMAN on Thur 29 Sept 2011. */ - -//------------------------------------------------------------------------------ -// *! (C) Copyright International Business Machines Corp. 2007 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -//------------------------------------------------------------------------------ -// *! TITLE :mss_draminit_training_advanced.C -// *! DESCRIPTION : Tools for centaur procedures -// *! OWNER NAME : Saravanan Sethuraman email ID:saravanans@in.ibm.com -// *! BACKUP NAME: Menlo Wuu email ID:menlowuu@us.ibm.com -// #! ADDITIONAL COMMENTS : -// -// General purpose funcs - -//------------------------------------------------------------------------------ -// Don't forget to create CVS comments when you check in your changes! -//------------------------------------------------------------------------------ -// CHANGE HISTORY: -//------------------------------------------------------------------------------ -// Version:| Author: | Date: | Comment: -//---------|----------|---------|----------------------------------------------- -// 1.27 | mwuu |25-Feb-14| Fixed setting opposite port slew values in -// | | | config_slew_rate -// 1.26 | mjjones |31-Jan-14| RAS Reviewed -// 1.25 | mjjones |22-Jan-14| Removed firmware header -// 1.24 | abhijsau |21-Jan-14| mike and menlo fixed ras review comments -// 1.23 | bellows |02-Dec-13| VPD attribute update -// 1.22 | mwuu |20-Sep-13| Updated ADR DDR3 slew calibration table for 1 setting, -// 1066 20ohms, 4V/ns, changed from 11 to 10. -// 1.21 | sasethur |16-Apr-13| Added DDR4 settings for rd_vref -// 1.20 | sasethur |09-Apr-13| Changed wr_vref register settings as per ddr3spec -// 1.19 | sasethur |05-Apr-13| Updated for port in parallel -// 1.18 | mwuu |25-Feb-13| Added return code per port for config slew FN -// 1.17 | mwuu |07-Feb-13| Improved the debug and trace messages. -// 1.16 | mwuu |24-Jan-13| Fixed cal_slew extraction of bits. -// 1.15 | mwuu |14-Jan-13| Altered error message for unsupported slew rate -// 1.14 | mwuu |14-Jan-13| Removed error messages from slew cal fail when -// | | | in SIM and using unsupported slew rates. -// 1.13 | mwuu |18-Dec-12| Took out initialization of array_rcs in declaration. -// 1.12 | mwuu |14-Dec-12| Updated additional fw review comments -// 1.11 | sasethur |07-Dec-12| Updated for fw review comments -// 1.10 | mwuu |28-Nov-12| Added changes suggested from FW team. -// 1.9 | mwuu |20-Nov-12| Changed warning status to not cause error. -// 1.8 | sasethur |19-Nov-12| Updated for fw review comments -// 1.7 | mwuu |14-Nov-12| Switched some old attributes to new, added -// Partial good support in slew_cal FN. -// 1.6 | bellows |13-Nov-12| SI attribute Updates -// 1.5 | mwuu |29-Oct-12| fixed config_drv_imp missed a '&' -// 1.4 | mwuu |26-Oct-12| Added mss_slew_cal FN, not 100% complete -// 1.3 | sasethur |26-Oct-12| Updated FW review comments - fapi::, const fapi:: Target -// 1.2 | mwuu |17-Oct-12| Updated return codes to use common error, also -// | | | updates to the slew function -// 1.1 | sasethur |15-Oct-12| Functions defined & moved from training adv, -// Menlo upated slew function - -// Saravanan - Yet to update DRV_IMP new attribute enum change - -// Not supported -// DDR4, DIMM Types -//---------------------------------------------------------------------- -// Includes - FAPI -//---------------------------------------------------------------------- - -#include <fapi.H> - -//---------------------------------------------------------------------- -//Centaur functions -//---------------------------------------------------------------------- -#include <mss_termination_control.H> -#include <cen_scom_addresses.H> -#include <mss_draminit_training_advanced.H> - -/*------------------------------------------------------------------------------ - * Function: config_drv_imp() - * This function will configure the Driver impedance values to the registers - * - * Parameters: target: mba; port: 0, 1 - * Driver_imp: OHM24 = 24, OHM30 = 30, OHM34 = 34, OHM40 = 40 - * ---------------------------------------------------------------------------*/ - -fapi::ReturnCode config_drv_imp(const fapi::Target & i_target_mba, uint8_t i_port, uint8_t i_drv_imp_dq_dqs) -{ - - ecmdDataBufferBase data_buffer(64); - fapi::ReturnCode rc; - uint32_t rc_num = 0; - uint8_t enslice_drv = 0xFF; - uint8_t enslice_ffedrv = 0xF; - uint8_t i = 0; - - //Driver impedance settings are per PORT basis - - if (i_port > 1) - { - FAPI_ERR("Driver impedance port input(%u) out of bounds", i_port); - const uint8_t & PORT_PARAM = i_port; - FAPI_SET_HWP_ERROR(rc, RC_CONFIG_DRV_IMP_INVALID_INPUT); - return rc; - } - for(i=0; i< MAX_DRV_IMP; i++) - { - if (drv_imp_array[i] == i_drv_imp_dq_dqs) - { - switch (i) - { - case 0: //40 ohms - enslice_drv = 0x3C; - enslice_ffedrv =0xF; - break; - case 1: //34 ohms - enslice_drv = 0x7C; - enslice_ffedrv =0xF; - break; - case 2: //30 ohms - enslice_drv = 0x7E; - enslice_ffedrv = 0xF; - break; - case 3: //24 ohms - enslice_drv = 0xFF; - enslice_ffedrv = 0xF; - break; - } - break; - } - } - - rc = fapiGetScom(i_target_mba, - DPHY01_DDRPHY_DP18_IO_TX_NFET_SLICE_P0_0_0x800000780301143F, - data_buffer); if(rc) return rc; - rc_num = data_buffer.insertFromRight(enslice_drv,48,8); - rc_num = rc_num | data_buffer.insertFromRight(enslice_ffedrv,56,4); - if (rc_num) - { - FAPI_ERR( "config_drv_imp: Error in setting up buffer "); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_IO_TX_NFET_SLICE_P0_0_0x800000780301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_IO_TX_NFET_SLICE_P0_1_0x800004780301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_IO_TX_NFET_SLICE_P0_2_0x800008780301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_IO_TX_NFET_SLICE_P0_3_0x80000C780301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_IO_TX_NFET_SLICE_P0_4_0x800010780301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_IO_TX_PFET_SLICE_P0_0_0x800000790301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_IO_TX_PFET_SLICE_P0_1_0x800004790301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_IO_TX_PFET_SLICE_P0_2_0x800008790301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_IO_TX_PFET_SLICE_P0_3_0x80000C790301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_IO_TX_PFET_SLICE_P0_4_0x800010790301143F, - data_buffer); if(rc) return rc; - - rc = fapiGetScom(i_target_mba, - DPHY01_DDRPHY_DP18_IO_TX_NFET_SLICE_P1_0_0x800100780301143F, - data_buffer); if(rc) return rc; - rc_num = data_buffer.insertFromRight(enslice_drv,48,8); - rc_num = rc_num | data_buffer.insertFromRight(enslice_ffedrv,56,4); - if (rc_num) - { - FAPI_ERR( "config_drv_imp: Error in setting up buffer "); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_IO_TX_NFET_SLICE_P1_0_0x800100780301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_IO_TX_NFET_SLICE_P1_1_0x800104780301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_IO_TX_NFET_SLICE_P1_2_0x800108780301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_IO_TX_NFET_SLICE_P1_3_0x80010C780301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_IO_TX_NFET_SLICE_P1_4_0x800110780301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_IO_TX_PFET_SLICE_P1_0_0x800100790301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_IO_TX_PFET_SLICE_P1_1_0x800104790301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_IO_TX_PFET_SLICE_P1_2_0x800108790301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_IO_TX_PFET_SLICE_P1_3_0x80010C790301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_IO_TX_PFET_SLICE_P1_4_0x800110790301143F, - data_buffer); if(rc) return rc; - return rc; -} - - -/*------------------------------------------------------------------------------ - * Function: config_rcv_imp() - * This function will configure the Receiver impedance values to the registers - * - * Parameters: target: mba; port: 0, 1 - * receiver_imp:OHM15 = 15, OHM20 = 20, OHM30 = 30, OHM40 = 40, OHM48 = 48, - * OHM60 = 60, OHM80 = 80, OHM120 = 120, OHM160 = 160, OHM240 = 240 - * ---------------------------------------------------------------------------*/ - -fapi::ReturnCode config_rcv_imp(const fapi::Target & i_target_mba, uint8_t i_port, uint8_t i_rcv_imp_dq_dqs) -{ - - ecmdDataBufferBase data_buffer(64); - fapi::ReturnCode rc; - uint32_t rc_num = 0; - uint8_t enslicepterm = 0xFF; - uint8_t enslicepffeterm = 0; - uint8_t i = 0; - - if (i_port > 1) - { - FAPI_ERR("Receiver impedance port input(%u) out of bounds", i_port); - const uint8_t & PORT_PARAM = i_port; - FAPI_SET_HWP_ERROR(rc, RC_CONFIG_RCV_IMP_INVALID_INPUT); - return rc; - } - - - for(i=0; i< MAX_RCV_IMP; i++) - { - if (rcv_imp_array[i] == i_rcv_imp_dq_dqs) - { - switch (i) - { - case 0: //120 OHMS - enslicepterm = 0x10; - enslicepffeterm =0x0; - break; - case 1: //80 OHMS - enslicepterm = 0x10; - enslicepffeterm =0x2; - break; - case 2: //60 OHMS - enslicepterm = 0x18; - enslicepffeterm =0x0; - break; - case 3: //48 OHMS - enslicepterm = 0x18; - enslicepffeterm =0x2; - break; - case 4: //40 OHMS - enslicepterm = 0x18; - enslicepffeterm =0x6; - break; - case 5: //34 OHMS - enslicepterm = 0x38; - enslicepffeterm =0x2; - break; - case 6: //30 OHMS - enslicepterm = 0x3C; - enslicepffeterm =0x0; - break; - case 7: //20 OHMS - enslicepterm = 0x7E; - enslicepffeterm = 0x0; - break; - case 8: //15 OHMS - enslicepterm = 0xFF; - enslicepffeterm = 0x0; - break; - } - break; - } - } - - - rc = fapiGetScom(i_target_mba, - DPHY01_DDRPHY_DP18_IO_TX_NFET_TERM_P0_0_0x8000007A0301143F, - data_buffer); if(rc) return rc; - rc_num = data_buffer.insertFromRight(enslicepterm,48,8); - rc_num = rc_num | data_buffer.insertFromRight(enslicepffeterm,56,4); - if (rc_num) - { - FAPI_ERR( "config_rcv_imp: Error in setting up buffer "); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_IO_TX_NFET_TERM_P0_0_0x8000007A0301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_IO_TX_NFET_TERM_P0_1_0x8000047A0301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_IO_TX_NFET_TERM_P0_2_0x8000087A0301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_IO_TX_NFET_TERM_P0_3_0x80000C7A0301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_IO_TX_NFET_TERM_P0_4_0x8000107A0301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_IO_TX_PFET_TERM_P0_0_0x8000007B0301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_IO_TX_PFET_TERM_P0_1_0x8000047B0301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_IO_TX_PFET_TERM_P0_2_0x8000087B0301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_IO_TX_PFET_TERM_P0_3_0x80000C7B0301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_IO_TX_PFET_TERM_P0_4_0x8000107B0301143F, - data_buffer); if(rc) return rc; - - rc = fapiGetScom(i_target_mba, - DPHY01_DDRPHY_DP18_IO_TX_NFET_TERM_P1_0_0x8001007A0301143F, - data_buffer); if(rc) return rc; - rc_num = data_buffer.insertFromRight(enslicepterm,48,8); - rc_num = rc_num | data_buffer.insertFromRight(enslicepffeterm,56,4); - if (rc_num) - { - FAPI_ERR( "config_rcv_imp: Error in setting up buffer "); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_IO_TX_NFET_TERM_P1_0_0x8001007A0301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_IO_TX_NFET_TERM_P1_1_0x8001047A0301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_IO_TX_NFET_TERM_P1_2_0x8001087A0301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_IO_TX_NFET_TERM_P1_3_0x80010C7A0301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_IO_TX_NFET_TERM_P1_4_0x8001107A0301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_IO_TX_PFET_TERM_P1_0_0x8001007B0301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_IO_TX_PFET_TERM_P1_1_0x8001047B0301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_IO_TX_PFET_TERM_P1_2_0x8001087B0301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_IO_TX_PFET_TERM_P1_3_0x80010C7B0301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_IO_TX_PFET_TERM_P1_4_0x8001107B0301143F, - data_buffer); if(rc) return rc; - return rc; -} - -/*------------------------------------------------------------------------------ - * Function: config_slew_rate() - * This function will configure the Slew rate values to the registers - * - * Parameters: target: mba; port: 0, 1 - * i_slew_type: SLEW_TYPE_DATA=0, SLEW_TYPE_ADR_ADDR=1, SLEW_TYPE_ADR_CNTL=2 - * i_slew_imp: OHM15=15, OHM20=20, OHM24=24, OHM30=30, OHM34=34, OHM40=40 - * note: 15, 20, 30, 40 valid for ADR; 24, 30, 34, 40 valid for DATA - * i_slew_rate: SLEW_3V_NS=3, SLEW_4V_NS=4, SLEW_5V_NS=5, SLEW_6V_NS=6, - * SLEW_MAXV_NS=7 (note SLEW_MAXV_NS bypasses slew calibration.) - * ---------------------------------------------------------------------------*/ -fapi::ReturnCode config_slew_rate(const fapi::Target & i_target_mba, - const uint8_t i_port, const uint8_t i_slew_type, const uint8_t i_slew_imp, - const uint8_t i_slew_rate) -{ - fapi::ReturnCode rc; - ecmdDataBufferBase data_buffer(64); - uint32_t rc_num = 0; - uint8_t slew_cal_value = 0; - uint8_t imp_idx = 255; - uint8_t slew_idx = 255; - // array for ATTR_MSS_SLEW_RATE_DATA/ADR [2][4][4] - // port,imp,slew_rat cal'd slew settings - uint8_t calibrated_slew_rate_table - [MAX_NUM_PORTS][MAX_NUM_IMP][MAX_NUM_CAL_SLEW_RATES]={{{0}}}; - - // FFDC for bad parameters - const uint8_t & PORT_PARAM = i_port; - const uint8_t & SLEW_TYPE_PARAM = i_slew_type; - const uint8_t & SLEW_IMP_PARAM = i_slew_imp; - const uint8_t & SLEW_RATE_PARAM = i_slew_rate; - - if (i_port >= MAX_NUM_PORTS) - { - FAPI_ERR("Slew port input(%u) out of bounds", i_port); - FAPI_SET_HWP_ERROR(rc, RC_CONFIG_SLEW_RATE_INVALID_INPUT); - return rc; - } - - if (i_slew_type >= MAX_NUM_SLEW_TYPES) - { - FAPI_ERR("Slew type input(%u) out of bounds, (>= %u)", - i_slew_type, MAX_NUM_SLEW_TYPES); - FAPI_SET_HWP_ERROR(rc, RC_CONFIG_SLEW_RATE_INVALID_INPUT); - return rc; - } - - switch (i_slew_rate) // get slew index - { - case SLEW_MAXV_NS: // max slew - FAPI_INF("Slew rate is set to MAX, using bypass mode"); - slew_cal_value = 0; // slew cal value for bypass mode - break; - case SLEW_6V_NS: - slew_idx = 3; - break; - case SLEW_5V_NS: - slew_idx = 2; - break; - case SLEW_4V_NS: - slew_idx = 1; - break; - case SLEW_3V_NS: - slew_idx = 0; - break; - default: - FAPI_ERR("Slew rate input(%u) out of bounds", i_slew_rate); - FAPI_SET_HWP_ERROR(rc, RC_CONFIG_SLEW_RATE_INVALID_INPUT); - return rc; - } - - if (i_slew_type == SLEW_TYPE_DATA) - { - switch (i_slew_imp) // get impedance index for data - { - case OHM40: - imp_idx = 3; - break; - case OHM34: - imp_idx = 2; - break; - case OHM30: - imp_idx = 1; - break; - case OHM24: - imp_idx = 0; - break; - default: // OHM15 || OHM20 not valid for data - FAPI_ERR("Slew impedance input(%u) invalid " - "or out of bounds, index=%u", i_slew_imp, imp_idx); - FAPI_SET_HWP_ERROR(rc, RC_CONFIG_SLEW_RATE_INVALID_INPUT); - return rc; - } - - if (i_slew_rate != SLEW_MAXV_NS) - { - rc = FAPI_ATTR_GET(ATTR_MSS_SLEW_RATE_DATA, &i_target_mba, - calibrated_slew_rate_table); if(rc) return rc; - - slew_cal_value = - calibrated_slew_rate_table[i_port][imp_idx][slew_idx]; - } - - if (slew_cal_value > MAX_SLEW_VALUE) - { - FAPI_INF("WARNING: Slew rate(0x%02x) unsupported, " - "but continuing... !!", slew_cal_value); - slew_cal_value = slew_cal_value & 0x0F; - } - - FAPI_INF("Setting DATA (dq/dqs) slew register, imped=%i, slewrate=%i, " - "reg_val=0x%X", i_slew_imp, i_slew_rate, slew_cal_value); - - FAPI_DBG("port%u type=%u imp_idx=%u slew_idx=%u cal_slew=%u", - i_port, i_slew_type, imp_idx, slew_idx, slew_cal_value); - - if (i_port == 0) // port 0 dq/dqs slew - { - rc = fapiGetScom(i_target_mba, - DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P0_0_0x800000750301143F, - data_buffer); if(rc) return rc; - - rc_num |= data_buffer.insertFromRight(slew_cal_value, 56, 4); - if (rc_num) - { - FAPI_ERR("Error in setting up DATA slew buffer"); - rc.setEcmdError(rc_num); - return rc; - } - // switch this later to use broadcast address, 0x80003C750301143F P0_[0:4] - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P0_0_0x800000750301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P0_1_0x800004750301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P0_2_0x800008750301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P0_3_0x80000C750301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P0_4_0x800010750301143F, - data_buffer); if(rc) return rc; - } - else // port 1 dq/dqs slew - { - rc = fapiGetScom(i_target_mba, - DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P1_0_0x800100750301143F, - data_buffer); if(rc) return rc; - - rc_num |= data_buffer.insertFromRight(slew_cal_value, 56, 4); - if (rc_num) - { - FAPI_ERR("Error in setting up DATA slew buffer"); - rc.setEcmdError(rc_num); - return rc; - } - // switch this later to use broadcast address, 0x80013C750301143F P1_[0:4] - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P1_0_0x800100750301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P1_1_0x800104750301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P1_2_0x800108750301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P1_3_0x80010C750301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P1_4_0x800110750301143F, - data_buffer); if(rc) return rc; - } - } // end DATA - else // Slew type = ADR - { - uint8_t adr_pos = 48; // SLEW_CTL0(48:51) of reg for ADR command slew - - for(uint8_t i=0; i < MAX_NUM_IMP; i++) // find ADR imp index - { - if (adr_imp_array[i] == i_slew_imp) - { - imp_idx = i; - break; - } - } - if ((i_slew_imp == OHM24) || (i_slew_imp == OHM34) || - (imp_idx >= MAX_NUM_IMP)) - { - FAPI_ERR("Slew impedance input(%u) out of bounds", i_slew_imp); - FAPI_SET_HWP_ERROR(rc, RC_CONFIG_SLEW_RATE_INVALID_INPUT); - return rc; - } - - if (i_slew_rate == SLEW_MAXV_NS) - { - slew_cal_value = 0; - } - else - { - rc = FAPI_ATTR_GET(ATTR_MSS_SLEW_RATE_ADR, &i_target_mba, - calibrated_slew_rate_table); if(rc) return rc; - - slew_cal_value = - calibrated_slew_rate_table[i_port][imp_idx][slew_idx]; - } - - if (slew_cal_value > MAX_SLEW_VALUE) - { - FAPI_INF("!! Slew rate(0x%02x) unsupported, but continuing... !!", - slew_cal_value); - slew_cal_value = slew_cal_value & 0x0F; - } - - switch (i_slew_type) // get impedance index for data - { - case SLEW_TYPE_ADR_ADDR: - // CTL0 for command slew (A0:15, BA0:3, ACT, PAR, CAS, RAS, WE) - FAPI_INF("Setting ADR command/address slew in CTL0 register " - "imped=%i, slewrate=%i, reg_val=0x%X", i_slew_imp, - i_slew_rate, slew_cal_value); - adr_pos = 48; - break; - case SLEW_TYPE_ADR_CNTL: - // CTL1 for control slew (CKE0:1, CKE4:5, ODT0:3, CSN0:3) - FAPI_INF("Setting ADR control slew in CTL1 register " - "imped=%i, slewrate=%i, reg_val=0x%X", i_slew_imp, - i_slew_rate, slew_cal_value); - adr_pos = 52; - break; - case SLEW_TYPE_ADR_CLK: - // CTL2 for clock slew (CLK0:3) - FAPI_INF("Setting ADR clock slew in CTL2 register " - "imped=%i, slewrate=%i, reg_val=0x%X", i_slew_imp, - i_slew_rate, slew_cal_value); - adr_pos = 56; - break; - case SLEW_TYPE_ADR_SPCKE: - // CTL3 for spare clock slew (CKE2:3) - FAPI_INF("Setting ADR Spare clock in CTL3 register " - "imped=%i, slewrate=%i, reg_val=0x%X", i_slew_imp, - i_slew_rate, slew_cal_value); - adr_pos = 60; - break; - } - - FAPI_DBG("port%u type=%u slew_idx=%u imp_idx=%u cal_slew=%u", - i_port, i_slew_type, slew_idx, imp_idx, slew_cal_value); - - if (i_port == 0) // port 0 adr slew - { - rc = fapiGetScom(i_target_mba, - DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P0_ADR0_0x8000401A0301143F, - data_buffer); if(rc) return rc; - - rc_num |= data_buffer.insertFromRight(slew_cal_value, adr_pos, 4); - if (rc_num) - { - FAPI_ERR( "Error in setting up ADR slew buffer"); - rc.setEcmdError(rc_num); - return rc; - } - // switch this later to use broadcast address, 0x80007C1A0301143f ADR[0:3] - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P0_ADR0_0x8000401A0301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P0_ADR1_0x8000441A0301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P0_ADR2_0x8000481A0301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P0_ADR3_0x80004C1A0301143F, - data_buffer); if(rc) return rc; - } - else // port 1 adr slew - { - rc = fapiGetScom(i_target_mba, - DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P1_ADR0_0x8001401A0301143F, - data_buffer); if(rc) return rc; - rc_num |= data_buffer.insertFromRight(slew_cal_value, adr_pos, 4); - if (rc_num) - { - FAPI_ERR( "Error in setting up ADR slew buffer"); - rc.setEcmdError(rc_num); - return rc; - } - // switch this later to use broadcast address, 0x80017C1A0301143f ADR[0:3] - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P1_ADR0_0x8001401A0301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P1_ADR1_0x8001441A0301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P1_ADR2_0x8001481A0301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P1_ADR3_0x80014C1A0301143F, - data_buffer); if(rc) return rc; - } - } // end ADR - return rc; -} - -/*------------------------------------------------------------------------------ - * Function: config_wr_dram_vref() - * This function configures PC_VREF_DRV_CONTROL registers to vary the DIMM VREF - * - * Parameters: target: mba; port: 0, 1 - * Wr_dram_vref: VDD420 = 420, VDD425 = 425, VDD430 = 430, VDD435 = 435, VDD440 = 440, - * VDD445 = 445, VDD450 = 450, VDD455 = 455, VDD460 = 460, VDD465 = 465, VDD470 = 470, - * VDD475 = 475, VDD480 = 480, VDD485 = 485, VDD490 = 490, VDD495 = 495, VDD500 = 500, - * VDD505 = 505, VDD510 = 510, VDD515 = 515, VDD520 = 520, VDD525 = 525, VDD530 = 530, - * VDD535 = 535, VDD540 = 540, VDD545 = 545, VDD550 = 550, VDD555 = 555, VDD560 = 560, - * VDD565 = 565, VDD570 = 570, VDD575 = 575 - * ---------------------------------------------------------------------------*/ - -fapi::ReturnCode config_wr_dram_vref(const fapi::Target & i_target_mba, uint8_t i_port, uint32_t i_wr_dram_vref) -{ - - ecmdDataBufferBase data_buffer(64); - fapi::ReturnCode rc; - uint32_t rc_num = 0; - uint32_t pcvref = 0; - uint32_t sign = 0; - - // For DDR3 vary from VDD*0.42 to VDD*575 - // For DDR4 internal voltage is there this function is not required - if (i_port > 1) - { - FAPI_ERR("Write Vref port input(%u) out of bounds", i_port); - const uint8_t & PORT_PARAM = i_port; - FAPI_SET_HWP_ERROR(rc, RC_CONFIG_WR_DRAM_VREF_INVALID_INPUT); - return rc; - } - - if(i_wr_dram_vref < 500) - { - sign = 1; - } - else - { - sign = 0; - } - if((i_wr_dram_vref == 420) || (i_wr_dram_vref == 575)) - { - pcvref = 0xF; - } - else if((i_wr_dram_vref == 425) || (i_wr_dram_vref == 570)) - { - pcvref = 0x7; - } - else if((i_wr_dram_vref == 430) || (i_wr_dram_vref == 565)) - { - pcvref = 0xB; - } - else if((i_wr_dram_vref == 435) || (i_wr_dram_vref == 560)) - { - pcvref = 0x3; - } - else if((i_wr_dram_vref == 440) || (i_wr_dram_vref == 555)) - { - pcvref = 0xD; - } - else if((i_wr_dram_vref == 445) || (i_wr_dram_vref == 550)) - { - pcvref = 0x5; - } - else if((i_wr_dram_vref == 450) || (i_wr_dram_vref == 545)) - { - pcvref = 0x9; - } - else if((i_wr_dram_vref == 455) || (i_wr_dram_vref == 540)) - { - pcvref = 0x1; - } - else if((i_wr_dram_vref == 460) || (i_wr_dram_vref == 535)) - { - pcvref = 0xE; - } - else if((i_wr_dram_vref == 465) || (i_wr_dram_vref == 530)) - { - pcvref = 0x6; - } - else if((i_wr_dram_vref == 470) || (i_wr_dram_vref == 525)) - { - pcvref = 0xA; - } - else if((i_wr_dram_vref == 475) || (i_wr_dram_vref == 520)) - { - pcvref = 0x2; - } - else if((i_wr_dram_vref == 480) || (i_wr_dram_vref == 515)) - { - pcvref = 0xC; - } - else if((i_wr_dram_vref == 485) || (i_wr_dram_vref == 510)) - { - pcvref = 0x4; - } - else if((i_wr_dram_vref == 490) || (i_wr_dram_vref == 505)) - { - pcvref = 0x8; - } - else if((i_wr_dram_vref == 495) || (i_wr_dram_vref == 500)) - { - pcvref = 0x0; - } - - rc = fapiGetScom(i_target_mba, DPHY01_DDRPHY_PC_VREF_DRV_CONTROL_P0_0x8000C0150301143F, data_buffer); if(rc) return rc; - rc_num = rc_num | data_buffer.insertFromRight(sign,48,1); - rc_num = rc_num | data_buffer.insertFromRight(sign,53,1); - rc_num = rc_num | data_buffer.insertFromRight(pcvref,49,4); - rc_num = rc_num | data_buffer.insertFromRight(pcvref,54,4); - if (rc_num) - { - FAPI_ERR( "config_wr_vref: Error in setting up buffer "); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, DPHY01_DDRPHY_PC_VREF_DRV_CONTROL_P0_0x8000C0150301143F, data_buffer); if(rc) return rc; - rc_num = rc_num | data_buffer.insertFromRight(sign,48,1); - rc_num = rc_num | data_buffer.insertFromRight(sign,53,1); - rc_num = rc_num | data_buffer.insertFromRight(pcvref,49,4); - rc_num = rc_num | data_buffer.insertFromRight(pcvref,54,4); - if (rc_num) - { - FAPI_ERR( "config_wr_vref: Error in setting up buffer "); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, DPHY01_DDRPHY_PC_VREF_DRV_CONTROL_P1_0x8001C0150301143F, data_buffer); if(rc) return rc; - return rc; -} -/*------------------------------------------------------------------------------ - * Function: config_rd_cen_vref() - * This function configures read vref registers to vary the CEN VREF - * - * Parameters: target: mba; port: 0, 1 - * Rd_cen_Vref: VDD40375 = 40375, VDD41750 = 41750, VDD43125 = 43125, VDD44500 = 44500, - * VDD45875 = 45875, VDD47250 = 47250, VDD48625 = 48625, VDD50000 = 50000, VDD51375 = 51375, - * VDD52750 = 52750, VDD54125 = 54125, VDD55500 = 55500, VDD56875 = 56875, VDD58250 = 58250, - * VDD59625 = 59625, VDD61000 = 61000, VDD60375 = 60375, VDD61750 = 61750, VDD63125 = 63125, - * VDD64500 = 64500, VDD65875 = 65875, VDD67250 = 67250, VDD68625 = 68625, VDD70000 = 70000, - * VDD71375 = 71375, VDD72750 = 72750, VDD74125 = 74125, VDD75500 = 75500, VDD76875 = 76875, - * VDD78250 = 78250, VDD79625 = 79625, VDD81000 = 81000 - * DDR3 supports upto 61000, DDR4 - full range - * ---------------------------------------------------------------------------*/ - -fapi::ReturnCode config_rd_cen_vref (const fapi::Target & i_target_mba, uint8_t i_port, uint32_t i_rd_cen_vref) -{ - - ecmdDataBufferBase data_buffer(64); - fapi::ReturnCode rc; - uint32_t rc_num = 0; - uint32_t rd_vref = 0; - - if (i_port > 1) - { - FAPI_ERR("Read vref port input(%u) out of bounds", i_port); - const uint8_t & PORT_PARAM = i_port; - FAPI_SET_HWP_ERROR(rc, RC_CONFIG_RD_CEN_VREF_INVALID_INPUT); - return rc; - } - - //if (rd_cen_vref == DDR3 rd_vref ) || (rd_cen_vref == DDR4) - - if((i_rd_cen_vref == 61000) || (i_rd_cen_vref == 81000)) - { - rd_vref = 0xF; - } - else if((i_rd_cen_vref == 59625) || (i_rd_cen_vref == 79625)) - { - rd_vref = 0xE; - } - else if((i_rd_cen_vref == 58250) || (i_rd_cen_vref == 78250)) - { - rd_vref = 0xD; - } - else if((i_rd_cen_vref == 56875) || (i_rd_cen_vref == 76875)) - { - rd_vref = 0xC; - } - else if((i_rd_cen_vref == 55500) || (i_rd_cen_vref == 75500)) - { - rd_vref = 0xB; - } - else if((i_rd_cen_vref == 54125) || (i_rd_cen_vref == 74125)) - { - rd_vref = 0xA; - } - else if((i_rd_cen_vref == 52750) || (i_rd_cen_vref == 72750)) - { - rd_vref = 0x9; - } - else if((i_rd_cen_vref == 51375) || (i_rd_cen_vref == 71375)) - { - rd_vref = 0x8; - } - else if((i_rd_cen_vref == 50000) || (i_rd_cen_vref == 70000)) - { - rd_vref = 0x0; - } - else if((i_rd_cen_vref == 48625) || (i_rd_cen_vref == 68625)) - { - rd_vref = 0x1; - } - else if((i_rd_cen_vref == 47250) || (i_rd_cen_vref == 67250)) - { - rd_vref = 0x2; - } - else if((i_rd_cen_vref == 45875) || (i_rd_cen_vref == 65875)) - { - rd_vref = 0x3; - } - else if((i_rd_cen_vref == 44500) || (i_rd_cen_vref == 64500)) - { - rd_vref = 0x4; - } - else if((i_rd_cen_vref == 43125) || (i_rd_cen_vref == 63125)) - { - rd_vref = 0x5; - } - else if((i_rd_cen_vref == 41750) || (i_rd_cen_vref == 61750)) - { - rd_vref = 0x6; - } - else if((i_rd_cen_vref == 40375) || (i_rd_cen_vref == 60375)) - { - rd_vref = 0x7; - } - else - { - rd_vref = 0x0; - } - - rc = fapiGetScom(i_target_mba, - DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P0_0_0x800000060301143F, - data_buffer); if(rc) return rc; - rc_num = rc_num | data_buffer.insertFromRight(rd_vref,56,4); - if (rc_num) - { - FAPI_ERR( "config_rd_vref: Error in setting up buffer "); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P0_0_0x800000060301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P0_1_0x800004060301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P0_2_0x800008060301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P0_3_0x80000c060301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P0_4_0x800010060301143F, - data_buffer); if(rc) return rc; - rc = fapiGetScom(i_target_mba, - DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P1_0_0x800100060301143F, - data_buffer); if(rc) return rc; - rc_num = rc_num | data_buffer.insertFromRight(rd_vref,56,4); - if (rc_num) - { - FAPI_ERR( "config_rd_vref: Error in setting up buffer "); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P1_0_0x800100060301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P1_1_0x800104060301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P1_2_0x800108060301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P1_3_0x80010c060301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P1_4_0x800110060301143F, - data_buffer); if(rc) return rc; - return rc; -} -/*------------------------------------------------------------------------------ - * Function: mss_slew_cal() - * This function runs the slew calibration engine to configure MSS_SLEW_DATA/ADR - * attributes and calls config_slew_rate to set the slew rate in the registers. - * - * Parameters: target: mba; - * ---------------------------------------------------------------------------*/ - -fapi::ReturnCode mss_slew_cal(const fapi::Target &i_target_mba) -{ - fapi::ReturnCode rc; - uint32_t rc_ecmd = 0; - fapi::ReturnCode array_rcs[MAX_NUM_PORTS]; // capture rc per port loop - uint32_t poll_count = 0; - uint8_t ports_valid = 0; - uint8_t is_sim = 0; - - uint8_t freq_idx = 0; // freq index into lookup table - uint32_t ddr_freq = 0; // current ddr freq - uint8_t ddr_idx = 0; // ddr type index into lookup table - uint8_t ddr_type = 0; // ATTR_EFF_DRAM_GEN{0=invalid, 1=ddr3, 2=ddr4} - - uint8_t cal_status = 0; - // bypass slew (MAX slew rate) not included since it is not calibrated. - // for output ATTR_MSS_SLEW_RATE_DATA(0), - // ATTR_MSS_SLEW_RATE_ADR(1), [port=2][imp=4][slew=4] - uint8_t calibrated_slew[2][MAX_NUM_PORTS][MAX_NUM_IMP] - [MAX_NUM_CAL_SLEW_RATES] = {{{{ 0 }}}}; - - fapi::Target l_target_centaur; // temporary target for parent - - ecmdDataBufferBase ctl_reg(64); - ecmdDataBufferBase stat_reg(64); - - // DD level 1.0-1.1, Version 1.0 - // [ddr3/4][dq/adr][speed][impedance][slew_rate] - // note: Assumes standard voltage for DDR3(1.35V), DDR4(1.2V), - // little endian, if >=128, lab only debug. - // - // ddr_type(2) ddr3=0, ddr4=1 - // data/adr(2) data(dq/dqs)=0, adr(cmd/cntl)=1 - // speed(4) 1066=0, 1333=1, 1600=2, 1866=3 - // imped(4) 24ohms=0, 30ohms=1, 34ohms=2, 40ohms=3 for DQ/DQS - // imped(4) 15ohms=0, 20ohms=1, 30ohms=2, 40ohms=3 for ADR driver - // slew(3) 3V/ns=0, 4V/ns=1, 5V/ns=2, 6V/ns=3 - const uint8_t slew_table[2][2][4][4][4] = { -// NOTE: bit 7 = unsupported slew, and actual value is in bits 4:0 - -/* DDR3(0) */ - { { - // dq/dqs(0) -/* Imp. ________24ohms______..________30ohms______..________34ohms______..________40ohms______ - Slew 3 4 5 6 3 4 5 6 3 4 5 6 3 4 5 6 (V/ns) */ -/*1066*/{{ 12, 9, 7, 134}, { 13, 9, 7, 133}, { 13, 10, 7, 134}, { 14, 10, 7, 132}}, -/*1333*/{{ 15, 11, 8, 135}, { 16, 12, 9, 135}, { 17, 12, 9, 135}, { 17, 12, 8, 133}}, -/*1600*/{{ 18, 13, 10, 136}, { 19, 14, 10, 136}, { 20, 15, 11, 136}, { 21, 14, 10, 134}}, -/*1866*/{{149, 143, 140, 138}, {151, 144, 140, 137}, {151, 145, 141, 138}, {152, 145, 139, 135}} - }, { - // adr(1), -/* Imp. ________15ohms______..________20ohms______..________30ohms______..________40ohms______ - Slew 3 4 5 6 3 4 5 6 3 4 5 6 3 4 5 6 (V/ns) */ -// 1066 {{ 17, 13, 10, 8}, { 13, 11, 7, 6}, { 12, 8, 5, 131}, { 7, 4, 131, 131}}, // old before May 2013 -/*1066*/{{ 17, 13, 10, 8}, { 13, 10, 7, 6}, { 12, 8, 5, 131}, { 7, 4, 131, 131}}, -/*1333*/{{ 21, 16, 12, 10}, { 17, 12, 9, 7}, { 15, 10, 6, 132}, { 6, 5, 132, 132}}, -/*1600*/{{ 25, 19, 15, 12}, { 20, 14, 13, 8}, { 19, 12, 7, 133}, { 7, 6, 133, 133}}, -/*1866*/{{157, 150, 145, 142}, {151, 145, 141, 138}, {150, 142, 136, 134}, {141, 134, 134, 134}} - } }, -/* DDR4(1) ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */ - { { - // dq/dqs(0) -/* Imp. ________24ohms______..________30ohms______..________34ohms______..________40ohms______ - Slew 3 4 5 6 3 4 5 6 3 4 5 6 3 4 5 6 (V/ns) */ -/*1066*/{{138, 135, 134, 133}, {139, 136, 134, 132}, {140, 136, 134, 132}, {140, 136, 132, 132}}, -/*1333*/{{139, 137, 135, 134}, {142, 138, 135, 133}, {143, 138, 135, 133}, {143, 138, 133, 132}}, -/*1600*/{{ 15, 11, 9, 135}, { 17, 11, 9, 135}, { 18, 13, 9, 134}, { 18, 11, 6, 133}}, -/*1866*/{{ 18, 13, 10, 137}, { 19, 13, 10, 136}, { 21, 15, 10, 135}, { 21, 13, 8, 134}} - }, { - // adr(1) -/* Imp. ________15ohms______..________20ohms______..________30ohms______..________40ohms______ - Slew 3 4 5 6 3 4 5 6 3 4 5 6 3 4 5 6 (V/ns) */ -/*1066*/{{142, 139, 136, 134}, {140, 136, 134, 133}, {138, 134, 131, 131}, {133, 131, 131, 131}}, -/*1333*/{{145, 142, 139, 136}, {143, 138, 135, 134}, {140, 135, 132, 132}, {134, 132, 132, 132}}, -/*1600*/{{ 21, 16, 13, 10}, { 18, 12, 9, 135}, { 15, 8, 133, 133}, { 7, 133, 133, 133}}, -/*1866*/{{ 24, 19, 15, 11}, { 21, 14, 10, 136}, { 17, 10, 134, 134}, { 9, 134, 134, 134}} - } } - }; - - // slew calibration control register - const uint64_t slew_cal_cntl[] = { - DPHY01_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S0_0x800080390301143F, // port 0 - DPHY01_DDRPHY_ADR_SLEW_CAL_CNTL_P1_ADR32S0_0x800180390301143F // port 1 - }; - // slew calibration status registers - const uint64_t slew_cal_stat[] = { - DPHY01_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S0_0x800080340301143F, - DPHY01_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P1_ADR32S0_0x800180340301143F - }; - const uint8_t ENABLE_BIT = 48; - const uint8_t START_BIT = 49; - const uint8_t BB_LOCK_BIT = 56; - // general purpose 100 ns delay for HW mode (2000 sim cycles if simclk = 20ghz) - const uint16_t DELAY_100NS = 100; - const uint16_t DELAY_2000NCLKS = 4000; // roughly 2000 nclks if DDR freq >= 1066 - // normally 2000, but since cal doesn't work in SIM, setting to 1 - const uint16_t DELAY_SIMCYCLES = 1; - const uint8_t MAX_POLL_LOOPS = 20; - - // verify which ports are functional - rc = FAPI_ATTR_GET(ATTR_MSS_EFF_DIMM_FUNCTIONAL_VECTOR, - &i_target_mba, ports_valid); - if (rc) - { - FAPI_ERR("Failed to get attribute: " - "ATTR_MSS_EFF_DIMM_FUNCTIONAL_VECTOR"); - return rc; - } - - // Check if in SIM - rc = FAPI_ATTR_GET(ATTR_IS_SIMULATION, NULL, is_sim); - if (rc) - { - FAPI_ERR("Failed to get attribute: ATTR_IS_SIMULATION"); - return rc; - } - // Get DDR type (DDR3 or DDR4) - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_GEN, &i_target_mba, ddr_type); - if (rc) - { - FAPI_ERR("Failed to get attribute: ATTR_EFF_DRAM_GEN"); - return rc; - } - // ddr_type(2) ddr3=0, ddr4=1 - if (ddr_type == fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR4) { //type=2 - ddr_idx = 1; - } else if (ddr_type == fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR3) { //type=1 - ddr_idx = 0; - } else { - FAPI_ERR("Invalid ATTR_DRAM_DRAM_GEN = %d, %s!", ddr_type, - i_target_mba.toEcmdString()); - const uint8_t & DRAM_GEN = ddr_type; - FAPI_SET_HWP_ERROR(rc, RC_MSS_SLEW_CAL_INVALID_DRAM_GEN); - return rc; - } - - // get freq from parent - rc = fapiGetParentChip(i_target_mba, l_target_centaur); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_MSS_FREQ, &l_target_centaur, ddr_freq); - if(rc) return rc; - - if (ddr_freq == 0) { - FAPI_ERR("Invalid ATTR_MSS_FREQ = %d on %s!", ddr_freq, - i_target_mba.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_SLEW_CAL_INVALID_FREQ); - return rc; - } - // speed(4) 1066=0, 1333=1, 1600=2, 1866=3 - if (ddr_freq > 1732) { - freq_idx= 3; // for 1866+ - } else if ((ddr_freq > 1460) && (ddr_freq <= 1732)) { - freq_idx = 2; // for 1600 - } else if ((ddr_freq > 1200) && (ddr_freq <= 1460)) { - freq_idx = 1; // for 1333 - } else { // (ddr_freq <= 1200) - freq_idx = 0; // for 1066- - } - - for (uint8_t l_port=0; l_port < MAX_NUM_PORTS; l_port++) - { - uint8_t port_val = (ports_valid & (0xF0 >> (4 * l_port))); - - if (port_val == 0) { - FAPI_INF("WARNING: port %u is invalid from " - "ATTR_MSS_EFF_DIMM_FUNCTIONAL_VECTOR (0x%02x), skipping.", - l_port, ports_valid); - continue; - } - // Step A: Configure ADR registers and MCLK detect (done in ddr_phy_reset) - // DPHY01_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S0_0x800080390301143F + port - rc = fapiGetScom(i_target_mba, slew_cal_cntl[l_port], ctl_reg); - if (rc) - { - FAPI_ERR("Error reading DDRPHY_ADR_SLEW_CAL_CNTL register."); - return rc; - } - - rc_ecmd = ctl_reg.flushTo0(); - rc_ecmd |= ctl_reg.setBit(ENABLE_BIT); // set enable (bit49) to 1 - if (rc_ecmd) - { - FAPI_ERR("Error setting enable bit in ADR Slew calibration " - "control register."); - rc.setEcmdError(rc_ecmd); - return rc; - } - - FAPI_INF("Enabling slew calibration engine on port %i: DDR%i(%u) " - "%u(%u) in %s", l_port, (ddr_type+2), ddr_idx, ddr_freq, - freq_idx, i_target_mba.toEcmdString()); - - // DPHY01_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S0_0x800080390301143F + port - rc = fapiPutScom(i_target_mba, slew_cal_cntl[l_port], ctl_reg); - if (rc) - { - FAPI_ERR("Error enabling slew calibration engine in " - "DDRPHY_ADR_SLEW_CAL_CNTL register."); - return rc; - } - // Note: must be 2000 nclks+ after setting enable bit - rc = fapiDelay(DELAY_2000NCLKS, 1); - if (rc) { - FAPI_ERR("Error executing fapiDelay of 2000 nclks or 1 simcycle"); - return rc; - } - - //---------------------------------------------------------------------/ - // Step 1. Check for BB lock. - FAPI_DBG("Wait for BB lock in status register, bit %u", BB_LOCK_BIT); - for (poll_count=0; poll_count < MAX_POLL_LOOPS; poll_count++) - { - rc = fapiDelay(DELAY_100NS, DELAY_SIMCYCLES); - if (rc) { - FAPI_ERR("Error executing fapiDelay of 100ns or 2000simcycles"); - return rc; - } - // DPHY01_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S0_0x800080340301143F + port - rc = fapiGetScom(i_target_mba, slew_cal_stat[l_port], stat_reg); - if (rc) - { - FAPI_ERR("Error reading DDRPHY_ADR_SYSCLK_PR_VALUE_RO register " - "for BB_Lock."); - return rc; - } - FAPI_DBG("stat_reg = 0x%04x, count=%i",stat_reg.getHalfWord(3), - poll_count); - - if (stat_reg.isBitSet(BB_LOCK_BIT)) break; - } - - if (poll_count == MAX_POLL_LOOPS) { - FAPI_INF("WARNING: Timeout on polling BB_Lock, continuing..."); - } - else - { - FAPI_DBG("polling finished in %i loops (%u ns)\n", - poll_count, (100*poll_count)); - } - - //---------------------------------------------------------------------/ - // Create calibrated slew settings - // dq/adr(2) dq/dqs=0, adr=1 - // slew(4) 3V/ns=0, 4V/ns=1, 5V/ns=2, 6V/ns=3 - for (uint8_t data_adr=0; data_adr < 2; data_adr++) - { - FAPI_INF("Starting %s(%i) slew calibration...", - (data_adr ? "ADR" : "DATA"), data_adr); - for (uint8_t imp=0; imp < MAX_NUM_IMP; imp++) - { - uint8_t cal_slew; - - for (uint8_t slew=0; slew < MAX_NUM_CAL_SLEW_RATES; slew++) - { - cal_slew = - slew_table[ddr_idx][data_adr][freq_idx][imp][slew]; - - // set slew phase rotator from slew_table - // slew_table[ddr3/4][dq/adr][freq][impedance][slew_rate] - rc_ecmd |= ctl_reg.insertFromRight(cal_slew, 59, 5); - - rc_ecmd |= ctl_reg.setBit(START_BIT); // set start bit(48) - if (rc_ecmd) - { - FAPI_ERR("Error setting start bit or cal input value."); - rc.setEcmdError(rc_ecmd); - return rc; - } - - FAPI_DBG("Slew data_adr=%i, imp_idx=%i, slewrate=%i, " - "i_slew=%i,0x%02X (59:63) cntl_reg(48:63)=0x%04X", - data_adr, imp, (slew+3), cal_slew, cal_slew, - ctl_reg.getHalfWord(3)); - - // DPHY01_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S0_0x800080390301143F + port - rc = fapiPutScom(i_target_mba, slew_cal_cntl[l_port], ctl_reg); - if (rc) - { - FAPI_ERR("Error starting slew calibration."); - return rc; - } - - // poll for calibration status done or timeout... - for (poll_count=0; poll_count < MAX_POLL_LOOPS; - poll_count++) - { - // DPHY01_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S0_0x800080340301143F + port - rc = fapiGetScom(i_target_mba, slew_cal_stat[l_port], - stat_reg); - if (rc) - { - FAPI_ERR("Error reading " - "DDRPHY_ADR_SYSCLK_PR_VALUE_RO " - "register for calibration status."); - return rc; - } - rc_ecmd = stat_reg.extractToRight(&cal_status, 58, 2); - if (rc_ecmd) - { - FAPI_ERR("Error getting calibration status bits"); - rc.setEcmdError(rc_ecmd); - return rc; - } - if (cal_status != 0) - break; - // wait (1020 mclks / MAX_POLL_LOOPS) - rc = fapiDelay(DELAY_100NS, DELAY_SIMCYCLES); - if(rc) - { - return rc; - } - } - - if (cal_status > 1) - { - if (cal_status == 3) - { - FAPI_DBG("slew calibration completed successfully," - " loop=%i input=0x%02x", poll_count, - (cal_slew & 0x1F)); - } - else if (cal_status == 2) - { - FAPI_INF("WARNING: occurred during slew calibration" - ", imped=%i, slewrate=%i %s ddr_idx[%i]", - data_adr ? adr_imp_array[imp] : - drv_imp_array[(4-imp)], (slew+3), - i_target_mba.toEcmdString(), ddr_idx); - FAPI_INF("data_adr[%i], freq_idx[%i], imp[%i], slew[%i]", - data_adr, freq_idx, imp, slew); - FAPI_INF("input=0x%02X, ctrl=0x%04X, status=0x%04X", - (cal_slew & 0x1F), ctl_reg.getHalfWord(3), - stat_reg.getHalfWord(3)); - } - cal_slew = cal_slew & 0x80; // clear bits 6:0 - rc_ecmd = stat_reg.extractPreserve(&cal_slew, 60, 4, 4); - FAPI_DBG("MSS_SLEW_RATE_%s port[%i]imp[%i]slew[%i] = " - "0x%02x\n", (data_adr ? "ADR" : "DATA"), l_port, - imp, slew, (cal_slew & 0xF)); - if (rc_ecmd) - { - FAPI_ERR("Error getting calibration output " - "slew value"); - rc.setEcmdError(rc_ecmd); - return rc; - } - calibrated_slew[data_adr][l_port][imp][slew] = cal_slew; - } - else - { - if (is_sim) { - // Calibration fails in sim since bb_lock not - // possible in cycle simulator, putting initial - // to be cal'd value in output table - FAPI_INF("In SIM setting input slew value in array" - ", status(%i) NOT clean.", cal_status); - calibrated_slew[data_adr][l_port][imp][slew] = - cal_slew; - } - else - { - FAPI_ERR("Slew calibration failed on %s slew: " - "imp_idx=%d(%i ohms)", - (data_adr ? "ADR" : "DATA"), imp, - (data_adr ? adr_imp_array[imp] : - drv_imp_array[(4-imp)])); - FAPI_ERR("slew_idx=%d(%i V/ns), slew_table=0x%02X", - slew, (slew+3), cal_slew); - FAPI_ERR("ctl_reg=0x%04X, status=0x%04X on %s!", - stat_reg.getHalfWord(3), - ctl_reg.getHalfWord(3), - i_target_mba.toEcmdString()); - - const uint8_t & DATA_ADR = data_adr; - const uint8_t & IMP = imp; - const uint8_t & SLEW = slew; - const fapi::Target & MBA_IN_ERROR = i_target_mba; - const ecmdDataBufferBase & STAT_REG = stat_reg; - - if (cal_status == 1) - { - if (l_port == 0) - { - FAPI_ERR("Error occurred during slew calibration on port 0"); - FAPI_SET_HWP_ERROR(rc, - RC_MSS_SLEW_CAL_ERROR_PORT0); - } - else - { - FAPI_ERR("Error occurred during slew calibration on port 1"); - FAPI_SET_HWP_ERROR(rc, - RC_MSS_SLEW_CAL_ERROR_PORT1); - } - } - else - { - if (l_port == 0) - { - FAPI_ERR("Slew calibration timed out on port 0, loop=%i", - poll_count); - FAPI_SET_HWP_ERROR(rc, - RC_MSS_SLEW_CAL_TIMEOUT_PORT0); - } - else - { - FAPI_ERR("Slew calibration timed out on port 1, loop=%i", - poll_count); - FAPI_SET_HWP_ERROR(rc, - RC_MSS_SLEW_CAL_TIMEOUT_PORT1); - } - } - - array_rcs[l_port]=rc; - continue; - } - } // end error check - } // end slew - } // end imp - } // end data_adr - - // disable calibration engine for port - ctl_reg.clearBit(ENABLE_BIT); - rc = fapiPutScom(i_target_mba, slew_cal_cntl[l_port], ctl_reg); - if (rc) - { - FAPI_ERR("Error disabling slew calibration engine in " - "DDRPHY_ADR_SLEW_CAL_CNTL register."); - return rc; - } - else - { - FAPI_INF("Finished slew calibration on port %i: " - "disabling cal engine\n", l_port); - } - } // end port loop - - for (uint8_t rn=0; rn < MAX_NUM_PORTS; rn++) - { - if (array_rcs[rn] != fapi::FAPI_RC_SUCCESS) - { - FAPI_ERR("Returning ERROR RC for port %u",rn); - return array_rcs[rn]; - } - } - FAPI_INF("Setting output slew tables ATTR_MSS_SLEW_RATE_DATA/ADR\n"); - // ATTR_MSS_SLEW_RATE_DATA [2][4][4] port, imped, slew_rate - rc = FAPI_ATTR_SET(ATTR_MSS_SLEW_RATE_DATA, &i_target_mba, calibrated_slew[0]); - if (rc) - { - FAPI_ERR("Failed to set attribute: ATTR_MSS_SLEW_RATE_DATA"); - return rc; - } - // ATTR_MSS_SLEW_RATE_ADR [2][4][4] port, imped, slew_rate - rc = FAPI_ATTR_SET(ATTR_MSS_SLEW_RATE_ADR, &i_target_mba, calibrated_slew[1]); - if (rc) - { - FAPI_ERR("Failed to set attribute: ATTR_MSS_SLEW_RATE_ADR"); - return rc; - } - -/******************************************************************************/ - uint8_t slew_imp_val [MAX_NUM_SLEW_TYPES][2][MAX_NUM_PORTS]={{{0}}}; - enum { - SLEW = 0, - IMP = 1, - }; - - // Get desired dq/dqs slew rate & impedance from attribute - rc = FAPI_ATTR_GET(ATTR_EFF_CEN_SLEW_RATE_DQ_DQS, &i_target_mba, - slew_imp_val[SLEW_TYPE_DATA][SLEW]); - if (rc) - { - FAPI_ERR("Failed to get attribute: ATTR_EFF_CEN_SLEW_RATE_DQ_DQS"); - return rc; - } - rc = FAPI_ATTR_GET(ATTR_EFF_CEN_DRV_IMP_DQ_DQS, &i_target_mba, - slew_imp_val[SLEW_TYPE_DATA][IMP]); - if (rc) - { - FAPI_ERR("Failed to get attribute: ATTR_EFF_CEN_DRV_IMP_DQ_DQS"); - return rc; - } - // convert enum value to actual ohms. - for (uint8_t j=0; j < MAX_NUM_PORTS; j++) - { -// FAPI_INF("DQ_DQS IMP Attribute[%i] = %u", j, -// slew_imp_val[SLEW_TYPE_DATA][IMP][j]); - - switch (slew_imp_val[SLEW_TYPE_DATA][IMP][j]) - { - case fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM24_FFE0: - slew_imp_val[SLEW_TYPE_DATA][IMP][j]=24; - break; - case fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE0: - case fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE480: - case fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE240: - case fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE160: - case fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE120: - slew_imp_val[SLEW_TYPE_DATA][IMP][j]=30; - break; - case fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0: - case fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE480: - case fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE240: - case fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE160: - case fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE120: - slew_imp_val[SLEW_TYPE_DATA][IMP][j]=34; - break; - case fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0: - case fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE480: - case fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE240: - case fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE160: - case fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE120: - slew_imp_val[SLEW_TYPE_DATA][IMP][j]=40; - break; - default: - FAPI_INF("WARNING: EFF_CEN_DRV_IMP_DQ_DQS attribute " - "invalid, using value of 0"); - } -// FAPI_DBG("switched imp to value of %u", -// slew_imp_val[SLEW_TYPE_DATA][IMP][j]); - } - // Get desired ADR control slew rate & impedance from attribute - rc = FAPI_ATTR_GET(ATTR_VPD_CEN_SLEW_RATE_CNTL, &i_target_mba, - slew_imp_val[SLEW_TYPE_ADR_CNTL][SLEW]); - if (rc) - { - FAPI_ERR("Failed to get attribute: ATTR_VPD_CEN_SLEW_RATE_CNTL"); - return rc; - } - rc = FAPI_ATTR_GET(ATTR_VPD_CEN_DRV_IMP_CNTL, &i_target_mba, - slew_imp_val[SLEW_TYPE_ADR_CNTL][IMP]); - if (rc) - { - FAPI_ERR("Failed to get attribute: ATTR_VPD_CEN_DRV_IMP_CNTL"); - return rc; - } - // Get desired ADR command slew rate & impedance from attribute - rc = FAPI_ATTR_GET(ATTR_VPD_CEN_SLEW_RATE_ADDR, &i_target_mba, - slew_imp_val[SLEW_TYPE_ADR_ADDR][SLEW]); - if (rc) - { - FAPI_ERR("Failed to get attribute: ATTR_VPD_CEN_SLEW_RATE_ADDR"); - return rc; - } - rc = FAPI_ATTR_GET(ATTR_VPD_CEN_DRV_IMP_ADDR, &i_target_mba, - slew_imp_val[SLEW_TYPE_ADR_ADDR][IMP]); - if (rc) - { - FAPI_ERR("Failed to get attribute: ATTR_VPD_CEN_DRV_IMP_ADDR"); - return rc; - } - // Get desired ADR clock slew rate & impedance from attribute - rc = FAPI_ATTR_GET(ATTR_VPD_CEN_SLEW_RATE_CLK, &i_target_mba, - slew_imp_val[SLEW_TYPE_ADR_CLK][SLEW]); - if (rc) - { - FAPI_ERR("Failed to get attribute: ATTR_VPD_CEN_SLEW_RATE_CLK"); - return rc; - } - rc = FAPI_ATTR_GET(ATTR_VPD_CEN_DRV_IMP_CLK, &i_target_mba, - slew_imp_val[SLEW_TYPE_ADR_CLK][IMP]); - if (rc) - { - FAPI_ERR("Failed to get attribute: ATTR_VPD_CEN_DRV_IMP_CLK"); - return rc; - } - // Get desired ADR Spare clock slew rate & impedance from attribute - rc = FAPI_ATTR_GET(ATTR_VPD_CEN_SLEW_RATE_SPCKE, &i_target_mba, - slew_imp_val[SLEW_TYPE_ADR_SPCKE][SLEW]); - if (rc) - { - FAPI_ERR("Failed to get attribute: ATTR_VPD_CEN_SLEW_RATE_SPCKE"); - return rc; - } - rc = FAPI_ATTR_GET(ATTR_VPD_CEN_DRV_IMP_SPCKE, &i_target_mba, - slew_imp_val[SLEW_TYPE_ADR_SPCKE][IMP]); - if (rc) - { - FAPI_ERR("Failed to get attribute: ATTR_VPD_CEN_DRV_IMP_SPCKE"); - return rc; - } - - for (uint8_t l_port=0; l_port < MAX_NUM_PORTS; l_port++) - { - //uint8_t ports_mask = 0xF0; // bits 0:3 = port0, bits 4:7 = port1 - uint8_t port_val = (ports_valid & (0xF0 >> (4 * l_port))); - - if (port_val == 0) - { - FAPI_INF("WARNING: port %u is invalid from " - "ATTR_MSS_EFF_DIMM_FUNCTIONAL_VECTOR, 0x%02x " - "skipping configuration of slew rate on this port", - l_port, ports_valid); - continue; - } - FAPI_INF("Setting slew registers for port %i", l_port); - for (uint8_t slew_type=0; slew_type < MAX_NUM_SLEW_TYPES; slew_type++) - { - fapi::ReturnCode config_rc = - config_slew_rate(i_target_mba, l_port, slew_type, - slew_imp_val[slew_type][IMP][l_port], - slew_imp_val[slew_type][SLEW][l_port]); - if (config_rc) - { - array_rcs[l_port] = config_rc; - } - } - } - - for (uint8_t rn=0; rn < MAX_NUM_PORTS; rn++) - { - if (array_rcs[rn] != fapi::FAPI_RC_SUCCESS) - { - FAPI_ERR("Returning ERROR RC for port %u",rn); - return array_rcs[rn]; - } - } - return rc; -} diff --git a/src/usr/hwpf/hwp/dram_training/mss_termination_control.H b/src/usr/hwpf/hwp/dram_training/mss_termination_control.H deleted file mode 100644 index cbebdda94..000000000 --- a/src/usr/hwpf/hwp/dram_training/mss_termination_control.H +++ /dev/null @@ -1,344 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/dram_training/mss_termination_control.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2012,2014 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: mss_termination_control.H,v 1.12 2014/01/22 15:39:22 mjjones Exp $ -/* File is created by SARAVANAN SETHURAMAN on Thur Sept 28 2011. */ - -//------------------------------------------------------------------------------ -// *! (C) Copyright International Business Machines Corp. 2007 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -//------------------------------------------------------------------------------ -// *! TITLE :mss_draminit_training_advanced.H -// *! DESCRIPTION : Tools for centaur procedures -// *! OWNER NAME : Saravanan sethuraman Email ID: saravanans@in.ibm.com -// *! BACKUP NAME : Menlo Wuu Email ID: menlowuu@us.ibm.com -// #! ADDITIONAL COMMENTS : -// -// General purpose funcs - -//------------------------------------------------------------------------------ -// Don't forget to create CVS comments when you check in your changes! -//------------------------------------------------------------------------------ -// CHANGE HISTORY: -//------------------------------------------------------------------------------ -// Version:| Author: | Date: | Comment: -//---------|---------- |--------- |--------------------------------------------- -// 1.12 | 22-Jan-14 | mjjones | Removed FW header -// 1.11 | 21-Jan-14 | abhijsau | mike and menlo fixed ras review comments -// 1.10 | 14-Dec-12 | sasethur | Updated for fw review comments -// 1.9 | 07-Dec-12 | sasethur | Updated for fw review comments -// 1.8 | 16-Nov-12 | mwuu | Added typedef for external call of -// mss_slew_cal F -// 1.7 | 14-Nov-12 | mwuu | Changed "l_" variables to "i_" in -// config_slew_rate FN -// 1.6 | 14-Nov-12 | mwuu | Fixed revision numbering in comments -// 1.5 | 14-Nov-12 | mwuu | Added additional slew rates, and new const -// 1.4 | 26-Oct-12 | mwuu | Added additional slew types enums, need to -// change MAX_NUM_SLEW_TYPES when attributes -// updated. -// 1.3 | 26-Oct-12 | sasethur | Updated FW review comments fapi::, -// const fapi::Target -// 1.2 | 17-Oct-12 | mwuu | updates to enum and consts -// 1.1 | 28-Sep-12 | sasethur | First draft - - -#ifndef MSS_TERMINATION_CONTROL_H -#define MSS_TERMINATION_CONTROL_H -//---------------------------------------------------------------------- -// Includes -//---------------------------------------------------------------------- -#include <fapi.H> - -enum { - SLEW_TYPE_DATA = 0, - SLEW_TYPE_ADR_ADDR = 1, - SLEW_TYPE_ADR_CNTL = 2, - SLEW_TYPE_ADR_CLK = 3, - SLEW_TYPE_ADR_SPCKE = 4, - - OHM15 = 15, - OHM20 = 20, - OHM24 = 24, - OHM30 = 30, - OHM34 = 34, - OHM40 = 40, - - SLEW_3V_NS = 3, - SLEW_4V_NS = 4, - SLEW_5V_NS = 5, - SLEW_6V_NS = 6, - SLEW_MAXV_NS = 7, -}; - -const uint8_t MAX_NUM_PORTS = 2; // max number of ports -const uint8_t MAX_NUM_SLEW_TYPES = 5; // data(dq/dqs), adr_cmd, adr_cntl, clk, spcke, used by slew_cal FN only -const uint8_t MAX_NUM_IMP = 4; // number of impedances valid per slew type - -//Address shmoo is not done as a part of Training advanced, so the order matches -//attribute enum -const uint8_t adr_imp_array[] = { - 15, - 20, - 30, - 40, -}; - -// bypass slew (MAX slew rate) not included since it is not calibrated. -const uint8_t MAX_NUM_CAL_SLEW_RATES = 4 ; // 3V/ns, 4V/ns, 5V/ns, 6V/n -const uint8_t MAX_NUM_SLEW_RATES = 4; // 3V/ns, 4V/ns, 5V/ns, 6V/n, MAX? -const uint8_t slew_rate_array[] = { - 6, - 5, - 4, - 3, -}; - -const uint8_t MAX_SLEW_VALUE = 15; // 4 bit value -const uint8_t MAX_WR_VREF = 32; - -const uint32_t wr_vref_array[] = { - 420, - 425, - 430, - 435, - 440, - 445, - 450, - 455, - 460, - 465, - 470, - 475, - 480, - 485, - 490, - 495, - 500, - 505, - 510, - 515, - 520, - 525, - 530, - 535, - 540, - 545, - 550, - 555, - 560, - 565, - 570, - 575 - }; - - -//The Array is re-arranged inorder to find the best Eye margin based on the -//Fitness level - 500 is the best value -const uint32_t wr_vref_array_fitness[] = { - 420, - 425, - 575, - 430, - 570, - 435, - 565, - 440, - 560, - 445, - 555, - 450, - 550, - 455, - 545, - 460, - 540, - 465, - 535, - 470, - 530, - 475, - 525, - 480, - 520, - 485, - 515, - 490, - 510, - 495, - 505, - 500 - }; - -const uint8_t MAX_RD_VREF = 16; -const uint32_t rd_cen_vref_array[] = { - 40375, - 41750, - 43125, - 44500, - 45875, - 47250, - 48625, - 50000, - 51375, - 52750, - 54125, - 55500, - 56875, - 58250, - 59625, - 61000 - }; - -//The Array is re-arranged inorder to find the best Eye margin based on the -//Fitness level - 50000 is the best value -const uint32_t rd_cen_vref_array_fitness[] = { - 61000, - 59625, - 40375, - 58250, - 41750, - 56875, - 43125, - 55500, - 44500, - 54125, - 45875, - 52750, - 47250, - 51375, - 48625, - 50000 - }; - -//The Array is re-arranged inorder to find the best Eye margin based on the -//Fitness level - 24 is the best value -const uint8_t MAX_DRV_IMP = 4; -const uint8_t drv_imp_array[] = { - 40, - 34, - 30, - 24 - }; - -//The Array is re-arranged inorder to find the best Eye margin based on the -//Fitness level - 15 is the best value -const uint8_t MAX_RCV_IMP = 9; -const uint8_t rcv_imp_array[] = { - 120, - 80, - 60, - 48, - 40, - 34, - 30, - 20, - 15 - }; - -extern "C" -{ -/** - * @brief configures PC_VREF_DRV_CONTROL registers to vary the DRAM VREF - * - * @param[in] i_target_mba Reference to centaur.mba target - * @param[in] i_port MBA Port - * @param[in] i_wr_dram_vref DRAM VREF to set - * - * @return ReturnCode - */ -fapi::ReturnCode config_wr_dram_vref(const fapi::Target & i_target_mba, - uint8_t i_port, - uint32_t i_wr_dram_vref); - -/** - * @brief configures read vref registers to vary the CEN VREF - * - * @param[in] i_target_mba Reference to centaur.mba target - * @param[in] i_port MBA Port - * @param[in] i_rd_cen_vref CEN VREF to set - * - * @return ReturnCode - */ -fapi::ReturnCode config_rd_cen_vref(const fapi::Target & i_target_mba, - uint8_t i_port, - uint32_t i_rd_cen_vref); - -/** - * @brief configures the Driver impedance values to the registers - * - * @param[in] i_target_mba Reference to centaur.mba target - * @param[in] i_port MBA Port - * @param[in] i_drv_imp_dq_dqs Driver impedance values - * - * @return ReturnCode - */ -fapi::ReturnCode config_drv_imp(const fapi::Target & i_target_mba, - uint8_t i_port, - uint8_t i_drv_imp_dq_dqs); - -/** - * @brief configures the Receiver impedance values to the registers - * - * @param[in] i_target_mba Reference to centaur.mba target - * @param[in] i_port MBA Port - * @param[in] i_rcv_imp_dq_dqs Receiver impedance values - * - * @return ReturnCode - */ -fapi::ReturnCode config_rcv_imp(const fapi::Target & i_target_mba, - uint8_t i_port, - uint8_t i_rcv_imp_dq_dqs); - -/** - * @brief configures the Slew rate values to the registers - * - * @param[in] i_target_mba Reference to centaur.mba target - * @param[in] i_port MBA Port - * @param[in] i_slew_type Slew Type - * @param[in] i_slew_imp Slew Impedance - * @param[in] i_slew_rate Slew Rate - * - * @return ReturnCode - */ -fapi::ReturnCode config_slew_rate(const fapi::Target & i_target_mba,
- const uint8_t i_port, - const uint8_t i_slew_type, - const uint8_t i_slew_imp,
- const uint8_t i_slew_rate); - -/** - * @brief runs the slew calibration engine - * - * Configures MSS_SLEW_DATA/ADR attributes and calls config_slew_rate to set - * the slew rate in the registers. - * - * @param[in] i_target_mba Reference to centaur.mba target - * - * @return ReturnCode - */ -fapi::ReturnCode mss_slew_cal(const fapi::Target & i_target_mba); - -} // extern C -#endif |
