1 files changed, 138 insertions, 0 deletions
diff --git a/src/usr/diag/prdf/plat/pegasus/Membuf_regs_MEM.rule b/src/usr/diag/prdf/plat/pegasus/Membuf_regs_MEM.rule
new file mode 100644
index 000000000..5de564fe3
--- /dev/null
+++ b/src/usr/diag/prdf/plat/pegasus/Membuf_regs_MEM.rule
@@ -0,0 +1,138 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+# 
+# $Source: src/usr/diag/prdf/plat/pegasus/Membuf_regs_MEM.rule $
+# 
+# IBM CONFIDENTIAL
+# 
+# COPYRIGHT International Business Machines Corp. 2012
+# 
+# p1
+# 
+# Object Code Only (OCO) source materials
+# Licensed Internal Code Source Materials
+# IBM HostBoot Licensed Internal Code
+# 
+# The source code for this program is not published or otherwise
+# divested of its trade secrets, irrespective of what has been
+# deposited with the U.S. Copyright Office.
+# 
+# Origin: 30
+# 
+# IBM_PROLOG_END_TAG 
+
+    ############################################################################
+    # MEM Chiplet Registers
+    ############################################################################
+
+    register MEM_CHIPLET_CS_FIR
+    {
+        name        "TCM.XFIR";
+        scomaddr    0x03040000;
+        capture     group default;
+    };
+
+    register MEM_CHIPLET_RE_FIR
+    {
+        name        "TCM.RFIR";
+        scomaddr    0x03040001;
+        capture     group default;
+    };
+
+    register MEM_CHIPLET_FIR_MASK
+    {
+        name        "TCM.FIR_MASK";
+        scomaddr    0x03040002;
+        capture     type secondary;
+        capture     group default;
+    };
+
+    register MEM_CHIPLET_SPA
+    {
+        name        "TCM.EPS.FIR.SPATTN";
+        scomaddr    0x03040004;
+        capture     group default;
+    };
+
+    register MEM_CHIPLET_SPA_MASK
+    {
+        name        "TCM.EPS.FIR.SPA_MASK";
+        scomaddr    0x03040007;
+        capture     type secondary;
+        capture     group default;
+    };
+
+    ############################################################################
+    # MEM Chiplet LFIR
+    ############################################################################
+
+    register MEM_LFIR
+    {
+        name        "TCM.LOCAL_FIR";
+        scomaddr    0x0304000a;
+        reset       (&, 0x0304000b);
+        mask        (|, 0x0304000f);
+        capture     group default;
+    };
+
+    register MEM_LFIR_MASK
+    {
+        name        "TCM.EPS.FIR.LOCAL_FIR_MASK";
+        scomaddr    0x0304000d;
+        capture     type secondary;
+        capture     group default;
+    };
+
+    register MEM_LFIR_ACT0
+    {
+        name        "TCM.EPS.FIR.LOCAL_FIR_ACTION0";
+        scomaddr    0x03040010;
+        capture     type secondary;
+        capture     group default;
+    };
+
+    register MEM_LFIR_ACT1
+    {
+        name        "TCM.EPS.FIR.LOCAL_FIR_ACTION1";
+        scomaddr    0x03040011;
+        capture     type secondary;
+        capture     group default;
+    };
+
+    ############################################################################
+    # MEM Chiplet MEMFBISTFIR
+    ############################################################################
+
+    register MEMFBISTFIR
+    {
+        name        "FBIST.FBM.FBM_FIR_REG";
+        scomaddr    0x03010480;
+        reset       (&, 0x03010481);
+        mask        (|, 0x03010485);
+        capture     group default;
+    };
+
+    register MEMFBISTFIR_MASK
+    {
+        name        "FBIST.FBM.FBM_FIR_MASK_REG";
+        scomaddr    0x03010483;
+        capture     type secondary;
+        capture     group default;
+    };
+
+    register MEMFBISTFIR_ACT0
+    {
+        name        "FBIST.FBM.FBM_FIR_ACTION0_REG";
+        scomaddr    0x03010486;
+        capture     type secondary;
+        capture     group default;
+    };
+
+    register MEMFBISTFIR_ACT1
+    {
+        name        "FBIST.FBM.FBM_FIR_ACTION1_REG";
+        scomaddr    0x03010487;
+        capture     type secondary;
+        capture     group default;
+    };
+