diff options
Diffstat (limited to 'src/import/chips')
-rw-r--r-- | src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/exp_mcbist_traits.H | 5 | ||||
-rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/lib/mcbist/mcbist_traits.H | 5 |
2 files changed, 10 insertions, 0 deletions
diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/exp_mcbist_traits.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/exp_mcbist_traits.H index 0afe9618e..72f06be05 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/exp_mcbist_traits.H +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/exp_mcbist_traits.H @@ -294,6 +294,10 @@ class mcbistTraits< mss::mc_type::EXPLORER, fapi2::TARGET_TYPE_OCMB_CHIP> enum { + // The start/end address config registers have common lengths and bits, just including 1 below + MCB_ADDR_CONFIG = EXPLR_MCBIST_MCBEA0Q_CFG_END_ADDR_0, + MCB_ADDR_CONFIG_LEN = EXPLR_MCBIST_MCBEA0Q_CFG_END_ADDR_0_LEN, + // Subtest control bits. These are the same in all '16 bit subtest' field COMPL_1ST_CMD = EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_COMPL_1ST_CMD, COMPL_2ND_CMD = EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_COMPL_2ND_CMD, @@ -557,6 +561,7 @@ class mcbistTraits< mss::mc_type::EXPLORER, fapi2::TARGET_TYPE_OCMB_CHIP> //MCBIST FIR mask MCB_PROGRAM_COMPLETE = EXPLR_MCBIST_MCBISTFIRQ_MCBIST_PROGRAM_COMPLETE, MCB_WAT_DEBUG_ATTN = EXPLR_MCBIST_MCBISTFIRQ_WAT_DEBUG_ATTN, + MCB_DATA_ERROR = EXPLR_MCBIST_MCBISTFIRQ_MCBIST_DATA_ERROR, //XLT address valid offset XLT0_SLOT1_D_VALID = EXPLR_MCBIST_MBXLT0Q_SLOT1_VALID, diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/mcbist_traits.H b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/mcbist_traits.H index c57ededbe..7d9d3ab2c 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/mcbist_traits.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/mcbist_traits.H @@ -300,6 +300,10 @@ class mcbistTraits<mss::mc_type::NIMBUS, fapi2::TARGET_TYPE_MCBIST> enum { + // The start/end address config registers have common lengths and bits, just including 1 below + MCB_ADDR_CONFIG = MCBIST_MCBEA0Q_CFG_END_ADDR_0, + MCB_ADDR_CONFIG_LEN = MCBIST_MCBEA0Q_CFG_END_ADDR_0_LEN, + // Subtest control bits. These are the same in all '16 bit subtest' field COMPL_1ST_CMD = MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_COMPL_1ST_CMD, COMPL_2ND_CMD = MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_COMPL_2ND_CMD, @@ -557,6 +561,7 @@ class mcbistTraits<mss::mc_type::NIMBUS, fapi2::TARGET_TYPE_MCBIST> MCB_WAT_DEBUG_ATTN = MCBIST_MCBISTFIRQ_WAT_DEBUG_ATTN, MCB_PROGRAM_COMPLETE_MASK = MCB_PROGRAM_COMPLETE, MCB_WAT_DEBUG_ATTN_MASK = MCB_WAT_DEBUG_ATTN, + MCB_DATA_ERROR = MCBIST_MCBISTFIRQ_MCBIST_DATA_ERROR, //XLT address valid offset XLT0_SLOT1_D_VALID = MCS_PORT13_MCP0XLT0_SLOT1_VALID, |