4 files changed, 454 insertions, 1 deletions
diff --git a/src/build/citest/etc/patches/p8_indScom_910431.act b/src/build/citest/etc/patches/p8_indScom_910431.act
new file mode 100644
index 000000000..534c52efe
--- /dev/null
+++ b/src/build/citest/etc/patches/p8_indScom_910431.act
@@ -0,0 +1,196 @@
+#This file was generated by /gsa/rchgsa-h1/02/missyc/sandboxes/hostboot/src/simu/fsp/buildIndScom.pl for scomdef: p8_910431.scomdef
+
+#The following actions are used for Indirect SCOMs
+
+CAUSE_EFFECT {
+  LABEL=[Indirect Scom Action for 0x020140BF]
+  WATCH=[REG(0x020140BF)]
+  CAUSE: TARGET=[REG(0x020140BF)] OP=[BIT,OFF] BIT=[0] #Write
+  #bits 12-31 contain the indirect address.
+  EFFECT: TARGET=[INDSCOM_0x020140BF(0xFF0000AA)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x020140BF)] MASK=[LITERAL(64,000FFFFF 00000000)]
+  #bits 48-63 contain the indirect SCOM data
+  EFFECT: TARGET=[INDSCOM_0x020140BF(0xFF0000DD)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x020140BF)] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #write 48-63 6010420 to the IND REG
+  EFFECT: TARGET=[INDSCOM_0x020140BF(CONTENTSOF{INDSCOM_0x020140BF(0xFF0000AA)})] OP=[EQUALTO,BUFSTRING] DATA=[INDSCOM_0x020140BF(0xFF0000DD]
+  #Turn on bits 32 and 38 to show successful write
+   EFFECT: TARGET=[REG(0x020140BF)] OP=[OR,ON,BUF] DATA=[LITERAL(64,00000000 82000000]
+  
+  ## Read => if Bit 0 = 1 in SCOM reg, it's a read request
+  #bits 12-31 contain the indirect address
+  ELSE: TARGET=[INDSCOM_0x020140BF(0xFF0000AA)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x020140BF)] MASK=[LITERAL(64,000FFFFF 00000000)]
+  #Move bits 48-63 from IND SCOM reg to 0xFF0000DD scratch reg (for debug)
+  ELSE: TARGET=[INDSCOM_0x020140BF(0xFF0000DD)]  OP=[EQUALTO,BUFSTRING,MASK]  DATA=[INDSCOM_0x020140BF(CONTENTSOF{INDSCOM_0x020140BF(0xFF0000AA)})] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #Move bits 48-63 from 0xFF0000DD scratch reg to SCOM Reg
+  ELSE: TARGET=[REG(0x020140BF)] OP=[EQUALTO,BUF,MASK] DATA=[INDSCOM_0x020140BF(0xFF0000DD)] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #Turn on bits 32, 38, 39 to show successful read
+  ELSE: TARGET=[REG(0x020140BF)] OP=[OR,ON,BUF] DATA=[LITERAL(64,00000000 83000000]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Indirect Scom Action for 0x0301187F]
+  WATCH=[REG(0x0301187F)]
+  CAUSE: TARGET=[REG(0x0301187F)] OP=[BIT,OFF] BIT=[0] #Write
+  #bits 12-31 contain the indirect address.
+  EFFECT: TARGET=[INDSCOM_0x0301187F(0xFF0000AA)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x0301187F)] MASK=[LITERAL(64,000FFFFF 00000000)]
+  #bits 48-63 contain the indirect SCOM data
+  EFFECT: TARGET=[INDSCOM_0x0301187F(0xFF0000DD)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x0301187F)] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #write 48-63 6010420 to the IND REG
+  EFFECT: TARGET=[INDSCOM_0x0301187F(CONTENTSOF{INDSCOM_0x0301187F(0xFF0000AA)})] OP=[EQUALTO,BUFSTRING] DATA=[INDSCOM_0x0301187F(0xFF0000DD]
+  #Turn on bits 32 and 38 to show successful write
+   EFFECT: TARGET=[REG(0x0301187F)] OP=[OR,ON,BUF] DATA=[LITERAL(64,00000000 82000000]
+  
+  ## Read => if Bit 0 = 1 in SCOM reg, it's a read request
+  #bits 12-31 contain the indirect address
+  ELSE: TARGET=[INDSCOM_0x0301187F(0xFF0000AA)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x0301187F)] MASK=[LITERAL(64,000FFFFF 00000000)]
+  #Move bits 48-63 from IND SCOM reg to 0xFF0000DD scratch reg (for debug)
+  ELSE: TARGET=[INDSCOM_0x0301187F(0xFF0000DD)]  OP=[EQUALTO,BUFSTRING,MASK]  DATA=[INDSCOM_0x0301187F(CONTENTSOF{INDSCOM_0x0301187F(0xFF0000AA)})] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #Move bits 48-63 from 0xFF0000DD scratch reg to SCOM Reg
+  ELSE: TARGET=[REG(0x0301187F)] OP=[EQUALTO,BUF,MASK] DATA=[INDSCOM_0x0301187F(0xFF0000DD)] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #Turn on bits 32, 38, 39 to show successful read
+  ELSE: TARGET=[REG(0x0301187F)] OP=[OR,ON,BUF] DATA=[LITERAL(64,00000000 83000000]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Indirect Scom Action for 0x08010C3F]
+  WATCH=[REG(0x08010C3F)]
+  CAUSE: TARGET=[REG(0x08010C3F)] OP=[BIT,OFF] BIT=[0] #Write
+  #bits 12-31 contain the indirect address.
+  EFFECT: TARGET=[INDSCOM_0x08010C3F(0xFF0000AA)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x08010C3F)] MASK=[LITERAL(64,000FFFFF 00000000)]
+  #bits 48-63 contain the indirect SCOM data
+  EFFECT: TARGET=[INDSCOM_0x08010C3F(0xFF0000DD)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x08010C3F)] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #write 48-63 6010420 to the IND REG
+  EFFECT: TARGET=[INDSCOM_0x08010C3F(CONTENTSOF{INDSCOM_0x08010C3F(0xFF0000AA)})] OP=[EQUALTO,BUFSTRING] DATA=[INDSCOM_0x08010C3F(0xFF0000DD]
+  #Turn on bits 32 and 38 to show successful write
+   EFFECT: TARGET=[REG(0x08010C3F)] OP=[OR,ON,BUF] DATA=[LITERAL(64,00000000 82000000]
+  
+  ## Read => if Bit 0 = 1 in SCOM reg, it's a read request
+  #bits 12-31 contain the indirect address
+  ELSE: TARGET=[INDSCOM_0x08010C3F(0xFF0000AA)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x08010C3F)] MASK=[LITERAL(64,000FFFFF 00000000)]
+  #Move bits 48-63 from IND SCOM reg to 0xFF0000DD scratch reg (for debug)
+  ELSE: TARGET=[INDSCOM_0x08010C3F(0xFF0000DD)]  OP=[EQUALTO,BUFSTRING,MASK]  DATA=[INDSCOM_0x08010C3F(CONTENTSOF{INDSCOM_0x08010C3F(0xFF0000AA)})] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #Move bits 48-63 from 0xFF0000DD scratch reg to SCOM Reg
+  ELSE: TARGET=[REG(0x08010C3F)] OP=[EQUALTO,BUF,MASK] DATA=[INDSCOM_0x08010C3F(0xFF0000DD)] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #Turn on bits 32, 38, 39 to show successful read
+  ELSE: TARGET=[REG(0x08010C3F)] OP=[OR,ON,BUF] DATA=[LITERAL(64,00000000 83000000]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Indirect Scom Action for 0x03010C3F]
+  WATCH=[REG(0x03010C3F)]
+  CAUSE: TARGET=[REG(0x03010C3F)] OP=[BIT,OFF] BIT=[0] #Write
+  #bits 12-31 contain the indirect address.
+  EFFECT: TARGET=[INDSCOM_0x03010C3F(0xFF0000AA)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x03010C3F)] MASK=[LITERAL(64,000FFFFF 00000000)]
+  #bits 48-63 contain the indirect SCOM data
+  EFFECT: TARGET=[INDSCOM_0x03010C3F(0xFF0000DD)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x03010C3F)] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #write 48-63 6010420 to the IND REG
+  EFFECT: TARGET=[INDSCOM_0x03010C3F(CONTENTSOF{INDSCOM_0x03010C3F(0xFF0000AA)})] OP=[EQUALTO,BUFSTRING] DATA=[INDSCOM_0x03010C3F(0xFF0000DD]
+  #Turn on bits 32 and 38 to show successful write
+   EFFECT: TARGET=[REG(0x03010C3F)] OP=[OR,ON,BUF] DATA=[LITERAL(64,00000000 82000000]
+  
+  ## Read => if Bit 0 = 1 in SCOM reg, it's a read request
+  #bits 12-31 contain the indirect address
+  ELSE: TARGET=[INDSCOM_0x03010C3F(0xFF0000AA)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x03010C3F)] MASK=[LITERAL(64,000FFFFF 00000000)]
+  #Move bits 48-63 from IND SCOM reg to 0xFF0000DD scratch reg (for debug)
+  ELSE: TARGET=[INDSCOM_0x03010C3F(0xFF0000DD)]  OP=[EQUALTO,BUFSTRING,MASK]  DATA=[INDSCOM_0x03010C3F(CONTENTSOF{INDSCOM_0x03010C3F(0xFF0000AA)})] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #Move bits 48-63 from 0xFF0000DD scratch reg to SCOM Reg
+  ELSE: TARGET=[REG(0x03010C3F)] OP=[EQUALTO,BUF,MASK] DATA=[INDSCOM_0x03010C3F(0xFF0000DD)] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #Turn on bits 32, 38, 39 to show successful read
+  ELSE: TARGET=[REG(0x03010C3F)] OP=[OR,ON,BUF] DATA=[LITERAL(64,00000000 83000000]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Indirect Scom Action for 0x0301103F]
+  WATCH=[REG(0x0301103F)]
+  CAUSE: TARGET=[REG(0x0301103F)] OP=[BIT,OFF] BIT=[0] #Write
+  #bits 12-31 contain the indirect address.
+  EFFECT: TARGET=[INDSCOM_0x0301103F(0xFF0000AA)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x0301103F)] MASK=[LITERAL(64,000FFFFF 00000000)]
+  #bits 48-63 contain the indirect SCOM data
+  EFFECT: TARGET=[INDSCOM_0x0301103F(0xFF0000DD)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x0301103F)] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #write 48-63 6010420 to the IND REG
+  EFFECT: TARGET=[INDSCOM_0x0301103F(CONTENTSOF{INDSCOM_0x0301103F(0xFF0000AA)})] OP=[EQUALTO,BUFSTRING] DATA=[INDSCOM_0x0301103F(0xFF0000DD]
+  #Turn on bits 32 and 38 to show successful write
+   EFFECT: TARGET=[REG(0x0301103F)] OP=[OR,ON,BUF] DATA=[LITERAL(64,00000000 82000000]
+  
+  ## Read => if Bit 0 = 1 in SCOM reg, it's a read request
+  #bits 12-31 contain the indirect address
+  ELSE: TARGET=[INDSCOM_0x0301103F(0xFF0000AA)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x0301103F)] MASK=[LITERAL(64,000FFFFF 00000000)]
+  #Move bits 48-63 from IND SCOM reg to 0xFF0000DD scratch reg (for debug)
+  ELSE: TARGET=[INDSCOM_0x0301103F(0xFF0000DD)]  OP=[EQUALTO,BUFSTRING,MASK]  DATA=[INDSCOM_0x0301103F(CONTENTSOF{INDSCOM_0x0301103F(0xFF0000AA)})] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #Move bits 48-63 from 0xFF0000DD scratch reg to SCOM Reg
+  ELSE: TARGET=[REG(0x0301103F)] OP=[EQUALTO,BUF,MASK] DATA=[INDSCOM_0x0301103F(0xFF0000DD)] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #Turn on bits 32, 38, 39 to show successful read
+  ELSE: TARGET=[REG(0x0301103F)] OP=[OR,ON,BUF] DATA=[LITERAL(64,00000000 83000000]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Indirect Scom Action for 0x0301143F]
+  WATCH=[REG(0x0301143F)]
+  CAUSE: TARGET=[REG(0x0301143F)] OP=[BIT,OFF] BIT=[0] #Write
+  #bits 12-31 contain the indirect address.
+  EFFECT: TARGET=[INDSCOM_0x0301143F(0xFF0000AA)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x0301143F)] MASK=[LITERAL(64,000FFFFF 00000000)]
+  #bits 48-63 contain the indirect SCOM data
+  EFFECT: TARGET=[INDSCOM_0x0301143F(0xFF0000DD)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x0301143F)] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #write 48-63 6010420 to the IND REG
+  EFFECT: TARGET=[INDSCOM_0x0301143F(CONTENTSOF{INDSCOM_0x0301143F(0xFF0000AA)})] OP=[EQUALTO,BUFSTRING] DATA=[INDSCOM_0x0301143F(0xFF0000DD]
+  #Turn on bits 32 and 38 to show successful write
+   EFFECT: TARGET=[REG(0x0301143F)] OP=[OR,ON,BUF] DATA=[LITERAL(64,00000000 82000000]
+  
+  ## Read => if Bit 0 = 1 in SCOM reg, it's a read request
+  #bits 12-31 contain the indirect address
+  ELSE: TARGET=[INDSCOM_0x0301143F(0xFF0000AA)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x0301143F)] MASK=[LITERAL(64,000FFFFF 00000000)]
+  #Move bits 48-63 from IND SCOM reg to 0xFF0000DD scratch reg (for debug)
+  ELSE: TARGET=[INDSCOM_0x0301143F(0xFF0000DD)]  OP=[EQUALTO,BUFSTRING,MASK]  DATA=[INDSCOM_0x0301143F(CONTENTSOF{INDSCOM_0x0301143F(0xFF0000AA)})] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #Move bits 48-63 from 0xFF0000DD scratch reg to SCOM Reg
+  ELSE: TARGET=[REG(0x0301143F)] OP=[EQUALTO,BUF,MASK] DATA=[INDSCOM_0x0301143F(0xFF0000DD)] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #Turn on bits 32, 38, 39 to show successful read
+  ELSE: TARGET=[REG(0x0301143F)] OP=[OR,ON,BUF] DATA=[LITERAL(64,00000000 83000000]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Indirect Scom Action for 0x0301183F]
+  WATCH=[REG(0x0301183F)]
+  CAUSE: TARGET=[REG(0x0301183F)] OP=[BIT,OFF] BIT=[0] #Write
+  #bits 12-31 contain the indirect address.
+  EFFECT: TARGET=[INDSCOM_0x0301183F(0xFF0000AA)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x0301183F)] MASK=[LITERAL(64,000FFFFF 00000000)]
+  #bits 48-63 contain the indirect SCOM data
+  EFFECT: TARGET=[INDSCOM_0x0301183F(0xFF0000DD)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x0301183F)] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #write 48-63 6010420 to the IND REG
+  EFFECT: TARGET=[INDSCOM_0x0301183F(CONTENTSOF{INDSCOM_0x0301183F(0xFF0000AA)})] OP=[EQUALTO,BUFSTRING] DATA=[INDSCOM_0x0301183F(0xFF0000DD]
+  #Turn on bits 32 and 38 to show successful write
+   EFFECT: TARGET=[REG(0x0301183F)] OP=[OR,ON,BUF] DATA=[LITERAL(64,00000000 82000000]
+  
+  ## Read => if Bit 0 = 1 in SCOM reg, it's a read request
+  #bits 12-31 contain the indirect address
+  ELSE: TARGET=[INDSCOM_0x0301183F(0xFF0000AA)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x0301183F)] MASK=[LITERAL(64,000FFFFF 00000000)]
+  #Move bits 48-63 from IND SCOM reg to 0xFF0000DD scratch reg (for debug)
+  ELSE: TARGET=[INDSCOM_0x0301183F(0xFF0000DD)]  OP=[EQUALTO,BUFSTRING,MASK]  DATA=[INDSCOM_0x0301183F(CONTENTSOF{INDSCOM_0x0301183F(0xFF0000AA)})] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #Move bits 48-63 from 0xFF0000DD scratch reg to SCOM Reg
+  ELSE: TARGET=[REG(0x0301183F)] OP=[EQUALTO,BUF,MASK] DATA=[INDSCOM_0x0301183F(0xFF0000DD)] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #Turn on bits 32, 38, 39 to show successful read
+  ELSE: TARGET=[REG(0x0301183F)] OP=[OR,ON,BUF] DATA=[LITERAL(64,00000000 83000000]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Indirect Scom Action for 0x020120BF]
+  WATCH=[REG(0x020120BF)]
+  CAUSE: TARGET=[REG(0x020120BF)] OP=[BIT,OFF] BIT=[0] #Write
+  #bits 12-31 contain the indirect address.
+  EFFECT: TARGET=[INDSCOM_0x020120BF(0xFF0000AA)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x020120BF)] MASK=[LITERAL(64,000FFFFF 00000000)]
+  #bits 48-63 contain the indirect SCOM data
+  EFFECT: TARGET=[INDSCOM_0x020120BF(0xFF0000DD)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x020120BF)] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #write 48-63 6010420 to the IND REG
+  EFFECT: TARGET=[INDSCOM_0x020120BF(CONTENTSOF{INDSCOM_0x020120BF(0xFF0000AA)})] OP=[EQUALTO,BUFSTRING] DATA=[INDSCOM_0x020120BF(0xFF0000DD]
+  #Turn on bits 32 and 38 to show successful write
+   EFFECT: TARGET=[REG(0x020120BF)] OP=[OR,ON,BUF] DATA=[LITERAL(64,00000000 82000000]
+  
+  ## Read => if Bit 0 = 1 in SCOM reg, it's a read request
+  #bits 12-31 contain the indirect address
+  ELSE: TARGET=[INDSCOM_0x020120BF(0xFF0000AA)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x020120BF)] MASK=[LITERAL(64,000FFFFF 00000000)]
+  #Move bits 48-63 from IND SCOM reg to 0xFF0000DD scratch reg (for debug)
+  ELSE: TARGET=[INDSCOM_0x020120BF(0xFF0000DD)]  OP=[EQUALTO,BUFSTRING,MASK]  DATA=[INDSCOM_0x020120BF(CONTENTSOF{INDSCOM_0x020120BF(0xFF0000AA)})] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #Move bits 48-63 from 0xFF0000DD scratch reg to SCOM Reg
+  ELSE: TARGET=[REG(0x020120BF)] OP=[EQUALTO,BUF,MASK] DATA=[INDSCOM_0x020120BF(0xFF0000DD)] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #Turn on bits 32, 38, 39 to show successful read
+  ELSE: TARGET=[REG(0x020120BF)] OP=[OR,ON,BUF] DATA=[LITERAL(64,00000000 83000000]
+}
+
diff --git a/src/build/citest/etc/patches/p8_indScom_910520.act b/src/build/citest/etc/patches/p8_indScom_910520.act
new file mode 100644
index 000000000..3c03fb738
--- /dev/null
+++ b/src/build/citest/etc/patches/p8_indScom_910520.act
@@ -0,0 +1,244 @@
+#This file was generated by /gsa/rchgsa-h1/02/missyc/sandboxes/hostboot/src/simu/fsp/buildIndScom.pl for scomdef: p8_910520.scomdef
+
+#The following actions are used for Indirect SCOMs
+
+CAUSE_EFFECT {
+  LABEL=[Indirect Scom Action for 0x08010C3F]
+  WATCH=[REG(0x08010C3F)]
+  CAUSE: TARGET=[REG(0x08010C3F)] OP=[BIT,OFF] BIT=[0] #Write
+  #bits 12-31 contain the indirect address.
+  EFFECT: TARGET=[INDSCOM_0x08010C3F(0xFF0000AA)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x08010C3F)] MASK=[LITERAL(64,000FFFFF 00000000)]
+  #bits 48-63 contain the indirect SCOM data
+  EFFECT: TARGET=[INDSCOM_0x08010C3F(0xFF0000DD)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x08010C3F)] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #write 48-63 6010420 to the IND REG
+  EFFECT: TARGET=[INDSCOM_0x08010C3F(CONTENTSOF{INDSCOM_0x08010C3F(0xFF0000AA)})] OP=[EQUALTO,BUFSTRING] DATA=[INDSCOM_0x08010C3F(0xFF0000DD]
+  #Turn on bits 32 and 38 to show successful write
+   EFFECT: TARGET=[REG(0x08010C3F)] OP=[OR,ON,BUF] DATA=[LITERAL(64,00000000 82000000]
+  
+  ## Read => if Bit 0 = 1 in SCOM reg, it's a read request
+  #bits 12-31 contain the indirect address
+  ELSE: TARGET=[INDSCOM_0x08010C3F(0xFF0000AA)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x08010C3F)] MASK=[LITERAL(64,000FFFFF 00000000)]
+  #Move bits 48-63 from IND SCOM reg to 0xFF0000DD scratch reg (for debug)
+  ELSE: TARGET=[INDSCOM_0x08010C3F(0xFF0000DD)]  OP=[EQUALTO,BUFSTRING,MASK]  DATA=[INDSCOM_0x08010C3F(CONTENTSOF{INDSCOM_0x08010C3F(0xFF0000AA)})] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #Move bits 48-63 from 0xFF0000DD scratch reg to SCOM Reg
+  ELSE: TARGET=[REG(0x08010C3F)] OP=[EQUALTO,BUF,MASK] DATA=[INDSCOM_0x08010C3F(0xFF0000DD)] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #Turn on bits 32, 38, 39 to show successful read
+  ELSE: TARGET=[REG(0x08010C3F)] OP=[OR,ON,BUF] DATA=[LITERAL(64,00000000 83000000]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Indirect Scom Action for 0x02011E3F]
+  WATCH=[REG(0x02011E3F)]
+  CAUSE: TARGET=[REG(0x02011E3F)] OP=[BIT,OFF] BIT=[0] #Write
+  #bits 12-31 contain the indirect address.
+  EFFECT: TARGET=[INDSCOM_0x02011E3F(0xFF0000AA)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x02011E3F)] MASK=[LITERAL(64,000FFFFF 00000000)]
+  #bits 48-63 contain the indirect SCOM data
+  EFFECT: TARGET=[INDSCOM_0x02011E3F(0xFF0000DD)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x02011E3F)] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #write 48-63 6010420 to the IND REG
+  EFFECT: TARGET=[INDSCOM_0x02011E3F(CONTENTSOF{INDSCOM_0x02011E3F(0xFF0000AA)})] OP=[EQUALTO,BUFSTRING] DATA=[INDSCOM_0x02011E3F(0xFF0000DD]
+  #Turn on bits 32 and 38 to show successful write
+   EFFECT: TARGET=[REG(0x02011E3F)] OP=[OR,ON,BUF] DATA=[LITERAL(64,00000000 82000000]
+  
+  ## Read => if Bit 0 = 1 in SCOM reg, it's a read request
+  #bits 12-31 contain the indirect address
+  ELSE: TARGET=[INDSCOM_0x02011E3F(0xFF0000AA)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x02011E3F)] MASK=[LITERAL(64,000FFFFF 00000000)]
+  #Move bits 48-63 from IND SCOM reg to 0xFF0000DD scratch reg (for debug)
+  ELSE: TARGET=[INDSCOM_0x02011E3F(0xFF0000DD)]  OP=[EQUALTO,BUFSTRING,MASK]  DATA=[INDSCOM_0x02011E3F(CONTENTSOF{INDSCOM_0x02011E3F(0xFF0000AA)})] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #Move bits 48-63 from 0xFF0000DD scratch reg to SCOM Reg
+  ELSE: TARGET=[REG(0x02011E3F)] OP=[EQUALTO,BUF,MASK] DATA=[INDSCOM_0x02011E3F(0xFF0000DD)] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #Turn on bits 32, 38, 39 to show successful read
+  ELSE: TARGET=[REG(0x02011E3F)] OP=[OR,ON,BUF] DATA=[LITERAL(64,00000000 83000000]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Indirect Scom Action for 0x0901183F]
+  WATCH=[REG(0x0901183F)]
+  CAUSE: TARGET=[REG(0x0901183F)] OP=[BIT,OFF] BIT=[0] #Write
+  #bits 12-31 contain the indirect address.
+  EFFECT: TARGET=[INDSCOM_0x0901183F(0xFF0000AA)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x0901183F)] MASK=[LITERAL(64,000FFFFF 00000000)]
+  #bits 48-63 contain the indirect SCOM data
+  EFFECT: TARGET=[INDSCOM_0x0901183F(0xFF0000DD)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x0901183F)] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #write 48-63 6010420 to the IND REG
+  EFFECT: TARGET=[INDSCOM_0x0901183F(CONTENTSOF{INDSCOM_0x0901183F(0xFF0000AA)})] OP=[EQUALTO,BUFSTRING] DATA=[INDSCOM_0x0901183F(0xFF0000DD]
+  #Turn on bits 32 and 38 to show successful write
+   EFFECT: TARGET=[REG(0x0901183F)] OP=[OR,ON,BUF] DATA=[LITERAL(64,00000000 82000000]
+  
+  ## Read => if Bit 0 = 1 in SCOM reg, it's a read request
+  #bits 12-31 contain the indirect address
+  ELSE: TARGET=[INDSCOM_0x0901183F(0xFF0000AA)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x0901183F)] MASK=[LITERAL(64,000FFFFF 00000000)]
+  #Move bits 48-63 from IND SCOM reg to 0xFF0000DD scratch reg (for debug)
+  ELSE: TARGET=[INDSCOM_0x0901183F(0xFF0000DD)]  OP=[EQUALTO,BUFSTRING,MASK]  DATA=[INDSCOM_0x0901183F(CONTENTSOF{INDSCOM_0x0901183F(0xFF0000AA)})] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #Move bits 48-63 from 0xFF0000DD scratch reg to SCOM Reg
+  ELSE: TARGET=[REG(0x0901183F)] OP=[EQUALTO,BUF,MASK] DATA=[INDSCOM_0x0901183F(0xFF0000DD)] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #Turn on bits 32, 38, 39 to show successful read
+  ELSE: TARGET=[REG(0x0901183F)] OP=[OR,ON,BUF] DATA=[LITERAL(64,00000000 83000000]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Indirect Scom Action for 0x0401143F]
+  WATCH=[REG(0x0401143F)]
+  CAUSE: TARGET=[REG(0x0401143F)] OP=[BIT,OFF] BIT=[0] #Write
+  #bits 12-31 contain the indirect address.
+  EFFECT: TARGET=[INDSCOM_0x0401143F(0xFF0000AA)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x0401143F)] MASK=[LITERAL(64,000FFFFF 00000000)]
+  #bits 48-63 contain the indirect SCOM data
+  EFFECT: TARGET=[INDSCOM_0x0401143F(0xFF0000DD)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x0401143F)] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #write 48-63 6010420 to the IND REG
+  EFFECT: TARGET=[INDSCOM_0x0401143F(CONTENTSOF{INDSCOM_0x0401143F(0xFF0000AA)})] OP=[EQUALTO,BUFSTRING] DATA=[INDSCOM_0x0401143F(0xFF0000DD]
+  #Turn on bits 32 and 38 to show successful write
+   EFFECT: TARGET=[REG(0x0401143F)] OP=[OR,ON,BUF] DATA=[LITERAL(64,00000000 82000000]
+  
+  ## Read => if Bit 0 = 1 in SCOM reg, it's a read request
+  #bits 12-31 contain the indirect address
+  ELSE: TARGET=[INDSCOM_0x0401143F(0xFF0000AA)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x0401143F)] MASK=[LITERAL(64,000FFFFF 00000000)]
+  #Move bits 48-63 from IND SCOM reg to 0xFF0000DD scratch reg (for debug)
+  ELSE: TARGET=[INDSCOM_0x0401143F(0xFF0000DD)]  OP=[EQUALTO,BUFSTRING,MASK]  DATA=[INDSCOM_0x0401143F(CONTENTSOF{INDSCOM_0x0401143F(0xFF0000AA)})] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #Move bits 48-63 from 0xFF0000DD scratch reg to SCOM Reg
+  ELSE: TARGET=[REG(0x0401143F)] OP=[EQUALTO,BUF,MASK] DATA=[INDSCOM_0x0401143F(0xFF0000DD)] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #Turn on bits 32, 38, 39 to show successful read
+  ELSE: TARGET=[REG(0x0401143F)] OP=[OR,ON,BUF] DATA=[LITERAL(64,00000000 83000000]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Indirect Scom Action for 0x0901143F]
+  WATCH=[REG(0x0901143F)]
+  CAUSE: TARGET=[REG(0x0901143F)] OP=[BIT,OFF] BIT=[0] #Write
+  #bits 12-31 contain the indirect address.
+  EFFECT: TARGET=[INDSCOM_0x0901143F(0xFF0000AA)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x0901143F)] MASK=[LITERAL(64,000FFFFF 00000000)]
+  #bits 48-63 contain the indirect SCOM data
+  EFFECT: TARGET=[INDSCOM_0x0901143F(0xFF0000DD)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x0901143F)] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #write 48-63 6010420 to the IND REG
+  EFFECT: TARGET=[INDSCOM_0x0901143F(CONTENTSOF{INDSCOM_0x0901143F(0xFF0000AA)})] OP=[EQUALTO,BUFSTRING] DATA=[INDSCOM_0x0901143F(0xFF0000DD]
+  #Turn on bits 32 and 38 to show successful write
+   EFFECT: TARGET=[REG(0x0901143F)] OP=[OR,ON,BUF] DATA=[LITERAL(64,00000000 82000000]
+  
+  ## Read => if Bit 0 = 1 in SCOM reg, it's a read request
+  #bits 12-31 contain the indirect address
+  ELSE: TARGET=[INDSCOM_0x0901143F(0xFF0000AA)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x0901143F)] MASK=[LITERAL(64,000FFFFF 00000000)]
+  #Move bits 48-63 from IND SCOM reg to 0xFF0000DD scratch reg (for debug)
+  ELSE: TARGET=[INDSCOM_0x0901143F(0xFF0000DD)]  OP=[EQUALTO,BUFSTRING,MASK]  DATA=[INDSCOM_0x0901143F(CONTENTSOF{INDSCOM_0x0901143F(0xFF0000AA)})] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #Move bits 48-63 from 0xFF0000DD scratch reg to SCOM Reg
+  ELSE: TARGET=[REG(0x0901143F)] OP=[EQUALTO,BUF,MASK] DATA=[INDSCOM_0x0901143F(0xFF0000DD)] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #Turn on bits 32, 38, 39 to show successful read
+  ELSE: TARGET=[REG(0x0901143F)] OP=[OR,ON,BUF] DATA=[LITERAL(64,00000000 83000000]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Indirect Scom Action for 0x04011C3F]
+  WATCH=[REG(0x04011C3F)]
+  CAUSE: TARGET=[REG(0x04011C3F)] OP=[BIT,OFF] BIT=[0] #Write
+  #bits 12-31 contain the indirect address.
+  EFFECT: TARGET=[INDSCOM_0x04011C3F(0xFF0000AA)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x04011C3F)] MASK=[LITERAL(64,000FFFFF 00000000)]
+  #bits 48-63 contain the indirect SCOM data
+  EFFECT: TARGET=[INDSCOM_0x04011C3F(0xFF0000DD)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x04011C3F)] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #write 48-63 6010420 to the IND REG
+  EFFECT: TARGET=[INDSCOM_0x04011C3F(CONTENTSOF{INDSCOM_0x04011C3F(0xFF0000AA)})] OP=[EQUALTO,BUFSTRING] DATA=[INDSCOM_0x04011C3F(0xFF0000DD]
+  #Turn on bits 32 and 38 to show successful write
+   EFFECT: TARGET=[REG(0x04011C3F)] OP=[OR,ON,BUF] DATA=[LITERAL(64,00000000 82000000]
+  
+  ## Read => if Bit 0 = 1 in SCOM reg, it's a read request
+  #bits 12-31 contain the indirect address
+  ELSE: TARGET=[INDSCOM_0x04011C3F(0xFF0000AA)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x04011C3F)] MASK=[LITERAL(64,000FFFFF 00000000)]
+  #Move bits 48-63 from IND SCOM reg to 0xFF0000DD scratch reg (for debug)
+  ELSE: TARGET=[INDSCOM_0x04011C3F(0xFF0000DD)]  OP=[EQUALTO,BUFSTRING,MASK]  DATA=[INDSCOM_0x04011C3F(CONTENTSOF{INDSCOM_0x04011C3F(0xFF0000AA)})] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #Move bits 48-63 from 0xFF0000DD scratch reg to SCOM Reg
+  ELSE: TARGET=[REG(0x04011C3F)] OP=[EQUALTO,BUF,MASK] DATA=[INDSCOM_0x04011C3F(0xFF0000DD)] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #Turn on bits 32, 38, 39 to show successful read
+  ELSE: TARGET=[REG(0x04011C3F)] OP=[OR,ON,BUF] DATA=[LITERAL(64,00000000 83000000]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Indirect Scom Action for 0x02011A3F]
+  WATCH=[REG(0x02011A3F)]
+  CAUSE: TARGET=[REG(0x02011A3F)] OP=[BIT,OFF] BIT=[0] #Write
+  #bits 12-31 contain the indirect address.
+  EFFECT: TARGET=[INDSCOM_0x02011A3F(0xFF0000AA)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x02011A3F)] MASK=[LITERAL(64,000FFFFF 00000000)]
+  #bits 48-63 contain the indirect SCOM data
+  EFFECT: TARGET=[INDSCOM_0x02011A3F(0xFF0000DD)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x02011A3F)] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #write 48-63 6010420 to the IND REG
+  EFFECT: TARGET=[INDSCOM_0x02011A3F(CONTENTSOF{INDSCOM_0x02011A3F(0xFF0000AA)})] OP=[EQUALTO,BUFSTRING] DATA=[INDSCOM_0x02011A3F(0xFF0000DD]
+  #Turn on bits 32 and 38 to show successful write
+   EFFECT: TARGET=[REG(0x02011A3F)] OP=[OR,ON,BUF] DATA=[LITERAL(64,00000000 82000000]
+  
+  ## Read => if Bit 0 = 1 in SCOM reg, it's a read request
+  #bits 12-31 contain the indirect address
+  ELSE: TARGET=[INDSCOM_0x02011A3F(0xFF0000AA)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x02011A3F)] MASK=[LITERAL(64,000FFFFF 00000000)]
+  #Move bits 48-63 from IND SCOM reg to 0xFF0000DD scratch reg (for debug)
+  ELSE: TARGET=[INDSCOM_0x02011A3F(0xFF0000DD)]  OP=[EQUALTO,BUFSTRING,MASK]  DATA=[INDSCOM_0x02011A3F(CONTENTSOF{INDSCOM_0x02011A3F(0xFF0000AA)})] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #Move bits 48-63 from 0xFF0000DD scratch reg to SCOM Reg
+  ELSE: TARGET=[REG(0x02011A3F)] OP=[EQUALTO,BUF,MASK] DATA=[INDSCOM_0x02011A3F(0xFF0000DD)] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #Turn on bits 32, 38, 39 to show successful read
+  ELSE: TARGET=[REG(0x02011A3F)] OP=[OR,ON,BUF] DATA=[LITERAL(64,00000000 83000000]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Indirect Scom Action for 0x0401183F]
+  WATCH=[REG(0x0401183F)]
+  CAUSE: TARGET=[REG(0x0401183F)] OP=[BIT,OFF] BIT=[0] #Write
+  #bits 12-31 contain the indirect address.
+  EFFECT: TARGET=[INDSCOM_0x0401183F(0xFF0000AA)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x0401183F)] MASK=[LITERAL(64,000FFFFF 00000000)]
+  #bits 48-63 contain the indirect SCOM data
+  EFFECT: TARGET=[INDSCOM_0x0401183F(0xFF0000DD)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x0401183F)] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #write 48-63 6010420 to the IND REG
+  EFFECT: TARGET=[INDSCOM_0x0401183F(CONTENTSOF{INDSCOM_0x0401183F(0xFF0000AA)})] OP=[EQUALTO,BUFSTRING] DATA=[INDSCOM_0x0401183F(0xFF0000DD]
+  #Turn on bits 32 and 38 to show successful write
+   EFFECT: TARGET=[REG(0x0401183F)] OP=[OR,ON,BUF] DATA=[LITERAL(64,00000000 82000000]
+  
+  ## Read => if Bit 0 = 1 in SCOM reg, it's a read request
+  #bits 12-31 contain the indirect address
+  ELSE: TARGET=[INDSCOM_0x0401183F(0xFF0000AA)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x0401183F)] MASK=[LITERAL(64,000FFFFF 00000000)]
+  #Move bits 48-63 from IND SCOM reg to 0xFF0000DD scratch reg (for debug)
+  ELSE: TARGET=[INDSCOM_0x0401183F(0xFF0000DD)]  OP=[EQUALTO,BUFSTRING,MASK]  DATA=[INDSCOM_0x0401183F(CONTENTSOF{INDSCOM_0x0401183F(0xFF0000AA)})] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #Move bits 48-63 from 0xFF0000DD scratch reg to SCOM Reg
+  ELSE: TARGET=[REG(0x0401183F)] OP=[EQUALTO,BUF,MASK] DATA=[INDSCOM_0x0401183F(0xFF0000DD)] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #Turn on bits 32, 38, 39 to show successful read
+  ELSE: TARGET=[REG(0x0401183F)] OP=[OR,ON,BUF] DATA=[LITERAL(64,00000000 83000000]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Indirect Scom Action for 0x0401103F]
+  WATCH=[REG(0x0401103F)]
+  CAUSE: TARGET=[REG(0x0401103F)] OP=[BIT,OFF] BIT=[0] #Write
+  #bits 12-31 contain the indirect address.
+  EFFECT: TARGET=[INDSCOM_0x0401103F(0xFF0000AA)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x0401103F)] MASK=[LITERAL(64,000FFFFF 00000000)]
+  #bits 48-63 contain the indirect SCOM data
+  EFFECT: TARGET=[INDSCOM_0x0401103F(0xFF0000DD)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x0401103F)] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #write 48-63 6010420 to the IND REG
+  EFFECT: TARGET=[INDSCOM_0x0401103F(CONTENTSOF{INDSCOM_0x0401103F(0xFF0000AA)})] OP=[EQUALTO,BUFSTRING] DATA=[INDSCOM_0x0401103F(0xFF0000DD]
+  #Turn on bits 32 and 38 to show successful write
+   EFFECT: TARGET=[REG(0x0401103F)] OP=[OR,ON,BUF] DATA=[LITERAL(64,00000000 82000000]
+  
+  ## Read => if Bit 0 = 1 in SCOM reg, it's a read request
+  #bits 12-31 contain the indirect address
+  ELSE: TARGET=[INDSCOM_0x0401103F(0xFF0000AA)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x0401103F)] MASK=[LITERAL(64,000FFFFF 00000000)]
+  #Move bits 48-63 from IND SCOM reg to 0xFF0000DD scratch reg (for debug)
+  ELSE: TARGET=[INDSCOM_0x0401103F(0xFF0000DD)]  OP=[EQUALTO,BUFSTRING,MASK]  DATA=[INDSCOM_0x0401103F(CONTENTSOF{INDSCOM_0x0401103F(0xFF0000AA)})] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #Move bits 48-63 from 0xFF0000DD scratch reg to SCOM Reg
+  ELSE: TARGET=[REG(0x0401103F)] OP=[EQUALTO,BUF,MASK] DATA=[INDSCOM_0x0401103F(0xFF0000DD)] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #Turn on bits 32, 38, 39 to show successful read
+  ELSE: TARGET=[REG(0x0401103F)] OP=[OR,ON,BUF] DATA=[LITERAL(64,00000000 83000000]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Indirect Scom Action for 0x09011C3F]
+  WATCH=[REG(0x09011C3F)]
+  CAUSE: TARGET=[REG(0x09011C3F)] OP=[BIT,OFF] BIT=[0] #Write
+  #bits 12-31 contain the indirect address.
+  EFFECT: TARGET=[INDSCOM_0x09011C3F(0xFF0000AA)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x09011C3F)] MASK=[LITERAL(64,000FFFFF 00000000)]
+  #bits 48-63 contain the indirect SCOM data
+  EFFECT: TARGET=[INDSCOM_0x09011C3F(0xFF0000DD)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x09011C3F)] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #write 48-63 6010420 to the IND REG
+  EFFECT: TARGET=[INDSCOM_0x09011C3F(CONTENTSOF{INDSCOM_0x09011C3F(0xFF0000AA)})] OP=[EQUALTO,BUFSTRING] DATA=[INDSCOM_0x09011C3F(0xFF0000DD]
+  #Turn on bits 32 and 38 to show successful write
+   EFFECT: TARGET=[REG(0x09011C3F)] OP=[OR,ON,BUF] DATA=[LITERAL(64,00000000 82000000]
+  
+  ## Read => if Bit 0 = 1 in SCOM reg, it's a read request
+  #bits 12-31 contain the indirect address
+  ELSE: TARGET=[INDSCOM_0x09011C3F(0xFF0000AA)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x09011C3F)] MASK=[LITERAL(64,000FFFFF 00000000)]
+  #Move bits 48-63 from IND SCOM reg to 0xFF0000DD scratch reg (for debug)
+  ELSE: TARGET=[INDSCOM_0x09011C3F(0xFF0000DD)]  OP=[EQUALTO,BUFSTRING,MASK]  DATA=[INDSCOM_0x09011C3F(CONTENTSOF{INDSCOM_0x09011C3F(0xFF0000AA)})] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #Move bits 48-63 from 0xFF0000DD scratch reg to SCOM Reg
+  ELSE: TARGET=[REG(0x09011C3F)] OP=[EQUALTO,BUF,MASK] DATA=[INDSCOM_0x09011C3F(0xFF0000DD)] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #Turn on bits 32, 38, 39 to show successful read
+  ELSE: TARGET=[REG(0x09011C3F)] OP=[OR,ON,BUF] DATA=[LITERAL(64,00000000 83000000]
+}
+
diff --git a/src/build/citest/etc/patches/patchlist.txt b/src/build/citest/etc/patches/patchlist.txt
index fdaef92ca..216b517ea 100644
--- a/src/build/citest/etc/patches/patchlist.txt
+++ b/src/build/citest/etc/patches/patchlist.txt
@@ -4,8 +4,16 @@ Enable ECCB-based LPC/PNOR access (temporary)
 -Files: p8_pnor.act
 -Coreq: associated changes are also in workarounds.presimsetup
 
+
 Update centaur.act for running DRAM hardware procedures
 -RTC: Story 38362 will be used to remove the patch
 -CQ: SW127616
 -Files: centaur.act
 -Coreq: the file is copied in place by the workarounds.presimsetup
+
+
+Update the Action Files to add behavior for Indirect SCOM error bits
+-RTC: task 38013  will be used to remove the patch
+-CMVC:  Defect 825800 was used to check in the changes in buildIndScom.pl
+-Files: p8_indScom_910431.act , p8_indScom_910520.act in the src/build/citest/etc/patches directory
+-Coreq: associated changes are also in workarounds.presimsetup that need to be removed.
diff --git a/src/build/citest/etc/workarounds.presimsetup b/src/build/citest/etc/workarounds.presimsetup
index 7836ed2b0..0bba2c8b4 100755
--- a/src/build/citest/etc/workarounds.presimsetup
+++ b/src/build/citest/etc/workarounds.presimsetup
@@ -72,7 +72,7 @@ echo "  0xDDDD0001,64  # dummy to hold pnor data" >> $sb/simu/data/cec-chip/p8.c
 echo "END" >> $sb/simu/data/cec-chip/p8.chip
 echo "DONE" >> $sb/simu/data/cec-chip/p8.chip
 cp $HOSTBOOTROOT/src/build/citest/etc/patches/p8_pnor.act $sb/simu/data/cec-chip/
-#fixme
+#fixme Story 37972
 
 
 echo "+++ Copy new centaur.act for DRAM hardware procedures."
@@ -88,3 +88,8 @@ cp $HOSTBOOTROOT/src/build/citest/etc/patches/centaur.act $sb/simu/data/cec-chip
 #sed -i -e's/^WSALIAS HOSTBOOT_LEVEL MAMBOLEVEL.*/WSALIAS HOSTBOOT_LEVEL MAMBOLEVEL env\/mamboa\/2011_11_10__4.2/' $sb/simu/data/simicsInfo
 #sed -i -e's/^WSALIAS HOSTBOOT_LEVEL PHYPLEVEL.*/WSALIAS HOSTBOOT_LEVEL PHYPLEVEL env\/phypa\/simics-4.2.0\/simics-4.2.83\/ph120201a700.42/' $sb/simu/data/simicsInfo
 #sed -i -e's/^WSALIAS HOSTBOOT_LEVEL PHYP_PATCH_LEVEL.*/WSALIAS HOSTBOOT_LEVEL PHYP_PATCH_LEVEL env\/phypa\/simics-4.2.0\/simics-4.2.82\/patches\/ph120201a700.42/' $sb/simu/data/simicsInfo
+
+# added this patch until defect 825800 is integrated and included in a hostboot bbuild.
+echo "+++ Add workaround for p8 Indirect SCOM action files."
+cp --update $HOSTBOOTROOT/src/build/citest/etc/patches/p8_indScom_910431.act $sb/simu/data/cec-chip/p8_indScom_910431.act
+cp --update $HOSTBOOTROOT/src/build/citest/etc/patches/p8_indScom_910520.act $sb/simu/data/cec-chip/p8_indScom_910520.act