diff options
14 files changed, 340 insertions, 234 deletions
diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_epsilon.C b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_epsilon.C index 16f920c4e..2984fc0ae 100644 --- a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_epsilon.C +++ b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_epsilon.C @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012,2013 */ +/* COPYRIGHT International Business Machines Corp. 2012,2014 */ /* */ /* p1 */ /* */ @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_build_smp_epsilon.C,v 1.8 2013/07/30 23:52:27 jmcgill Exp $ +// $Id: proc_build_smp_epsilon.C,v 1.9 2013/11/13 01:46:55 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_build_smp_epsilon.C,v $ //------------------------------------------------------------------------------ // *| @@ -1151,7 +1151,6 @@ fapi::ReturnCode proc_build_smp_calc_epsilons( io_smp.eps_cfg.r_f = PROC_BUILD_SMP_EPSILON_R_F_HE[io_smp.core_floor_ratio]; io_smp.eps_cfg.w_t2 = PROC_BUILD_SMP_EPSILON_W_HE[io_smp.core_floor_ratio]; io_smp.eps_cfg.w_f = PROC_BUILD_SMP_EPSILON_W_F_HE[io_smp.core_floor_ratio]; - io_smp.eps_cfg.p = PROC_BUILD_SMP_EPSILON_P_HE[io_smp.core_floor_ratio]; break; case PROC_FAB_SMP_EPSILON_TABLE_TYPE_LE: if (io_smp.pump_mode == PROC_FAB_SMP_PUMP_MODE1) @@ -1167,7 +1166,6 @@ fapi::ReturnCode proc_build_smp_calc_epsilons( io_smp.eps_cfg.r_f = PROC_BUILD_SMP_EPSILON_R_F_LE[io_smp.core_floor_ratio]; io_smp.eps_cfg.w_t2 = PROC_BUILD_SMP_EPSILON_W_LE[io_smp.core_floor_ratio]; io_smp.eps_cfg.w_f = PROC_BUILD_SMP_EPSILON_W_F_LE[io_smp.core_floor_ratio]; - io_smp.eps_cfg.p = PROC_BUILD_SMP_EPSILON_P_LE[io_smp.core_floor_ratio]; break; case PROC_FAB_SMP_EPSILON_TABLE_TYPE_1S: if (io_smp.pump_mode == PROC_FAB_SMP_PUMP_MODE1) @@ -1183,7 +1181,6 @@ fapi::ReturnCode proc_build_smp_calc_epsilons( io_smp.eps_cfg.r_f = PROC_BUILD_SMP_EPSILON_R_F_1S[io_smp.core_floor_ratio]; io_smp.eps_cfg.w_t2 = PROC_BUILD_SMP_EPSILON_W_1S[io_smp.core_floor_ratio]; io_smp.eps_cfg.w_f = PROC_BUILD_SMP_EPSILON_W_F_1S[io_smp.core_floor_ratio]; - io_smp.eps_cfg.p = PROC_BUILD_SMP_EPSILON_P_1S[io_smp.core_floor_ratio]; break; default: FAPI_ERR("proc_build_smp_calc_epsilons: Invalid epsilon table type"); @@ -1203,9 +1200,44 @@ fapi::ReturnCode proc_build_smp_calc_epsilons( FAPI_DBG("proc_build_smp_calc_epsilons: R_F = %d", io_smp.eps_cfg.r_f); FAPI_DBG("proc_build_smp_calc_epsilons: W_T2 = %d", io_smp.eps_cfg.w_t2); FAPI_DBG("proc_build_smp_calc_epsilons: W_F = %d", io_smp.eps_cfg.w_f); - FAPI_DBG("proc_build_smp_calc_epsilons: P = %d", io_smp.eps_cfg.p); - // apply guardband to base epsilon values + // scale base epsilon values if core is running 2x nest frequency + if (io_smp.core_ceiling_ratio == PROC_BUILD_SMP_CORE_RATIO_8_8) + { + FAPI_DBG("proc_build_smp_calc_epsilons: Scaling based on ceiling frequency"); + uint8_t scale_percentage = + 100 * + io_smp.freq_core_ceiling / + (2 * io_smp.freq_pb); + scale_percentage -= 100; + + proc_build_smp_guardband_epsilon( + io_smp.eps_cfg.gb_positive, + scale_percentage, + io_smp.eps_cfg.r_t0); + proc_build_smp_guardband_epsilon( + io_smp.eps_cfg.gb_positive, + scale_percentage, + io_smp.eps_cfg.r_t1); + proc_build_smp_guardband_epsilon( + io_smp.eps_cfg.gb_positive, + scale_percentage, + io_smp.eps_cfg.r_t2); + proc_build_smp_guardband_epsilon( + io_smp.eps_cfg.gb_positive, + scale_percentage, + io_smp.eps_cfg.r_f); + proc_build_smp_guardband_epsilon( + io_smp.eps_cfg.gb_positive, + scale_percentage, + io_smp.eps_cfg.w_t2); + proc_build_smp_guardband_epsilon( + io_smp.eps_cfg.gb_positive, + scale_percentage, + io_smp.eps_cfg.w_f); + } + + // apply guardband to epsilon values proc_build_smp_guardband_epsilon( io_smp.eps_cfg.gb_positive, io_smp.eps_cfg.gb_percentage, @@ -1230,10 +1262,9 @@ fapi::ReturnCode proc_build_smp_calc_epsilons( io_smp.eps_cfg.gb_positive, io_smp.eps_cfg.gb_percentage, io_smp.eps_cfg.w_f); - proc_build_smp_guardband_epsilon( - io_smp.eps_cfg.gb_positive, - io_smp.eps_cfg.gb_percentage, - io_smp.eps_cfg.p); + + // max pre-epsilon counter + io_smp.eps_cfg.p = PROC_BUILD_SMP_EPSILON_MCD_MAX_VALUE_P-1; // dump scaled epsilon values FAPI_DBG("proc_build_smp_calc_epsilons: Scaled epsilon values based on %s%d%% guardband:", diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_epsilon.H b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_epsilon.H index 42115520c..00a3ae2e2 100644 --- a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_epsilon.H +++ b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_epsilon.H @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012,2013 */ +/* COPYRIGHT International Business Machines Corp. 2012,2014 */ /* */ /* p1 */ /* */ @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_build_smp_epsilon.H,v 1.6 2013/07/30 23:46:30 jmcgill Exp $ +// $Id: proc_build_smp_epsilon.H,v 1.7 2013/11/13 01:49:53 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_build_smp_epsilon.H,v $ //------------------------------------------------------------------------------ // *| @@ -62,7 +62,6 @@ const uint32_t PROC_BUILD_SMP_EPSILON_R_T2_HE[] = { 102, 104, 105, 108, 111 const uint32_t PROC_BUILD_SMP_EPSILON_R_F_HE[] = { 66, 67, 69, 71, 75, 93 }; const uint32_t PROC_BUILD_SMP_EPSILON_W_HE[] = { 46, 47, 47, 48, 50, 55 }; const uint32_t PROC_BUILD_SMP_EPSILON_W_F_HE[] = { 37, 38, 39, 40, 40, 46 }; -const uint32_t PROC_BUILD_SMP_EPSILON_P_HE[] = { 771, 1338, 1338, 1338, 1338, 1338 }; // LE epsilon (2 chips per-group) const uint32_t PROC_BUILD_SMP_EPSILON_R_T0_LE[] = { 6, 6, 7, 8, 9, 15 }; @@ -71,7 +70,6 @@ const uint32_t PROC_BUILD_SMP_EPSILON_R_T2_LE[] = { 93, 95, 96, 99, 102 const uint32_t PROC_BUILD_SMP_EPSILON_R_F_LE[] = { 66, 67, 69, 71, 75, 93 }; const uint32_t PROC_BUILD_SMP_EPSILON_W_LE[] = { 46, 47, 47, 48, 50, 55 }; const uint32_t PROC_BUILD_SMP_EPSILON_W_F_LE[] = { 37, 38, 39, 40, 40, 46 }; -const uint32_t PROC_BUILD_SMP_EPSILON_P_LE[] = { 925, 1605, 1605, 1605, 1605, 1605 }; // Stradale epsilon (1 chip per-group) const uint32_t PROC_BUILD_SMP_EPSILON_R_T0_1S[] = { 6, 6, 7, 8, 9, 15 }; @@ -80,7 +78,6 @@ const uint32_t PROC_BUILD_SMP_EPSILON_R_T2_1S[] = { 63, 64, 65, 68, 72 const uint32_t PROC_BUILD_SMP_EPSILON_R_F_1S[] = { 66, 67, 69, 71, 75, 93 }; const uint32_t PROC_BUILD_SMP_EPSILON_W_1S[] = { 14, 14, 15, 15, 16, 23 }; const uint32_t PROC_BUILD_SMP_EPSILON_W_F_1S[] = { 37, 38, 39, 40, 40, 46 }; -const uint32_t PROC_BUILD_SMP_EPSILON_P_1S[] = { 925, 1605, 1605, 1605, 1605, 1605 }; // diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pmc_deconfig_setup_errors.xml b/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pmc_deconfig_setup_errors.xml index 6c0b4bc87..e447f7c0c 100644 --- a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pmc_deconfig_setup_errors.xml +++ b/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pmc_deconfig_setup_errors.xml @@ -5,7 +5,7 @@ <!-- --> <!-- IBM CONFIDENTIAL --> <!-- --> -<!-- COPYRIGHT International Business Machines Corp. 2012,2013 --> +<!-- COPYRIGHT International Business Machines Corp. 2012,2014 --> <!-- --> <!-- p1 --> <!-- --> @@ -20,13 +20,10 @@ <!-- Origin: 30 --> <!-- --> <!-- IBM_PROLOG_END_TAG --> -<!-- $Id: p8_pmc_deconfig_setup_errors.xml,v 1.2 2013/05/23 18:44:24 stillgs Exp $ --> +<!-- $Id: p8_pmc_deconfig_setup_errors.xml,v 1.3 2013/10/15 17:36:08 dcrowell Exp $ --> <!-- Error definitions for p8_pmc_deconfig_setup procedure --> <hwpErrors> <!-- *********************************************************************** --> - <hwpError> - <rc>RC_PROCPM_PMC_DECONFIG_NO_CORES</rc> - <description>p8_pmc_deconfig_setup did not find any configured core.</description> - </hwpError> + <!-- No errors yet, keeping as placeholder --> <!-- *********************************************************************** --> </hwpErrors> diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_pore_table_gen_api_fixed.C b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_pore_table_gen_api_fixed.C index df9f260a0..df348368d 100644 --- a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_pore_table_gen_api_fixed.C +++ b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_pore_table_gen_api_fixed.C @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2013 */ +/* COPYRIGHT International Business Machines Corp. 2013,2014 */ /* */ /* p1 */ /* */ @@ -20,23 +20,22 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: p8_pore_table_gen_api_fixed.C,v 1.10 2013/09/16 17:55:05 cmolsen Exp $ +// $Id: p8_pore_table_gen_api_fixed.C,v 1.12 2014/01/28 04:16:57 cmolsen Exp $ // /*------------------------------------------------------------------------------*/ /* *! (C) Copyright International Business Machines Corp. 2012 */ /* *! All Rights Reserved -- Property of IBM */ /* *! *** IBM Confidential *** */ /*------------------------------------------------------------------------------*/ -/* *! TITLE : p8_pore_table_gen_api_fixed.C */ +/* *! TITLE : p8_pore_table_gen_api_fixed.C */ /* *! DESCRIPTION : PORE SLW table generaion APIs */ /* *! OWNER NAME : Michael Olsen Email: cmolsen@us.ibm.com */ +// /* *! USAGE : To build for PHYP command-line - */ -// buildecmdprcd_cmo -D "p8_pore_table_gen_api_fixed.C" -d "p8_pore_table_static_data.c,sbe_xip_image.c,pore_inline_assembler.c" -u "SLW_COMMAND_LINE_RAM" p8_pore_table_gen_api_fixed_main.C -// Other usages: +/* buildecmdprcd -C "p8_pore_table_gen_api_fixed.C" -c "p8_pore_table_static_data.c,sbe_xip_image.c,pore_inline_assembler.c" -u "SLW_COMMAND_LINE_RAM" p8_pore_table_gen_api_fixed_main.C */ // -/* *! COMMENTS : - Start file: p7p_pore_api.c */ -// - The DYNAMIC_RAM_TABLE_PPD was dropped in v1.12 of this -// code. See v1.12 for explanation and code implementation. +/* *! COMMENTS : - The DYNAMIC_RAM_TABLE_PPD was dropped in v1.12 of this */ +/* code. See v1.12 for explanation and code implementation. */ // /*------------------------------------------------------------------------------*/ @@ -67,8 +66,8 @@ uint32_t p8_pore_gen_cpureg_fixed( void *io_image, void *hostSlwSectionFixed; uint64_t xipRamTableThis; void *hostRamVector; - void *hostRamTableThis; - void *hostRamEntryThis, *hostRamEntryNext; + void *hostRamTableThis=NULL; + void *hostRamEntryThis=NULL, *hostRamEntryNext=NULL; uint8_t bNewTable=0, bFound=0; uint8_t bEntryEnd=1, headerType=0; SbeXipSection xipSection; @@ -211,64 +210,15 @@ uint32_t p8_pore_gen_cpureg_fixed( void *io_image, } } - // ------------------------------------------------------------------------- - // Determine insertion point, hostRamEntryThis, of new RAM entry - // - if (bNewTable) { - // Append to beginning of agreed upon static Ram table position for this coreId. - hostRamEntryThis = hostRamTableThis; - if (i_modeBuild==P8_SLW_MODEBUILD_SRAM) { - // Update RAM vector (since it is currently NULL) - *((uint64_t*)hostRamVector + i_coreId) = - myRev64( xipSlwRamSection + - SLW_RAM_TABLE_SPACE_PER_CORE*i_coreId ); - } - bEntryEnd = 1; - } - else { - // Insert at end of existing Ram table for this coreId. - hostRamEntryNext = hostRamTableThis; - ramEntryNext = (RamTableEntry*)hostRamEntryNext; - iCount = 1; - while ((myRev32(ramEntryNext->header) & RAM_HEADER_END_MASK_C)==0) { - if (iCount>=SLW_MAX_CPUREGS_OPS) { - MY_ERR("Bad table! Header end bit not found and RAM table full (=%i entries).\n",SLW_MAX_CPUREGS_OPS); - return IMGBUILD_ERR_RAM_TABLE_END_NOT_FOUND; - } - hostRamEntryNext = (void*)((uint8_t*)hostRamEntryNext + XIPSIZE_RAM_ENTRY); - ramEntryNext = (RamTableEntry*)hostRamEntryNext; - iCount++; - } - if (iCount<SLW_MAX_CPUREGS_OPS) { - // ...zero out previous END bit in header - if ((myRev32(ramEntryNext->header) & RAM_HEADER_END_MASK_C)) { - ramEntryNext->header = ramEntryNext->header & myRev32(~RAM_HEADER_END_MASK_C); - } - else { - MY_ERR("We should never get here. Check code. Dumping data:\n"); - MY_ERR("myRev32(ramEntryNext->header) = 0x%08x\n",myRev32(ramEntryNext->header)); - MY_ERR("RAM_HEADER_END_MASK_C = 0x%08x\n",RAM_HEADER_END_MASK_C); - return IMGBUILD_ERR_RAM_CODE; - } - } - else { - MY_ERR("RAM table is full. Max %i entries allowed.\n",SLW_MAX_CPUREGS_OPS); - return IMGBUILD_ERR_RAM_TABLE_FULL; - } - // ...this is the spot for the new entry - hostRamEntryThis = (void*)((uint8_t*)hostRamEntryNext + XIPSIZE_RAM_ENTRY); - bEntryEnd = 1; - } - - // ------------------------------------------------------------------------- - // Create, or modify, the RAM entry. + // ------------------------------------------------------------------------- + // Create most of the RAM entry, so it can be used to find a potential existing entry to + // replace. Postpone decision about bEntryEnd and assume its zero for now (not end). // if (i_regName==P8_MSR_MSR) { // ...make the MSR header headerType = 0x1; // MTMSRD header. - ramEntryThis.header = ( ((uint32_t)bEntryEnd) << RAM_HEADER_END_START_C & RAM_HEADER_END_MASK_C ) | - ( ((uint32_t)headerType) << RAM_HEADER_TYPE_START_C & RAM_HEADER_TYPE_MASK_C ) | + ramEntryThis.header = ( ((uint32_t)headerType) << RAM_HEADER_TYPE_START_C & RAM_HEADER_TYPE_MASK_C ) | ( i_threadId << RAM_HEADER_THREAD_START_C & RAM_HEADER_THREAD_MASK_C ); // ...make the MSR instr ramEntryThis.instr = RAM_MTMSRD_INSTR_TEMPL_C; @@ -276,8 +226,7 @@ uint32_t p8_pore_gen_cpureg_fixed( void *io_image, else { // ...make the SPR header headerType = 0x0; // MTSPR header. - ramEntryThis.header = ( ((uint32_t)bEntryEnd) << RAM_HEADER_END_START_C & RAM_HEADER_END_MASK_C ) | - ( ((uint32_t)headerType) << RAM_HEADER_TYPE_START_C & RAM_HEADER_TYPE_MASK_C ) | + ramEntryThis.header = ( ((uint32_t)headerType) << RAM_HEADER_TYPE_START_C & RAM_HEADER_TYPE_MASK_C ) | ( i_regName << RAM_HEADER_SPRN_START_C & RAM_HEADER_SPRN_MASK_C ) | ( i_threadId << RAM_HEADER_THREAD_START_C & RAM_HEADER_THREAD_MASK_C ); // ...make the SPR instr @@ -292,7 +241,104 @@ uint32_t p8_pore_gen_cpureg_fixed( void *io_image, } // ...make the data ramEntryThis.data = i_regData; - // ...summarize new table entry data + + + + // ------------------------------------------------------------------------- + // Determine insertion point of new RAM entry, hostRamEntryThis. The possibilities are: + // - New table => First entry + // - Existing Ram entry => Replace said entry + // - Existing table, new Ram entry => Last entry + // + uint8_t bReplaceEntry=0; + uint32_t headerNext=0; + uint32_t instrNext=0; + + bReplaceEntry = 0; + if (bNewTable) { + // Append to beginning of agreed upon static Ram table position for this coreId. + bEntryEnd = 1; + ramEntryThis.header = ( ((uint32_t)bEntryEnd) << RAM_HEADER_END_START_C & RAM_HEADER_END_MASK_C ) | + ramEntryThis.header; + hostRamEntryThis = hostRamTableThis; + if (i_modeBuild==P8_SLW_MODEBUILD_SRAM) { + // Update RAM vector (since it is currently NULL) + *((uint64_t*)hostRamVector + i_coreId) = + myRev64( xipSlwRamSection + SLW_RAM_TABLE_SPACE_PER_CORE*i_coreId ); + } + } + else { + // Append at end of existing Ram table for this coreId + // or + // Replace an existing Ram entry + hostRamEntryNext = hostRamTableThis; + ramEntryNext = (RamTableEntry*)hostRamEntryNext; + headerNext = myRev32(ramEntryNext->header); + instrNext = myRev32(ramEntryNext->instr); + iCount = 1; + // Examine all entries, except last entry. + while ((headerNext & RAM_HEADER_END_MASK_C)==0 && bReplaceEntry==0) { + if (iCount>=SLW_MAX_CPUREGS_OPS) { + MY_ERR("Bad table! Header end bit not found and RAM table full (=%i entries).\n",SLW_MAX_CPUREGS_OPS); + return IMGBUILD_ERR_RAM_TABLE_END_NOT_FOUND; + } + if (ramEntryThis.header==headerNext && ramEntryThis.instr==instrNext) { + // Its a replacement. Stop searching. Go do the replacement. + bReplaceEntry = 1; + hostRamEntryThis = hostRamEntryNext; + } + else { + hostRamEntryNext = (void*)((uint8_t*)hostRamEntryNext + XIPSIZE_RAM_ENTRY); + ramEntryNext = (RamTableEntry*)hostRamEntryNext; + headerNext = myRev32(ramEntryNext->header); + instrNext = myRev32(ramEntryNext->instr); + iCount++; + } + } + if (bReplaceEntry==0) { + // Examine the last entry. + if (headerNext & RAM_HEADER_END_MASK_C) { + // Now we know for sure that our new Ram entry will also be the last, either as a + // replace or append. So put the end bit into the new entry. + bEntryEnd = 1; + ramEntryThis.header = ( ((uint32_t)bEntryEnd) << RAM_HEADER_END_START_C & RAM_HEADER_END_MASK_C ) | + ramEntryThis.header; + // Determine if to replace or append. + if (ramEntryThis.header==headerNext && ramEntryThis.instr==instrNext) { + // Its a replacement. And it would be legal to replace the very last Ram in a completely full table. + if (iCount<=SLW_MAX_CPUREGS_OPS) { + bReplaceEntry = 1; + hostRamEntryThis = hostRamEntryNext; + } + else { + MY_ERR("RAM table is full. Max %i entries allowed.\n",SLW_MAX_CPUREGS_OPS); + return IMGBUILD_ERR_RAM_TABLE_FULL; + } + } + else { + // Its an append. Make sure there's room for one more Ram entry. + if (iCount<SLW_MAX_CPUREGS_OPS) { + // Zero out the end bit in last entrys header (which will now be 2nd last). + ramEntryNext->header = ramEntryNext->header & myRev32(~RAM_HEADER_END_MASK_C); + hostRamEntryThis = (void*)((uint8_t*)hostRamEntryNext + XIPSIZE_RAM_ENTRY); + } + else { + MY_ERR("RAM table is full. Max %i entries allowed.\n",SLW_MAX_CPUREGS_OPS); + return IMGBUILD_ERR_RAM_TABLE_FULL; + } + } + } + else { + MY_ERR("We should never get here. Check code. Dumping data:\n"); + MY_ERR("myRev32(ramEntryNext->header) = 0x%08x\n",myRev32(ramEntryNext->header)); + MY_ERR("RAM_HEADER_END_MASK_C = 0x%08x\n",RAM_HEADER_END_MASK_C); + return IMGBUILD_ERR_RAM_CODE; + } + } + } + + + // Summarize new table entry data MY_INF("New table entry data (host format):\n"); MY_INF("\theader = 0x%08x\n",ramEntryThis.header); MY_INF("\tinstr = 0x%08x\n",ramEntryThis.instr); @@ -313,6 +359,7 @@ uint32_t p8_pore_gen_cpureg_fixed( void *io_image, rc = IMGBUILD_WARN_RAM_TABLE_CONTAMINATION; } } + // ..insert the new Ram entry. ramEntryNext->header = myRev32(ramEntryThis.header); ramEntryNext->instr = myRev32(ramEntryThis.instr); ramEntryNext->data = myRev64(ramEntryThis.data); diff --git a/src/usr/hwpf/hwp/centaur_ec_attributes.xml b/src/usr/hwpf/hwp/centaur_ec_attributes.xml index ca96e6f95..56de022c3 100644 --- a/src/usr/hwpf/hwp/centaur_ec_attributes.xml +++ b/src/usr/hwpf/hwp/centaur_ec_attributes.xml @@ -22,7 +22,24 @@ <!-- IBM_PROLOG_END_TAG --> <attributes> <!-- ********************************************************************* --> - <!-- $Id: centaur_ec_attributes.xml,v 1.16 2013/12/19 17:12:52 pardeik Exp $ --> + <!-- $Id: centaur_ec_attributes.xml,v 1.17 2014/01/21 15:19:37 yctschan Exp $ --> + <attribute> + <id>ATTR_CENTAUR_EC_ENABLE_PAGE_MODE_FOR_RRQ</id> + <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> + <description> + Set by the platform depending on DD2.x or newer (TRUE), otherwise FALSE. If true, it allows super fast read to go faster. MBA_RRQ0Q(57) cfg_rrq_opp_page_mode_en RW DD2 is set. + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_CENTAUR</name> + <ec> + <value>0x20</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <attribute> <id>ATTR_CENTAUR_EC_ENABLE_TRACE_LCL_CLK_GATE_CTRL</id> <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> diff --git a/src/usr/hwpf/hwp/core_activate/proc_prep_master_winkle/proc_sbe_trigger_winkle.H b/src/usr/hwpf/hwp/core_activate/proc_prep_master_winkle/proc_sbe_trigger_winkle.H index 3abd8a176..dc6161377 100644 --- a/src/usr/hwpf/hwp/core_activate/proc_prep_master_winkle/proc_sbe_trigger_winkle.H +++ b/src/usr/hwpf/hwp/core_activate/proc_prep_master_winkle/proc_sbe_trigger_winkle.H @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012 */ +/* COPYRIGHT International Business Machines Corp. 2012,2014 */ /* */ /* p1 */ /* */ @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_sbe_trigger_winkle.H,v 1.6 2012/09/21 19:29:25 stillgs Exp $ +// $Id: proc_sbe_trigger_winkle.H,v 1.8 2013/10/18 17:23:48 jeshua Exp $ /// Substep numbers for the proc_sbe_trigger_winkle procedure @@ -30,6 +30,7 @@ #include "fapi_sbe_common.H" #include "sbe_vital.H" +//NOTE: The following values must stay constant as HB looks for them CONST_UINT8_T(SUBSTEP_PROC_ENTRY, ULL(0x0)); CONST_UINT8_T(SUBSTEP_SBE_READY, ULL(0x1)); CONST_UINT8_T(SUBSTEP_DEADMAN_START, ULL(0x2)); @@ -38,5 +39,13 @@ CONST_UINT8_T(SUBSTEP_DEADMAN_WAITING_FOR_WAKEUP, ULL(0x4)); CONST_UINT8_T(SUBSTEP_DEADMAN_WAITING_FOR_HOSTBOOT, ULL(0x5)); CONST_UINT8_T(SUBSTEP_HOSTBOOT_ALIVE_AGAIN, ULL(0x6)); +#ifdef __ASSEMBLER__ +// The location in the proc_sbe_trigger_winkle_control +// containing the mask of threads to start +//WARNING: if thread_start_vector_start is changed from 16, +//then the code needs to be updated to shift it to bit 16 +.set THREAD_START_VECTOR_START, 16 +.set THREAD_START_VECTOR_LENGTH, 8 +#endif #endif // __PROC_SBE_TRIGGER_WINKLE_H diff --git a/src/usr/hwpf/hwp/dmi_training/mss_getecid/mss_get_cen_ecid_decode.C b/src/usr/hwpf/hwp/dmi_training/mss_getecid/mss_get_cen_ecid_decode.C index 2d83f9854..8e90d6159 100644 --- a/src/usr/hwpf/hwp/dmi_training/mss_getecid/mss_get_cen_ecid_decode.C +++ b/src/usr/hwpf/hwp/dmi_training/mss_getecid/mss_get_cen_ecid_decode.C @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2013 */ +/* COPYRIGHT International Business Machines Corp. 2013,2014 */ /* */ /* p1 */ /* */ @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_get_cen_ecid_decode.C,v 1.6 2013/10/07 11:42:06 bellows Exp $ +// $Id: mss_get_cen_ecid_decode.C,v 1.8 2013/10/14 16:22:30 bellows Exp $ //------------------------------------------------------------------------------ // *| // *! (C) Copyright International Business Machines Corp. 2013 @@ -39,6 +39,8 @@ //------------------------------------------------------------------------------ // Version:| Author: | Date: | Comment: //---------|----------|---------|----------------------------------------------- +// 1.8 | bellows |14-OCT-13| One more sprintf update to make this hostboot/cronus agnostic +// 1.7 | bellows |08-OCT-13| Made update so it compiles with cronus + hostboot // 1.6 | thi |05-OCT-13| Fix compiler error // 1.5 | bellows |02-OCT-13| Minor Review Comments addressed // 1.4 | bellows |27-SEP-13| Removed std::string @@ -131,9 +133,9 @@ extern "C" { if(!(i_user_info.i_user_defined & CSV)) { - sprintf(temp_string, "ECID(1:64) 0x%016lx\n", i_user_info.io_ecid[0]); + sprintf(temp_string, "ECID(1:64) 0x%016llx\n", static_cast<unsigned long long int>(i_user_info.io_ecid[0])); strcat(o_display_string, temp_string); - sprintf(temp_string, "ECID(65:128) 0x%016lx\n", i_user_info.io_ecid[1]); + sprintf(temp_string, "ECID(65:128) 0x%016llx\n", static_cast<unsigned long long int>(i_user_info.io_ecid[1])); strcat(o_display_string, temp_string); sprintf(temp_string, " Wafer ID: %s\n", ECID); strcat(o_display_string, temp_string); diff --git a/src/usr/hwpf/hwp/initfiles/mba_def.initfile b/src/usr/hwpf/hwp/initfiles/mba_def.initfile index 8b98151e7..591bf552d 100644 --- a/src/usr/hwpf/hwp/initfiles/mba_def.initfile +++ b/src/usr/hwpf/hwp/initfiles/mba_def.initfile @@ -1,9 +1,11 @@ -#-- $Id: mba_def.initfile,v 1.55 2014/01/10 17:03:04 yctschan Exp $ +#-- $Id: mba_def.initfile,v 1.57 2014/01/24 16:03:14 yctschan Exp $ #-- CHANGE HISTORY: #-------------------------------------------------------------------------------- #-- Version:|Author: | Date: | Comment: #-- --------|--------|--------|-------------------------------------------------- +#-- 1.57|tschang | 1/22/14| DD2 enhancement - Enable Page Mode for the Read Reorder Queue - MBA_RRQ0Q(57) = 1 +#-- 1.56|baysah | 1/16/14| Changed row hammer primary decrement interval from 64K DRAM clocks (3200 accesses) to 512 DRAM clocks (100K accesses) to hash group. #-- 1.55|tschang | 1/07/14| ATTR_EFF_DRAM_TFAW attribute used for TFAW timing register. #-- 1.54|tschang |11/21/13| HW271989 - updated SCOM write to do a full 64 bit write instead of a RMW #-- 1.53|tschang |11/12/13|EFF to VPD attribute update @@ -1675,6 +1677,16 @@ define def_mcb_addr_total22_max24 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATT define def_mcb_addr_total22_max25 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) == 8) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 22 )); ####################################### +# MBA01_MBA_RRQ0Q Base Address: 0x0301040E +# MBA23_MBA_RRQ0Q Base Address: 0x03010C0E +####################################### + +scom 0x0301040E { + bits , scom_data , ATTR_FUNCTIONAL, expr; + 57 , 0b1 , 1 , (ATTR_CENTAUR_EC_ENABLE_PAGE_MODE_FOR_RRQ == 1); # Enable Page Mode for the Read Reorder Queue +} + +####################################### #MBA01 MBASRQ Base Address: 0x03010416 #MBA23 MBASRQ Base Address: 0x03010C16 ####################################### @@ -1700,7 +1712,6 @@ scom 0x03010416 { 31:44 , ATTR_MSS_MEM_THROTTLE_DENOMINATOR , 1 , any; # cfg_nm_m MSS_MEM_THROTTLE_DENOMINATOR 45:47 , ATTR_MSS_THROTTLE_CONTROL_RAS_WEIGHT , 1 , any; # cfg_nm_ras_weight 48:50 , ATTR_MSS_THROTTLE_CONTROL_CAS_WEIGHT , 1 , any; # cfg_nm_cas_weight -# 51 , 0b1 , 1 , any; # cfg_nm_per_slot_enabled 1 51 , 0b0 , 1 , (ATTR_EFF_DIMM_TYPE == 0); # cfg_nm_per_slot_enabled Set to 0 for CDIMM, Set to 1 for everything else 51 , 0b1 , 1 , ((ATTR_EFF_DIMM_TYPE == 1) || (ATTR_EFF_DIMM_TYPE == 2) || (ATTR_EFF_DIMM_TYPE == 3)); # cfg_nm_per_slot_enabled Set to 0 for CDIMM, Set to 1 for everything else 52 , 0b0 , 1 , (ATTR_EFF_DIMM_TYPE == 0); # cfg_nm_count_other_mba_dis Set to 0 for CDIMM, Set to 1 for everything else @@ -1719,6 +1730,7 @@ scom 0x03010416 { #MBA_FARB4Q(4:9) Reserved 000000 Don't Care #MBA_FARB4Q(10:11) cfg_rhmr_decrement_weight 01 Decrement by 1 (minimum weight) #MBA_FARB4Q(12:18) cfg_rhmr_primary_decr_intv 1111111 Slowest rate of decrements. Once ever 2^14 or 16K DRAM clocks* +#MBA_FARB4Q(12:18) cfg_rhmr_primary_decr_intv 0000011 decrement every 512 DRAM clocks for 100K accesses to hash group #MBA_FARB4Q(19:25) cfg_rhmr_secondary_decr_intv 0000000 Don't care #MBA_FARB4Q(26) cfg_rhmr_sim_en 0 Disable sim mode #*I think this corresponds to protecting a row from being hammered 64K times. @@ -1730,7 +1742,7 @@ scom 0x03010417 { 3 , 0b0 , 1 , (ATTR_CENTAUR_EC_ENABLE_ROW_HAMMER_FEATURE == 1); 4:9 , 0b000000 , 1 , (ATTR_CENTAUR_EC_ENABLE_ROW_HAMMER_FEATURE == 1); 10:11 , 0b01 , 1 , (ATTR_CENTAUR_EC_ENABLE_ROW_HAMMER_FEATURE == 1); - 12:18 , 0b1111111 , 1 , (ATTR_CENTAUR_EC_ENABLE_ROW_HAMMER_FEATURE == 1); + 12:18 , 0b0000011 , 1 , (ATTR_CENTAUR_EC_ENABLE_ROW_HAMMER_FEATURE == 1); 19:25 , 0b0000000 , 1 , (ATTR_CENTAUR_EC_ENABLE_ROW_HAMMER_FEATURE == 1); 26 , 0b0 , 1 , (ATTR_CENTAUR_EC_ENABLE_ROW_HAMMER_FEATURE == 1); } @@ -2068,15 +2080,6 @@ scom 0x0301040C { 7:13 , 0b0110011 , 1 , (def_mba_tmr1q_cfg_twap51 == 1); # cfg_twap 17 7:13 , 0b0110101 , 1 , (def_mba_tmr1q_cfg_twap53 == 1); # cfg_twap 17 14:19 , ATTR_EFF_DRAM_TFAW, 1 , any; # cfg_tfaw # uncomment when Anuwat has added in fix -# 14:19 , 0b010100 , 1 , (def_mba_tmr1q_cfg_tfaw_dly20 == 1); # cfg_tfaw 18 -# 14:19 , 0b010110 , 1 , (def_mba_tmr1q_cfg_tfaw_dly22 == 1); # cfg_tfaw 18 -# 14:19 , 0b010111 , 1 , (def_mba_tmr1q_cfg_tfaw_dly23 == 1); # cfg_tfaw 18 -# 14:19 , 0b011000 , 1 , (def_mba_tmr1q_cfg_tfaw_dly24 == 1); # cfg_tfaw 18 -# 14:19 , 0b011010 , 1 , (def_mba_tmr1q_cfg_tfaw_dly26 == 1); # cfg_tfaw 18 -# 14:19 , 0b011011 , 1 , (def_mba_tmr1q_cfg_tfaw_dly27 == 1); # cfg_tfaw 18 -# 14:19 , 0b011110 , 1 , (def_mba_tmr1q_cfg_tfaw_dly30 == 1); # cfg_tfaw 18 -# 14:19 , 0b100000 , 1 , (def_mba_tmr1q_cfg_tfaw_dly32 == 1); # cfg_tfaw 18 -# 14:19 , 0b100001 , 1 , (def_mba_tmr1q_cfg_tfaw_dly33 == 1); # cfg_tfaw 18 20:23 , 0b0000 , 1 , (def_mba_tmr1q_RRSBG_dlys0 == 1); # RRSBG_dly 19 20:23 , 0b0101 , 1 , (def_mba_tmr1q_RRSBG_dlys5 == 1); # RRSBG_dly 19 20:23 , 0b0110 , 1 , (def_mba_tmr1q_RRSBG_dlys6 == 1); # RRSBG_dly 19 diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_shmoo.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_shmoo.C index 91e7ac74e..fae8f3560 100644 --- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_shmoo.C +++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_shmoo.C @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2013 */ +/* COPYRIGHT International Business Machines Corp. 2013,2014 */ /* */ /* p1 */ /* */ @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_eff_config_shmoo.C,v 1.8 2013/09/02 08:33:13 sasethur Exp $ +// $Id: mss_eff_config_shmoo.C,v 1.10 2014/01/26 13:52:49 bellows Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_eff_config_shmoo.C,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 @@ -47,7 +47,9 @@ // 1.5 | sauchadh |15-May-13| Fixed FW comments // 1.6 | sauchadh |6-Jun-13 | Added some more attributes // 1.7 | bellows |09-Aug-13| Set default pattern to 0, per Sarvanan Req -// 1.8 | sauchadh |2- Sep-13| Added random seed attribute +// 1.8 | sauchadh |2- Sep-13| Added random seed attribute +// 1.9 | sauchadh |20-Dec-13| change test type to 38 +// 1.10 | bellows |26-Jan-14| moved driver attribute setting from eff termination //---------------------------------------------------------------------- // My Includes @@ -74,7 +76,7 @@ fapi::ReturnCode mss_eff_config_shmoo(const fapi::Target & i_target_mba) { FAPI_INF("*** Running %s on %s ... ***", PROCEDURE_NAME, i_target_mba.toEcmdString()); uint32_t datapattern=0; // mdb - type 8 is not valid per Saravanan's Sametime - uint32_t testtype=1; + uint32_t testtype=37; // SIMPLE_FIX_RF uint8_t addr_modes=1; uint8_t rank=0; uint64_t start_addr=0; @@ -120,8 +122,31 @@ fapi::ReturnCode mss_eff_config_shmoo(const fapi::Target & i_target_mba) { uint8_t shmoo_mul_setup_call=0; uint32_t rand_seed_val=0; uint8_t rand_seed_type=0x01; + + // space for VPD attributes that need to be read from VPD and put into scratch pads + const uint8_t PORT_SIZE = 2; + + uint32_t attr_eff_cen_rd_vref[PORT_SIZE]; + uint32_t attr_eff_dram_wr_vref[PORT_SIZE]; + uint8_t attr_eff_cen_rcv_imp_dq_dqs[PORT_SIZE]; + uint8_t attr_eff_cen_drv_imp_dq_dqs[PORT_SIZE]; + uint8_t attr_eff_cen_slew_rate_dq_dqs[PORT_SIZE]; - + + // get these attributes from the VPD but allow the code to override later + rc = FAPI_ATTR_GET(ATTR_VPD_CEN_RD_VREF, &i_target_mba, attr_eff_cen_rd_vref); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_WR_VREF, &i_target_mba, attr_eff_dram_wr_vref); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_VPD_CEN_RCV_IMP_DQ_DQS, &i_target_mba, attr_eff_cen_rcv_imp_dq_dqs); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_VPD_CEN_DRV_IMP_DQ_DQS, &i_target_mba, attr_eff_cen_drv_imp_dq_dqs); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_VPD_CEN_SLEW_RATE_DQ_DQS, &i_target_mba, attr_eff_cen_slew_rate_dq_dqs); if(rc) return rc; + + // attriubtes that are needing to be copied from VPD into scratch pads + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_RD_VREF, &i_target_mba, attr_eff_cen_rd_vref); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_WR_VREF, &i_target_mba, attr_eff_dram_wr_vref); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_RCV_IMP_DQ_DQS, &i_target_mba, attr_eff_cen_rcv_imp_dq_dqs); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_DRV_IMP_DQ_DQS, &i_target_mba, attr_eff_cen_drv_imp_dq_dqs); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_SLEW_RATE_DQ_DQS, &i_target_mba, attr_eff_cen_slew_rate_dq_dqs); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_MCBIST_PRINTING_DISABLE, &i_target_mba, mcb_print_disable); if(rc) return rc; rc = FAPI_ATTR_SET(ATTR_MCBIST_DATA_ENABLE, &i_target_mba, mcb_data_en); if(rc) return rc; diff --git a/src/usr/hwpf/hwp/p8_pmc_deconfig_setup_errors.xml b/src/usr/hwpf/hwp/p8_pmc_deconfig_setup_errors.xml deleted file mode 100644 index c500fbf43..000000000 --- a/src/usr/hwpf/hwp/p8_pmc_deconfig_setup_errors.xml +++ /dev/null @@ -1,32 +0,0 @@ -<!-- IBM_PROLOG_BEGIN_TAG --> -<!-- This is an automatically generated prolog. --> -<!-- --> -<!-- $Source: src/usr/hwpf/hwp/p8_pmc_deconfig_setup_errors.xml $ --> -<!-- --> -<!-- IBM CONFIDENTIAL --> -<!-- --> -<!-- COPYRIGHT International Business Machines Corp. 2012,2013 --> -<!-- --> -<!-- p1 --> -<!-- --> -<!-- Object Code Only (OCO) source materials --> -<!-- Licensed Internal Code Source Materials --> -<!-- IBM HostBoot Licensed Internal Code --> -<!-- --> -<!-- The source code for this program is not published or otherwise --> -<!-- divested of its trade secrets, irrespective of what has been --> -<!-- deposited with the U.S. Copyright Office. --> -<!-- --> -<!-- Origin: 30 --> -<!-- --> -<!-- IBM_PROLOG_END_TAG --> -<!-- $Id: p8_pmc_deconfig_setup_errors.xml,v 1.2 2013/05/23 18:44:24 stillgs Exp $ --> -<!-- Error definitions for p8_pmc_deconfig_setup procedure --> -<hwpErrors> - <!-- *********************************************************************** --> - <hwpError> - <rc>RC_PROCPM_PMC_DECONFIG_NO_CORES</rc> - <description>p8_pmc_deconfig_setup did not find any configured core.</description> - </hwpError> - <!-- *********************************************************************** --> -</hwpErrors> diff --git a/src/usr/hwpf/hwp/runtime_errors/p8_pmc_deconfig_setup_errors.xml b/src/usr/hwpf/hwp/runtime_errors/p8_pmc_deconfig_setup_errors.xml deleted file mode 100644 index 21210120f..000000000 --- a/src/usr/hwpf/hwp/runtime_errors/p8_pmc_deconfig_setup_errors.xml +++ /dev/null @@ -1,29 +0,0 @@ -<!-- IBM_PROLOG_BEGIN_TAG --> -<!-- This is an automatically generated prolog. --> -<!-- --> -<!-- $Source: src/usr/hwpf/hwp/runtime_errors/p8_pmc_deconfig_setup_errors.xml $ --> -<!-- --> -<!-- IBM CONFIDENTIAL --> -<!-- --> -<!-- COPYRIGHT International Business Machines Corp. 2013 --> -<!-- --> -<!-- p1 --> -<!-- --> -<!-- Object Code Only (OCO) source materials --> -<!-- Licensed Internal Code Source Materials --> -<!-- IBM HostBoot Licensed Internal Code --> -<!-- --> -<!-- The source code for this program is not published or otherwise --> -<!-- divested of its trade secrets, irrespective of what has been --> -<!-- deposited with the U.S. Copyright Office. --> -<!-- --> -<!-- Origin: 30 --> -<!-- --> -<!-- IBM_PROLOG_END_TAG --> -<!-- $Id: p8_pmc_deconfig_setup_errors.xml,v 1.3 2013-10-15 17:36:08 dcrowell Exp $ --> -<!-- Error definitions for p8_pmc_deconfig_setup procedure --> -<hwpErrors> - <!-- *********************************************************************** --> - <!-- No errors yet, keeping as placeholder --> - <!-- *********************************************************************** --> -</hwpErrors> diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_read_seeprom.C b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_read_seeprom.C index 05c9c4b33..5bc8a4aca 100644 --- a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_read_seeprom.C +++ b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_read_seeprom.C @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012,2013 */ +/* COPYRIGHT International Business Machines Corp. 2012,2014 */ /* */ /* p1 */ /* */ @@ -22,7 +22,7 @@ /* IBM_PROLOG_END_TAG */ // -*- mode: C++; c-file-style: "linux"; -*- -// $Id: proc_read_seeprom.C,v 1.9 2012/11/16 23:44:55 szhong Exp $ +// $Id: proc_read_seeprom.C,v 1.11 2013/09/18 18:48:38 szhong Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/utils/proc_read_seeprom.C,v $ //------------------------------------------------------------------------------ // *| @@ -79,10 +79,7 @@ extern "C" // o_data => The data that is read is sent back to the user // returns: FAPI_RC_SUCCESS if operation was successful, else error //------------------------------------------------------------------------------ - - - - + fapi::ReturnCode check_status_register_errors(ecmdDataBufferBase is_ready) { @@ -169,7 +166,6 @@ extern "C" FAPI_SET_HWP_ERROR(rc,RC_PROC_READ_SEEPROM_I2C_STOP_ERR_BIT_SET); break; } - //check if bits 54, 55 are errors. if(is_ready.isBitSet(56)) { FAPI_ERR("ERROR:I2C_STOP_ERR"); @@ -193,7 +189,7 @@ extern "C" break; } - uint16_t e_41_43=(err32to47 & 0x0070)>>4;; + uint16_t e_41_43=(err32to47 & 0x0070)>>4; if(e_41_43!=0) { if(e_41_43==4)//0b100 @@ -257,39 +253,37 @@ extern "C" uint32_t & i_start_addr, uint32_t & i_length, bool & i_ecc_disable, uint64_t * return_data, bool & use_secondary) { fapi::ReturnCode rc; + uint32_t rc_ecmd=0; //----------------------------Buffers----------------------------------------------- //The buffer that set 000A0006 which we need to do before anything else - ecmdDataBufferBase beginning_buff = ecmdDataBufferBase (64); + ecmdDataBufferBase beginning_buff = ecmdDataBufferBase (64); //The buffer that will tell whether or not the data is ready to be read - ecmdDataBufferBase is_ready = ecmdDataBufferBase (64); + ecmdDataBufferBase is_ready = ecmdDataBufferBase (64); //The buffer that will hold the data to be returned - ecmdDataBufferBase data = ecmdDataBufferBase (64); - uint64_t clearallbits = 0x0000000000000000LLU; - data.setDoubleWord(0,clearallbits); + ecmdDataBufferBase data = ecmdDataBufferBase (64); //The buffer that contains the value of the first time we call the control register ecmdDataBufferBase control_reg_buff1 = ecmdDataBufferBase (64); - //The buffer that contins the value of the second time we call the control register - ecmdDataBufferBase control_reg_buff2 = ecmdDataBufferBase (64); - //The buffer that contains the value of continuing to get more than just 8 bytes of data - ecmdDataBufferBase control_reg_buff3 = ecmdDataBufferBase (64); //The device_id buffer - ecmdDataBufferBase device_id_buff = ecmdDataBufferBase (64); + ecmdDataBufferBase device_id_buff = ecmdDataBufferBase (64); //The port number buffer - ecmdDataBufferBase port_buff = ecmdDataBufferBase (64); + ecmdDataBufferBase port_buff = ecmdDataBufferBase (64); //The address buffer - ecmdDataBufferBase address_buff = ecmdDataBufferBase (64); + ecmdDataBufferBase address_buff = ecmdDataBufferBase (64); //ECC Buffer - ecmdDataBufferBase ecc_buff = ecmdDataBufferBase (64); - ecmdDataBufferBase vital_reg_buff=ecmdDataBufferBase(64); + ecmdDataBufferBase ecc_buff = ecmdDataBufferBase (64); + ecmdDataBufferBase vital_reg_buff = ecmdDataBufferBase (64); - - - - + uint64_t clearallbits = 0x0000000000000000LLU; uint64_t ecc_value; - //uint64_t fix_offset=0;//read from logic address of 2000 - uint32_t rc_ecmd=0; + rc_ecmd|=data.setDoubleWord(0,clearallbits); + rc.setEcmdError(rc_ecmd); + if(!rc.ok()) + { + FAPI_ERR("proc_read_seeprom: Error 0x%x failed clearing data bits",rc_ecmd); + return rc; + } + do { //Putting the value of the 000A0006 into the buffer @@ -305,51 +299,98 @@ extern "C" ecc_value = 0x0000FFFF00001C78LLU; FAPI_DBG("ecc enabled\n"); } + //Put the ecc value into the ecc buffer - ecc_buff.setDoubleWord(0, ecc_value); + rc_ecmd|=ecc_buff.setDoubleWord(0, ecc_value); + rc.setEcmdError(rc_ecmd); + if(!rc.ok()) + { + FAPI_ERR("proc_read_seeprom: Error 0x%x failed clearing data bits",rc_ecmd); + break; + } //Figure out how many times we will need to get data int num_times = i_length / 8 ; - - //Put the value of the device_id into the device_id buffer - uint64_t device_id = 86; //0b1010110 - if(use_secondary) + + uint64_t device_id =0; //seeprom device id + uint8_t di[2]={0,0}; //device id array to be filled by attribute + uint8_t pi[2]={0,0}; //port id array to be filled by attribute + rc=FAPI_ATTR_GET (ATTR_SBE_SEEPROM_I2C_DEVICE_ADDRESS,&i_target,di); + if(rc) + { + FAPI_ERR ("Problem doing fapi_attr_get on ATTR_SBE_SEEPROM_I2C_DEVICE_ADDRESS"); + } + rc=FAPI_ATTR_GET (ATTR_SBE_SEEPROM_I2C_PORT,&i_target,pi); + if(rc) + { + FAPI_ERR ("Problem doing fapi_attr_get on ATTR_SBE_SEEPROM_I2C_PORT"); + } + device_id= di[0]; //seeprom 1 + if(use_secondary) + { + device_id=di[1]; //secondary + } + FAPI_DBG ("Device ID: %llu\n",device_id); + device_id = device_id << 49; + rc_ecmd|=device_id_buff.setDoubleWord(0, device_id); + rc.setEcmdError(rc_ecmd); + if(!rc.ok()) { - device_id=87; //secondary seeprom id, test this. + FAPI_ERR("proc_read_seeprom: Error 0x%x failed setting device_id_buff",rc_ecmd); + break; } - - device_id = device_id << 49; - device_id_buff.setDoubleWord(0, device_id); - //Put the value of the port number into the port buffer - uint64_t port = 0; // 0b00000; - port = port << 39; - port_buff.setDoubleWord(0, port); + uint64_t port = pi[0]; // default port id; + if(use_secondary) + { + port=pi[1]; + } + + FAPI_DBG ("Port: %llu\n", port); + port = port << 41;//41 (bit 18 to 22 is the port number); + rc_ecmd|=port_buff.setDoubleWord(0, port); + rc.setEcmdError(rc_ecmd); + if(!rc.ok()) + { + FAPI_ERR("proc_read_seeprom: Error 0x%x failed setting port_buff",rc_ecmd); + break; + } //Put the value of the address into the address buffer FAPI_DBG("i_start_addr: %08x\n",i_start_addr); uint64_t start_addr = i_start_addr << 16; - address_buff.setDoubleWord(0, start_addr); - + rc_ecmd|=address_buff.setDoubleWord(0, start_addr); + rc.setEcmdError(rc_ecmd); + if(!rc.ok()) + { + FAPI_ERR("proc_read_seeprom: Error 0x%x failed setting address_buff",rc_ecmd); + break; + } + //The base value of the first time that the control register is used uint64_t control_reg_data1 = 0xD801008000000000LLU; //11011000<device ID>100<port number>010000000<register address> //Put the initial value of the control registers - control_reg_buff1.setDoubleWord (0, control_reg_data1); - //control_reg_buff2.setDoubleWord (0, control_reg_data2); - + rc_ecmd|=control_reg_buff1.setDoubleWord (0, control_reg_data1); + //Include the device id in the control registers - //control_reg_buff2.merge(device_id_buff); - control_reg_buff1.merge(device_id_buff); + rc_ecmd|=control_reg_buff1.merge(device_id_buff); //Include the port number in the control registers - control_reg_buff1.merge(port_buff); - //control_reg_buff2.merge(port_buff); + rc_ecmd|=control_reg_buff1.merge(port_buff); //Include the starting address in the control registers - control_reg_buff1.merge(address_buff); - //control_reg_buff2.merge(address_buff); + rc_ecmd|=control_reg_buff1.merge(address_buff); + + rc.setEcmdError(rc_ecmd); + if(!rc.ok()) + { + FAPI_ERR("proc_read_seeprom: Error 0x%x failed setting merging control_reg_buff1",rc_ecmd); + break; + } + + //Set the ECC write or no ECC write rc = fapiPutScom(i_target, 0x000C0004, ecc_buff); @@ -366,14 +407,12 @@ extern "C" FAPI_ERR("Failed to perform fapiPutScom on MODE_REGISTER_0 0x000A0006"); break; } - //Write control registerclk - + //Read Status Register int i = 0; - rc_ecmd=0; for(i = 0; i < num_times; i++) { - if(i==0) + if(i==0)//first read { if(num_times==1) { @@ -393,7 +432,7 @@ extern "C" rc.setEcmdError(rc_ecmd); if(!rc.ok()) { - FAPI_ERR("proc_read_seeprom: Error 0x%x failed setting/clearing bits",rc_ecmd); + FAPI_ERR("proc_read_seeprom: Error 0x%x failed setting bit2/clearing bit3 of control_reg_buff1",rc_ecmd); break; } FAPI_DBG("control: %016llx\n",control_reg_buff1.getDoubleWord(0)); @@ -429,7 +468,7 @@ extern "C" break; } } - else + else //other { rc_ecmd|=control_reg_buff1.clearBit(0); rc_ecmd|=control_reg_buff1.clearBit(1); diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_sbe_check_master.H b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_sbe_check_master.H index f48908c7c..46b7e8636 100644 --- a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_sbe_check_master.H +++ b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_sbe_check_master.H @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012 */ +/* COPYRIGHT International Business Machines Corp. 2012,2014 */ /* */ /* p1 */ /* */ @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_sbe_check_master.H,v 1.2 2012/10/16 02:43:51 jmcgill Exp $ +// $Id: proc_sbe_check_master.H,v 1.3 2013/10/03 20:53:15 jeshua Exp $ /// Substep numbers for proc_sbe_check_master @@ -31,6 +31,7 @@ #include "sbe_vital.H" CONST_UINT8_T(SUBSTEP_CHECK_MASTER_PROC_ENTRY, ULL(0x0)); +//NOTE: The slave chip substep value can never change, because HB checks for it CONST_UINT8_T(SUBSTEP_CHECK_MASTER_SLAVE_CHIP, ULL(0x1)); CONST_UINT8_T(SUBSTEP_CHECK_MASTER_MASTER_CHIP, ULL(0x2)); diff --git a/src/usr/hwpf/makefile b/src/usr/hwpf/makefile index f18836178..8d5a91fc2 100644 --- a/src/usr/hwpf/makefile +++ b/src/usr/hwpf/makefile @@ -126,7 +126,6 @@ HWP_ERROR_XML_FILES = hwp/fapiHwpErrorInfo.xml \ hwp/build_winkle_images/proc_mailbox_utils/p8_mailbox_utils_errors.xml \ hwp/proc_otprom_registers.xml \ hwp/runtime_errors/p8_gpe_registers.xml \ - hwp/runtime_errors/p8_pmc_deconfig_setup_errors.xml \ hwp/runtime_errors/p8_pss_registers.xml \ hwp/proc_hwreconfig/proc_enable_reconfig/proc_enable_reconfig_errors.xml \ hwp/dram_training/mem_startclocks/cen_mem_startclocks_errors.xml \ |
