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-rwxr-xr-xsrc/build/mkrules/dist.targets.mk4
-rwxr-xr-xsrc/build/mkrules/hbfw/img/makefile32
-rwxr-xr-xsrc/build/simics/startup.simics2
-rwxr-xr-xsrc/build/tools/hbRelease4
-rwxr-xr-xsrc/usr/targeting/common/xmltohb/common.mk2
-rw-r--r--src/usr/targeting/common/xmltohb/simics_AXONE.mrw.xml23
-rw-r--r--src/usr/targeting/common/xmltohb/simics_AXONE.system.xml614
-rw-r--r--src/usr/targeting/common/xmltohb/target_types.xml15
-rwxr-xr-xsrc/usr/targeting/xmltohb/makefile3
9 files changed, 680 insertions, 19 deletions
diff --git a/src/build/mkrules/dist.targets.mk b/src/build/mkrules/dist.targets.mk
index 0df6a59d4..f791aa2fe 100755
--- a/src/build/mkrules/dist.targets.mk
+++ b/src/build/mkrules/dist.targets.mk
@@ -94,6 +94,7 @@ COPY_FILES = \
src/usr/targeting/common/xmltohb/simics_NIMBUS.system.xml:openpower \
src/usr/targeting/common/xmltohb/simics_CUMULUS.system.xml:openpower \
src/usr/targeting/common/xmltohb/simics_CUMULUS_CDIMM.system.xml:openpower \
+ src/usr/targeting/common/xmltohb/simics_AXONE.system.xml:openpower \
src/usr/targeting/common/xmltohb/xmltohb.pl:openpower \
src/usr/targeting/xmltohb/updatetempsxml.pl:openpower \
src/include/usr/vmmconst.h:openpower \
@@ -269,12 +270,15 @@ fsp.tar_CONTENTS = \
img/simics_NIMBUS_targeting.bin \
img/simics_CUMULUS_targeting.bin \
img/simics_CUMULUS_CDIMM_targeting.bin \
+ img/simics_AXONE_targeting.bin \
img/simics_NIMBUS_targeting.bin.protected \
img/simics_NIMBUS_targeting.bin.unprotected \
img/simics_CUMULUS_targeting.bin.protected \
img/simics_CUMULUS_targeting.bin.unprotected \
img/simics_CUMULUS_CDIMM_targeting.bin.protected \
img/simics_CUMULUS_CDIMM_targeting.bin.unprotected \
+ img/simics_AXONE_targeting.bin.protected \
+ img/simics_AXONE_targeting.bin.unprotected \
obj/genfiles/fapiattrs.xml \
obj/genfiles/attribute_types_sp.xml \
obj/genfiles/target_types_sp.xml \
diff --git a/src/build/mkrules/hbfw/img/makefile b/src/build/mkrules/hbfw/img/makefile
index 2bb352fb2..4f5a72219 100755
--- a/src/build/mkrules/hbfw/img/makefile
+++ b/src/build/mkrules/hbfw/img/makefile
@@ -265,6 +265,8 @@ SBE_BUILD_SCRIPT = ${buildSbePart.pl:P}
NIMBUS_SBE_IMG = p9n.SbePartition.bin
CUMULUS_SBE_IMG = p9c.SbePartition.bin
+# TODO RTC 197497 - Use Axone SBE image once it exists
+#AXONE_SBE_IMG = p9a.SbePartition.bin
P9N_EC20_BIN = ${SBEI_OBJPATH:Fp9n_20.sbe_seeprom.hdr.bin}
P9N_EC21_BIN = ${SBEI_OBJPATH:Fp9n_21.sbe_seeprom.hdr.bin}
@@ -272,11 +274,13 @@ P9N_EC22_BIN = ${SBEI_OBJPATH:Fp9n_22.sbe_seeprom.hdr.bin}
P9C_EC13_BIN = ${SBEI_OBJPATH:Fp9c_13.sbe_seeprom.hdr.bin}
P9C_EC11_BIN = ${SBEI_OBJPATH:Fp9c_11.sbe_seeprom.hdr.bin}
P9C_EC12_BIN = ${SBEI_OBJPATH:Fp9c_12.sbe_seeprom.hdr.bin}
+# TODO RTC 197497 - Use Axone SBE image once it exists
+#P9A_EC10_BIN = ${SBEI_OBJPATH:Fp9a_10.sbe_seeprom.hdr.bin}
SBE_PART_INFO = \
${NIMBUS_SBE_IMG}:20=${P9N_EC20_BIN},21=${P9N_EC21_BIN},22=${P9N_EC22_BIN} \
${CUMULUS_SBE_IMG}:13=${P9C_EC13_BIN},11=${P9C_EC11_BIN},12=${P9C_EC12_BIN}
-
+# TODO RTC 197497 - ${AXONE_SBE_IMG}:10=${P9A_EC10_BIN}
__SBE_PART_BUILD/% : .SPECTARG .PMAKE
@${MAKE:T:R} BUILD_SPECIFIC_SBEPART \
@@ -334,12 +338,20 @@ ENGD_OBJPATH = ${HBFW_OBJPATH:S/hbfw\/img/engd\/href/g}
NIMBUS_HBD_IMG = simics_NIMBUS_targeting.bin
CUMULUS_HBD_IMG = simics_CUMULUS_targeting.bin
CUMULUS_CDIMM_HBD_IMG = simics_CUMULUS_CDIMM_targeting.bin
+AXONE_HBD_IMG = simics_AXONE_targeting.bin
+
NIMBUS_HCODE_IMG = ${ENGD_SRCPATH:Fp9n.hw_ref_image.bin}
CUMULUS_HCODE_IMG = ${ENGD_SRCPATH:Fp9c.hw_ref_image.bin}
+# TODO RTC 197497 - Use Axone HCODE image once it exists
+AXONE_HCODE_IMG = ${ENGD_SRCPATH:Fp9c.hw_ref_image.bin}
+
CUMULUS_CENHWIMG_IMG = ${ENGD_SRCPATH:Fcen.hw_ref_image.bin}
NIMBUS_CENHWIMG_IMG = cen.hw_ref_image.bin.fake
+AXONE_CENHWIMG_IMG = cen.hw_ref_image.bin.fake
NIMBUS_OCC_IMG = ${bb}/images/ppc/lab/fs/p9le/rootfs/opt/extucode/81e00430.lid
CUMULUS_OCC_IMG = ${bb}/images/ppc/lab/fs/p9le/rootfs/opt/extucode/81e00430.lid
+AXONE_OCC_IMG = ${bb}/images/ppc/lab/fs/p9le/rootfs/opt/extucode/81e00430.lid
+
## System Specific
ZZ_WOFDATA_IMG = ${ENGD_WOFPATH:Fzz_wof_data.bin}
ZEPPELIN_WOFDATA_IMG = ${ENGD_WOFPATH:Fzeppelin_wof_data.bin}
@@ -363,14 +375,19 @@ NIMBUS_VPO_HBD_IMG = vbu_NIMBUS_targeting.bin
NIMBUS_HBD_FINAL_IMG = NIMBUS.HBD.bin
CUMULUS_HBD_FINAL_IMG = CUMULUS.HBD.bin
CUMULUS_CDIMM_HBD_FINAL_IMG = CUMULUS_CDIMM.HBD.bin
+AXONE_HBD_FINAL_IMG = AXONE.HBD.bin
NIMBUS_HCODE_FINAL_IMG = NIMBUS.HCODE.bin
CUMULUS_HCODE_FINAL_IMG = CUMULUS.HCODE.bin
+AXONE_HCODE_FINAL_IMG = AXONE.HCODE.bin
CUMULUS_CENHWIMG_FINAL_IMG = CUMULUS.CENHWIMG.bin
NIMBUS_CENHWIMG_FINAL_IMG = NIMBUS.CENHWIMG.bin
+AXONE_CENHWIMG_FINAL_IMG = AXONE.CENHWIMG.bin
NIMBUS_SBE_FINAL_IMG = NIMBUS.SBE.bin
CUMULUS_SBE_FINAL_IMG = CUMULUS.SBE.bin
+AXONE_SBE_FINAL_IMG = AXONE.SBE.bin
NIMBUS_OCC_FINAL_IMG = NIMBUS.OCC.bin
CUMULUS_OCC_FINAL_IMG = CUMULUS.OCC.bin
+AXONE_OCC_FINAL_IMG = AXONE.OCC.bin
## System Specific
ZZ_WOFDATA_FINAL_IMG = ZZ.WOFDATA.bin
ZEPPELIN_WOFDATA_FINAL_IMG = ZEPPELIN.WOFDATA.bin
@@ -393,10 +410,13 @@ ZZ2U_HBD_FINAL_IMG = ZZ-2U.HBD.bin
GEN_NIMBUS_BIN_FILES = NIMBUS:SBE=${${NIMBUS_SBE_IMG}:P},HCODE=${${NIMBUS_HCODE_IMG}:P},OCC=${${NIMBUS_OCC_IMG}:P},HBD=${${NIMBUS_HBD_IMG}:P},CENHWIMG=${NIMBUS_CENHWIMG_IMG}
GEN_CUMULUS_BIN_FILES = CUMULUS:SBE=${${CUMULUS_SBE_IMG}:P},HCODE=${${CUMULUS_HCODE_IMG}:P},OCC=${${CUMULUS_OCC_IMG}:P},HBD=${${CUMULUS_HBD_IMG}:P},CENHWIMG=${${CUMULUS_CENHWIMG_IMG}:P}
GEN_CUMULUS_CDIMM_BIN_FILES = CUMULUS_CDIMM:SBE=${${CUMULUS_SBE_IMG}:P},HCODE=${${CUMULUS_HCODE_IMG}:P},OCC=${${CUMULUS_OCC_IMG}:P},HBD=${${CUMULUS_CDIMM_HBD_IMG}:P},CENHWIMG=${${CUMULUS_CENHWIMG_IMG}:P}
+ # TODO RTC 197497 -- Use Axone SBE Image when available
+ GEN_AXONE_BIN_FILES = AXONE:SBE=${${CUMULUS_SBE_IMG}:P},HCODE=${${AXONE_HCODE_IMG}:P},OCC=${${AXONE_OCC_IMG}:P},HBD=${${AXONE_HBD_IMG}:P},CENHWIMG=${AXONE_CENHWIMG_IMG}
.else
GEN_NIMBUS_BIN_FILES = NIMBUS:SBE=${${NIMBUS_SBE_IMG}:P},HCODE=${${NIMBUS_HCODE_IMG}:P},OCC=${${NIMBUS_OCC_IMG}:P},HBD=${${NIMBUS_HBD_IMG}:P},CENHWIMG=${NIMBUS_CENHWIMG_IMG}
GEN_CUMULUS_BIN_FILES = CUMULUS:SBE=${${CUMULUS_SBE_IMG}:P},HCODE=${${CUMULUS_HCODE_IMG}:P},OCC=${${CUMULUS_OCC_IMG}:P},HBD=${${CUMULUS_HBD_IMG}:P},CENHWIMG=${${CUMULUS_CENHWIMG_IMG}:P}
GEN_CUMULUS_CDIMM_BIN_FILES = CUMULUS_CDIMM:SBE=${${CUMULUS_SBE_IMG}:P},HCODE=${${CUMULUS_HCODE_IMG}:P},OCC=${${CUMULUS_OCC_IMG}:P},HBD=${${CUMULUS_CDIMM_HBD_IMG}:P},CENHWIMG=${${CUMULUS_CENHWIMG_IMG}:P}
+ GEN_AXONE_BIN_FILES = AXONE:SBE=${${CUMULUS_SBE_IMG}:P},HCODE=${${AXONE_HCODE_IMG}:P},OCC=${${AXONE_OCC_IMG}:P},HBD=${${AXONE_HBD_IMG}:P},CENHWIMG=${AXONE_CENHWIMG_IMG}
.endif
GEN_ZZ_BIN_FILES = ZZ:WOFDATA=${${ZZ_WOFDATA_IMG}:P},MEMD=${${ZZ_MEMD_IMG}:P},HBD=${${ZZ_HBD_IMG}:P}
GEN_ZEPPELIN_BIN_FILES = ZEPPELIN:WOFDATA=${${ZEPPELIN_WOFDATA_IMG}:P},MEMD=${${ZEPPELIN_MEMD_IMG}:P},HBD=${${ZEPPELIN_HBD_IMG}:P}
@@ -408,6 +428,7 @@ ZZ2U_HBD_FINAL_IMG = ZZ-2U.HBD.bin
--systemBinFiles ${GEN_NIMBUS_BIN_FILES} \
--systemBinFiles ${GEN_CUMULUS_BIN_FILES} \
--systemBinFiles ${GEN_CUMULUS_CDIMM_BIN_FILES} \
+ --systemBinFiles ${GEN_AXONE_BIN_FILES} \
--systemBinFiles ${GEN_ZZ_BIN_FILES} \
--systemBinFiles ${GEN_ZEPPELIN_BIN_FILES} \
--systemBinFiles ${GEN_FLEETWOOD_BIN_FILES} \
@@ -418,9 +439,11 @@ ZZ2U_HBD_FINAL_IMG = ZZ-2U.HBD.bin
GEN_NIMBUS_BIN_FILES = NIMBUS:HCODE=${${NIMBUS_HCODE_IMG}:P},HBD=${${NIMBUS_VPO_HBD_IMG}:P},CENHWIMG=EMPTY
GEN_CUMULUS_BIN_FILES = CUMULUS:HCODE=${${CUMULUS_HCODE_IMG}:P},CENHWIMG=${${CUMULUS_CENHWIMG_IMG}:P}
GEN_CUMULUS_CDIMM_BIN_FILES = CUMULUS:HCODE=${${CUMULUS_HCODE_IMG}:P},CENHWIMG=${${CUMULUS_CENHWIMG_IMG}:P}
+ GEN_AXONE_BIN_FILES = AXONE:HCODE=${${AXONE_HCODE_IMG}:P},HBD=${${AXONE_VPO_HBD_IMG}:P},CENHWIMG=EMPTY
SYSTEM_SPECIFIC_PARAMS = --pnorLayout ${PNOR_LAYOUT} \
--systemBinFiles ${GEN_NIMBUS_BIN_FILES} \
--systemBinFiles ${GEN_CUMULUS_BIN_FILES} \
+ --systemBinFiles ${GEN_AXONE_BIN_FILES} \
--systemBinFiles ${GEN_CUMULUS_CDIMM_BIN_FILES}
.endif
@@ -445,16 +468,20 @@ gen_system_specific_images: build_sbe_partitions .PMAKE
NIMBUS_SECT = HBD=${NIMBUS_HBD_FINAL_IMG},SBE=${NIMBUS_SBE_FINAL_IMG},HCODE=${NIMBUS_HCODE_FINAL_IMG},OCC=${NIMBUS_OCC_FINAL_IMG},WOFDATA=${ZZ_WOFDATA_FINAL_IMG},CENHWIMG=${NIMBUS_CENHWIMG_FINAL_IMG},MEMD=${ZZ_MEMD_FINAL_IMG}
CUMULUS_SECT = HBD=${CUMULUS_HBD_FINAL_IMG},SBE=${CUMULUS_SBE_FINAL_IMG},HCODE=${CUMULUS_HCODE_FINAL_IMG},OCC=${CUMULUS_OCC_FINAL_IMG},WOFDATA=${ZEPPELIN_WOFDATA_FINAL_IMG},CENHWIMG=${CUMULUS_CENHWIMG_FINAL_IMG},MEMD=${ZEPPELIN_MEMD_FINAL_IMG}
CUMULUS_CDIMM_SECT = HBD=${CUMULUS_CDIMM_HBD_FINAL_IMG},SBE=${CUMULUS_SBE_FINAL_IMG},HCODE=${CUMULUS_HCODE_FINAL_IMG},OCC=${CUMULUS_OCC_FINAL_IMG},WOFDATA=${ZEPPELIN_WOFDATA_FINAL_IMG},CENHWIMG=${CUMULUS_CENHWIMG_FINAL_IMG},MEMD=${MEMD_FINAL_IMG}
+ AXONE_SECT = HBD=${AXONE_HBD_FINAL_IMG},SBE=${AXONE_SBE_FINAL_IMG},HCODE=${AXONE_HCODE_FINAL_IMG},OCC=${AXONE_OCC_FINAL_IMG},WOFDATA=${ZZ_WOFDATA_FINAL_IMG},CENHWIMG=${AXONE_CENHWIMG_FINAL_IMG},MEMD=${ZZ_MEMD_FINAL_IMG}
.else
HOSTBOOT_DEFAULT_SECTIONS = HBBL=${HBBL_FINAL_IMG},HBB=${HBB_FINAL_IMG},HBI=${HBI_FINAL_IMG},HBRT=${HBRT_FINAL_IMG},HBEL=${HBEL_FINAL_IMG},GUARD=${GUARD_FINAL_IMG},GLOBAL=${GLOBAL_FINAL_IMG},CVPD=${CVPD_FINAL_IMG},MVPD=${MVPD_FINAL_IMG},DJVPD=${DJVPD_FINAL_IMG},RINGOVD=${RINGOVD_FINAL_IMG},SBKT=${SBKT_FINAL_IMG}
NIMBUS_SECT = HBD=${NIMBUS_HBD_FINAL_IMG},SBE=${NIMBUS_SBE_FINAL_IMG},HCODE=${NIMBUS_HCODE_FINAL_IMG},OCC=${NIMBUS_OCC_FINAL_IMG},WOFDATA=${ZZ_WOFDATA_FINAL_IMG},CENHWIMG=${NIMBUS_CENHWIMG_FINAL_IMG},MEMD=${ZZ_MEMD_FINAL_IMG}
CUMULUS_SECT = HBD=${CUMULUS_HBD_FINAL_IMG},SBE=${CUMULUS_SBE_FINAL_IMG},HCODE=${CUMULUS_HCODE_FINAL_IMG},OCC=${CUMULUS_OCC_FINAL_IMG},WOFDATA=${ZEPPELIN_WOFDATA_FINAL_IMG},CENHWIMG=${CUMULUS_CENHWIMG_FINAL_IMG},MEMD=${ZEPPELIN_MEMD_FINAL_IMG}
CUMULUS_CDIMM_SECT = HBD=${CUMULUS_CDIMM_HBD_FINAL_IMG},SBE=${CUMULUS_SBE_FINAL_IMG},HCODE=${CUMULUS_HCODE_FINAL_IMG},OCC=${CUMULUS_OCC_FINAL_IMG},WOFDATA=${ZEPPELIN_WOFDATA_FINAL_IMG},CENHWIMG=${CUMULUS_CENHWIMG_FINAL_IMG},MEMD=${MEMD_FINAL_IMG}
+ # TODO RTC 197497 -- Use Axone MEMD image
+ AXONE_SECT = HBD=${AXONE_HBD_FINAL_IMG},SBE=${AXONE_SBE_FINAL_IMG},HCODE=${AXONE_HCODE_FINAL_IMG},OCC=${AXONE_OCC_FINAL_IMG},WOFDATA=${ZZ_WOFDATA_FINAL_IMG},CENHWIMG=${AXONE_CENHWIMG_FINAL_IMG},MEMD=${ZZ_MEMD_FINAL_IMG}
.endif
PNOR_IMG_INFO = \
nimbus.pnor:${PNOR_LAYOUT}:${NIMBUS_SECT},${HOSTBOOT_DEFAULT_SECTIONS} \
cumulus.pnor:${PNOR_LAYOUT}:${CUMULUS_SECT},${HOSTBOOT_DEFAULT_SECTIONS} \
cumulus_cdimm.pnor:${PNOR_LAYOUT}:${CUMULUS_CDIMM_SECT},${HOSTBOOT_DEFAULT_SECTIONS} \
+ axone.pnor:${PNOR_LAYOUT}:${AXONE_SECT},${HOSTBOOT_DEFAULT_SECTIONS} \
${FIPS_PNOR_INFO}
# To build fake PNOR, set FAKEPNOR to filename of file to build,
@@ -468,8 +495,9 @@ PNOR_IMG_INFO = \
NIMBUS_SECT = HBD=${NIMBUS_HBD_FINAL_IMG},HCODE=${NIMBUS_HCODE_FINAL_IMG},CENHWIMG=${NIMBUS_CENHWIMG_FINAL_IMG}
CUMULUS_SECT = HBD=${CUMULUS_HBD_FINAL_IMG},HCODE=${CUMULUS_HCODE_FINAL_IMG},CENHWIMG=${CUMULUS_CENHWIMG_FINAL_IMG}
CUMULUS_CDIMM_SECT = HBD=${CUMULUS_CDIMM_HBD_FINAL_IMG},HCODE=${CUMULUS_HCODE_FINAL_IMG},CENHWIMG=${CUMULUS_CENHWIMG_FINAL_IMG}
+ AXONE_SECT = HBD=${AXONE_HBD_FINAL_IMG},HCODE=${AXONE_HCODE_FINAL_IMG},CENHWIMG=${AXONE_CENHWIMG_FINAL_IMG}
PNOR_IMG_INFO = \
- ${FAKEPNOR}:${PNOR_LAYOUT}:${NIMBUS_SECT}:${CUMULUS_SECT}:${CUMULUS_CDIMM_SECT},${HOSTBOOT_DEFAULT_SECTIONS} \
+ ${FAKEPNOR}:${PNOR_LAYOUT}:${NIMBUS_SECT}:${CUMULUS_SECT}:${CUMULUS_CDIMM_SECT},${HOSTBOOT_DEFAULT_SECTIONS},${AXONE_SECT} \
${FIPS_PNOR_INFO}
.endif
diff --git a/src/build/simics/startup.simics b/src/build/simics/startup.simics
index f712811ac..389cf7db9 100755
--- a/src/build/simics/startup.simics
+++ b/src/build/simics/startup.simics
@@ -12,6 +12,8 @@ if ($model == "p9_cumulus") {
if ($machine_name == "CUMULUS_CDIMM") { $hb_machine = "cumulus_cdimm" }
if ($machine_name != "CUMULUS_CDIMM") { $hb_machine = "cumulus" }
}
+if ($model == "p9_axone") {$hb_machine = "axone"}
+
python "os.environ['HB_MACHINE'] = \""+$hb_machine+"\""
echo "HB_MACHINE is: "+$hb_machine
diff --git a/src/build/tools/hbRelease b/src/build/tools/hbRelease
index 8eb545e62..3c0e024ff 100755
--- a/src/build/tools/hbRelease
+++ b/src/build/tools/hbRelease
@@ -65,7 +65,9 @@ if((defined $ENV{'FIPS_RELEASE'}) and
"src/hbfw/cumulus/cumulus.pnor ".
"src/hbfw/cumulus/simics.tar ".
"src/hbfw/cumulus_cdimm/cumulus_cdimm.pnor ".
- "src/hbfw/cumulus_cdimm/simics.tar ";
+ "src/hbfw/cumulus_cdimm/simics.tar ".
+ "src/hbfw/axone/axone.pnor ".
+ "src/hbfw/axone/simics.tar ";
}
# Directory to look up latest release tag for a specific release
diff --git a/src/usr/targeting/common/xmltohb/common.mk b/src/usr/targeting/common/xmltohb/common.mk
index 7b3b8dd90..eaf1fdcd1 100755
--- a/src/usr/targeting/common/xmltohb/common.mk
+++ b/src/usr/targeting/common/xmltohb/common.mk
@@ -50,9 +50,9 @@ XMLTOHB_SOURCE_TARGETS += mapsystemattrsize.C
XMLTOHB_SYSTEM_BINARIES += vbu_NIMBUS_targeting.bin
XMLTOHB_SYSTEM_BINARIES += simics_NIMBUS_targeting.bin
-
XMLTOHB_SYSTEM_BINARIES += simics_CUMULUS_targeting.bin
XMLTOHB_SYSTEM_BINARIES += simics_CUMULUS_CDIMM_targeting.bin
+XMLTOHB_SYSTEM_BINARIES += simics_AXONE_targeting.bin
XMLTOHB_TARGETS += ${XMLTOHB_HEADER_TARGETS}
XMLTOHB_TARGETS += ${XMLTOHB_SOURCE_TARGETS}
diff --git a/src/usr/targeting/common/xmltohb/simics_AXONE.mrw.xml b/src/usr/targeting/common/xmltohb/simics_AXONE.mrw.xml
new file mode 100644
index 000000000..6da5d05bd
--- /dev/null
+++ b/src/usr/targeting/common/xmltohb/simics_AXONE.mrw.xml
@@ -0,0 +1,23 @@
+<!-- IBM_PROLOG_BEGIN_TAG -->
+<!-- This is an automatically generated prolog. -->
+<!-- -->
+<!-- $Source: src/usr/targeting/common/xmltohb/simics_AXONE.mrw.xml $ -->
+<!-- -->
+<!-- OpenPOWER HostBoot Project -->
+<!-- -->
+<!-- Contributors Listed Below - COPYRIGHT 2018 -->
+<!-- -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -->
+<!-- implied. See the License for the specific language governing -->
+<!-- permissions and limitations under the License. -->
+<!-- -->
+<!-- IBM_PROLOG_END_TAG -->
diff --git a/src/usr/targeting/common/xmltohb/simics_AXONE.system.xml b/src/usr/targeting/common/xmltohb/simics_AXONE.system.xml
new file mode 100644
index 000000000..cad476757
--- /dev/null
+++ b/src/usr/targeting/common/xmltohb/simics_AXONE.system.xml
@@ -0,0 +1,614 @@
+<!-- IBM_PROLOG_BEGIN_TAG -->
+<!-- This is an automatically generated prolog. -->
+<!-- -->
+<!-- $Source: src/usr/targeting/common/xmltohb/simics_AXONE.system.xml $ -->
+<!-- -->
+<!-- OpenPOWER HostBoot Project -->
+<!-- -->
+<!-- Contributors Listed Below - COPYRIGHT 2018 -->
+<!-- -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -->
+<!-- implied. See the License for the specific language governing -->
+<!-- permissions and limitations under the License. -->
+<!-- -->
+<!-- IBM_PROLOG_END_TAG -->
+
+<attributes>
+<version>1.0.0</version>
+
+<!-- =====================================================================
+ HOST BOOT TARGET INSTANCES
+ Contains target instance declarations for the Simics Axone
+ configuration
+ * Maximum amount of Axone chips in this Simics model is TBD.
+ * Currently created for 1 chip and will be expanded as needed.
+ * Each Axone has 6 EQ units
+ * Each EQ unit has 2 EX units (a total of 12 per chip)
+ * Each EX has 2 cores, 1 L2, 1 L3 (a total of 24 cores per chip)
+ * Each Axone has has 2 MC units
+ * Each MC unit has 2 MI units (a total of 4 per chip)
+ * Each MI unit has 2 MCC units (a total of 8 per chip)
+ * Each MCC unit has 4 OMI Units (A total of 16 per chip)
+ * OMI Units are special as they have two parents (MI + OMIC (more description below))
+ * Each OMI unit connects to 1 OCMB chip
+ * Each OCMB unit contains 1 MEM_PORT unit
+ * Each MEM_PORT unit connects to 2 DIMMS (Only 1 dimm per mem_port in this XML)
+ * Each MC unit has 3 OMIC units (a total of 12 per chip)
+ * Each OMIC unit contains 2 or 3 OMI Units (OMIC0/1/3/4 contain 3 and OMIC2/5 contain 2 for a total of 16 per chip)
+ * OMI Units are special as they have two parents (OMIC + MCC (described above))
+ * Each Axone has 3 PECs
+ * PEC 0 has 1 PHB
+ * PEC 1 has 2 PHBs
+ * PEC 2 has 3 PHBs
+ * Each Axone has 1 XBUS chiplet (1 XBUS Chiplet translates to multiple xbus units)
+ * Each Axone has 4 OBUS (OB0 to OB3)
+ * Each OBUS has 3 OBUS_BRICK
+ * Each Axone has 21 PPE units (including the SBE):
+ * 1 SBE, 1 Powerbus/Fabric PPE, 4 GPEs, 12 CMEs, and 3 IO PPEs.
+ * Each chiplet existing in an Axone has 1 equivalent PERV unit
+ * Each Axone has 2 CAPP units ##TBD## has 2 sys0node0proc0capp0 units
+ * with same target ID...input MRW has capp0 and capp1...something
+ * wrong in the processMrw.pl (same observed for Witherspoon)
+ * Each Axone has 1 OCC unit
+
+ - p9Proc0(axone chip)
+ - mc0
+ - - mi0
+ - - - mcc0
+ - - - - omi0
+ - - - - omi1
+ - - - mcc1
+ - - - - omi2
+ - - - - omi3
+ - - mi1
+ - - - mcc2
+ - - - - omi4
+ - - - - omi5
+ - - - mcc3
+ - - - - omi6
+ - - - - omi7
+ - - omic0 - - (connects to) - - proc0/mc0/mi1/mcc0/omi0 (omi4)
+ - - /omi1 (omi5)
+ - - /mcc1/omi0 (omi6)
+
+ - - omic1 - - (connects to) - - proc0/mc0/mi1/mcc1/omi1 (omi7)
+ - - /mi0/mcc1/omi0 (omi2)
+ - - /omi1 (omi3)
+
+ - - omic2 - - (connects to) - - proc0/mc0/mi0/mcc0/omi0 (omi0)
+ - - omi1 (omi1)
+
+ - mc1
+ - - mi0
+ - - - mcc0
+ - - - - omi0
+ - - - - omi0
+ - - - mcc0
+ - - - - omi0
+ - - - - omi1
+ - - mi1
+ - - - mcc0
+ - - - - omi0
+ - - - - omi1
+ - - - mcc1
+ - - - - omi0
+ - - - - omi1
+ - - omic3 - - (connects to) - - proc0/mc1/mi1/mcc0/omi0 (omi12)
+ - - /omi1 (omi13)
+ - - /mcc1/omi0 (omi14)
+
+ - - omic4 - - (connects to) - - proc0/mc1/mi1/mcc1/omi1 (omi15)
+ - - /mi0/mcc1/omi1 (omi0)
+ - - /omi1 (omi1)
+
+ - - omic5 - - (connects to) - - proc0/mc1/mi0/mcc0/omi0 (omi8)
+ - - omi1 (omi9)
+
+ ***********************************************************************************
+ * RTC TODO 197498 - Fix these Names after getting an Axone Model:
+
+ **** Information from Simics team ****
+ - Axone Planar
+ - p9Proc0(Axone chip)
+ - MobyDick0(memory riser card)
+ - centaur-0)
+ (isdimms)
+ - IsDimm0_0_0_0
+ - IsDimm0_0_0_1
+ - IsDimm0_0_0_2
+ - IsDimm0_0_0_3
+ - -centaur-1)
+ - IsDimm0_0_1_0
+ - IsDimm0_0_1_1
+ - IsDimm0_0_1_2
+ - IsDimm0_0_1_3
+ - p9Proc0.sbe.ppe(SBE PPE core)
+ - OccComplex0(OCC complex)
+ - OccComplex0.PowmanOccSlot.gpe_ppe0(OCC GPE-0)
+ - OccComplex0.PowmanOccSlot.gpe_ppe1(OCC GPE-1)
+ - OccComplex0.PowmanOccSlot.gpe_ppe2(OCC GPE-2)
+ - OccComplex0.PowmanOccSlot.gpe_ppe0(OCC GPR-3)
+ - proc_p9chip0.tpm_chip(TPM Module)
+ - bmc0(AST2400 Chip that contains : NOR Flash, SIO, LPC and IPMI Responder model)
+
+ Summary:
+ - 1 Axone chip
+ - 8 DIMM's
+ - 1 SBE PPE
+ - 4 OCC GPE
+ - 1 TPM Module
+ - 1 BMC
+ ================================================================= -->
+
+<!-- ===================================================================== -->
+<!-- System Unit -->
+<!-- ===================================================================== -->
+<targetInstance>
+ <id>sys0</id>
+ <type>sys-sys-power9</type>
+ <attribute>
+ <id>AFFINITY_PATH</id>
+ <default>affinity:sys-0</default>
+ </attribute>
+ <attribute>
+ <id>O_EREPAIR_THRESHOLD_FIELD</id>
+ <default>1</default>
+ </attribute>
+ <attribute>
+ <id>O_EREPAIR_THRESHOLD_MNFG</id>
+ <default>0</default>
+ </attribute>
+ <attribute>
+ <id>CLASS</id>
+ <default>SYS</default>
+ </attribute>
+ <attribute>
+ <id>EXECUTION_PLATFORM</id>
+ <default>1</default> <!-- HOST = 0x01 -->
+ </attribute>
+ <attribute>
+ <id>FAPI_NAME</id>
+ <default>k0</default>
+ </attribute>
+ <attribute>
+ <id>FREQ_MEM_REFCLOCK</id>
+ <default>133</default>
+ </attribute>
+ <attribute>
+ <id>FREQ_PROC_REFCLOCK</id>
+ <default>133</default>
+ </attribute>
+ <attribute>
+ <id>FREQ_PB_MHZ</id>
+ <default>2000</default>
+ </attribute>
+ <attribute>
+ <id>HB_SETTINGS</id>
+ <default>
+ <field><id>reserved</id><value/></field>
+ <field><id>traceContinuous</id><value/></field>
+ <field><id>traceFapiDebug</id><value/></field>
+ <field><id>traceScanDebug</id><value/></field>
+ </default>
+ </attribute>
+ <attribute>
+ <id>HUID</id>
+ <default>0x00010000</default>
+ </attribute>
+ <attribute>
+ <id>IS_SIMULATION</id>
+ <default>0</default>
+ </attribute>
+ <attribute>
+ <id>MAX_CHIPLETS_PER_PROC</id>
+ <default>32</default>
+ </attribute>
+ <attribute>
+ <id>MAX_DIMMS_PER_MBA_PORT</id>
+ <default>2</default>
+ </attribute>
+ <attribute>
+ <id>MAX_EXS_PER_PROC_CHIP</id>
+ <default>12</default>
+ </attribute>
+ <attribute>
+ <id>MAX_MBA_PORTS_PER_MBA</id>
+ <default>2</default>
+ </attribute>
+ <attribute>
+ <id>MAX_PROC_CHIPS_PER_NODE</id>
+ <default>4</default>
+ </attribute>
+ <attribute>
+ <id>MEM_MIRROR_PLACEMENT_POLICY</id>
+ <default>0</default>
+ </attribute>
+ <attribute>
+ <id>MRW_DDR3_VDDR_MAX_LIMIT</id>
+ <default>1425</default>
+ </attribute>
+ <attribute>
+ <id>MRW_DDR4_VDDR_MAX_LIMIT</id>
+ <default>1260</default>
+ </attribute>
+ <attribute>
+ <id>MRW_MEM_THROTTLE_DENOMINATOR</id>
+ <default>512</default>
+ </attribute>
+ <attribute>
+ <id>MRW_VMEM_REGULATOR_MEMORY_POWER_LIMIT_PER_DIMM_DDR3</id>
+ <default>3881</default>
+ </attribute>
+ <attribute>
+ <id>MRW_VMEM_REGULATOR_MEMORY_POWER_LIMIT_PER_DIMM_DDR4</id>
+ <default>3449</default>
+ </attribute>
+ <attribute>
+ <id>MSS_INTERLEAVE_ENABLE</id>
+ <default>0x06</default>
+ </attribute>
+ <attribute>
+ <id>MSS_MBA_ADDR_INTERLEAVE_BIT</id>
+ <default>24</default>
+ </attribute>
+ <attribute>
+ <id>MSS_MBA_CACHELINE_INTERLEAVE_MODE</id>
+ <default>2</default>
+ </attribute>
+ <attribute>
+ <id>MSS_VOLT_DDR3_VDDR_INTERCEPT</id>
+ <default>1425</default>
+ </attribute>
+ <attribute>
+ <id>MSS_VOLT_DDR3_VDDR_SLOPE</id>
+ <default>1375</default>
+ </attribute>
+ <attribute>
+ <id>MSS_VOLT_DDR4_VDDR_INTERCEPT</id>
+ <default>1225</default>
+ </attribute>
+ <attribute>
+ <id>MSS_VOLT_DDR4_VDDR_SLOPE</id>
+ <default>425</default>
+ </attribute>
+ <attribute>
+ <id>ORDINAL_ID</id>
+ <default>0</default>
+ </attribute>
+ <attribute>
+ <id>PAYLOAD_BASE</id>
+ <!-- Value of 0x0 for standalone systems, no payload to start -->
+ <default>0x0</default>
+ </attribute>
+ <attribute>
+ <id>PAYLOAD_ENTRY</id>
+ <!-- Value of 0x0 for standalone systems, no payload to start -->
+ <default>0x0</default>
+ </attribute>
+ <attribute>
+ <id>PAYLOAD_KIND</id>
+ <default>NONE</default>
+ </attribute>
+ <attribute>
+ <id>PHYS_PATH</id>
+ <default>physical:sys-0</default>
+ </attribute>
+ <attribute>
+ <id>PROC_EPS_TABLE_TYPE</id>
+ <default>1</default>
+ </attribute>
+ <attribute>
+ <id>PROC_FABRIC_PUMP_MODE</id>
+ <default>1</default>
+ </attribute>
+ <attribute>
+ <id>REDUNDANT_CLOCKS</id>
+ <default>1</default>
+ </attribute>
+ <attribute>
+ <id>SP_FUNCTIONS</id>
+ <default>
+ <field><id>baseServices</id><value>1</value></field>
+ <field><id>fsiMasterInit</id><value>1</value></field>
+ <field><id>fsiSlaveInit</id><value>1</value></field>
+ <field><id>hardwareChangeDetection</id><value>1</value></field>
+ <field><id>mailboxEnabled</id><value>0</value></field>
+ <field><id>powerLineDisturbance</id><value>1</value></field>
+ <field><id>reserved</id><value>0</value></field>
+ </default>
+ </attribute>
+ <attribute>
+ <id>TYPE</id>
+ <default>SYS</default>
+ </attribute>
+ <attribute>
+ <id>X_EREPAIR_THRESHOLD_FIELD</id>
+ <default>1</default>
+ </attribute>
+ <attribute>
+ <id>X_EREPAIR_THRESHOLD_MNFG</id>
+ <default>0</default>
+ </attribute>
+</targetInstance>
+
+<!-- ===================================================================== -->
+<!-- Node Unit -->
+<!-- ===================================================================== -->
+<targetInstance>
+ <id>sys0node0</id>
+ <type>enc-node-power9</type>
+ <attribute>
+ <id>AFFINITY_PATH</id>
+ <default>affinity:sys-0/node-0</default>
+ </attribute>
+ <attribute>
+ <id>EEPROM_VPD_PRIMARY_INFO</id>
+ <default>
+ <field><id>byteAddrOffset</id><value>0x02</value></field>
+ <field><id>chipCount</id><value>0x01</value></field>
+ <field><id>devAddr</id><value>0xA0</value></field>
+ <field><id>engine</id><value>2</value></field>
+ <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-0</value></field>
+ <field><id>maxMemorySizeKB</id><value>0x40</value></field>
+ <field><id>port</id><value>0</value></field>
+ <field><id>writeCycleTime</id><value>20</value></field>
+ <field><id>writePageSize</id><value>32</value></field>
+ </default>
+ </attribute>
+ <attribute>
+ <id>FAPI_NAME</id>
+ <default>NA</default>
+ </attribute>
+ <attribute>
+ <id>HUID</id>
+ <default>0x00020000</default>
+ </attribute>
+ <attribute>
+ <id>ORDINAL_ID</id>
+ <default>0</default>
+ </attribute>
+ <attribute>
+ <id>PHYS_PATH</id>
+ <default>physical:sys-0/node-0</default>
+ </attribute>
+ <attribute>
+ <id>TYPE</id>
+ <default>NODE</default>
+ </attribute>
+</targetInstance>
+
+<!-- ===================================================================== -->
+<!-- Proc Units -->
+<!-- ===================================================================== -->
+<targetInstance>
+ <id>sys0node0proc0</id>
+ <type>chip-processor-axone</type>
+ <attribute>
+ <id>AFFINITY_PATH</id>
+ <default>affinity:sys-0/node-0/proc-0</default>
+ </attribute>
+ <attribute>
+ <id>ALTFSI_MASTER_CHIP</id>
+ <default>physical:na</default>
+ </attribute>
+ <attribute>
+ <id>ALTFSI_MASTER_PORT</id>
+ <default>0x1</default>
+ </attribute>
+ <attribute>
+ <id>CLASS</id>
+ <default>CHIP</default>
+ </attribute>
+ <attribute>
+ <id>EEPROM_SBE_BACKUP_INFO</id>
+ <default>
+ <field><id>byteAddrOffset</id><value>0x02</value></field>
+ <field><id>chipCount</id><value>0x04</value></field>
+ <field><id>devAddr</id><value>0xA8</value></field>
+ <field><id>engine</id><value>1</value></field>
+ <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-0</value></field>
+ <field><id>maxMemorySizeKB</id><value>0x100</value></field>
+ <field><id>port</id><value>3</value></field>
+ <field><id>writeCycleTime</id><value>0x0A</value></field>
+ <field><id>writePageSize</id><value>0x80</value></field>
+ </default>
+ </attribute>
+ <attribute>
+ <id>EEPROM_SBE_PRIMARY_INFO</id>
+ <default>
+ <field><id>byteAddrOffset</id><value>0x02</value></field>
+ <field><id>chipCount</id><value>0x04</value></field>
+ <field><id>devAddr</id><value>0xA8</value></field>
+ <field><id>engine</id><value>1</value></field>
+ <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-0</value></field>
+ <field><id>maxMemorySizeKB</id><value>0x100</value></field>
+ <field><id>port</id><value>1</value></field>
+ <field><id>writeCycleTime</id><value>0x0A</value></field>
+ <field><id>writePageSize</id><value>0x80</value></field>
+ </default>
+ </attribute>
+ <attribute>
+ <id>EEPROM_VPD_BACKUP_INFO</id>
+ <default>
+ <field><id>byteAddrOffset</id><value>0x02</value></field>
+ <field><id>chipCount</id><value>0x02</value></field>
+ <field><id>devAddr</id><value>0xA0</value></field>
+ <field><id>engine</id><value>1</value></field>
+ <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-0</value></field>
+ <field><id>maxMemorySizeKB</id><value>0x80</value></field>
+ <field><id>port</id><value>2</value></field>
+ <field><id>writeCycleTime</id><value>0x0A</value></field>
+ <field><id>writePageSize</id><value>0x80</value></field>
+ </default>
+ </attribute>
+ <attribute>
+ <id>EEPROM_VPD_PRIMARY_INFO</id>
+ <default>
+ <field><id>byteAddrOffset</id><value>0x02</value></field>
+ <field><id>chipCount</id><value>0x02</value></field>
+ <field><id>devAddr</id><value>0xA0</value></field>
+ <field><id>engine</id><value>1</value></field>
+ <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-0</value></field>
+ <field><id>maxMemorySizeKB</id><value>0x80</value></field>
+ <field><id>port</id><value>0</value></field>
+ <field><id>writeCycleTime</id><value>0x0A</value></field>
+ <field><id>writePageSize</id><value>0x80</value></field>
+ </default>
+ </attribute>
+ <attribute>
+ <id>FABRIC_CHIP_ID</id>
+ <default>0</default>
+ </attribute>
+ <attribute>
+ <id>FABRIC_GROUP_ID</id>
+ <default>0</default>
+ </attribute>
+ <attribute>
+ <id>FAPI_NAME</id>
+ <default>pu:k0:n0:s0:p00</default>
+ </attribute>
+ <attribute>
+ <id>FAPI_POS</id>
+ <default>0</default>
+ </attribute>
+ <attribute>
+ <id>FSI_MASTER_CHIP</id>
+ <default>physical:na</default>
+ </attribute>
+ <attribute>
+ <id>FSI_MASTER_PORT</id>
+ <default>0xFF</default>
+ </attribute>
+ <attribute>
+ <id>FSI_MASTER_TYPE</id>
+ <default>MFSI</default>
+ </attribute>
+ <attribute>
+ <id>FSI_OPTION_FLAGS</id>
+ <default>
+ <field><id>flipPort</id><value>0</value></field>
+ <field><id>reserved</id><value>0</value></field>
+ </default>
+ </attribute>
+ <attribute>
+ <id>FSI_SLAVE_CASCADE</id>
+ <default>0</default>
+ </attribute>
+ <attribute>
+ <id>FSP_BASE_ADDR</id>
+ <default>0x0006030100000000</default>
+ </attribute>
+ <attribute>
+ <id>HUID</id>
+ <default>0x00050000</default>
+ </attribute>
+ <attribute>
+ <id>I2C_BUS_SPEED_ARRAY</id>
+ <default>400,400,0,0,0,0,0,0,0,0,0,0,0,
+ 400,400,400,400,0,0,0,0,0,0,0,0,0,
+ 400,400,0,0,0,0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,0,0,0,0,0</default>
+ </attribute>
+ <attribute>
+ <id>MRU_ID</id>
+ <default>0x00010000</default>
+ </attribute>
+ <attribute>
+ <id>ORDINAL_ID</id>
+ <default>0</default>
+ </attribute>
+ <attribute>
+ <id>PHYS_PATH</id>
+ <default>physical:sys-0/node-0/proc-0</default>
+ </attribute>
+ <attribute>
+ <id>POSITION</id>
+ <default>0</default>
+ </attribute>
+ <attribute>
+ <id>PRIMARY_CAPABILITIES</id>
+ <default>
+ <field><id>reserved</id><value>0</value></field>
+ <field><id>supportsFsiScom</id><value>1</value></field>
+ <field><id>supportsInbandScom</id><value>0</value></field>
+ <field><id>supportsXscom</id><value>1</value></field>
+ </default>
+ </attribute>
+ <attribute>
+ <id>PROC_EFF_FABRIC_CHIP_ID</id>
+ <default>0</default>
+ </attribute>
+ <attribute>
+ <id>PROC_EFF_FABRIC_GROUP_ID</id>
+ <default>0</default>
+ </attribute>
+ <attribute>
+ <id>PROC_MASTER_TYPE</id>
+ <default>ACTING_MASTER</default>
+ </attribute>
+ <attribute>
+ <id>PROC_R_DISTLOSS_VCS_UOHM</id>
+ <default>0x640</default>
+ </attribute>
+ <attribute>
+ <id>PROC_R_DISTLOSS_VDD_UOHM</id>
+ <default>0xAA</default>
+ </attribute>
+ <attribute>
+ <id>PROC_R_DISTLOSS_VDN_UOHM</id>
+ <default>0xAA</default>
+ </attribute>
+ <attribute>
+ <id>PROC_R_LOADLINE_VCS_UOHM</id>
+ <default>0x1F4</default>
+ </attribute>
+ <attribute>
+ <id>PROC_R_LOADLINE_VDD_UOHM</id>
+ <default>0x1F4</default>
+ </attribute>
+ <attribute>
+ <id>PROC_R_LOADLINE_VDN_UOHM</id>
+ <default>0x1F4</default>
+ </attribute>
+ <attribute>
+ <id>PROC_VRM_VOFFSET_VCS_UV</id>
+ <default>0x30D4</default>
+ </attribute>
+ <attribute>
+ <id>PROC_VRM_VOFFSET_VDD_UV</id>
+ <default>0x30D4</default>
+ </attribute>
+ <attribute>
+ <id>PROC_VRM_VOFFSET_VDN_UV</id>
+ <default>0x30D4</default>
+ </attribute>
+ <attribute>
+ <id>SCOM_SWITCHES</id>
+ <default>
+ <field><id>reserved</id><value>0</value></field>
+ <field><id>useFsiScom</id><value>0</value></field>
+ <field><id>useInbandScom</id><value>0</value></field>
+ <field><id>useSbeScom</id><value>0</value></field>
+ <field><id>useXscom</id><value>1</value></field>
+ </default>
+ </attribute>
+ <attribute>
+ <id>TYPE</id>
+ <default>PROC</default>
+ </attribute>
+ <attribute>
+ <id>VPD_REC_NUM</id>
+ <default>0</default>
+ </attribute>
+</targetInstance>
+
+</attributes>
diff --git a/src/usr/targeting/common/xmltohb/target_types.xml b/src/usr/targeting/common/xmltohb/target_types.xml
index 6914dd347..d0f776d86 100644
--- a/src/usr/targeting/common/xmltohb/target_types.xml
+++ b/src/usr/targeting/common/xmltohb/target_types.xml
@@ -1179,9 +1179,6 @@
<id>ISTEP_PAUSE_ENABLE</id>
</attribute>
<attribute>
- <id>ISTEP_PAUSE_ENABLE</id>
- </attribute>
- <attribute>
<default>0x0006030000000000</default>
<id>LPC_BUS_ADDR</id>
</attribute>
@@ -1190,9 +1187,6 @@
<id>MAX_CHIPLETS_PER_PROC</id>
</attribute>
<attribute>
- <id>MAX_CHIPLETS_PER_PROC</id>
- </attribute>
- <attribute>
<id>MAX_COMPUTE_NODES_PER_SYSTEM</id>
</attribute>
<attribute>
@@ -1205,9 +1199,6 @@
<id>MAX_EXS_PER_PROC_CHIP</id>
</attribute>
<attribute>
- <id>MAX_EXS_PER_PROC_CHIP</id>
- </attribute>
- <attribute>
<id>MAX_MBAS_PER_MEMBUF_CHIP</id>
</attribute>
<attribute>
@@ -1217,12 +1208,6 @@
<id>MAX_MCS_PER_SYSTEM</id>
</attribute>
<attribute>
- <id>MAX_MCS_PER_SYSTEM</id>
- </attribute>
- <attribute>
- <id>MAX_PROC_CHIPS_PER_NODE</id>
- </attribute>
- <attribute>
<id>MAX_PROC_CHIPS_PER_NODE</id>
</attribute>
<attribute>
diff --git a/src/usr/targeting/xmltohb/makefile b/src/usr/targeting/xmltohb/makefile
index e67a87235..154a71950 100755
--- a/src/usr/targeting/xmltohb/makefile
+++ b/src/usr/targeting/xmltohb/makefile
@@ -197,6 +197,9 @@ XMLTOHB_SYSTEM_BINARIES += simics_CUMULUS_targeting.bin.unprotected
XMLTOHB_SYSTEM_BINARIES += simics_CUMULUS_CDIMM_targeting.bin.protected
XMLTOHB_SYSTEM_BINARIES += simics_CUMULUS_CDIMM_targeting.bin.unprotected
+XMLTOHB_SYSTEM_BINARIES += simics_AXONE_targeting.bin.protected
+XMLTOHB_SYSTEM_BINARIES += simics_AXONE_targeting.bin.unprotected
+
#debug :
# @echo COMMON_TARGETING_PATH_PREFIX = ${COMMON_TARGETING_PATH_PREFIX}
# @echo COMMON_TARGETING_REL_PATH = ${COMMON_TARGETING_REL_PATH}
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