diff options
| -rw-r--r-- | src/usr/intr/intrrp.C | 53 | ||||
| -rw-r--r-- | src/usr/intr/intrrp.H | 8 |
2 files changed, 61 insertions, 0 deletions
diff --git a/src/usr/intr/intrrp.C b/src/usr/intr/intrrp.C index 96d24a7f5..321a2943d 100644 --- a/src/usr/intr/intrrp.C +++ b/src/usr/intr/intrrp.C @@ -550,6 +550,13 @@ errlHndl_t IntrRp::initIRSCReg(TARGETING::Target * i_target) size_t scom_len = sizeof(uint64_t); + // Mask off interrupts from isn's on this target + // This also sets the source isn and PIR destination + // such that if an interrupt is pending when when the ISRN + // is written, simics get the right destination for the + // interrupt. + err = maskXIVR(i_target); + // Setup PHBISR // EN.TPC.PSIHB.PSIHB_ISRN_REG set to 0x00030003FFFF0000 PSIHB_ISRN_REG_t reg; @@ -696,7 +703,53 @@ errlHndl_t IntrRp::initXIVR(enum ISNvalue_t i_isn, bool i_enable) return err; } +//---------------------------------------------------------------------------- + +// Set priority highest (disabled) ,but with valid PIR +errlHndl_t IntrRp::maskXIVR(TARGETING::Target *i_target) +{ + struct XIVR_INFO + { + ISNvalue_t isn:8; + uint32_t addr; + }; + + static const XIVR_INFO xivr_info[] = + { + {ISN_OCC, PsiHbXivr::OCC_XIVR_ADRR}, + {ISN_FSI, PsiHbXivr::FSI_XIVR_ADRR}, + {ISN_LPC, PsiHbXivr::LPC_XIVR_ADRR}, + {ISN_LCL_ERR, PsiHbXivr::LCL_ERR_XIVR_ADDR}, + {ISN_HOST, PsiHbXivr::HOST_XIVR_ADRR} + }; + + errlHndl_t err = NULL; + size_t scom_len = sizeof(uint64_t); + PIR_t pir = intrDestCpuId(); + PsiHbXivr xivr; + + xivr.pir = pir.word; + xivr.priority = PsiHbXivr::PRIO_DISABLED; + + for(size_t i = 0; i < sizeof(xivr_info)/sizeof(xivr_info[0]); ++i) + { + xivr.source = xivr_info[i].isn; + err = deviceWrite + (i_target, + &xivr, + scom_len, + DEVICE_SCOM_ADDRESS(xivr_info[i].addr)); + + if(err) + { + break; + } + } + return err; +} + +//---------------------------------------------------------------------------- errlHndl_t IntrRp::registerInterruptISN(msg_q_t i_msgQ, uint32_t i_msg_type, diff --git a/src/usr/intr/intrrp.H b/src/usr/intr/intrrp.H index 2a32edca4..884fc27fc 100644 --- a/src/usr/intr/intrrp.H +++ b/src/usr/intr/intrrp.H @@ -403,6 +403,14 @@ namespace INTR errlHndl_t initXIVR(enum ISNvalue_t i_isn, bool i_enable); /** + * Setup XIVR with intr masked and isn & destination set for + * xivr/isn that hostboot uses. + * @param i_target : The target processor chip + * @return error handle + */ + errlHndl_t maskXIVR(TARGETING::Target * i_target); + + /** * Shutdown procedure */ void shutDown(); |
