diff options
3 files changed, 25 insertions, 2 deletions
diff --git a/src/build/citest/etc/workarounds.postsimsetup b/src/build/citest/etc/workarounds.postsimsetup index 5e945a745..fc424a148 100755 --- a/src/build/citest/etc/workarounds.postsimsetup +++ b/src/build/citest/etc/workarounds.postsimsetup @@ -27,15 +27,24 @@ ## Workarounds that are run after start_simics is executed for the first time ## to setup the sandbox ## - ### Example applying a patch to cec-chip files #echo "+++ Updating something wonderful in a simics file" #mkdir -p $sb/simu/data/cec-chip/ #cp $BACKING_BUILD/src/simu/data/cec-chip/base_cec_chip_file $sb/simu/data/cec-chip #patch -p0 $sb/simu/data/cec-chip/base_cec_chip_file $PROJECT_ROOT/src/build/citest/etc/patches/my_patch_File - #pull in new actions in p9_memory.act RTC 171066 echo "+++ Updating p9n_memory.act file for p9_mss_ddr_phy_reset" sbex -t 1019444 +#pull in href makefile fix +echo "+++ Updating href makefile" +sbex -t 1020522 + +#pull in new sbe image +echo "+++ Updating sbe image" +sbex -t 1020384 +chmod 777 $sb/sbei/sbfw/img/* +mkdir -p $sb/engd/href/ +cd $sb/engd/href +mk -a -k diff --git a/src/import/chips/p9/procedures/hwp/customize/p9_xip_customize.C b/src/import/chips/p9/procedures/hwp/customize/p9_xip_customize.C index 3ea3a465b..e6bb1fdf5 100644 --- a/src/import/chips/p9/procedures/hwp/customize/p9_xip_customize.C +++ b/src/import/chips/p9/procedures/hwp/customize/p9_xip_customize.C @@ -100,6 +100,7 @@ fapi2::ReturnCode writeMboxRegs ( MBOX_ATTR_SET (ATTR_PROC_SBE_MASTER_CHIP, i_proc_target, i_image); MBOX_ATTR_CLEAR (ATTR_PROC_FABRIC_GROUP_ID, i_proc_target, i_image); MBOX_ATTR_CLEAR (ATTR_PROC_FABRIC_CHIP_ID, i_proc_target, i_image); + MBOX_ATTR_WRITE (ATTR_DD1_SLOW_PCI_REF_CLOCK, FAPI_SYSTEM, i_image); fapi_try_exit: FAPI_DBG("writeMboxRegs Exiting..."); diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_setup_sbe_config.C b/src/import/chips/p9/procedures/hwp/perv/p9_setup_sbe_config.C index e5b849e5a..693adad98 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_setup_sbe_config.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_setup_sbe_config.C @@ -82,6 +82,7 @@ enum P9_SETUP_SBE_CONFIG_Private_Constants ATTR_RISK_LEVEL_BIT = 2, ATTR_DISABLE_HBBL_VECTORS_BIT = 3, ATTR_MC_SYNC_MODE_BIT = 4, + ATTR_SLOW_PCI_REF_CLOCK_BIT = 5, // Scratch_reg_6 ATTR_PROC_FABRIC_GROUP_ID_STARTBIT = 26, @@ -277,6 +278,7 @@ fapi2::ReturnCode p9_setup_sbe_config(const uint8_t l_disable_hbbl_vectors; uint32_t l_pll_mux; uint8_t l_mc_sync_mode; + uint8_t l_slow_pci_ref_clock; FAPI_DBG("Reading Scratch_reg5"); //Getting SCRATCH_REGISTER_5 register value @@ -289,6 +291,7 @@ fapi2::ReturnCode p9_setup_sbe_config(const FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_RISK_LEVEL, FAPI_SYSTEM, l_risk_level)); FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_DISABLE_HBBL_VECTORS, FAPI_SYSTEM, l_disable_hbbl_vectors)); FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MC_SYNC_MODE, i_target_chip, l_mc_sync_mode)); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_DD1_SLOW_PCI_REF_CLOCK, FAPI_SYSTEM, l_slow_pci_ref_clock)); // set cache contained flag if (l_system_ipl_phase == fapi2::ENUM_ATTR_SYSTEM_IPL_PHASE_CACHE_CONTAINED) @@ -340,6 +343,16 @@ fapi2::ReturnCode p9_setup_sbe_config(const l_read_scratch_reg.clearBit<ATTR_MC_SYNC_MODE_BIT>(); } + // set slow PCI ref clock bit + if (l_slow_pci_ref_clock == fapi2::ENUM_ATTR_DD1_SLOW_PCI_REF_CLOCK_SLOW) + { + l_read_scratch_reg.clearBit<ATTR_SLOW_PCI_REF_CLOCK_BIT>(); + } + else + { + l_read_scratch_reg.setBit<ATTR_SLOW_PCI_REF_CLOCK_BIT>(); + } + FAPI_DBG("Reading PLL mux attributes"); FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CLOCK_PLL_MUX, i_target_chip, l_pll_mux)); // set PLL MUX bits |
