diff options
5 files changed, 54 insertions, 13 deletions
diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_common.H b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_common.H index 05fc2fa21..1f8b72590 100644 --- a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_common.H +++ b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_common.H @@ -93,9 +93,12 @@ //------------------------- // Constants //------------------------- - +#ifndef __PPE_PLAT +#ifdef __cplusplus namespace p9hcd { +#endif +#endif // Bit masks used by CME hcode enum P9_HCD_CME_CORE_MASKS @@ -271,8 +274,11 @@ enum SICR_DEFS PCBMUX_REQ_C1 = 11 }; +#ifndef __PPE_PLAT +#ifdef __cplusplus } // END OF NAMESPACE p9hcd - +#endif +#endif #define P9_HCD_SCAN_FUNC_REPEAT 1 #define P9_HCD_SCAN_GPTR_REPEAT 1 diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H index 6e3b54d49..f3b1fcf9a 100644 --- a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H +++ b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H @@ -221,16 +221,17 @@ HCD_CONST(SGPE_RESET_ADDR_IMAGE_OFFSET, (SGPE_HEADER_IMAGE_OFFSET + SGPE HCD_CONST(SGPE_BUILD_DATE_IMAGE_OFFSET, (SGPE_HEADER_IMAGE_OFFSET + SGPE_BUILD_DATE_BYTE)) HCD_CONST(SGPE_BUILD_VER_IMAGE_OFFSET, (SGPE_HEADER_IMAGE_OFFSET + SGPE_BUILD_VER_BYTE)) -HCD_CONST(SGPE_STOP_4_TO_2_BIT_POS, 0x80000000) -HCD_CONST(SGPE_STOP_5_TO_4_BIT_POS, 0x40000000) -HCD_CONST(SGPE_STOP_8_TO_5_BIT_POS, 0x20000000) -HCD_CONST(SGPE_STOP_11_TO_8_BIT_POS, 0x10000000) -HCD_CONST(SGPE_ENABLE_CME_TRACE_ARRAY_BIT_POS, 0x08000000) -HCD_CONST(SGPE_VDM_ENABLE_BIT_POS, 0x04000000) -HCD_CONST(SGPE_ENABLE_CHTM_TRACE_CME_BIT_POS, 0x02000000) -HCD_CONST(SGPE_PROC_FAB_PUMP_MODE_BIT_POS, 0x00004000) -HCD_CONST(SGPE_CACHE_SKEWADJ_DISABLE_BIT_POS, 0x00002000) -HCD_CONST(SGPE_CACHE_DCADJ_DISABLE_BIT_POS, 0x00001000) +HCD_CONST(SGPE_STOP_4_TO_2_BIT_POS, 0x80000000) +HCD_CONST(SGPE_STOP_5_TO_4_BIT_POS, 0x40000000) +HCD_CONST(SGPE_STOP_8_TO_5_BIT_POS, 0x20000000) +HCD_CONST(SGPE_STOP_11_TO_8_BIT_POS, 0x10000000) +HCD_CONST(SGPE_ENABLE_CME_TRACE_ARRAY_BIT_POS, 0x08000000) +HCD_CONST(SGPE_VDM_ENABLE_BIT_POS, 0x04000000) +HCD_CONST(SGPE_ENABLE_CHTM_TRACE_CME_BIT_POS, 0x02000000) +HCD_CONST(SGPE_CORE_PERIODIC_QUIESCE_DISABLE_POS, 0x01000000) +HCD_CONST(SGPE_PROC_FAB_PUMP_MODE_BIT_POS, 0x00004000) +HCD_CONST(SGPE_CACHE_SKEWADJ_DISABLE_BIT_POS, 0x00002000) +HCD_CONST(SGPE_CACHE_DCADJ_DISABLE_BIT_POS, 0x00001000) ///24x7 HCD_CONST(QPMR_AUX_OFFSET, (512 * ONE_KB)) diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C index 274c1660b..590ca568d 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C @@ -936,6 +936,18 @@ fapi2::ReturnCode updateImageFlags( Homerlayout_t* i_pChipHomer, CONST_FAPI2_PRO FAPI_DBG("Cache DC Adjust Disabled : %s", attrVal ? "TRUE" : "FALSE" ); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SYSTEM_CORE_PERIODIC_QUIESCE_DISABLE, + FAPI_SYSTEM, + attrVal), + "Error from FAPI_ATTR_GET for attribute ATTR_SYSTEM_CORE_PERIODIC_QUIESCE_DISABLE"); + + if( attrVal ) + { + sgpeFlag |= SGPE_CORE_PERIODIC_QUIESCE_DISABLE_POS; + } + + FAPI_DBG("Core Periodic Quiesce Disabled: %s", attrVal ? "TRUE" : "FALSE" ); + // Set PGPE Header Flags from Attributes FAPI_DBG(" -------------------- PGPE Flags -----------------"); FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PGPE_HCODE_FUNCTION_ENABLE, diff --git a/src/import/chips/p9/procedures/xml/attribute_info/pm_plat_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/pm_plat_attributes.xml index 02eafb14a..fa8e5440d 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/pm_plat_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/pm_plat_attributes.xml @@ -901,6 +901,23 @@ </attribute> <!-- ********************************************************************* --> <attribute> + <id>ATTR_SYSTEM_CORE_PERIODIC_QUIESCE_DISABLE</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description>Disable the Core Periodic Quiesce Hang Buster function + + Producer: Lab tools + + Consumer: p9_hcode_image_build.C -> SGPE Hcode -> CME Hcode + + Platform default: OFF + </description> + <valueType>uint8</valueType> + <enum>OFF=0, ON=1</enum> + <platInit/> + <initToZero/> + </attribute> + <!-- ********************************************************************* --> + <attribute> <id>ATTR_SYSTEM_WOF_DISABLE</id> <targetType>TARGET_TYPE_SYSTEM</targetType> <description>Disables Work Load Optimized Frequency (WOF) algorithms to @@ -1881,7 +1898,7 @@ Consumer: p9_hcode_image_build.c -> PGPE Header field - Platform default: ON + Platform default: ON <!-- @todo RTC 169662 at some point in the program, this default may be switched to the opposite setting. However, coordination needs to occur with all CIs diff --git a/src/import/hwpf/fapi2/xml/attribute_info/hb_temp_defaults.xml b/src/import/hwpf/fapi2/xml/attribute_info/hb_temp_defaults.xml index 423016c74..3c927243d 100644 --- a/src/import/hwpf/fapi2/xml/attribute_info/hb_temp_defaults.xml +++ b/src/import/hwpf/fapi2/xml/attribute_info/hb_temp_defaults.xml @@ -346,6 +346,11 @@ <default>0x00</default> </attribute> + <attribute> + <id>ATTR_SYSTEM_CORE_PERIODIC_QUIESCE_DISABLE</id> + <default>0x00</default> + </attribute> + <!-- ===================================================================== End of temporary definitions ================================================================= --> |
