INITPROC: Hostboot - High Priority HW Init Procedures for week of 4/30

SW201168

Change-Id: I94c46f56d68bc9c0a6c0bfcd9c08465be337ba12
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/4505
Tested-by: Jenkins Server
Reviewed-by: Van H. Lee <vanlee@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

11 files changed, 413 insertions, 38 deletions

diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.C b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.C
index 0139bdf55..9396db2c5 100644
--- a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.C
+++ b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.C
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_setup_bars.C,v 1.9 2013/03/17 22:56:03 jmcgill Exp $
+// $Id: proc_setup_bars.C,v 1.10 2013/04/27 21:48:59 jmcgill Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_setup_bars.C,v $
 //------------------------------------------------------------------------------
 // *|
@@ -3290,6 +3290,158 @@ proc_setup_bars_write_bars(
 
 
 //------------------------------------------------------------------------------
+// function: enable MCD probes/unmask FIRs
+// parameters: i_smp                        => structure encapsulating fully
+//                                             specified SMP topology
+//             i_init_local_chip_local_node => boolean qualifying application
+//                                             of local chip/local node range
+//                                             specific BAR resources
+// returns: FAPI_RC_SUCCESS if all register writes are successful,
+//          else failing return code from failing SCOM access
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_setup_bars_config_mcd(
+    proc_setup_bars_smp_system& i_smp,
+    const bool& i_init_local_chip_local_node)
+{
+    // return code
+    fapi::ReturnCode rc;
+    uint32_t rc_ecmd = 0;
+
+    ecmdDataBufferBase mcd_fir_mask_data(64);
+    ecmdDataBufferBase mcd_recov_data(64);
+    ecmdDataBufferBase mcd_recov_mask(64);
+    std::map<proc_fab_smp_node_id, proc_setup_bars_smp_node>::iterator n_iter;
+    std::map<proc_fab_smp_chip_id, proc_setup_bars_smp_chip>::iterator p_iter;
+
+    FAPI_DBG("proc_setup_bars_config_mcd: Start");
+
+    do
+    {
+        for (n_iter = i_smp.nodes.begin();
+             (n_iter != i_smp.nodes.end()) && (rc.ok());
+             n_iter++)
+        {
+            for (p_iter = n_iter->second.chips.begin();
+                 (p_iter != n_iter->second.chips.end()) && (rc.ok());
+                 p_iter++)
+            {
+                bool config_mcd = false;
+                bool cfg_enable[PROC_SETUP_BARS_NUM_MCD_CFG] =
+                    { false, false, false, false };
+
+                // ensure MCD probes are enabled and FIR is unmasked if:
+                //   initializing local chip resources and there is a
+                //     non-mirrored/mirrored range enabled OR
+                //   initializing foreign resources and there is a
+                //     near range enabled
+
+                if (i_init_local_chip_local_node &&
+                    (p_iter->second.non_mirrored_range.enabled ||
+                     p_iter->second.mirrored_range.enabled))
+                {
+                    config_mcd = true;
+                    cfg_enable[0] = p_iter->second.non_mirrored_range.enabled;
+                    cfg_enable[1] = p_iter->second.mirrored_range.enabled;
+                }
+
+                bool process_f_links[PROC_FAB_SMP_NUM_F_LINKS] =
+                {
+                    p_iter->second.chip->process_f0,
+                    p_iter->second.chip->process_f1
+                };
+
+                // process ranges
+                for (uint8_t r = 0;
+                     (r < PROC_FAB_SMP_NUM_F_LINKS);
+                     r++)
+                {
+                    if (process_f_links[r] &&
+                        p_iter->second.foreign_near_ranges[r].enabled)
+                    {
+                        config_mcd = true;
+                        cfg_enable[2+r] = true;
+                    }
+                }
+
+                if (config_mcd)
+                {
+                    // unmask MCD FIR
+                    rc_ecmd |= mcd_fir_mask_data.setDoubleWord(
+                        0,
+                        MCD_FIR_MASK_RUNTIME_VAL);
+
+                    // check buffer manipulation return codes
+                    if (rc_ecmd)
+                    {
+                        FAPI_ERR("proc_setup_bars_config_mcd: Error 0x%X setting up FIR mask data buffer",
+                                 rc_ecmd);
+                        rc.setEcmdError(rc_ecmd);
+                        break;
+                    }
+
+                    rc = fapiPutScom(p_iter->second.chip->this_chip,
+                                     MCD_FIR_MASK_0x02013403,
+                                     mcd_fir_mask_data);
+                    if (!rc.ok())
+                    {
+                        FAPI_ERR("proc_setup_bars_config_mcd: fapiPutScomUnderMask error (MCD_FIR_MASK_0x02013403)");
+                        break;
+                    }
+
+                    // enable MCD probes for selected config registers
+                    rc_ecmd |= mcd_recov_data.setBit(MCD_RECOVERY_ENABLE_BIT);
+                    rc_ecmd |= mcd_recov_mask.setBit(MCD_RECOVERY_ENABLE_BIT);
+                    for (uint8_t i = 0;
+                         i < PROC_SETUP_BARS_NUM_MCD_CFG;
+                         i++)
+                    {
+                        rc_ecmd |= mcd_recov_data.writeBit(
+                            MCD_RECOVERY_CFG_EN_BIT[i],
+                            cfg_enable[i]);
+                        rc_ecmd |= mcd_recov_mask.writeBit(
+                            MCD_RECOVERY_CFG_EN_BIT[i],
+                            cfg_enable[i]);
+                    }
+
+                    // check buffer manipulation return codes
+                    if (rc_ecmd)
+                    {
+                        FAPI_ERR("proc_setup_bars_config_mcd: Error 0x%X setting up recovery data buffer",
+                                 rc_ecmd);
+                        rc.setEcmdError(rc_ecmd);
+                        break;
+                    }
+
+                    rc = fapiPutScomUnderMask(p_iter->second.chip->this_chip,
+                                              MCD_REC_EVEN_0x02013410,
+                                              mcd_recov_data,
+                                              mcd_recov_mask);
+                    if (!rc.ok())
+                    {
+                        FAPI_ERR("proc_setup_bars_config_mcd: fapiPutScomUnderMask error (MCD_REC_EVEN_0x02013410)");
+                        break;
+                    }
+
+                    rc = fapiPutScomUnderMask(p_iter->second.chip->this_chip,
+                                              MCD_REC_ODD_0x02013411,
+                                              mcd_recov_data,
+                                              mcd_recov_mask);
+                    if (!rc.ok())
+                    {
+                        FAPI_ERR("proc_setup_bars_config_mcd: fapiPutScomUnderMask error (MCD_REC_ODD_0x02013411)");
+                        break;
+                    }
+                }
+            }
+        }
+    } while(0);
+
+    FAPI_DBG("proc_setup_bars_config_mcd: End");
+    return rc;
+}
+
+
+//------------------------------------------------------------------------------
 // function: proc_setup_bars HWP entry point
 //           NOTE: see comments above function prototype in header
 //------------------------------------------------------------------------------
@@ -3329,6 +3481,15 @@ fapi::ReturnCode proc_setup_bars(
             break;
         }
 
+        // configure MCD resources
+        rc = proc_setup_bars_config_mcd(smp,
+                                         i_init_local_chip_local_node);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_setup_bars: Error from proc_setup_bars_config_mcd");
+            break;
+        }
+
     } while(0);
 
     // log function exit
diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.H b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.H
index fc1b68da7..871a79d09 100644
--- a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.H
+++ b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.H
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_setup_bars.H,v 1.5 2013/03/17 22:56:07 jmcgill Exp $
+// $Id: proc_setup_bars.H,v 1.6 2013/04/27 21:49:01 jmcgill Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_setup_bars.H,v $
 //------------------------------------------------------------------------------
 // *|
@@ -904,6 +904,15 @@ const proc_setup_bars_bar_reg_def mcd_f1_bar_reg_def =
     0x780000000000001CULL
 };
 
+// MCD FIR Register constants
+const uint64_t MCD_FIR_MASK_RUNTIME_VAL = 0x2700000000000000ULL;
+
+// MCD Evn/Odd Recovery Control Register field/bit definitions
+const uint8_t PROC_SETUP_BARS_NUM_MCD_CFG = 4;
+
+const uint64_t MCD_RECOVERY_ENABLE_BIT = 0;
+const uint64_t MCD_RECOVERY_CFG_EN_BIT[PROC_SETUP_BARS_NUM_MCD_CFG] = {40,41,42,43};
+
 // PCIe BAR constants
 const uint32_t PROC_SETUP_BARS_PCIE_CHIP_NON_MIRRORED_BAR[PROC_SETUP_BARS_PCIE_NUM_UNITS] =
 {
diff --git a/src/usr/hwpf/hwp/include/common_scom_addresses.H b/src/usr/hwpf/hwp/include/common_scom_addresses.H
index 709301edc..b3a5eddd8 100755
--- a/src/usr/hwpf/hwp/include/common_scom_addresses.H
+++ b/src/usr/hwpf/hwp/include/common_scom_addresses.H
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: common_scom_addresses.H,v 1.44 2013/03/18 19:43:27 jeshua Exp $
+// $Id: common_scom_addresses.H,v 1.46 2013/05/06 21:03:10 jeshua Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/common_scom_addresses.H,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
@@ -175,6 +175,9 @@ CONST_UINT64_T( GENERIC_GP3_OR_0x000F0014             , ULL(0x000F0014) );
 // PM GP0 Register
 CONST_UINT64_T( GENERIC_PMGP0_OR_0x000F0102           , ULL(0x000F0102) );
 
+// PCB ERROR
+CONST_UINT64_T( GENERIC_PCB_ERR_0x000F001F            , ULL(0x000F001F) );
+
 //------------------------------------------------------------------------------
 //      GENERIC PLLLOCK REG
 //------------------------------------------------------------------------------
@@ -212,28 +215,12 @@ CONST_UINT32_T( CFAM_FSI_GP7_0x00001016               , ULL(0x00001016) );
 CONST_UINT32_T( CFAM_FSI_GP8_0x00001017               , ULL(0x00001017) );
 CONST_UINT32_T( CFAM_FSI_GP3_MIRROR_0x0000101B        , ULL(0x0000101B) );
 
-CONST_UINT32_T( CFAM_FSI_GP3_0x00002812               , ULL(0x00002812) );
-CONST_UINT32_T( CFAM_FSI_GP4_0x00002813               , ULL(0x00002813) );
-CONST_UINT32_T( CFAM_FSI_GP5_0x00002814               , ULL(0x00002814) );
-CONST_UINT32_T( CFAM_FSI_GP6_0x00002815               , ULL(0x00002815) );
-CONST_UINT32_T( CFAM_FSI_GP7_0x00002816               , ULL(0x00002816) );
-CONST_UINT32_T( CFAM_FSI_GP8_0x00002817               , ULL(0x00002817) );
-CONST_UINT32_T( CFAM_FSI_GP3_MIRROR_0x0000281B        , ULL(0x0000281B) );
-CONST_UINT32_T( CFAM_FSI_SBE_VITAL_0x0000281C         , ULL(0x0000281C) );
-
 //------------------------------------------------------------------------------
 //      OTPROM
 //------------------------------------------------------------------------------
 CONST_UINT64_T( OTPROM_0x00010000                     , ULL(0x00010000) );
 
 //------------------------------------------------------------------------------
-//      PIBMEM
-//------------------------------------------------------------------------------
-
-CONST_UINT64_T( PIBMEM_REPAIR_0x00088007              , ULL(0x00088007) );
-
-
-//------------------------------------------------------------------------------
 //      MFSI0
 //------------------------------------------------------------------------------
 CONST_UINT64_T( MFSI0_0x00020000                      , ULL(0x00020000) );
@@ -634,6 +621,12 @@ This section is automatically updated by CVS when you check in this file.
 Be sure to create CVS comments when you commit so that they can be included here.
 
 $Log: common_scom_addresses.H,v $
+Revision 1.46  2013/05/06 21:03:10  jeshua
+Added GENERIC_PCB_ERR_0x000F001F
+
+Revision 1.45  2013/04/16 22:16:16  jeshua
+Moved P8 cfam addresses and PIBMEM_REPAIR_0x00088007 to p8_scom_addresses.H
+
 Revision 1.44  2013/03/18 19:43:27  jeshua
 Removed OTPROM_SECURE_SWITCHES_0x00010005 because it's not common between P8 and Centaur. P8 code should use OTPC_M_SECURITY_SWITCH_0x00010005
 
diff --git a/src/usr/hwpf/hwp/include/p8_scom_addresses.H b/src/usr/hwpf/hwp/include/p8_scom_addresses.H
index fed63d932..95ecceed3 100755
--- a/src/usr/hwpf/hwp/include/p8_scom_addresses.H
+++ b/src/usr/hwpf/hwp/include/p8_scom_addresses.H
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: p8_scom_addresses.H,v 1.143 2013/04/08 14:56:05 jmcgill Exp $
+// $Id: p8_scom_addresses.H,v 1.149 2013/05/09 04:05:36 jmcgill Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/p8_scom_addresses.H,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
@@ -158,6 +158,16 @@ CONST_UINT64_T( DEVICE_ID_REG_0x000F000F            , ULL(0x000F000F) );
 //------------------------------------------------------------------------------
 //      FSI MBOX (CFAM)
 //------------------------------------------------------------------------------
+CONST_UINT32_T( CFAM_FSI_GP3_0x00002812               , ULL(0x00002812) );
+CONST_UINT32_T( CFAM_FSI_GP4_0x00002813               , ULL(0x00002813) );
+CONST_UINT32_T( CFAM_FSI_GP5_0x00002814               , ULL(0x00002814) );
+CONST_UINT32_T( CFAM_FSI_GP6_0x00002815               , ULL(0x00002815) );
+CONST_UINT32_T( CFAM_FSI_GP7_0x00002816               , ULL(0x00002816) );
+CONST_UINT32_T( CFAM_FSI_GP8_0x00002817               , ULL(0x00002817) );
+CONST_UINT32_T( CFAM_FSI_WRITE_PROTECT_0x00002818     , ULL(0x00002818) );
+CONST_UINT32_T( CFAM_FSI_GP3_MIRROR_0x0000281B        , ULL(0x0000281B) );
+CONST_UINT32_T( CFAM_FSI_SBE_VITAL_0x0000281C         , ULL(0x0000281C) );
+
 CONST_UINT64_T( MBOX_SCRATCH_REG0_0x00002838          , ULL(0x00002838) );
 CONST_UINT64_T( MBOX_SCRATCH_REG1_0x00002839          , ULL(0x00002839) );
 CONST_UINT64_T( MBOX_SCRATCH_REG2_0x0000283A          , ULL(0x0000283A) );
@@ -394,6 +404,24 @@ CONST_UINT64_T( OCC_SRAM_BOOT_VEC1_0x00066005         , ULL(0x00066005) );
 CONST_UINT64_T( OCC_SRAM_BOOT_VEC2_0x00066006         , ULL(0x00066006) );
 CONST_UINT64_T( OCC_SRAM_BOOT_VEC3_0x00066007         , ULL(0x00066007) );
 
+// interrupt controller registers
+CONST_UINT64_T( OCC_ITP_SOURCE0_MASK_AND_0x0006A001   , ULL(0x0006A001) );
+CONST_UINT64_T( OCC_ITP_SOURCE1_MASK_AND_0x0006A011   , ULL(0x0006A011) );
+CONST_UINT64_T( OCC_ITP_MASK0_MASK_OR_0x0006A006      , ULL(0x0006A006) );
+CONST_UINT64_T( OCC_ITP_MASK1_MASK_OR_0x0006A016      , ULL(0x0006A016) );
+CONST_UINT64_T( OCC_ITP_TYPE0_0x0006A008              , ULL(0x0006A008) );
+CONST_UINT64_T( OCC_ITP_TYPE1_0x0006A018              , ULL(0x0006A018) );
+CONST_UINT64_T( OCC_ITP_EDGE_POLARITY0_0x0006A009     , ULL(0x0006A009) );
+CONST_UINT64_T( OCC_ITP_EDGE_POLARITY1_0x0006A019     , ULL(0x0006A019) );
+CONST_UINT64_T( OCC_ITP_CRITICAL_EN0_0x0006A00A       , ULL(0x0006A00A) );
+CONST_UINT64_T( OCC_ITP_CRITICAL_EN1_0x0006A01A       , ULL(0x0006A01A) );
+CONST_UINT64_T( OCC_ITP_DEBUG_HALT_EN0_0x0006A00E     , ULL(0x0006A00E) );
+CONST_UINT64_T( OCC_ITP_DEBUG_HALT_EN1_0x0006A01E     , ULL(0x0006A01E) );
+CONST_UINT64_T( OCC_ITP_UNCOND_DEBUG_EN0_0x0006A00C   , ULL(0x0006A00C) );
+CONST_UINT64_T( OCC_ITP_UNCOND_DEBUG_EN1_0x0006A01C   , ULL(0x0006A01C) );
+CONST_UINT64_T( OCC_ITP_TIMER0_0x0006A100             , ULL(0x0006A100) );
+CONST_UINT64_T( OCC_ITP_TIMER1_0x0006A101             , ULL(0x0006A101) );
+
 //------------------------------------------------------------------------------
 //      PMC
 //------------------------------------------------------------------------------
@@ -497,7 +525,7 @@ CONST_UINT64_T( PIBMEM_DATA_INC_0x00088003            , ULL(0x00088003) );
 CONST_UINT64_T( PIBMEM_DATA_DEC_0x00088004            , ULL(0x00088004) );
 CONST_UINT64_T( PIBMEM_STATUS_0x00088005              , ULL(0x00088005) );
 CONST_UINT64_T( PIBMEM_RESET_0x00088006               , ULL(0x00088006) );
-CONST_UINT64_T( PIBMEM_REPAIR_LOAD_0x00088007         , ULL(0x00088007) );
+CONST_UINT64_T( PIBMEM_REPAIR_0x00088007              , ULL(0x00088007) );
 
 //------------------------------------------------------------------------------
 //      I2C MASTER (MODE)
@@ -1017,24 +1045,32 @@ CONST_UINT64_T( NX_FAR_BAR_F0_0x0201309A              , ULL(0x0201309A) );
 CONST_UINT64_T( NX_NEAR_BAR_F1_0x0201309B             , ULL(0x0201309B) );
 CONST_UINT64_T( NX_FAR_BAR_F1_0x0201309C              , ULL(0x0201309C) );
 CONST_UINT64_T( NX_CQ_EPS_0x0201309D                  , ULL(0x0201309D) );
-
+CONST_UINT64_T( NX_AS_MMIO_BAR_0x0201309E             , ULL(0x0201309E) );
 
 CONST_UINT64_T( NX_CAPP_FIR_AND_0x02013001            , ULL(0x02013001) );
 CONST_UINT64_T( NX_DMA_ENG_FIR_AND_0x02013101         , ULL(0x02013101) );
 CONST_UINT64_T( NX_CQ_FIR_AND_0x02013081              , ULL(0x02013081) );
 CONST_UINT64_T( NX_AS_FIR_AND_0x020130C1              , ULL(0x020130C1) );
 
-CONST_UINT64_T( EH_PB_MCDCTL_FIR_AND_0x02013401       , ULL(0x02013401) );
-
-
 //------------------------------------------------------------------------------
 //      MCD
 //------------------------------------------------------------------------------
+CONST_UINT64_T( MCD_FIR_0x02013400                    , ULL(0x02013400) );
+CONST_UINT64_T( MCD_FIR_AND_0x02013401                , ULL(0x02013401) );
+CONST_UINT64_T( MCD_FIR_OR_0x02013402                 , ULL(0x02013402) );
+CONST_UINT64_T( MCD_FIR_MASK_0x02013403               , ULL(0x02013403) );
+CONST_UINT64_T( MCD_FIR_MASK_AND_0x02013404           , ULL(0x02013404) );
+CONST_UINT64_T( MCD_FIR_MASK_OR_0x02013405            , ULL(0x02013405) );
+CONST_UINT64_T( MCD_FIR_ACTION0_0x02013406            , ULL(0x02013406) );
+CONST_UINT64_T( MCD_FIR_ACTION1_0x02013407            , ULL(0x02013407) );
+
 CONST_UINT64_T( MCD_PRE_EPS_0x0201340B                , ULL(0x0201340B) );
 CONST_UINT64_T( MCD_CN00_0x0201340C                   , ULL(0x0201340C) );
 CONST_UINT64_T( MCD_CN01_0x0201340D                   , ULL(0x0201340D) );
 CONST_UINT64_T( MCD_CN10_0x0201340E                   , ULL(0x0201340E) );
 CONST_UINT64_T( MCD_CN11_0x0201340F                   , ULL(0x0201340F) );
+CONST_UINT64_T( MCD_REC_EVEN_0x02013410               , ULL(0x02013410) );
+CONST_UINT64_T( MCD_REC_ODD_0x02013411                , ULL(0x02013411) );
 
 
 /******************************************************************************/
@@ -1856,6 +1892,26 @@ This section is automatically updated by CVS when you check in this file.
 Be sure to create CVS comments when you commit so that they can be included here.
 
 $Log: p8_scom_addresses.H,v $
+Revision 1.149  2013/05/09 04:05:36  jmcgill
+add AS MMIO BAR
+
+Revision 1.148  2013/04/28 02:30:41  jmcgill
+add MCD recovery config register definitions
+
+Revision 1.147  2013/04/23 16:30:27  jimyac
+added additional OCC interrupt registers
+
+Revision 1.146  2013/04/17 16:16:32  jimyac
+added OCC registers - OUDER0/1 & OTR0/1
+
+Revision 1.145  2013/04/16 22:15:34  jeshua
+Moved in cfam addresses from common file
+Added in write protect cfam address
+Renamed PIBMEM_REPAIR_LOAD_0x00088007 to PIBMEM_REPAIR_0x00088007
+
+Revision 1.144  2013/04/15 19:28:23  jmcgill
+add MCD FIR entries
+
 Revision 1.143  2013/04/08 14:56:05  jmcgill
 add PCIE ETU reset registers
 
diff --git a/src/usr/hwpf/hwp/initfiles/p8.fbc.define b/src/usr/hwpf/hwp/initfiles/p8.fbc.define
index e6b4d98da..cfc34cfae 100644
--- a/src/usr/hwpf/hwp/initfiles/p8.fbc.define
+++ b/src/usr/hwpf/hwp/initfiles/p8.fbc.define
@@ -1,4 +1,4 @@
-#-- $Id: p8.fbc.define,v 1.5 2013/03/05 02:54:25 jmcgill Exp $
+#-- $Id: p8.fbc.define,v 1.7 2013/05/07 23:15:00 jmcgill Exp $
 #-------------------------------------------------------------------------------
 #--
 #-- (C) Copyright International Business Machines Corp. 2011
@@ -37,6 +37,15 @@ define apm_en = 0;
 define pmucnt_en = 3;
 define pmucnt_sel = 4:5;
 
+#-- MCD Even/Odd Recovery Control Registers (MCD_REC_[EVEN_ODD] / 0x0201341[01])
+define mcd_recov_continuous = 2;
+define mcd_recov_pace_delay = 8:19;
+define mcd_recov_recov_all = 20;
+define mcd_recov_granule_count = 46:63;
+
+#-- MCD Recovery Pre Epsilon Configuration Register (MCD_PRE / 0x0201340B)
+define mcd_retry_count = 40:43;
+
 #-- MCD Debug Configuration Register (MCD_DBG / 0x02013416)
 define mcd_debug_enable = 3;
 define mcd_debug_select = 4:7;
diff --git a/src/usr/hwpf/hwp/initfiles/p8.fbc.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.fbc.scom.initfile
index bbfa5a0ef..2cc5635db 100644
--- a/src/usr/hwpf/hwp/initfiles/p8.fbc.scom.initfile
+++ b/src/usr/hwpf/hwp/initfiles/p8.fbc.scom.initfile
@@ -1,4 +1,4 @@
-#-- $Id: p8.fbc.scom.initfile,v 1.8 2013/03/05 02:54:23 jmcgill Exp $
+#-- $Id: p8.fbc.scom.initfile,v 1.9 2013/04/27 21:49:42 jmcgill Exp $
 #-------------------------------------------------------------------------------
 #--
 #-- (C) Copyright International Business Machines Corp. 2011
@@ -68,6 +68,36 @@ scom 0x02010C50 {
     pmucnt_sel,                 0b11;                                                     #-- PMU counter select = rcmd 0 OR rcmd 1
 }
 
+#-- MCD FIR Mask Register (MCDCTL.FIR_MASK_REG / 0x02013403)
+#-- NOTE: init to all bits masked, proc_setup_bars will unmask if MCD is enabled on this chip
+scom 0x02013403 {
+    bits,                       scom_data;
+    0:63,                       0xFFC0000000000000;
+}
+
+#-- MCD FIR Action0 Register (MCDCTL.FIR_ACTION0_REG / 0x02013406)
+scom 0x02013406 {
+    bits,                       scom_data;
+    0:63,                       0x0000000000000000;
+}
+
+#-- MCD FIR Action1 Register (MCDCTL.FIR_ACTION1_REG / 0x02013407)
+scom 0x02013407 {
+    bits,                       scom_data;
+    0:63,                       0xC800000000000000;
+}
+
+#-- MCD Even/Odd Recovery Control Registers (MCD_REC_[EVEN_ODD] / 0x0201341[01])
+#-- NOTE: set base configuration, proc_setup_bars will enable recovery for
+#--       valid configuration registers based on memory configuration of this chip
+scom 0x0201341(0,1) {
+    bits,                       scom_data;
+    mcd_recov_continuous,       0b1;                                                      #-- enable continuous recovery
+    mcd_recov_pace_delay,       0x040;                                                    #-- 1024 cycle wait between probes
+    mcd_recov_recov_all,        0b0;                                                      #-- disable recover all function
+    mcd_recov_granule_count,    0x3FFFF;                                                  #-- set granule count
+}
+
 #-- MCD Debug Configuration Register (MCD_DBG / 0x02013416)
 scom 0x02013416 {
     bits,                       scom_data;
diff --git a/src/usr/hwpf/hwp/initfiles/p8.mcs.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.mcs.scom.initfile
index 67dee1974..551bd91d1 100644
--- a/src/usr/hwpf/hwp/initfiles/p8.mcs.scom.initfile
+++ b/src/usr/hwpf/hwp/initfiles/p8.mcs.scom.initfile
@@ -1,8 +1,15 @@
-#-- $Id: p8.mcs.scom.initfile,v 1.4 2013/04/08 20:22:28 jmcgill Exp $
+#-- $Id: p8.mcs.scom.initfile,v 1.8 2013/05/02 16:32:15 jmcgill Exp $
 #-- CHANGE HISTORY:
 #--------------------------------------------------------------------------------
 #-- Version:|Author: | Date:  | Comment:
 #-- --------|--------|--------|--------------------------------------------------
+#--     1.70|baysah  |04/26/13|- Disabled MCMODE0Q_ENABLE_FAULT_LINE_FOR_GLOBAL_CHECKSTOP per firmware request for MPIPL.
+#--         |        |        |
+#--     1.60|baysah  |04/25/13|- Fix problem with incorrectly setting mcmode0 bit 1 which is marked as reserved, but its actually used to
+#--         |        |        |- reset MCS channel fail.
+#--         |        |        |
+#--     1.41|baysah  |04/23/13|- Disable MCS bypass for dd1 less than 2.0 for defect HW247907
+#--         |        |        |
 #--     1.30|baysah  |04/04/13|- Set MCI Replay timeout value to 2ms.
 #--         |        |        |- Disable MCS arbiter blocking after checkstop.
 #--         |        |        |
@@ -25,7 +32,7 @@ SyntaxVersion = 1
  scom 0x0000000002011807              {
      bits ,                    scom_data        ;
      0    ,                    0b1              ;              # MCMODE0Q_ENABLE_CMD_BYP_STUTTER
-     1    ,                    0b1              ;              # MCMODE0Q_RESERVED Reserved
+     1    ,                    0b0              ;              # MCMODE0Q_RESERVED Reserved
      2    ,                    0b1              ;              # MCMODE0Q_ENABLE_NS_RD_AO_SFU_FOR_DCBZ
      3    ,                    0b1              ;              # MCMODE0Q_ENABLE_CENTAUR_LOCAL_CHECKSTOP_COMMAND
      4:7  ,                    0xF              ;              # MCMODE0Q_L3_PREFETCH_RETRY_THRESHOLD
@@ -38,7 +45,7 @@ SyntaxVersion = 1
      32:35,                    0x0              ;              # MCMODE0Q_NUMBER_OF_CL_ENTRIES_RESERVED_FOR_HA_ASSIST
      36   ,                    0b1              ;              # MCMODE0Q_MCFGRP_19_IS_HO_BIT
      37   ,                    0b1              ;              # MCMODE0Q_CL_CHANNEL_TIMEOUT_FORCES_CHANNEL_FAIL
-     38   ,                    0b1              ;              # MCMODE0Q_ENABLE_FAULT_LINE_FOR_GLOBAL_CHECKSTOP
+     38   ,                    0b0              ;              # MCMODE0Q_ENABLE_FAULT_LINE_FOR_GLOBAL_CHECKSTOP
      39:43,                    0b00000          ;              # MCMODE0Q_RESERVED_39_43 Reserved
      44:52,                    0b001100010      ;              # MCMODE0Q_ADDRESS_COLLISION_MODES
      53   ,                    0b0              ;              # MCMODE0Q_INCLUDE_CP_IG_IN_CP_WRITE_FULLNESS_GROUP
@@ -56,6 +63,36 @@ SyntaxVersion = 1
 
 
 #--******************************************************************************
+#-- MCS Mode1 Register
+#--******************************************************************************
+ scom 0x0000000002011808              {
+     bits ,                    scom_data           ,     expr             ;
+     0    ,                    0b0                 ,     any              ;    # MCMODE1Q_DISABLE_ADDRESS_SELECT_LFSR_MODE
+     1    ,                    0b0                 ,     any              ;    # MCMODE1Q_NODAL_SCOPE_MCD_VALID
+     2:6  ,                    0b00000             ,     any              ;    # MCMODE1Q_DISABLE_HIGH_PRIORITY
+     7:9  ,                    0b000               , (TGT1.ATTR_CHIP_EC_FEATURE_MCS_ECC_BYPASS_DISABLE == 0x0)     ;    # MCMODE1Q_DISABLE_CRC_ECC_BYPASS
+     7:9  ,                    0b111               , (TGT1.ATTR_CHIP_EC_FEATURE_MCS_ECC_BYPASS_DISABLE != 0x0)     ;    # MCMODE1Q_DISABLE_CRC_ECC_BYPASS
+     10:15,                    0b000000            ,     any              ;    # MCMODE1Q_DISABLE_READ_ALLOCATION_TO_CACHE
+     16   ,                    0b0                 ,     any              ;    # MCMODE1Q_DISABLE_READ_ALLOCATION_TO_CACHE_FOR_FASTPATH_OP
+     17   ,                    0b0                 ,     any              ;    # MCMODE1Q_ENABLE_CRC_ECC_BYPASS_NODAL_SCOPE_ONLY
+     18:26,                    0b000000000         ,     any              ;    # MCMODE1Q_DISABLE_SPEC_OPS_BY_SOURCE_AND_OR_SCOPE
+     27:30,                    0b0000              ,     any              ;    # MCMODE1Q_DISABLE_PREFETCH
+     31   ,                    0b0                 ,     any              ;    # MCMODE1Q_DISABLE_ALL_SPEC_OPS
+     32:48,                    0b00000000000000000 ,     any              ;    # MCMODE1Q_DISABLE_SPEC_OPS
+     49   ,                    0b0                 ,     any              ;    # MCMODE1Q_DISABLE_OP_SOURCE_AND_SCOPE
+     50:51,                    0b00                ,     any              ;    # MCMODE1Q_DISABLE_CACHE_INHIBITED
+     52   ,                    0b0                 ,     any              ;    # MCMODE1Q_DISABLE_ALL_MCS_COMMAND_BYPASS
+     53:59,                    0b0000000           ,     any              ;    # MCMODE1Q_DISABLE_MCS_COMMAND_BYPASS
+     60   ,                    0b0                 ,     any              ;    # MCMODE1Q_ENABLE_DISABLE_SPEC_READ_FOR_NONDMA_GROUP_PUMP_LOCAL_READ
+     61   ,                    0b0                 ,     any              ;    # MCMODE1Q_ENABLE_DISABLE_SPEC_READ_FOR_NONDMA_SYSTEM_PUMP_LOCAL_READ
+     62   ,                    0b0                 ,     any              ;    # MCMODE1Q_DISABLE_FASTPATH_MCS_COMMAND_BYPASS
+     63   ,                    0b0                 ,     any              ;    # MCMODE1Q_DISABLE_FASTPATH_CRC_ECC_BYPASS
+
+ }
+
+
+
+#--******************************************************************************
 #-- MCS Mode2 Register
 #--******************************************************************************
  scom 0x0000000002011809              {
diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_chiplet_scominit.C b/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_chiplet_scominit.C
index 51f913ac7..56f3d04c8 100644
--- a/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_chiplet_scominit.C
+++ b/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_chiplet_scominit.C
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_chiplet_scominit.C,v 1.12 2013/04/08 13:49:08 jmcgill Exp $
+// $Id: proc_chiplet_scominit.C,v 1.13 2013/05/02 16:33:30 jmcgill Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_chiplet_scominit.C,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2012
@@ -204,6 +204,7 @@ fapi::ReturnCode proc_chiplet_scominit(const fapi::Target & i_target)
                 // execute MCS SCOM initfile
                 initfile_targets.clear();
                 initfile_targets.push_back(*i);
+                initfile_targets.push_back(i_target);
                 FAPI_INF("proc_chiplet_scominit: Executing %s on %s",
                          PROC_CHIPLET_SCOMINIT_MCS_IF, i->toEcmdString());
                 FAPI_EXEC_HWP(
diff --git a/src/usr/hwpf/hwp/proc_chip_ec_feature.xml b/src/usr/hwpf/hwp/proc_chip_ec_feature.xml
index 71436fc80..da135602a 100644
--- a/src/usr/hwpf/hwp/proc_chip_ec_feature.xml
+++ b/src/usr/hwpf/hwp/proc_chip_ec_feature.xml
@@ -20,6 +20,8 @@
 <!-- Origin: 30                                                             -->
 <!--                                                                        -->
 <!-- IBM_PROLOG_END_TAG                                                     -->
+<!-- $Id: proc_chip_ec_feature.xml,v 1.14 2013/05/01 22:08:25 jmcgill Exp $ -->
+<!-- Defines the attributes that are based on EC level -->
 <attributes>
   <attribute>
     <id>ATTR_CHIP_EC_FEATURE_HW_BUG_PIBSLVRESET</id>
@@ -154,11 +156,12 @@
   </attribute>
   <attribute>
     <id>ATTR_CHIP_EC_FEATURE_RECAL_DFE_ENABLE</id>
-    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <targetType>TARGET_TYPE_PROC_CHIP,TARGET_TYPE_MEMBUF_CHIP</targetType>
     <description>
       True if:
         Murano EC 0x20 or greater
         Venice EC 0x10 or greater
+        Centaur EC 0x20 or greater
     </description>
     <chipEcFeature>
       <chip>
@@ -175,15 +178,23 @@
           <test>GREATER_THAN_OR_EQUAL</test>
         </ec>
       </chip>
+      <chip>
+        <name>ENUM_ATTR_NAME_CENTAUR</name>
+        <ec>
+          <value>0x20</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
     </chipEcFeature>
   </attribute>
   <attribute>
     <id>ATTR_CHIP_EC_FEATURE_RECAL_DDC_ENABLE</id>
-    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <targetType>TARGET_TYPE_PROC_CHIP,TARGET_TYPE_MEMBUF_CHIP</targetType>
     <description>
       True if:
         Murano EC 0x20 or greater
         Venice EC 0x10 or greater
+        Centaur EC 0x20 or greater 
     </description>
     <chipEcFeature>
       <chip>
@@ -200,15 +211,23 @@
           <test>GREATER_THAN_OR_EQUAL</test>
         </ec>
       </chip>
+      <chip>
+        <name>ENUM_ATTR_NAME_CENTAUR</name>
+        <ec>
+          <value>0x20</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
     </chipEcFeature>
   </attribute>
   <attribute>
     <id>ATTR_CHIP_EC_FEATURE_RECAL_CTLE_ENABLE</id>
-    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <targetType>TARGET_TYPE_PROC_CHIP,TARGET_TYPE_MEMBUF_CHIP</targetType>
     <description>
       True if:
         Murano EC 0x20 or greater
         Venice EC 0x10 or greater
+        Centaur EC 0x20 or greater
     </description>
     <chipEcFeature>
       <chip>
@@ -225,6 +244,13 @@
           <test>GREATER_THAN_OR_EQUAL</test>
         </ec>
       </chip>
+      <chip>
+        <name>ENUM_ATTR_NAME_CENTAUR</name>
+        <ec>
+          <value>0x20</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
     </chipEcFeature>
   </attribute>
   <attribute>
@@ -261,4 +287,54 @@
       </chip>
     </chipEcFeature>
   </attribute>
+  <attribute>
+    <id>ATTR_CHIP_EC_FEATURE_ADU_PBINIT_LAUNCH_BUG</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      True if: 
+        Murano EC less than 0x20
+        Venice EC less than 0x20
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_MURANO</name>
+        <ec>
+          <value>0x20</value>
+          <test>LESS_THAN</test>
+        </ec>
+      </chip>
+      <chip>
+        <name>ENUM_ATTR_NAME_VENICE</name>
+        <ec>
+          <value>0x20</value>
+          <test>LESS_THAN</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+  <attribute>
+    <id>ATTR_CHIP_EC_FEATURE_MCS_ECC_BYPASS_DISABLE</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      True if:
+        Murano EC less than 0x20
+        Venice EC less than 0x20
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_MURANO</name>
+        <ec>
+          <value>0x20</value>
+          <test>LESS_THAN</test>
+        </ec>
+      </chip>
+      <chip>
+        <name>ENUM_ATTR_NAME_VENICE</name>
+        <ec>
+          <value>0x20</value>
+          <test>LESS_THAN</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
 </attributes>
diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_revert_sbe_mcs_setup/proc_revert_sbe_mcs_setup.C b/src/usr/hwpf/hwp/slave_sbe/proc_revert_sbe_mcs_setup/proc_revert_sbe_mcs_setup.C
index a981d8c5a..36db42962 100644
--- a/src/usr/hwpf/hwp/slave_sbe/proc_revert_sbe_mcs_setup/proc_revert_sbe_mcs_setup.C
+++ b/src/usr/hwpf/hwp/slave_sbe/proc_revert_sbe_mcs_setup/proc_revert_sbe_mcs_setup.C
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_revert_sbe_mcs_setup.C,v 1.6 2013/01/20 15:55:42 jmcgill Exp $
+// $Id: proc_revert_sbe_mcs_setup.C,v 1.7 2013/04/27 17:23:41 jmcgill Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_revert_sbe_mcs_setup.C,v $
 //------------------------------------------------------------------------------
 // *|
@@ -140,7 +140,7 @@ fapi::ReturnCode proc_revert_sbe_mcs_setup_reset_mcfgp(
 
 
 //------------------------------------------------------------------------------
-// function: set MCI FIR Mask channel timeout bit, to restore register flush
+// function: set MCI FIR Mask channel timeout bits, to restore register flush
 //           state
 // parameters: i_target       => chip target
 //             i_mcs_unit_num => chip unit number
@@ -162,6 +162,8 @@ fapi::ReturnCode proc_revert_sbe_mcs_setup_reset_mcifirmask(
     {
         // set fields manipulated by SBE (to restore logic flush state)
         rc_ecmd |= mcifirmask_or_data.setBit(
+            MCIFIR_CL_TIMEOUT_BIT);
+       rc_ecmd |= mcifirmask_or_data.setBit(
             MCIFIR_CL_TIMEOUT_DUE_TO_CHANNEL_BIT);
 
         // check buffer manipulation return code
diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_revert_sbe_mcs_setup/proc_revert_sbe_mcs_setup.H b/src/usr/hwpf/hwp/slave_sbe/proc_revert_sbe_mcs_setup/proc_revert_sbe_mcs_setup.H
index 90719e5ba..0dca948db 100644
--- a/src/usr/hwpf/hwp/slave_sbe/proc_revert_sbe_mcs_setup/proc_revert_sbe_mcs_setup.H
+++ b/src/usr/hwpf/hwp/slave_sbe/proc_revert_sbe_mcs_setup/proc_revert_sbe_mcs_setup.H
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_revert_sbe_mcs_setup.H,v 1.3 2013/01/20 15:55:45 jmcgill Exp $
+// $Id: proc_revert_sbe_mcs_setup.H,v 1.4 2013/04/27 17:23:43 jmcgill Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_revert_sbe_mcs_setup.H,v $
 //------------------------------------------------------------------------------
 // *|
@@ -73,7 +73,8 @@ const uint32_t MCFGP_GROUP_BASE_ADDR_START_BIT = 26;
 const uint32_t MCFGP_GROUP_BASE_ADDR_END_BIT = 43;
 
 // MCIFIR register constants
-const uint32_t MCIFIR_CL_TIMEOUT_DUE_TO_CHANNEL_BIT = 28;
+const uint32_t MCIFIR_CL_TIMEOUT_BIT = 27;
+const uint32_t MCIFIR_CL_TIMEOUT_DUE_TO_CHANNEL_BIT = 40;
 
 
 //------------------------------------------------------------------------------