INITPROC: Hostboot - SW228674 - C4 mapping & ddr4 supports

Change-Id: I3c7885aee2d14aff642488ff61afa56367a48eda
CQ:SW228674
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/6710
Tested-by: Jenkins Server
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

10 files changed, 908 insertions, 29 deletions

diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_ddr4_funcs.H b/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_ddr4_funcs.H
new file mode 100644
index 000000000..2201485ee
--- /dev/null
+++ b/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_ddr4_funcs.H
@@ -0,0 +1,71 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/usr/hwpf/hwp/dram_training/mss_draminit/mss_ddr4_funcs.H $ */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* COPYRIGHT International Business Machines Corp. 2013                   */
+/*                                                                        */
+/* p1                                                                     */
+/*                                                                        */
+/* Object Code Only (OCO) source materials                                */
+/* Licensed Internal Code Source Materials                                */
+/* IBM HostBoot Licensed Internal Code                                    */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* Origin: 30                                                             */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id: mss_ddr4_funcs.H,v 1.3 2013/10/10 20:28:25 bellows Exp $
+
+//------------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2013
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//------------------------------------------------------------------------------
+// *! TITLE : mss_ddr4_funcs.H
+// *! DESCRIPTION : Tools for DDR4 DIMMs centaur procedures
+// *! OWNER NAME : jdsloat@us.ibm.com
+// *! BACKUP NAME : sglancy@us.ibm.com
+// #! ADDITIONAL COMMENTS :
+//
+
+//------------------------------------------------------------------------------
+// Don't forget to create CVS comments when you check in your changes!
+//------------------------------------------------------------------------------
+// CHANGE HISTORY:
+//------------------------------------------------------------------------------
+// Version:|  Author: |  Date:  | Comment:
+//---------|----------|---------|-----------------------------------------------
+//         |          |         |
+//  1.3    | 10/10/13 | bellows | Added required CVS Id comment
+//  1.2    | 10/09/13 | jdsloat | Fixed argument list in function call
+//  1.1    | 10/04/13 | jdsloat | First revision
+
+#ifndef _MSS_DDR4_FUNCS_H
+#define _MSS_DDR4_FUNCS_H
+
+
+//----------------------------------------------------------------------
+// DDR4 FUNCS
+//----------------------------------------------------------------------
+
+
+//--------------------------------------------------------------
+// mss_mrs_load_ddr4
+// Set MRS1 settings for Rank 0 and Rank 1
+// Target = centaur.mba
+//--------------------------------------------------------------
+fapi::ReturnCode mss_mrs_load_ddr4( fapi::Target& i_target,
+                                      uint32_t i_port_number,
+                                      uint32_t& io_ccs_inst_cnt);
+
+
+
+#endif /* _MSS_DDR4_FUNCS_H */
+
+
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.C b/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.C
index 741c63394..4dd219b8d 100755
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.C
+++ b/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.C
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_draminit.C,v 1.56 2013/09/16 13:56:28 bellows Exp $
+// $Id: mss_draminit.C,v 1.58 2013/10/15 14:16:33 jdsloat Exp $
 //------------------------------------------------------------------------------
 // Don't forget to create CVS comments when you check in your changes!
 //------------------------------------------------------------------------------
@@ -28,6 +28,8 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|-----------------------------------------------
+//  1.58   | jdsloat  | 10/15/13| Added rc checks in ddr4 shadow regs check per review request
+//  1.57   | jdsloat  | 10/09/13| Added mrs_load_ddr4 with defines for ddr4 usage, added shadow regs, removed complicated flow
 //  1.56   | bellows  | 09/16/13| Hostboot compile fix
 //  1.55   | kcook    | 09/13/13| Updated define FAPI_LRDIMM token.
 //  1.54   | kcook    | 08/27/13| Removed LRDIMM support to mss_lrdimm_funcs.C. 
@@ -109,6 +111,7 @@
 #include "cen_scom_addresses.H"
 #include <mss_unmask_errors.H>
 #include <mss_lrdimm_funcs.H>
+#include <mss_ddr4_funcs.H>
 
 
 
@@ -134,6 +137,20 @@ ReturnCode mss_lrdimm_mrs_load(Target& i_target, uint32_t i_port_number, uint32_
 }
 #endif
 
+ #ifndef FAPI_DDR4
+using namespace fapi;
+fapi::ReturnCode mss_mrs_load_ddr4(Target& i_target, uint32_t port_number, uint32_t& ccs_inst_cnt)
+{
+   ReturnCode rc;
+
+   FAPI_ERR("Invalid exec of mrs_load_ddr4  %s!", i_target.toEcmdString());
+   FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR);
+   return rc;
+
+}
+
+#endif
+
 //----------------------------------------------------------------------
 //  Constants
 //----------------------------------------------------------------------
@@ -143,8 +160,11 @@ const uint8_t MAX_NUM_RANK_PAIR = 4;
 const uint8_t MAX_NUM_LR_RANKS = 8;
 const uint8_t MRS0_BA = 0;
 const uint8_t MRS1_BA = 1;
-const uint8_t MRS2_BA = 2;
+const uint8_t MRS2_BA = 2;  
 const uint8_t MRS3_BA = 3;
+const uint8_t MRS4_BA = 4;
+const uint8_t MRS5_BA = 5;
+const uint8_t MRS6_BA = 6;
 const uint8_t INVALID = 255;
 
 
@@ -198,14 +218,20 @@ ReturnCode mss_draminit_cloned(Target& i_target)
     uint8_t rank_pair_group = 0;
     uint8_t bit_position = 0;
     ecmdDataBufferBase data_buffer_64(64);
-    ecmdDataBufferBase mrs0(16);
+    ecmdDataBufferBase mrs0(16); 
     ecmdDataBufferBase mrs1(16);
     ecmdDataBufferBase mrs2(16);
     ecmdDataBufferBase mrs3(16);
+    ecmdDataBufferBase mrs4(16);
+    ecmdDataBufferBase mrs5(16);
+    ecmdDataBufferBase mrs6(16);
     uint16_t MRS0 = 0;
     uint16_t MRS1 = 0;
     uint16_t MRS2 = 0;
     uint16_t MRS3 = 0;
+    uint16_t MRS4 = 0;
+    uint16_t MRS5 = 0;
+    uint16_t MRS6 = 0;
     uint8_t num_drops_per_port;
     uint8_t primary_ranks_array[4][2]; //primary_ranks_array[group][port]
     uint8_t secondary_ranks_array[4][2]; //secondary_ranks_array[group][port]
@@ -441,15 +467,12 @@ ReturnCode mss_draminit_cloned(Target& i_target)
 	}
     }
 
-    //if ((!(dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM)) && (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR3))
-    if (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR3)
-    {
         //Commented because Master Attention Reg Check not written yet.
         //Master Attntion Reg Check... Need to add appropriate call below.
         //MASTER_ATTENTION_REG_CHECK();
 
         // Step one: Deassert Force_mclk_low signal
-      // this action needs to be done in ddr_phy_reset so that the plls can actually lock
+        // this action needs to be done in ddr_phy_reset so that the plls can actually lock
 
         // Step two: Assert Resetn signal, Begin driving mem clks
         rc = mss_assert_resetn_drive_mem_clks(i_target);
@@ -505,13 +528,26 @@ ReturnCode mss_draminit_cloned(Target& i_target)
         // Ports 0-1
         for ( port_number = 0; port_number < MAX_NUM_PORTS; port_number++)
         {
+
             // Step four: Load MRS Setting
-            rc = mss_mrs_load(i_target, port_number, ccs_inst_cnt);
-            if(rc)
-            {
-                FAPI_ERR(" mrs_load Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
-                return rc;
-            }
+	    if (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR3)
+	    {
+		    rc = mss_mrs_load(i_target, port_number, ccs_inst_cnt);
+		    if(rc)
+		    {
+		        FAPI_ERR(" mrs_load Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
+		        return rc;
+		    }
+	    }
+	    else
+	    {
+		    rc = mss_mrs_load_ddr4(i_target, port_number, ccs_inst_cnt);
+		    if(rc)
+		    {
+		        FAPI_ERR(" mrs_load_ddr4 Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
+		        return rc;
+		    }
+	    }
 
         }
 
@@ -551,7 +587,8 @@ ReturnCode mss_draminit_cloned(Target& i_target)
 	    if((primary_ranks_array[rank_pair_group][0] != INVALID) || (primary_ranks_array[rank_pair_group][1] != INVALID))
 	    {
 
-		if (port_number == 0){
+		if (port_number == 0)
+		{
 	    		// Get contents of MRS Shadow Regs and Print it to output
 			if (rank_pair_group == 0)
 			{
@@ -583,6 +620,30 @@ ReturnCode mss_draminit_cloned(Target& i_target)
 		    		rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0);
 		    		FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 3 RP %d VALUE: 0x%04X",  i_target.toEcmdString(), port_number, rank_pair_group, MRS3);
 
+				if (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4)
+				{
+			    		rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_SEC_RP0_P0_0x8000C0200301143F, data_buffer_64);
+                                	if(rc) return rc;
+			    		rc_num = rc_num | data_buffer_64.reverse();
+			    		rc_num = rc_num | mrs4.insert(data_buffer_64, 0, 16);
+			    		rc_num = rc_num | mrs4.extractPreserve(&MRS4, 0, 16, 0);
+			    		FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 4 RP %d VALUE: 0x%04X",  i_target.toEcmdString(),  port_number, rank_pair_group, MRS4);
+
+			    		rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_SEC_RP0_P0_0x8000C0210301143F, data_buffer_64);
+                                	if(rc) return rc;
+			    		rc_num = rc_num | data_buffer_64.reverse();
+			    		rc_num = rc_num | mrs5.insert(data_buffer_64, 0, 16);
+			    		rc_num = rc_num | mrs5.extractPreserve(&MRS5, 0, 16, 0);
+			    		FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 5 RP %d VALUE: 0x%04X",  i_target.toEcmdString(),  port_number, rank_pair_group, MRS5);
+
+			    		rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_SEC_RP0_P0_0x8000C0220301143F, data_buffer_64);
+                                	if(rc) return rc;
+			    		rc_num = rc_num | data_buffer_64.reverse();
+			    		rc_num = rc_num | mrs6.insert(data_buffer_64, 0, 16);
+			    		rc_num = rc_num | mrs6.extractPreserve(&MRS6, 0, 16, 0);
+			    		FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 6 RP %d VALUE: 0x%04X",  i_target.toEcmdString(),  port_number, rank_pair_group, MRS6);
+				}
+
 			}
 			else if (rank_pair_group == 1)
 			{
@@ -614,6 +675,30 @@ ReturnCode mss_draminit_cloned(Target& i_target)
 		    		rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0);
 		    		FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 3 RP %d VALUE: 0x%04X",  i_target.toEcmdString(), port_number, rank_pair_group, MRS3);
 
+				if (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4)
+				{
+			    		rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_SEC_RP1_P0_0x8000C1200301143F, data_buffer_64);
+                                	if(rc) return rc;
+			    		rc_num = rc_num | data_buffer_64.reverse();
+			    		rc_num = rc_num | mrs4.insert(data_buffer_64, 0, 16);
+			    		rc_num = rc_num | mrs4.extractPreserve(&MRS4, 0, 16, 0);
+			    		FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 4 RP %d VALUE: 0x%04X",  i_target.toEcmdString(), port_number, rank_pair_group, MRS4);
+
+			    		rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_SEC_RP1_P0_0x8000C1210301143F, data_buffer_64);
+                                	if(rc) return rc;
+			    		rc_num = rc_num | data_buffer_64.reverse();
+			    		rc_num = rc_num | mrs5.insert(data_buffer_64, 0, 16);
+			    		rc_num = rc_num | mrs5.extractPreserve(&MRS5, 0, 16, 0);
+			    		FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 5 RP %d VALUE: 0x%04X",  i_target.toEcmdString(), port_number, rank_pair_group, MRS5);
+
+			    		rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_SEC_RP1_P0_0x8000C1220301143F, data_buffer_64);
+                                	if(rc) return rc;
+			    		rc_num = rc_num | data_buffer_64.reverse();
+			    		rc_num = rc_num | mrs6.insert(data_buffer_64, 0, 16);
+			    		rc_num = rc_num | mrs6.extractPreserve(&MRS6, 0, 16, 0);
+			    		FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 6 RP %d VALUE: 0x%04X",  i_target.toEcmdString(), port_number, rank_pair_group, MRS6);
+				}
+
 			}
 			else if (rank_pair_group == 2)
 			{
@@ -644,6 +729,31 @@ ReturnCode mss_draminit_cloned(Target& i_target)
 		   	       rc_num = rc_num | mrs3.insert(data_buffer_64, 0, 16);
 		   	       rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0);
 		   	       FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 3 RP %d VALUE: 0x%04X",  i_target.toEcmdString(), port_number, rank_pair_group, MRS3);
+
+				if (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4)
+				{
+			    		rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_SEC_RP2_P0_0x8000C2200301143F, data_buffer_64);
+                                	if(rc) return rc;
+			    		rc_num = rc_num | data_buffer_64.reverse();
+			    		rc_num = rc_num | mrs4.insert(data_buffer_64, 0, 16);
+			    		rc_num = rc_num | mrs4.extractPreserve(&MRS4, 0, 16, 0);
+			    		FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 4 RP %d VALUE: 0x%04X",  i_target.toEcmdString(), port_number, rank_pair_group, MRS4);
+
+			    		rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_SEC_RP2_P0_0x8000C2210301143F, data_buffer_64);
+                                	if(rc) return rc;
+			    		rc_num = rc_num | data_buffer_64.reverse();
+			    		rc_num = rc_num | mrs5.insert(data_buffer_64, 0, 16);
+			    		rc_num = rc_num | mrs5.extractPreserve(&MRS5, 0, 16, 0);
+			    		FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 5 RP %d VALUE: 0x%04X",  i_target.toEcmdString(), port_number, rank_pair_group, MRS5);
+
+			    		rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_SEC_RP2_P0_0x8000C2220301143F, data_buffer_64);
+                                	if(rc) return rc;
+			    		rc_num = rc_num | data_buffer_64.reverse();
+			    		rc_num = rc_num | mrs6.insert(data_buffer_64, 0, 16);
+			    		rc_num = rc_num | mrs6.extractPreserve(&MRS6, 0, 16, 0);
+			    		FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 6 RP %d VALUE: 0x%04X",  i_target.toEcmdString(), port_number, rank_pair_group, MRS6);
+				}
+
 			}
 			else if (rank_pair_group == 3)
 			{
@@ -674,6 +784,31 @@ ReturnCode mss_draminit_cloned(Target& i_target)
 		   	       rc_num = rc_num | mrs3.insert(data_buffer_64, 0, 16);
 		   	       rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0);
 		   	       FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 3 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS3);
+
+				if (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4)
+				{
+			    		rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_SEC_RP3_P0_0x8000C3200301143F, data_buffer_64);
+                                	if(rc) return rc;
+			    		rc_num = rc_num | data_buffer_64.reverse();
+			    		rc_num = rc_num | mrs4.insert(data_buffer_64, 0, 16);
+			    		rc_num = rc_num | mrs4.extractPreserve(&MRS4, 0, 16, 0);
+			    		FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 4 RP %d VALUE: 0x%04X",  i_target.toEcmdString(), port_number, rank_pair_group, MRS4);
+
+			    		rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_SEC_RP3_P0_0x8000C3210301143F, data_buffer_64);
+                                	if(rc) return rc;
+			    		rc_num = rc_num | data_buffer_64.reverse();
+			    		rc_num = rc_num | mrs5.insert(data_buffer_64, 0, 16);
+			    		rc_num = rc_num | mrs5.extractPreserve(&MRS5, 0, 16, 0);
+			    		FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 5 RP %d VALUE: 0x%04X",  i_target.toEcmdString(), port_number, rank_pair_group, MRS5);
+
+			    		rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_SEC_RP3_P0_0x8000C3220301143F, data_buffer_64);
+                                	if(rc) return rc;
+			    		rc_num = rc_num | data_buffer_64.reverse();
+			    		rc_num = rc_num | mrs6.insert(data_buffer_64, 0, 16);
+			    		rc_num = rc_num | mrs6.extractPreserve(&MRS6, 0, 16, 0);
+			    		FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 6 RP %d VALUE: 0x%04X",  i_target.toEcmdString(), port_number, rank_pair_group, MRS6);
+				}
+
 			}
 		}
 		else if (port_number == 1)
@@ -708,6 +843,30 @@ ReturnCode mss_draminit_cloned(Target& i_target)
 		    		rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0);
 		    		FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 3 RP %d VALUE: 0x%04X",  i_target.toEcmdString(), port_number, rank_pair_group, MRS3);
 
+				if (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4)
+				{
+			    		rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_SEC_RP0_P1_0x8001C0200301143F, data_buffer_64);
+                                	if(rc) return rc;
+			    		rc_num = rc_num | data_buffer_64.reverse();
+			    		rc_num = rc_num | mrs4.insert(data_buffer_64, 0, 16);
+			    		rc_num = rc_num | mrs4.extractPreserve(&MRS4, 0, 16, 0);
+			    		FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 4 RP %d VALUE: 0x%04X",  i_target.toEcmdString(), port_number, rank_pair_group, MRS4);
+
+			    		rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_SEC_RP0_P1_0x8001C0210301143F, data_buffer_64);
+                                	if(rc) return rc;
+			    		rc_num = rc_num | data_buffer_64.reverse();
+			    		rc_num = rc_num | mrs5.insert(data_buffer_64, 0, 16);
+			    		rc_num = rc_num | mrs5.extractPreserve(&MRS5, 0, 16, 0);
+			    		FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 5 RP %d VALUE: 0x%04X",  i_target.toEcmdString(), port_number, rank_pair_group, MRS5);
+
+			    		rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_SEC_RP0_P1_0x8001C0220301143F, data_buffer_64);
+                                	if(rc) return rc;
+			    		rc_num = rc_num | data_buffer_64.reverse();
+			    		rc_num = rc_num | mrs6.insert(data_buffer_64, 0, 16);
+			    		rc_num = rc_num | mrs6.extractPreserve(&MRS6, 0, 16, 0);
+			    		FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 6 RP %d VALUE: 0x%04X",  i_target.toEcmdString(), port_number, rank_pair_group, MRS6);
+				}
+
 			}
 			else if (rank_pair_group == 1)
 			{
@@ -739,6 +898,31 @@ ReturnCode mss_draminit_cloned(Target& i_target)
 		    		rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0);
 		    		FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 3 RP %d VALUE: 0x%04X",  i_target.toEcmdString(), port_number, rank_pair_group, MRS3);
 
+				if (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4)
+				{
+			    		rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_SEC_RP1_P1_0x8001C1200301143F, data_buffer_64);
+                                	if(rc) return rc;
+			    		rc_num = rc_num | data_buffer_64.reverse();
+			    		rc_num = rc_num | mrs4.insert(data_buffer_64, 0, 16);
+			    		rc_num = rc_num | mrs4.extractPreserve(&MRS4, 0, 16, 0);
+			    		FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 4 RP %d VALUE: 0x%04X",  i_target.toEcmdString(), port_number, rank_pair_group, MRS4);
+
+			    		rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_SEC_RP1_P1_0x8001C1210301143F, data_buffer_64);
+                                	if(rc) return rc;
+			    		rc_num = rc_num | data_buffer_64.reverse();
+			    		rc_num = rc_num | mrs5.insert(data_buffer_64, 0, 16);
+			    		rc_num = rc_num | mrs5.extractPreserve(&MRS5, 0, 16, 0);
+			    		FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 5 RP %d VALUE: 0x%04X",  i_target.toEcmdString(), port_number, rank_pair_group, MRS5);
+
+			    		rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_SEC_RP1_P1_0x8001C1220301143F, data_buffer_64);
+                                	if(rc) return rc;
+			    		rc_num = rc_num | data_buffer_64.reverse();
+			    		rc_num = rc_num | mrs6.insert(data_buffer_64, 0, 16);
+			    		rc_num = rc_num | mrs6.extractPreserve(&MRS6, 0, 16, 0);
+			    		FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 6 RP %d VALUE: 0x%04X",  i_target.toEcmdString(), port_number, rank_pair_group, MRS6);
+
+				}
+
 			}
 			else if (rank_pair_group == 2)
 		        {
@@ -769,6 +953,31 @@ ReturnCode mss_draminit_cloned(Target& i_target)
 		   	       rc_num = rc_num | mrs3.insert(data_buffer_64, 0, 16);
 		   	       rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0);
 		   	       FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 3 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS3);
+
+				if (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4)
+				{
+			    		rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_SEC_RP2_P1_0x8001C2200301143F, data_buffer_64);
+                                	if(rc) return rc;
+			    		rc_num = rc_num | data_buffer_64.reverse();
+			    		rc_num = rc_num | mrs4.insert(data_buffer_64, 0, 16);
+			    		rc_num = rc_num | mrs4.extractPreserve(&MRS4, 0, 16, 0);
+			    		FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 4 RP %d VALUE: 0x%04X",  i_target.toEcmdString(), port_number, rank_pair_group, MRS4);
+
+			    		rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_SEC_RP2_P1_0x8001C2210301143F, data_buffer_64);
+                                	if(rc) return rc;
+			    		rc_num = rc_num | data_buffer_64.reverse();
+			    		rc_num = rc_num | mrs5.insert(data_buffer_64, 0, 16);
+			    		rc_num = rc_num | mrs5.extractPreserve(&MRS5, 0, 16, 0);
+			    		FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 5 RP %d VALUE: 0x%04X",  i_target.toEcmdString(), port_number, rank_pair_group, MRS5);
+
+			    		rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_SEC_RP2_P1_0x8001C2220301143F, data_buffer_64);
+                                	if(rc) return rc;
+			    		rc_num = rc_num | data_buffer_64.reverse();
+			    		rc_num = rc_num | mrs6.insert(data_buffer_64, 0, 16);
+			    		rc_num = rc_num | mrs6.extractPreserve(&MRS6, 0, 16, 0);
+			    		FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 6 RP %d VALUE: 0x%04X",  i_target.toEcmdString(), port_number, rank_pair_group, MRS6);
+				}
+
 			}
 			else if (rank_pair_group == 3)
 			{
@@ -799,6 +1008,31 @@ ReturnCode mss_draminit_cloned(Target& i_target)
 		   	       rc_num = rc_num | mrs3.insert(data_buffer_64, 0, 16);
 		   	       rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0);
 		   	       FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 3 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS3);
+
+				if (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4)
+				{
+			    		rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_SEC_RP3_P1_0x8001C3200301143F, data_buffer_64);
+                                	if(rc) return rc;
+			    		rc_num = rc_num | data_buffer_64.reverse();
+			    		rc_num = rc_num | mrs4.insert(data_buffer_64, 0, 16);
+			    		rc_num = rc_num | mrs4.extractPreserve(&MRS4, 0, 16, 0);
+			    		FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 4 RP %d VALUE: 0x%04X",  i_target.toEcmdString(), port_number, rank_pair_group, MRS4);
+
+			    		rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_SEC_RP3_P1_0x8001C3210301143F, data_buffer_64);
+                                	if(rc) return rc;
+			    		rc_num = rc_num | data_buffer_64.reverse();
+			    		rc_num = rc_num | mrs5.insert(data_buffer_64, 0, 16);
+			    		rc_num = rc_num | mrs5.extractPreserve(&MRS5, 0, 16, 0);
+			    		FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 5 RP %d VALUE: 0x%04X",  i_target.toEcmdString(), port_number, rank_pair_group, MRS5);
+
+			    		rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_SEC_RP3_P1_0x8001C3220301143F, data_buffer_64);
+                                	if(rc) return rc;
+			    		rc_num = rc_num | data_buffer_64.reverse();
+			    		rc_num = rc_num | mrs6.insert(data_buffer_64, 0, 16);
+			    		rc_num = rc_num | mrs6.extractPreserve(&MRS6, 0, 16, 0);
+			    		FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 6 RP %d VALUE: 0x%04X",  i_target.toEcmdString(), port_number, rank_pair_group, MRS6);
+				}
+
 			}
 
 		}
@@ -826,14 +1060,6 @@ ReturnCode mss_draminit_cloned(Target& i_target)
         //Master Attntion Reg Check... Need to add appropriate call below.
         //MASTER_ATTENTION_REG_CHECK();
 
-    }
-    else
-    {
-        FAPI_INF( "++ COMPLICATED FLOW GOES HERE ++");
-        // TODO:
-        // This is Commented out because COMPLICATED_FLOW_CONTROL has not been written yet.
-        //COMPLICATED_FLOW_CONTROL(); //--- currently dummy function
-    }
     return rc;
 }
 
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_access_delay_reg.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_access_delay_reg.C
index df79c60c5..e7b4ab1bd 100644
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_access_delay_reg.C
+++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_access_delay_reg.C
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_access_delay_reg.C,v 1.17 2013/07/18 06:22:49 sauchadh Exp $
+// $Id: mss_access_delay_reg.C,v 1.19 2013/10/09 11:28:41 sasethur Exp $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
 // *! All Rights Reserved -- Property of IBM
@@ -53,6 +53,7 @@
 //   1.15  | sauchadh |20-may-13| Fixed swizzle issue in DQSCLK phase rotators
 //   1.16  | sauchadh |12-jun-13| ADDED	 CAC registers for read dqs
 //   1.17  | sauchadh |18-Jul-13| Added data bit disable registers
+//   1.19  | abhijsau |9-Oct-13 | Added mss_c4_phy() function 
 
 
 //----------------------------------------------------------------------
@@ -2685,7 +2686,503 @@ fapi::ReturnCode mss_getrankpair(const fapi::Target & i_target_mba,uint8_t i_por
 } //end of mss_getrankpair
     
 
-
+//******************************************************************************
+//Function name: mss_c4_phy()
+//Description:This function returns address,start bit and bit length for RD_DQ, WR_DQ, RD_DQS, WR_DQS
+//Input  : Target MBA=i_target_mba, i_port_u8=0 or 1, i_rank_pair=0 or 1 or 2 or 3, i_input_type_e=RD_DQ or RD_DQS or WR_DQ or WR_DQS,i_input_index_u8=0-79/0-71/0-8/0-19 , i_verbose-extra print statements  
+//Output : out (address,start bit and bit length)
+//******************************************************************************    
+        
+fapi::ReturnCode mss_c4_phy(const fapi::Target & i_target_mba,uint8_t i_port, uint8_t i_rank_pair,input_type_t i_input_type_e,uint8_t &i_input_index,uint8_t i_verbose,uint8_t &phy_lane,uint8_t &phy_block,uint8_t flag)
+{    
+   fapi::ReturnCode rc; 
+   const uint8_t l_dqmax=80;
+   const uint8_t l_dqsmax=20;
+   //const uint8_t l_blkmax=5;
+   const uint8_t lane_dq_p0[l_dqmax]={4,6,5,7,2,1,3,0,13,15,12,14,8,9,11,10,13,15,12,14,9,8,11,10,13,15,12,14,11,9,10,8,11,8,9,10,12,13,14,15,7,6,5,4,1,3,2,0,5,6,4,7,3,1,2,0,7,4,5,6,2,0,3,1,3,0,1,2,6,5,4,7,11,8,9,10,15,13,12,14}; 
+   const uint8_t lane_dq_p1[l_dqmax]={9,11,8,10,13,14,15,12,10,8,11,9,12,13,14,15,1,0,2,3,4,5,6,7,9,11,10,8,15,12,13,14,5,7,6,4,1,0,2,3,0,2,1,3,5,4,6,7,0,2,3,1,4,5,6,7,12,15,13,14,11,8,10,9,5,7,4,6,3,2,0,1,14,12,15,13,9,8,11,10}; 
+   const uint8_t lane_dq_p2[l_dqmax]={13,15,12,14,11,9,10,8,13,12,14,15,10,9,11,8,5,6,7,4,2,3,0,1,10,9,8,11,13,12,15,14,15,12,13,14,11,10,9,8,7,6,4,5,1,0,3,2,0,2,1,3,5,6,4,7,5,7,6,4,1,0,2,3,1,2,3,0,7,6,5,4,9,10,8,11,12,15,14,13};
+   const uint8_t lane_dq_p3[l_dqmax]={4,5,6,7,0,1,3,2,12,13,15,14,8,9,10,11,10,8,11,9,12,13,15,14,3,0,1,2,4,6,7,5,9,10,11,8,14,13,15,12,7,5,6,4,3,1,2,0,5,6,7,4,1,2,3,0,14,12,15,13,8,10,9,11,0,3,2,1,6,5,7,4,10,11,9,8,12,13,15,14};
+   const uint8_t dqs_dq_lane_p0[l_dqsmax]={4,0,12,8,12,8,12,8,8,12,4,0,4,0,4,0,0,4,8,12};
+   const uint8_t dqs_dq_lane_p1[l_dqsmax]={8,12,8,12,0,4,8,12,4,0,0,4,0,4,12,8,4,0,12,8};
+   const uint8_t dqs_dq_lane_p2[l_dqsmax]={12,8,12,8,4,0,8,12,12,8,4,0,0,4,4,0,0,4,8,12};
+   const uint8_t dqs_dq_lane_p3[l_dqsmax]={4,0,12,8,8,12,0,4,8,12,4,0,4,0,12,8,0,4,8,12};
+   const uint8_t block_p1[l_dqmax]={0,0,0,0,0,0,0,0,3,3,3,3,3,3,3,3,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,2,2,2,2,2,2,2,2,3,3,3,3,3,3,3,3,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,1,1,1,1,1,1,1,1,2,2,2,2,2,2,2,2};
+   const uint8_t block_p0[l_dqmax]={2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,0,0,0,0,0,0,0,0,3,3,3,3,3,3,3,3,4,4,4,4,4,4,4,4,3,3,3,3,3,3,3,3,4,4,4,4,4,4,4,4,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1};
+   const uint8_t block_p2[l_dqmax]={1,1,1,1,1,1,1,1,3,3,3,3,3,3,3,3,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,3,3,3,3,3,3,3,3,4,4,4,4,4,4,4,4,1,1,1,1,1,1,1,1,4,4,4,4,4,4,4,4};
+   const uint8_t block_p3[l_dqmax]={2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1};
+   const uint8_t block_dqs_p0[l_dqsmax]={2,2,2,2,0,0,3,3,4,4,3,3,4,4,1,1,0,0,1,1};
+   const uint8_t block_dqs_p1[l_dqsmax]={0,0,3,3,0,0,1,1,2,2,3,3,4,4,4,4,1,1,2,2};
+   const uint8_t block_dqs_p2[l_dqsmax]={1,1,3,3,0,0,0,0,2,2,2,2,3,3,4,4,1,1,4,4};
+   const uint8_t block_dqs_p3[l_dqsmax]={2,2,2,2,0,0,0,0,3,3,3,3,4,4,4,4,1,1,1,1};
+   uint8_t l_mbapos = 0;
+   uint8_t l_dram_width=0;
+   uint8_t l_lane=0;
+   uint8_t l_block=0;
+   uint8_t lane_dqs[4];
+   uint8_t l_index=0;
+   uint8_t l_dq=0;
+   uint8_t l_phy_dq=0;
+   //uint8_t l_phy_block=0;
+   uint64_t l_scom_address_64=0x0ull;
+   uint8_t l_start_bit=0;
+   uint8_t l_len=0;
+   ip_type_t l_input_type;
+   ecmdDataBufferBase data_buffer_64(64);
+   uint8_t l_dimmtype=0;
+   uint8_t l_swizzle=0;
+      
+   rc = FAPI_ATTR_GET(ATTR_MSS_DQS_SWIZZLE_TYPE, &i_target_mba, l_swizzle); if(rc) return rc;
+      
+   rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target_mba, l_mbapos); if(rc) return rc;
+   
+   rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target_mba, l_dimmtype); if(rc) return rc;
+         
+   rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target_mba, l_dram_width); if(rc) return rc;
+   
+      
+   if(i_input_type_e==RD_DQ || i_input_type_e==WR_DQ)
+   {
+   
+      if(i_port==0 && l_mbapos==0)
+      {
+	  
+	  if(flag==1){
+		for(l_phy_dq=0;l_phy_dq<l_dqmax;l_phy_dq++){
+			if(phy_block==block_p0[l_phy_dq]){
+				if(phy_lane==lane_dq_p0[l_phy_dq]){
+				i_input_index=l_phy_dq;
+				}
+			}
+		}	
+	  }else{
+	  
+         l_lane=lane_dq_p0[i_input_index];
+		l_block=block_p0[i_input_index];	 
+		}
+      }
+      else if(i_port==1 && l_mbapos==0)
+      {
+	  
+	  if(flag==1){
+		for(l_phy_dq=0;l_phy_dq<l_dqmax;l_phy_dq++){
+			if(phy_block==block_p1[l_phy_dq]){
+				if(phy_lane==lane_dq_p1[l_phy_dq]){
+				i_input_index=l_phy_dq;
+				}
+			}
+		}
+	}else{
+         l_lane=lane_dq_p1[i_input_index];
+         l_block=block_p1[i_input_index];	    
+		}
+	} 
+    else if(i_port==0 && l_mbapos==1)
+      {
+	  if(flag==1){
+		for(l_phy_dq=0;l_phy_dq<l_dqmax;l_phy_dq++){
+			if(phy_block==block_p2[l_phy_dq]){
+				if(phy_lane==lane_dq_p2[l_phy_dq]){
+				i_input_index=l_phy_dq;
+				}
+			}
+		}
+	}else{
+	  
+         l_lane=lane_dq_p2[i_input_index];
+         l_block=block_p2[i_input_index];	
+		}
+    }
+    else
+      {
+	  if(flag==1){
+		for(l_phy_dq=0;l_phy_dq<l_dqmax;l_phy_dq++){
+			if(phy_block==block_p3[l_phy_dq]){
+				if(phy_lane==lane_dq_p3[l_phy_dq]){
+				i_input_index=l_phy_dq;
+				}
+			}
+		}
+	}else{
+		l_lane=lane_dq_p3[i_input_index];
+		l_block=block_p3[i_input_index];	
+	 }
+    }
+      
+      if(i_verbose==1)
+      {
+         FAPI_INF("block=%d",l_block);
+         FAPI_INF("lane=%d",l_lane);
+      } 
+      // if(i_input_type_e==RD_DQ)
+      // {
+         // l_input_type=RD_DQ_t;
+      // }
+      // else 	
+      // {
+         // l_input_type=WR_DQ_t;    
+      // }
+      
+            
+      // rc=get_address(i_target_mba,i_port,i_rank_pair,l_input_type,l_block,l_lane,l_scom_address_64,l_start_bit,l_len); if(rc) return rc; 		 
+      if(flag==0){
+	  phy_lane=l_lane;
+	  phy_block=l_block;
+	  }
+	  // out.scom_addr=l_scom_address_64;
+      // out.start_bit=l_start_bit;
+      // out.bit_length=l_len; 
+   }
+   
+   else if (i_input_type_e==WR_DQS ||  i_input_type_e==DQS_ALIGN)	    
+   {
+      if(i_port==0 && l_mbapos==0)
+      {
+         l_dq=dqs_dq_lane_p0[i_input_index];
+         l_block=block_dqs_p0[i_input_index]; 
+      }
+             
+      else if(i_port==1 && l_mbapos==0)
+      {
+         l_dq=dqs_dq_lane_p1[i_input_index];   
+         l_block=block_dqs_p1[i_input_index]; 
+      }   
+      else if(i_port==0 && l_mbapos==1)
+      {
+         l_dq=dqs_dq_lane_p2[i_input_index];   
+         l_block=block_dqs_p2[i_input_index]; 
+      }
+      else 
+      {
+         l_dq=dqs_dq_lane_p3[i_input_index];   
+         l_block=block_dqs_p3[i_input_index]; 
+      }
+       
+      if(i_verbose==1)
+      {
+         FAPI_INF("block=%d",l_block);
+         FAPI_INF("dqs_dq_lane=%d",l_dq);
+      }
+      l_input_type=RD_CLK_t; 
+      rc=get_address(i_target_mba,i_port,i_rank_pair, l_input_type,l_block,l_lane,l_scom_address_64,l_start_bit,l_len); if(rc) return rc;
+      if(i_verbose==1)
+      {
+         FAPI_INF("read clock address=%llx",l_scom_address_64);
+      }
+      rc=fapiGetScom(i_target_mba,l_scom_address_64,data_buffer_64);if(rc) return rc; 
+            
+      if(l_dram_width==fapi::ENUM_ATTR_EFF_DRAM_WIDTH_X4)
+      {
+         
+         if (data_buffer_64.isBitSet(48))
+         {
+            lane_dqs[l_index]=16;
+            l_index++;
+         }
+         else if(data_buffer_64.isBitSet(52))
+         { 
+            lane_dqs[l_index]=18;
+            l_index++;
+         }
+        
+         if (data_buffer_64.isBitSet(49))
+         {
+            lane_dqs[l_index]=16;
+            l_index++;
+         }
+     
+         else if (data_buffer_64.isBitSet(53))
+         {
+            lane_dqs[l_index]=18;
+            l_index++;
+         }
+         
+         if (data_buffer_64.isBitSet(54))
+         {
+            lane_dqs[l_index]=20;
+            l_index++;
+         }
+         else if (data_buffer_64.isBitSet(56))
+         {
+            lane_dqs[l_index]=22;
+            l_index++;
+         }
+      
+         if (data_buffer_64.isBitSet(55))
+         {
+            lane_dqs[l_index]=20;
+            l_index++;
+         }
+         else if (data_buffer_64.isBitSet(57))   // else is not possible as one of them will definitely get set
+         {
+            lane_dqs[l_index]=22;
+            l_index++;
+         }
+         if(i_verbose==1)
+         {
+            FAPI_INF("array is=%d and %d and %d and %d",lane_dqs[0],lane_dqs[1],lane_dqs[2],lane_dqs[3]);
+         }   
+         if(l_dq==0)
+         {
+            l_lane=lane_dqs[0];
+         }
+         else if(l_dq==4)
+         {
+            l_lane=lane_dqs[1];
+         }  
+         else if(l_dq==8)
+         {
+            l_lane=lane_dqs[2];
+         }
+         else 
+         {
+            l_lane=lane_dqs[3];
+         }
+         
+         if(i_verbose==1)
+         {
+            FAPI_INF("lane is=%d",l_lane); 
+         }
+      }			  
+   
+     
+      else
+      {   
+         if (data_buffer_64.isBitSet(48)&& data_buffer_64.isBitSet(49))
+         {		  
+            lane_dqs[l_index]=16;
+            l_index++; 		    
+         }
+         else if (data_buffer_64.isBitSet(52)&& data_buffer_64.isBitSet(53))
+         {		  
+            lane_dqs[l_index]=18;
+            l_index++; 		    
+         }
+         if (data_buffer_64.isBitSet(54)&& data_buffer_64.isBitSet(55))
+         {		  
+            lane_dqs[l_index]=20;
+            l_index++; 		    
+         }
+         else if (data_buffer_64.isBitSet(56)&& data_buffer_64.isBitSet(57))   // else is not possible as one of them will definitely get set
+         {		  
+            lane_dqs[l_index]=22;
+            l_index++; 		    
+         }
+         if(i_verbose==1)
+         {
+            FAPI_INF("array is=%d and %d",lane_dqs[0],lane_dqs[1]); 
+         } 
+         if((l_dq==0) || (l_dq==4))
+         {
+            l_lane=lane_dqs[0];
+         }
+         else 
+         {
+            l_lane=lane_dqs[1];
+         }
+         
+         if(l_dimmtype==fapi::ENUM_ATTR_EFF_DIMM_TYPE_CDIMM)
+         {
+            if((i_input_index==1) || (i_input_index==3) || (i_input_index==5) || (i_input_index==7) || (i_input_index==9) || (i_input_index==11) || (i_input_index==13) || (i_input_index==15) || (i_input_index==17) || (i_input_index==19))
+            {
+               if(l_lane==16)
+               {
+                  l_lane=18;
+               }
+               else if(l_lane==18)
+               {
+                  l_lane=16;
+               }
+               
+               else if(l_lane==20)
+               {
+                  l_lane=22;
+               }
+               
+               else
+               {
+                  l_lane=20;
+               }
+               
+            }
+         }
+         
+         else
+         {
+            if((i_port==0) && (l_mbapos==0))
+            {
+               if(l_swizzle==1)
+               {
+                  if((i_input_index==3) || (i_input_index==1) || (i_input_index==4) || (i_input_index==17)|| (i_input_index==9) || (i_input_index==11) || (i_input_index==13) || (i_input_index==15) ||  (i_input_index==6))
+                  {
+                     if(l_lane==16)
+                     {
+                        l_lane=18;
+                     }
+                     else if(l_lane==18)
+                     {
+                        l_lane=16;
+                     }
+                     
+                     else if(l_lane==20)
+                     {
+                        l_lane=22;
+                     }
+                     
+                     else
+                     {
+                        l_lane=20;
+                     }
+                  
+                  }   
+               }
+                           
+               else
+               {
+                  if((i_input_index==3) || (i_input_index==1) || (i_input_index==5) || (i_input_index==7)|| (i_input_index==9) || (i_input_index==11) || (i_input_index==13) || (i_input_index==15) ||  (i_input_index==17))
+                  {
+                     if(l_lane==16)
+                     {
+                        l_lane=18;
+                     }
+                     else if(l_lane==18)
+                     {
+                        l_lane=16;
+                     }
+                       
+                     else if(l_lane==20)
+                     {
+                        l_lane=22;
+                     }
+                       
+                     else
+                     {
+                        l_lane=20;
+                     }
+                  }   
+                          
+               }
+            }   
+            
+            else if((i_port==1) && (l_mbapos==0))
+            {
+               if(l_swizzle==1)
+               {
+                  if((i_input_index==2) || (i_input_index==0) || (i_input_index==4) || (i_input_index==17)|| (i_input_index==9) || (i_input_index==11) || (i_input_index==13) || (i_input_index==15) ||  (i_input_index==7))
+                  {
+                     if(l_lane==16)
+                     {
+                        l_lane=18;
+                     }
+                     else if(l_lane==18)
+                     {
+                        l_lane=16;
+                     }
+                     
+                     else if(l_lane==20)
+                     {
+                        l_lane=22;
+                     }
+                  
+                     else
+                     {
+                        l_lane=20;
+                     }
+                  }   
+               }
+               
+               else
+               {
+                  if((i_input_index==1) || (i_input_index==3) || (i_input_index==5) || (i_input_index==7)|| (i_input_index==9) || (i_input_index==11) || (i_input_index==13) || (i_input_index==15) ||  (i_input_index==17))
+                  {
+                     if(l_lane==16)
+                     {
+                        l_lane=18;
+                     }
+                     else if(l_lane==18)
+                     {
+                        l_lane=16;
+                     }
+                     
+                     else if(l_lane==20)
+                     {
+                        l_lane=22;
+                     }
+                  
+                     else
+                     {
+                        l_lane=20;
+                     }
+                  }   
+               }
+            }
+                  
+                  
+            else
+            {
+               if((i_input_index==1) || (i_input_index==3) || (i_input_index==5) || (i_input_index==7)|| (i_input_index==9) || (i_input_index==11) || (i_input_index==13) || (i_input_index==15) ||  (i_input_index==17))
+               {
+                  if(l_lane==16)
+                  {
+                     l_lane=18;
+                  }
+                  else if(l_lane==18)
+                  {
+                     l_lane=16;
+                  }
+                  
+                  else if(l_lane==20)
+                  {
+                     l_lane=22;
+                  }
+                  
+                  else
+                  {
+                     l_lane=20;
+                  }
+               
+               }   
+            }
+            
+            
+            
+         }
+         if(i_verbose==1)
+         {
+            FAPI_INF("lane is=%d",l_lane);
+         }   
+      }  
+      
+      // if(i_input_type_e==WR_DQS)	  		  
+      // {
+         // l_input_type=WR_DQS_t;  
+      // }
+      // else
+      // {
+         // l_input_type=DQS_ALIGN_t;
+      // }
+      
+      // rc=get_address(i_target_mba,i_port,i_rank_pair,l_input_type,l_block,l_lane,l_scom_address_64,l_start_bit,l_len); if(rc) return rc; 		 
+	 if(flag==0){
+	 phy_lane=l_lane;
+	  phy_block=l_block;
+	  }
+	  // out.scom_addr=l_scom_address_64;
+      // out.start_bit=l_start_bit;
+      // out.bit_length=l_len; 
+   }   
+      
+   else
+   {
+      FAPI_SET_HWP_ERROR(rc, RC_MSS_INPUT_ERROR);
+      FAPI_ERR("Wrong input type specified rc = 0x%08X ", uint32_t(rc));
+      return rc;      
+   }  
+      
+                
+   return rc; 
+}     
+ 
 
 
 
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_access_delay_reg.H b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_access_delay_reg.H
index 69c6d0e9d..885c27688 100644
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_access_delay_reg.H
+++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_access_delay_reg.H
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-//$Id: mss_access_delay_reg.H,v 1.9 2013/07/18 06:23:03 sauchadh Exp $
+//$Id: mss_access_delay_reg.H,v 1.10 2013/10/09 11:28:54 sasethur Exp $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
 // *! All Rights Reserved -- Property of IBM
@@ -193,6 +193,8 @@ fapi::ReturnCode mss_access_delay_reg(const fapi::Target & i_target_mba, access_
 
 fapi::ReturnCode cross_coupled(const fapi::Target & i_target_mba,uint8_t i_port, uint8_t i_rank_pair,input_type_t i_input_type_e,uint8_t i_input_index,uint8_t i_verbose,scom_location& out);
 
+fapi::ReturnCode mss_c4_phy(const fapi::Target & i_target_mba,uint8_t i_port, uint8_t i_rank_pair,input_type_t i_input_type_e,uint8_t &dq_lane,uint8_t i_verbose,uint8_t &phy_lane,uint8_t &phy_block,uint8_t flag);
+
 fapi::ReturnCode get_address(const fapi::Target & i_target_mba,uint8_t i_port, uint8_t i_rank_pair,ip_type_t i_input_type_e,uint8_t i_block,uint8_t i_lane,uint64_t &o_scom_address_64,uint8_t &o_start_bit,uint8_t &o_len);
 
 fapi::ReturnCode rosetta_map(const fapi::Target & i_target_mba,uint8_t i_port, input_type i_input_type_e ,uint8_t i_input_index,uint8_t i_verbose,uint8_t &o_value); 
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_shmoo_common.H b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_shmoo_common.H
index 37e7c9b91..0d533adc9 100644
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_shmoo_common.H
+++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_shmoo_common.H
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_shmoo_common.H,v 1.16 2013/08/08 11:09:15 sasethur Exp $
+// $Id: mss_shmoo_common.H,v 1.17 2013/10/07 08:35:41 sasethur Exp $
 // *!***************************************************************************
 // *! (C) Copyright International Business Machines Corp. 1997, 1998
 // *!           All Rights Reserved -- Property of IBM 
@@ -47,7 +47,7 @@
 #ifndef MSS_SHMOO_COMMON_H
 #define MSS_SHMOO_COMMON_H
 
-enum shmoo_type_t { TEST_NONE=0,MCBIST=1,WR_EYE=2, WRT_DQS=4,RD_EYE=8,RD_GATE=16 };
+enum shmoo_type_t { TEST_NONE=0,MCBIST=1,WR_EYE=2, WRT_DQS=8,RD_EYE=4,RD_GATE=16 };
 
 
 enum shmoo_algorithm_t { SEQ_LIN}; // Parallel bytes/ranks here .. no parallel targets in HB
diff --git a/src/usr/hwpf/hwp/runtime_attributes/memory_occ_attributes.xml b/src/usr/hwpf/hwp/runtime_attributes/memory_occ_attributes.xml
new file mode 100644
index 000000000..03b98b07e
--- /dev/null
+++ b/src/usr/hwpf/hwp/runtime_attributes/memory_occ_attributes.xml
@@ -0,0 +1,49 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: src/usr/hwpf/hwp/runtime_attributes/memory_occ_attributes.xml $ -->
+<!--                                                                        -->
+<!-- IBM CONFIDENTIAL                                                       -->
+<!--                                                                        -->
+<!-- COPYRIGHT International Business Machines Corp. 2013                   -->
+<!--                                                                        -->
+<!-- p1                                                                     -->
+<!--                                                                        -->
+<!-- Object Code Only (OCO) source materials                                -->
+<!-- Licensed Internal Code Source Materials                                -->
+<!-- IBM HostBoot Licensed Internal Code                                    -->
+<!--                                                                        -->
+<!-- The source code for this program is not published or otherwise         -->
+<!-- divested of its trade secrets, irrespective of what has been           -->
+<!-- deposited with the U.S. Copyright Office.                              -->
+<!--                                                                        -->
+<!-- Origin: 30                                                             -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<attributes>
+<!-- $Id: memory_occ_attributes.xml,v 1.1 2013/10/08 08:23:08 bellows Exp $ -->
+<!-- *********************************************************************** -->
+
+<attribute>
+    <id>ATTR_MSS_DATABUS_UTIL_PER_MBA</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>MBA DRAM data bus utilization percent to use to determine cfg_nm_n_per_mba</description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <persistRuntime/>
+</attribute>
+
+<attribute>
+    <id>ATTR_MSS_UTIL_N_PER_MBA</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>cfg_nm_n_per_mba throttle N value that was calculated from MSS_DATABUS_UTIL_PER_MBA</description>
+    <valueType>uint32</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <persistRuntime/>
+</attribute>
+
+</attributes>
diff --git a/src/usr/hwpf/makefile b/src/usr/hwpf/makefile
index 3694635fe..0a282126b 100644
--- a/src/usr/hwpf/makefile
+++ b/src/usr/hwpf/makefile
@@ -154,7 +154,8 @@ HWP_ATTR_XML_FILES = hwp/memory_attributes.xml \
                      hwp/proc_winkle_scan_override_attributes.xml \
                      hwp/erepair_thresholds.xml \
                      hwp/dram_training/mem_pll_setup/memb_pll_ring_attributes.xml \
-                     hwp/proc_chip_ec_feature.xml
+                     hwp/proc_chip_ec_feature.xml \
+                     hwp/runtime_attributes/memory_occ_attributes.xml
 
 #------------------------------------------------------------------------------
 # PLL files
diff --git a/src/usr/targeting/common/xmltohb/attribute_types.xml b/src/usr/targeting/common/xmltohb/attribute_types.xml
index faf2b9672..2b06b940b 100644
--- a/src/usr/targeting/common/xmltohb/attribute_types.xml
+++ b/src/usr/targeting/common/xmltohb/attribute_types.xml
@@ -12838,4 +12838,34 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript
     <writeable/>
 </attribute>
 
+<attribute>
+  <id>MSS_DATABUS_UTIL_PER_MBA</id>
+  <description>MBA DRAM data bus utilization percent to use to determine cfg_nm_n_per_mba</description>
+  <simpleType>
+      <uint8_t></uint8_t>
+  </simpleType>
+  <persistency>volatile-zeroed</persistency>
+  <readable/>
+  <writeable/>
+  <hwpfToHbAttrMap>
+      <id>ATTR_MSS_DATABUS_UTIL_PER_MBA</id>
+      <macro>DIRECT</macro>
+  </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+  <id>MSS_UTIL_N_PER_MBA</id>
+  <description>cfg_nm_n_per_mba throttle N value that was calculated from MSS_DATABUS_UTIL_PER_MBA</description>
+  <simpleType>
+      <uint32_t></uint32_t>
+  </simpleType>
+  <persistency>volatile-zeroed</persistency>
+  <readable/>
+  <writeable/>
+  <hwpfToHbAttrMap>
+      <id>ATTR_MSS_UTIL_N_PER_MBA</id>
+      <macro>DIRECT</macro>
+  </hwpfToHbAttrMap>
+</attribute>
+
 </attributes>
diff --git a/src/usr/targeting/common/xmltohb/common.mk b/src/usr/targeting/common/xmltohb/common.mk
index c9ca8f874..24b400440 100644
--- a/src/usr/targeting/common/xmltohb/common.mk
+++ b/src/usr/targeting/common/xmltohb/common.mk
@@ -90,7 +90,8 @@ FAPI_ATTR_SOURCES =          \
     mcbist_attributes.xml \
     proc_winkle_scan_override_attributes.xml \
     erepair_thresholds.xml \
-    dram_training/mem_pll_setup/memb_pll_ring_attributes.xml
+    dram_training/mem_pll_setup/memb_pll_ring_attributes.xml \
+    runtime_attributes/memory_occ_attributes.xml
 
 XMLTOHB_GENERIC_XML     = generic.xml
 XMLTOHB_FAPI_XML        = fapiattrs.xml
diff --git a/src/usr/targeting/common/xmltohb/target_types.xml b/src/usr/targeting/common/xmltohb/target_types.xml
index e0e95f7e5..9fdfa1f37 100644
--- a/src/usr/targeting/common/xmltohb/target_types.xml
+++ b/src/usr/targeting/common/xmltohb/target_types.xml
@@ -1058,6 +1058,8 @@
     <attribute><id>MSS_THROTTLE_CONTROL_CAS_WEIGHT</id></attribute>
     <attribute><id>MCBIST_RANDOM_SEED_VALUE</id></attribute>
     <attribute><id>MCBIST_RANDOM_SEED_TYPE</id></attribute>
+    <attribute><id>MSS_DATABUS_UTIL_PER_MBA</id></attribute>
+    <attribute><id>MSS_UTIL_N_PER_MBA</id></attribute>
 </targetType>
 
 <targetType>