Add PNOR support for AST2400 BMC

Changes from Palmetto board bringup to enable PNOR reads.

Change-Id: I13ad550eb7103a27af9ee4cb774dd504cae240a7
RTC: 106881
Origin: Google Shared Technology
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/11544
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

4 files changed, 71 insertions, 100 deletions

diff --git a/src/usr/pnor/HBconfig b/src/usr/pnor/HBconfig
new file mode 100644
index 000000000..05640191b
--- /dev/null
+++ b/src/usr/pnor/HBconfig
@@ -0,0 +1,20 @@
+config SFC_IS_IBM_DPSS
+    default y if !SFC_IS_AST2400
+    depends on !SFC_IS_AST2400
+    help
+        The Serial Flash Controller is the IBM DPSS FPGA.
+
+config SFC_IS_AST2400
+    default n
+    depends on !SFC_IS_IBM_DPSS && BMC_DOES_SFC_INIT
+    help
+        The Serial Flash Controller is the AST2400 BMC.
+
+
+
+config BMC_DOES_SFC_INIT
+    default y
+    help
+        The BMC is completely responsible for initializing and configuring the
+        SFC before Hostboot is started.
+
diff --git a/src/usr/pnor/pnordd.C b/src/usr/pnor/pnordd.C
index 0fcd8d7ef..f785623a4 100644
--- a/src/usr/pnor/pnordd.C
+++ b/src/usr/pnor/pnordd.C
@@ -5,7 +5,10 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2011,2014              */
+/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
+/* [+] Google Inc.                                                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
 /*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
@@ -45,9 +48,7 @@
 #include <sys/time.h>
 #include <initservice/initserviceif.H>
 #include <util/align.H>
-
-// Uncomment this to enable smart writing
-//#define SMART_WRITE
+#include <config.h>
 
 
 extern trace_desc_t* g_trac_pnor;
@@ -444,123 +445,43 @@ void PnorDD::sfcInit( )
     TRACFCOMP(g_trac_pnor, "PnorDD::sfcInit> iv_mode=0x%.8x", iv_mode );
     errlHndl_t  l_err  =   NULL;
 
-    //Initial configuration settings for SFC:
-    #define oadrnb_init 0x0C000000  //Set MMIO/Direct window to start at 64MB
-    #define oadrns_init 0x0000000F  //Set the MMIO/Direct window size to 64MB
-    #define adrcbf_init 0x00000000  //Set the flash index to 0
-    #define adrcmf_init 0x0000000F  //Set the flash size to 64MB
-    #define conf_init 0x00000002  //Disable Direct Access Cache
-
     do {
+#ifdef CONFIG_SFC_IS_AST2400
+        TRACFCOMP( g_trac_pnor, "PnorDD::sfcInit> Nothing to do yet for AST2400" );
+        break;
+        //@todo RTC:106881 - Fix up to support erase/write later
+#endif //CONFIG_SFC_IS_AST2400
+
         mutex_lock(&cv_mutex);
 
         if(!cv_sfcInitDone)
         {
-#define PNORDD_FSPATTACHED
-#ifdef PNORDD_FSPATTACHED
+#ifdef CONFIG_BMC_DOES_SFC_INIT
 
             //Determine NOR Flash type - triggers vendor specific workarounds
             //We also use the chipID in some FFDC situations.
             l_err = getNORChipId(cv_nor_chipid);
+            if(l_err) { break; }
             TRACFCOMP(g_trac_pnor,
                       "PnorDD::sfcInit: cv_nor_chipid=0x%.8x> ",
                       cv_nor_chipid );
 
-
+            // Re-initialize internal erase size cached value.
             l_err = readRegSfc(SFC_CMD_SPACE,
                                SFC_REG_ERASMS,
                                iv_erasesize_bytes);
             if(l_err) { break; }
             TRACFCOMP(g_trac_pnor,"iv_erasesize_bytes=%X",iv_erasesize_bytes);
 
-            cv_sfcInitDone = true;
-
-#else
-//SPLESS system - not official supported, but keeping framework in place
-//for possible future use.
-            l_err = writeRegSfc(SFC_CMD_SPACE,
-                                SFC_REG_OADRNB,
-                                oadrnb_init);
-            if(l_err) { break; }
-
-            l_err = writeRegSfc(SFC_CMD_SPACE,
-                                SFC_REG_OADRNS,
-                                oadrns_init);
-            if(l_err) { break; }
-
-            l_err = writeRegSfc(SFC_CMD_SPACE,
-                                SFC_REG_ADRCBF,
-                                adrcbf_init);
-            if(l_err) { break; }
-
-            l_err = writeRegSfc(SFC_CMD_SPACE,
-                                SFC_REG_ADRCMF,
-                                adrcmf_init);
-            if(l_err) { break; }
-
-            l_err = writeRegSfc(SFC_CMD_SPACE,
-                                SFC_REG_CONF,
-                                conf_init);
-            if(l_err) { break; }
-
-            //Determine NOR Flash type, configure SFC and PNOR DD as needed
-            l_err = getNORChipId(cv_nor_chipid);
-            TRACFCOMP(g_trac_pnor,
-                      "PnorDD::sfcInit: cv_nor_chipid=0x%.8x> ",
-                      cv_nor_chipid );
-
-            //A proper SPLESS implementation would require enhancements for
-            //Supported NOR Vendors
-            if(MICRON_NOR_ID == cv_nor_chipid)  /* Simics currently Micron */
-            {
-                TRACFCOMP(g_trac_pnor,
-                          "PnorDD::sfcInit: Configuring SFC for SIMICS NOR> " );
-                uint32_t sm_erase_op = SPI_SIM_SM_ERASE_OP;
-                iv_erasesize_bytes = SPI_SIM_SM_ERASE_SZ;
-
-                /*Simics model doesn't currently support this*/
-                l_err = writeRegSfc(SFC_CMD_SPACE,
-                                    SFC_REG_CONF4,
-                                    sm_erase_op);
-                if(l_err) { break; }
-
-
-                l_err = writeRegSfc(SFC_CMD_SPACE,
-                                    SFC_REG_CONF5,
-                                    iv_erasesize_bytes);
-                if(l_err) { break; }
-
-                //Enable 4-byte addressing
-                SfcCmdReg_t sfc_cmd;
-                sfc_cmd.opcode = SPI_START4BA;
-                sfc_cmd.length = 0;
+#else //==!CONFIG_BMC_DOES_SFC_INIT
 
-                l_err = writeRegSfc(SFC_CMD_SPACE,
-                                    SFC_REG_CMD,
-                                    sfc_cmd.data32);
-                if(l_err) { break; }
+            TRACFCOMP( g_trac_pnor, INFO_MRK "Initializing SFC registers -- unsupported!!!" );
+            //@todo RTC:97493 - Add SFC initialization from Host
+            INITSERVICE::doShutdown( PNOR::RC_UNSUPPORTED_MODE);
 
-            }
-            else if(VPO_NOR_ID == cv_nor_chipid)
-            {
-                TRACFCOMP( g_trac_pnor, "PnorDD::sfcInit> Detected VPO NOR Chip(0x%.4X).  Erase not currently supported", cv_nor_chipid );
-                //Set chip ID back to zero to avoid later chip specific logic.
-                cv_nor_chipid = 0;
-            }
-            else
-            {
-                TRACFCOMP( g_trac_pnor,  ERR_MRK"PnorDD::sfcInit> Unsupported NOR type detected : cv_nor_chipid=%.4X. Calling doShutdown(PNOR::RC_UNSUPPORTED_HARDWARE)",
-                           cv_nor_chipid );
-
-                //Shutdown if we detect unsupported Hardware
-                INITSERVICE::doShutdown( PNOR::RC_UNSUPPORTED_HARDWARE);
-
-                //Set chip ID back to zero to avoid later chip specific logic.
-                cv_nor_chipid = 0;
-            }
+#endif //CONFIG_BMC_DOES_SFC_INIT
 
             cv_sfcInitDone = true;
-#endif
         }
 
     }while(0);
diff --git a/src/usr/pnor/pnordd.H b/src/usr/pnor/pnordd.H
index 25c670440..b5628930d 100644
--- a/src/usr/pnor/pnordd.H
+++ b/src/usr/pnor/pnordd.H
@@ -5,7 +5,10 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2011,2014              */
+/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
+/* [+] Google Inc.                                                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
 /*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
@@ -24,6 +27,7 @@
 #define __PNOR_PNORDD_H
 
 #include <limits.h>
+#include <config.h>
 
 /** @file pnordd.H
  *  @brief Provides the interfaces to the PNOR Device Driver
@@ -140,6 +144,11 @@ class PnorDD
         SPI_MICRON_READ_SFDP    = 0x5A, /**< Read Serial Flash Disc Parms */
         SPI_MICRON_CHIPID       = 0x9F, /**< Read ChipID */
 
+        /* SPI protocol command bytes */
+        SPI_JEDEC_FAST_READ = 0x0B,
+        SPI_JEDEC_SECTOR_ERASE = 0x20,
+        SPI_JEDEC_BLOCK_ERASE = 0xD8,
+
         SPI_SIM_SM_ERASE_OP = 0x00000020, /**< Simics Op Code for Small Erase */
         SPI_SIM_SM_ERASE_SZ = 0x1000, /**< Simics Small Erase Size */
     };
@@ -151,6 +160,7 @@ class PnorDD
     enum NorChipIDs
     {
         /* Note: Simics currently models Micron NOR  */
+        UNKNOWN_NOR_ID    = 0,  /**< Unknown NOR chip ID */
         MICRON_NOR_ID     = 0x20ba2000,  /**< Micron NOR chip ID */
         VPO_NOR_ID        = 0x20201800,  /**< VPO NOR chip ID */
         MACRONIX_NOR_ID   = 0xC2201A00,  /**< Macronix NOR chip ID */
@@ -173,12 +183,14 @@ class PnorDD
     enum SfcRegAddr {
         SFC_REG_CONF    = 0x10, /**< CONF: Direct Access Configuration */
         SFC_REG_STATUS  = 0x0C, /**< STATUS : Status Reg */
+        SFC_REG_SPICLK  = 0x3C, /**< SPICLK: SPI clock rate config */
         SFC_REG_CMD     = 0x40, /**< CMD : Command */
         SFC_REG_ADR     = 0x44, /**< ADR : Address */
         SFC_REG_ERASMS  = 0x48, /**< ERASMS : Small Erase Block Size */
         SFC_REG_ERASLGS = 0x4C, /**< ERALGS : Large Erase Block Size */
         SFC_REG_CONF4   = 0x54, /**< CONF4  : SPI Op Code for Small Erase */
         SFC_REG_CONF5   = 0x58, /**< CONF5  : Small Erase Size config reg */
+        SFC_REG_CONF8   = 0x64, /**< CONF8  : Read Command */
         SFC_REG_ADRCBF  = 0x80, /**< ADRCBF : First Intf NOR Addr Offset */
         SFC_REG_ADRCMF  = 0x84, /**< ADRCMF : First Intf NOR Allocation */
         SFC_REG_ADRCBS  = 0x88, /**< ADRCBS : Second Intf NOR Addr Offset */
@@ -528,7 +540,11 @@ class PnorDD
 
         LPC_SFC_CMDREG_OFFSET = 0xF0000C00, /** LPC Offest to SFC Cmd Regs */
         LPC_SFC_CMDBUF_OFFSET = 0xF0000D00, /** LPC Off to SFC Cmd Buf space */
+#ifdef CONFIG_SFC_IS_AST2400
+        LPC_SFC_MMIO_OFFSET = 0xFE000000, /** LPC Off to SFC Direct Read space*/
+#else //default to IBM DPSS controller
         LPC_SFC_MMIO_OFFSET = 0xFC000000, /** LPC Off to SFC Direct Read space*/
+#endif
         LPC_TOP_OF_FLASH_OFFSET = 0xFFFFFFFF,
 
         ECCB_CTL_REG  = 0x000B0020, /**< ECCB Control Reg (FW) */
diff --git a/src/usr/pnor/pnorrp.C b/src/usr/pnor/pnorrp.C
index 9ec472384..f0507aa83 100644
--- a/src/usr/pnor/pnorrp.C
+++ b/src/usr/pnor/pnorrp.C
@@ -5,7 +5,10 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2011,2014              */
+/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
+/* [+] Google Inc.                                                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
 /*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
@@ -499,6 +502,10 @@ errlHndl_t PnorRP::readTOC()
                     {
                         INITSERVICE::doShutdown( PNOR::RC_PARTITION_TABLE_INVALID);
                     }
+                    else
+                    {
+                        TOC_0_failed = true;
+                    }
                     //Try TOC1
                     continue;
                 }
@@ -882,6 +889,13 @@ errlHndl_t PnorRP::writeToDevice( uint64_t i_offset,
 
     do
     {
+#ifdef CONFIG_SFC_IS_AST2400
+        //@todo RTC:106881 -- Add full write/erase support
+        TRACFCOMP(g_trac_pnor, "PnorRP::writeToDevice> Skipping all writes in BMC for now" );
+        break;
+#endif
+
+
         TARGETING::Target* pnor_target = TARGETING::MASTER_PROCESSOR_CHIP_TARGET_SENTINEL;
 
         // assume a single page to write