Fix GCOV build errors for AXONE configuration

This commit fixes two problems that were preventing GCOV
instrumentation from building:

1. There was an uninitialized variable in fapi2GetChildrenTest.H
2. The PNOR layout for AXONE had physical offsets for each partition
   specified manually, which was thwarting the automatic offset
   calculation required to be able to successfully adjust the partition
   layout when the size of HBI exceeds its initial allotment due to
   GCOV instrumentation

There is another uninitialized-variable warning in the import tree
which will be fixed by another commit.

Change-Id: Ibcd5e9d62a93589836cb10697e9a963428571131
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/83524
Reviewed-by: Nicholas E Bofferding <bofferdn@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M Crowell <dcrowell@us.ibm.com>

3 files changed, 4 insertions, 25 deletions

diff --git a/src/build/buildpnor/defaultPnorLayout.xml b/src/build/buildpnor/defaultPnorLayout.xml
index fd4c8ebb5..6e7c88e3d 100644
--- a/src/build/buildpnor/defaultPnorLayout.xml
+++ b/src/build/buildpnor/defaultPnorLayout.xml
@@ -170,7 +170,7 @@ Layout Description
         <ecc/>
     </section>
     <section>
-        <description>Payload (19.875MB)</description>
+        <description>Payload (6MB)</description>
         <eyeCatch>PAYLOAD</eyeCatch>
         <physicalRegionSize>0x0600000</physicalRegionSize>
         <sha512Version/>
diff --git a/src/build/buildpnor/pnorLayoutAxone.xml b/src/build/buildpnor/pnorLayoutAxone.xml
index 1c736060f..2f1d02fc1 100644
--- a/src/build/buildpnor/pnorLayoutAxone.xml
+++ b/src/build/buildpnor/pnorLayoutAxone.xml
@@ -88,7 +88,6 @@ Layout Description
     <section>
         <description>Guard Data (20K)</description>
         <eyeCatch>GUARD</eyeCatch>
-        <physicalOffset>0x2C000</physicalOffset>
         <physicalRegionSize>0x5000</physicalRegionSize>
         <side>sideless</side>
         <ecc/>
@@ -96,7 +95,6 @@ Layout Description
     <section>
         <description>Hostboot Base (1MB)</description>
         <eyeCatch>HBB</eyeCatch>
-        <physicalOffset>0x31000</physicalOffset>
         <physicalRegionSize>0x100000</physicalRegionSize>
         <side>sideless</side>
         <sha512Version/>
@@ -105,7 +103,6 @@ Layout Description
     <section>
         <description>Hostboot Data (2MB)</description>
         <eyeCatch>HBD</eyeCatch>
-        <physicalOffset>0x131000</physicalOffset>
         <physicalRegionSize>0x200000</physicalRegionSize>
         <sha512Version/>
         <side>sideless</side>
@@ -114,7 +111,6 @@ Layout Description
     <section>
         <description>Hostboot Extended image (17.77MB w/o ECC)</description>
         <eyeCatch>HBI</eyeCatch>
-        <physicalOffset>0x331000</physicalOffset>
         <physicalRegionSize>0x1400000</physicalRegionSize>
         <sha512Version/>
         <side>sideless</side>
@@ -123,7 +119,6 @@ Layout Description
     <section>
         <description>SBE-IPL (Staging Area) (752K)</description>
         <eyeCatch>SBE</eyeCatch>
-        <physicalOffset>0x1731000</physicalOffset>
         <physicalRegionSize>0xBC000</physicalRegionSize>
         <sha512perEC/>
         <sha512Version/>
@@ -133,7 +128,6 @@ Layout Description
     <section>
         <description>HCODE Ref Image (1.125MB)</description>
         <eyeCatch>HCODE</eyeCatch>
-        <physicalOffset>0x17ED000</physicalOffset>
         <physicalRegionSize>0x120000</physicalRegionSize>
         <sha512Version/>
         <side>sideless</side>
@@ -142,17 +136,15 @@ Layout Description
     <section>
         <description>Hostboot Runtime Services for Sapphire (8.0MB)</description>
         <eyeCatch>HBRT</eyeCatch>
-        <physicalOffset>0x190D000</physicalOffset>
         <physicalRegionSize>0x800000</physicalRegionSize>
         <sha512Version/>
         <side>sideless</side>
         <ecc/>
     </section>
     <section>
-        <description>Payload (19.875MB)</description>
+        <description>Payload (16KB)</description>
         <eyeCatch>PAYLOAD</eyeCatch>
-        <physicalOffset>0x210D000</physicalOffset>
-        <physicalRegionSize>0x13E0000</physicalRegionSize>
+        <physicalRegionSize>0x4000</physicalRegionSize>
         <sha512Version/>
         <side>sideless</side>
         <ecc/>
@@ -160,7 +152,6 @@ Layout Description
     <section>
         <description>Special PNOR Test Space (36K)</description>
         <eyeCatch>TEST</eyeCatch>
-        <physicalOffset>0x34ED000</physicalOffset>
         <physicalRegionSize>0x9000</physicalRegionSize>
         <testonly/>
         <side>sideless</side>
@@ -171,7 +162,6 @@ Layout Description
              from skipping header. Signing is forced in build pnor phase -->
         <description>Special PNOR Test Space with Header (36K)</description>
         <eyeCatch>TESTRO</eyeCatch>
-        <physicalOffset>0x34F6000</physicalOffset>
         <physicalRegionSize>0x9000</physicalRegionSize>
         <side>sideless</side>
         <testonly/>
@@ -182,7 +172,6 @@ Layout Description
     <section>
         <description>Hostboot Bootloader (28K)</description>
         <eyeCatch>HBBL</eyeCatch>
-        <physicalOffset>0x34FF000</physicalOffset>
         <!-- Physical Size includes Header rounded to ECC valid size -->
         <!-- Max size of actual HBBL content is 20K and 22.5K with ECC -->
         <physicalRegionSize>0x7000</physicalRegionSize>
@@ -193,7 +182,6 @@ Layout Description
     <section>
         <description>Ref Image Ring Overrides (20K)</description>
         <eyeCatch>RINGOVD</eyeCatch>
-        <physicalOffset>0x3506000</physicalOffset>
         <physicalRegionSize>0x5000</physicalRegionSize>
         <side>sideless</side>
         <ecc/>
@@ -201,7 +189,6 @@ Layout Description
     <section>
         <description>SecureBoot Key Transition Partition (16K)</description>
         <eyeCatch>SBKT</eyeCatch>
-        <physicalOffset>0x350B000</physicalOffset>
         <physicalRegionSize>0x4000</physicalRegionSize>
         <side>sideless</side>
         <ecc/>
@@ -209,7 +196,6 @@ Layout Description
     <section>
         <description>OCC Lid (1.125M)</description>
         <eyeCatch>OCC</eyeCatch>
-        <physicalOffset>0x350F000</physicalOffset>
         <physicalRegionSize>0x120000</physicalRegionSize>
         <sha512Version/>
         <side>sideless</side>
@@ -220,7 +206,6 @@ Layout Description
         <!-- We need 266KB per module sort, going to support
              40 tables by default, plus ECC  -->
         <eyeCatch>WOFDATA</eyeCatch>
-        <physicalOffset>0x362F000</physicalOffset>
         <physicalRegionSize>0x600000</physicalRegionSize>
         <side>sideless</side>
         <sha512Version/>
@@ -229,7 +214,6 @@ Layout Description
     <section>
         <description>FIRDATA (12K)</description>
         <eyeCatch>FIRDATA</eyeCatch>
-        <physicalOffset>0x3C2F000</physicalOffset>
         <physicalRegionSize>0x3000</physicalRegionSize>
         <side>sideless</side>
         <ecc/>
@@ -237,7 +221,6 @@ Layout Description
     <section>
         <description>Secureboot Test Load (12K)</description>
         <eyeCatch>TESTLOAD</eyeCatch>
-        <physicalOffset>0x3C32000</physicalOffset>
         <physicalRegionSize>0x3000</physicalRegionSize>
         <side>sideless</side>
         <sha512Version/>
@@ -246,7 +229,6 @@ Layout Description
     <section>
         <description>Secure Boot (144K)</description>
         <eyeCatch>SECBOOT</eyeCatch>
-        <physicalOffset>0x3C35000</physicalOffset>
         <physicalRegionSize>0x24000</physicalRegionSize>
         <side>sideless</side>
         <ecc/>
@@ -255,7 +237,6 @@ Layout Description
     <section>
         <description>Open CAPI Memory Buffer (OCMB) Firmware (1164K)</description>
         <eyeCatch>OCMBFW</eyeCatch>
-        <physicalOffset>0x3C59000</physicalOffset>
         <physicalRegionSize>0x123000</physicalRegionSize>
         <side>sideless</side>
         <sha512Version/>
@@ -265,7 +246,6 @@ Layout Description
     <section>
         <description>HDAT Data (16K)</description>
         <eyeCatch>HDAT</eyeCatch>
-        <physicalOffset>0x3D7C000</physicalOffset>
         <physicalRegionSize>0x4000</physicalRegionSize>
         <side>sideless</side>
         <sha512Version/>
@@ -275,7 +255,6 @@ Layout Description
         <!-- NOTE must update standalone.simics if EECACHE offset changes-->
         <description>Eeprom Cache(512K)</description>
         <eyeCatch>EECACHE</eyeCatch>
-        <physicalOffset>0x3D80000</physicalOffset>
         <physicalRegionSize>0x80000</physicalRegionSize>
         <side>sideless</side>
         <ecc/>
diff --git a/src/usr/fapi2/test/fapi2GetChildrenTest.H b/src/usr/fapi2/test/fapi2GetChildrenTest.H
index 09ed9a401..5dcf02547 100644
--- a/src/usr/fapi2/test/fapi2GetChildrenTest.H
+++ b/src/usr/fapi2/test/fapi2GetChildrenTest.H
@@ -706,7 +706,7 @@ void test_fapi2GetChildren()
                     TARGET_STATE_PRESENT).size(); } },
         };
 
-        pervasiveChildTestRec* ptr;
+        pervasiveChildTestRec* ptr = nullptr;
         int numPervTests = 0;
         TARGETING::ATTR_MODEL_type l_model = l_proc->getAttr<TARGETING::ATTR_MODEL>();
         if (l_model == TARGETING::MODEL_NIMBUS)