Fix p9_mss_scrub (sim only) for 4 port configs

Change-Id: I32a076c1d8c57d21acf3908fd82da2ce1cd13553
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24009
Tested-by: Jenkins Server
Tested-by: Hostboot CI
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: Brian R. Silver <bsilver@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24010
Tested-by: FSP CI Jenkins
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

1 files changed, 18 insertions, 22 deletions

diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_scrub.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_scrub.C
index da0552a9b..9dadf7e05 100644
--- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_scrub.C
+++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_scrub.C
@@ -58,23 +58,23 @@ fapi2::ReturnCode p9_mss_scrub( const fapi2::Target<TARGET_TYPE_MCBIST>& i_targe
         std::vector<uint64_t> l_pr;
         mss::mcbist::program<TARGET_TYPE_MCBIST> l_program;
 
+        mss::mcbist::address l_start;
+        mss::mcbist::address l_end;
+
+        size_t l_rank_address_pair = 0;
+
         // In sim we know a few things ...
         // Get the primary ranks for this port. We know there can only be 4, and we know we only trained the primary
         // ranks. Therefore, we only need to clean up the primary ranks. And because there's 4 max, we can do it
         // all using the 4 address range registers of tne MCBIST (broadcast currently not considered.)
         // So we can write 0's to those to get their ECC fixed up.
         FAPI_TRY( mss::primary_ranks(p, l_pr) );
+        fapi2::Assert( l_pr.size() <= mss::MAX_RANK_PER_DIMM);
 
-        for (const auto& r : l_pr)
+        for (auto r = l_pr.begin(); r != l_pr.end(); ++l_rank_address_pair, ++r)
         {
-            mss::mcbist::address l_start;
-            mss::mcbist::address l_end;
-
             // Setup l_start to represent this rank, and then make the end address from that.
-            l_start.set_master_rank(r);
-
-            // For checking 8Gb DRAM, add row 16 to the mix - should see valid traffic in the AET
-            l_start.set_row(0b10);
+            l_start.set_master_rank(*r);
 
             // l_end starts like as the max as we want to scrub the entire thing. If we're in sim,
             // we'll wratchet that back.
@@ -89,8 +89,7 @@ fapi2::ReturnCode p9_mss_scrub( const fapi2::Target<TARGET_TYPE_MCBIST>& i_targe
 
             // By default we're in maint address mode, not address counting mode. So we give it a start and end, and ignore
             // anything invalid - that's what maint address mode is all about
-//            mss::mcbist::config_address_range(i_target, l_start, l_end, r);
-            mss::mcbist::config_address_range(i_target, l_start, l_start + 4, r);
+            mss::mcbist::config_address_range(i_target, l_start, l_end, l_rank_address_pair);
 
             // Write
             {
@@ -100,10 +99,10 @@ fapi2::ReturnCode p9_mss_scrub( const fapi2::Target<TARGET_TYPE_MCBIST>& i_targe
                     mss::mcbist::write_subtest<TARGET_TYPE_MCBIST>();
 
                 l_fw_subtest.enable_port(mss::relative_pos<TARGET_TYPE_MCBIST>(p));
-                l_fw_subtest.change_addr_sel(r);
-                l_fw_subtest.enable_dimm(mss::get_dimm_from_rank(r));
+                l_fw_subtest.change_addr_sel(l_rank_address_pair);
+                l_fw_subtest.enable_dimm(mss::get_dimm_from_rank(*r));
                 l_program.iv_subtests.push_back(l_fw_subtest);
-                FAPI_DBG("adding superfast write for %s rank %d (dimm %d)", mss::c_str(p), r, mss::get_dimm_from_rank(r));
+                FAPI_DBG("adding superfast write for %s rank %d (dimm %d)", mss::c_str(p), *r, mss::get_dimm_from_rank(*r));
             }
 
             // Read
@@ -113,10 +112,10 @@ fapi2::ReturnCode p9_mss_scrub( const fapi2::Target<TARGET_TYPE_MCBIST>& i_targe
                     mss::mcbist::read_subtest<TARGET_TYPE_MCBIST>();
 
                 l_fr_subtest.enable_port(mss::relative_pos<TARGET_TYPE_MCBIST>(p));
-                l_fr_subtest.change_addr_sel(r);
-                l_fr_subtest.enable_dimm(mss::get_dimm_from_rank(r));
+                l_fr_subtest.change_addr_sel(l_rank_address_pair);
+                l_fr_subtest.enable_dimm(mss::get_dimm_from_rank(*r));
                 l_program.iv_subtests.push_back(l_fr_subtest);
-                FAPI_DBG("adding superfast read for %s rank %d (dimm %d)", mss::c_str(p), r, mss::get_dimm_from_rank(r));
+                FAPI_DBG("adding superfast read for %s rank %d (dimm %d)", mss::c_str(p), *r, mss::get_dimm_from_rank(*r));
             }
         }
 
@@ -131,15 +130,12 @@ fapi2::ReturnCode p9_mss_scrub( const fapi2::Target<TARGET_TYPE_MCBIST>& i_targe
         FAPI_TRY( mss::putScom(i_target, MCBIST_MCBFD7Q, 0x1234567890ABCDEF) );
 
         // Setup the sim polling based on a heuristic <cough>guess</cough>
-        // Looks like ~250ck per address for a write/read program on the sim-dimm, and add a long number of polls
-        // and a 64x fudge factor. Testing shows this takes about 50 or so poll loops to complete, which is ok
-        l_program.iv_poll.iv_initial_sim_delay = mss::cycles_to_simcycles((64 * l_pr.size()) * 250);
-        l_program.iv_poll.iv_delay = 200;
-
+        // Looks like ~400ck per address for a write/read program on the sim-dimm, and add a long number of polls
         // On real hardware wait 100ms and then start polling for another 5s
+        l_program.iv_poll.iv_initial_sim_delay = mss::cycles_to_simcycles(((l_end - l_start) * l_pr.size()) * 800);
         l_program.iv_poll.iv_initial_delay = 100 * mss::DELAY_1MS;
+        l_program.iv_poll.iv_sim_delay = 100000;
         l_program.iv_poll.iv_delay = 10 * mss::DELAY_1MS;
-
         l_program.iv_poll.iv_poll_count = 500;
 
         // Just one port for now. Per Shelton we need to set this in maint address mode