Prevent flood of interrupts early in host boot start-up on MPIPL.

RTC: 72995
CQ: SW181350
Change-Id: Ia1061c4fc28987227a8cb5f02a539de9851863b8
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/4922
Tested-by: Jenkins Server
Reviewed-by: Van H. Lee <vanlee@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

4 files changed, 90 insertions, 10 deletions

diff --git a/src/include/kernel/intmsghandler.H b/src/include/kernel/intmsghandler.H
index 168b99d4a..3f888f94b 100644
--- a/src/include/kernel/intmsghandler.H
+++ b/src/include/kernel/intmsghandler.H
@@ -66,6 +66,8 @@ class InterruptMsgHdlr : public MessageHandler
             P8_IP_NODEID_LSL   = (22-10),
             XIRR_ADDR_OFFSET   = 4,
             MFRR_ADDR_OFFSET   = 12,
+
+            INTP_BAR_VALUE     = 0xFFFFE000,    // upper 32 bits of IPCBAR 
         };
 
         /**
diff --git a/src/kernel/intmsghandler.C b/src/kernel/intmsghandler.C
index 610335731..4a9ae26e7 100644
--- a/src/kernel/intmsghandler.C
+++ b/src/kernel/intmsghandler.C
@@ -108,19 +108,38 @@ void InterruptMsgHdlr::handleInterrupt()
             cv_instance->iv_lock.unlock();
         }
     }
-
-    if(cv_ipc_base_address == 0 || cv_instance == NULL)
+    else
     {
-        static bool hit = false;
+        printk("InterrurptMsgHdlr got called before IPC was setup\n");
 
-        // print the message once
-        if(!hit)
-        {
-            printk("InterrurptMsgHdlr got called before IPC was setup\n");
-            hit = true;
-        }
-    }
+        // The INTR mmio base address is not yet available via the attributes.
+        // If we get here during an MPIPL then the BAR value could be read
+        // from the ICP BAR SCOM register, however, since this value will
+        // never change unless PHYP changes its memory map, it is deemed
+        // sufficient to hard code the value.  If this is not an MPIPL then
+        // there is a serious problem elsewhere. 
 
+        cv_ipc_base_address = (uint64_t)(INTP_BAR_VALUE) << 32; // val in BAR
+        cv_ipc_base_address >>= 14;                 // convert to base address
+
+        uint64_t xirrAddress =
+            cv_ipc_base_address + mmio_offset(pir) + XIRR_ADDR_OFFSET;
+
+        // Ignore HRMOR setting
+        xirrAddress |= 0x8000000000000000ul;
+
+        uint32_t xirr = 0;
+
+        asm volatile("lwzcix %0, 0, %1"
+                     : "=r" (xirr)
+                     : "r" (xirrAddress)
+                     : );
+
+        // There should not be any more interrupts until an eoi is sent
+        // by writing the xirr back with the value read.
+
+        printk("XIRR @ %lx = %x\n",xirrAddress,xirr);
+    }
 }
 
 void InterruptMsgHdlr::addCpuCore(uint64_t i_pir)
diff --git a/src/usr/intr/intrrp.C b/src/usr/intr/intrrp.C
index 39ea2d470..a8dd2ca6d 100644
--- a/src/usr/intr/intrrp.C
+++ b/src/usr/intr/intrrp.C
@@ -219,6 +219,14 @@ errlHndl_t IntrRp::_init()
                 err = NULL;
             }
         }
+        else
+        {
+            // The XIRR should be clean at this point, if not there is a
+            // serious problem. The routine will assert if an interrupt is
+            // found.
+            cleanCheck();
+        }
+        
 
         // Set up the interrupt provider registers
         // NOTE: It's only possible to set up the master core at this point.
@@ -1550,6 +1558,52 @@ errlHndl_t IntrRp::hw_disableIntrMpIpl()
     return err;
 }
 
+void IntrRp::cleanCheck()
+{
+    TARGETING::TargetHandleList procCores;
+    getAllChiplets(procCores, TYPE_CORE);
+
+    for(TARGETING::TargetHandleList::iterator 
+        core = procCores.begin();
+        core != procCores.end();
+        ++core)
+    {
+        const TARGETING::Target * proc = getParentChip(*core);
+
+        FABRIC_CHIP_ID_ATTR chip = proc->getAttr<ATTR_FABRIC_CHIP_ID>();
+        FABRIC_NODE_ID_ATTR node = proc->getAttr<ATTR_FABRIC_NODE_ID>();
+        CHIP_UNIT_ATTR coreId = 
+            (*core)->getAttr<TARGETING::ATTR_CHIP_UNIT>();
+
+        PIR_t pir(0);
+        pir.nodeId = node;
+        pir.chipId = chip;
+        pir.coreId = coreId;
+
+        size_t threads = cpu_thread_count();
+        for(size_t thread = 0; thread < threads; ++thread)
+        {
+            pir.threadId = thread;
+            uint64_t xirrAddr =
+                cpuOffsetAddr(pir) + iv_baseAddr + XIRR_RO_OFFSET;
+            uint32_t * xirrPtr = reinterpret_cast<uint32_t*>(xirrAddr);
+            uint32_t xirr = (*xirrPtr) & 0x00FFFFFF; // mask off CPPR
+
+            if(xirr != 0)
+            {
+                // mbox is not available at this point.
+                // errl is not functional at this point.
+                // This is probably a bug in SIMICS or FSP or HARDWARE
+                TRACFCOMP(g_trac_intr, ERR_MRK
+                          "Unexpected early interrupt on non-mpipl path."
+                          " xirr = %x",
+                          xirr);
+                assert(xirr == 0);
+            }
+        }
+    }
+}
+
 //----------------------------------------------------------------------------
 // External interfaces
 //----------------------------------------------------------------------------
diff --git a/src/usr/intr/intrrp.H b/src/usr/intr/intrrp.H
index b6896ebbc..c4301e7eb 100644
--- a/src/usr/intr/intrrp.H
+++ b/src/usr/intr/intrrp.H
@@ -464,6 +464,11 @@ namespace INTR
             errlHndl_t hw_disableIntrMpIpl();
 
             /**
+             * cleanCheck - verify there are no active interrupts
+             */
+            void cleanCheck();
+
+            /**
              * Shutdown procedure
              */
             void shutDown();