Merge DDR3/DDR4 attributes with different raw data into common attributes

There are 4 SPD FAPI Attributes where there are separate FAPI Attributes
for DDR3 and DDR4 because the raw data is interpreted differently and
the FAPI enumeration matches the raw data. I agreed with Ken Wright
that for these, there should be a common FAPI attribute that is handled
by an Accessor HWP, the Accessor converts the data appropriately to the
common enumeration. Right now the common enumeration matches DDR3 where
possible to facilitate Cronus switchover from SPD Driver to Accessor,
but eventually this could change. This change helps HWP code to not need
to know the different between DDR3 and DDR4 DIMMs.

Change-Id: I108937ab0bdfc534d9ffc1e391675f4c87875048
RTC: 82631
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/6326
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

9 files changed, 1097 insertions, 159 deletions

diff --git a/src/include/usr/hwpf/hwp/spd_accessors/getSpdAttrAccessor.H b/src/include/usr/hwpf/hwp/spd_accessors/getSpdAttrAccessor.H
new file mode 100644
index 000000000..c61fbc31a
--- /dev/null
+++ b/src/include/usr/hwpf/hwp/spd_accessors/getSpdAttrAccessor.H
@@ -0,0 +1,89 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/include/usr/hwpf/hwp/spd_accessors/getSpdAttrAccessor.H $ */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* COPYRIGHT International Business Machines Corp. 2013                   */
+/*                                                                        */
+/* p1                                                                     */
+/*                                                                        */
+/* Object Code Only (OCO) source materials                                */
+/* Licensed Internal Code Source Materials                                */
+/* IBM HostBoot Licensed Internal Code                                    */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* Origin: 30                                                             */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/**
+ *  @file getSpdAttrAccessor.H
+ *
+ *  @brief Accessor HWP that gets DDR neutral DIMM SPD FAPI Attributes
+ *
+ *  Handles DDR neutral attributes where raw SPD data cannot be returned,
+ *  either:
+ *  - The raw data has a different meaning between DDR3 and DDR4.
+ *  - The raw data has a different size between DDR3 and DDR4.
+ *  - The attribute does not map to a single field in both DDR3 and DDR4.
+ *
+ *  This Accessor HWP reads the DDR specific attribute and figures out the
+ *  data to return for the DDR neutral attribute.
+ */
+
+#ifndef _GETSPDDATAACCESSOR_
+#define _GETSPDDATAACCESSOR_
+
+#include <fapi.H>
+
+namespace fapi
+{
+    // Attributes supported
+    namespace getSpdAttr
+    {
+        enum Attr
+        {
+            SPD_SDRAM_BANKS             = 0x01,
+            SPD_MODULE_NOMINAL_VOLTAGE  = 0x02,
+            SPD_CAS_LATENCIES_SUPPORTED = 0x03,
+            SPD_MODULE_REVISION_CODE    = 0x04,
+        };
+    }
+}
+
+// function pointer typedef definition for HWP call support
+typedef fapi::ReturnCode (*getSpdAttrAccessor_FP_t) (
+    const fapi::Target &,
+    const fapi::getSpdAttr::Attr,
+    void *,
+    const size_t);
+
+extern "C"
+{
+/**
+ * @brief Accessor HWP that gets DDR neutral DIMM SPD FAPI Attribute data
+ *
+ * FAPI_ATTR_GET checks at compile time that the user's attribute is the correct
+ * type. Assuming that the platform routes the access of the attribute to the
+ * corresponding attribute enum defined in this file (e.g. ATTR_SPD_SDRAM_BANKS
+ * -> SPD_SDRAM_BANKS) then the size of o_pVal will be correct, in the unlikely
+ * event of a misroute where the buffer is too small, an error will be returned.
+ *
+ * @param[in]  i_dimm Reference to DIMM fapi target
+ * @param[in]  i_attr The Attribute to get
+ * @param[out] o_pVal Pointer to data buffer filled in with attribute data
+ * @param[in]  i_len  Size of o_pVal
+ *
+ * @return fapi::ReturnCode Indicating success or error
+ */
+fapi::ReturnCode getSpdAttrAccessor(const fapi::Target & i_dimm,
+                                    const fapi::getSpdAttr::Attr i_attr,
+                                    void * o_pVal,
+                                    const size_t i_len);
+}
+
+#endif
diff --git a/src/include/usr/hwpf/plat/fapiPlatAttributeService.H b/src/include/usr/hwpf/plat/fapiPlatAttributeService.H
index 5e49540dc..31d654190 100644
--- a/src/include/usr/hwpf/plat/fapiPlatAttributeService.H
+++ b/src/include/usr/hwpf/plat/fapiPlatAttributeService.H
@@ -29,18 +29,6 @@
  *  Note that platform code must provide the code.
  */
 
-/*
- * Change Log ******************************************************************
- * Flag     Defect/Feature  User        Date        Description
- * ------   --------------  ----------  ----------- ----------------------------
- *                          mjjones     06/27/2011  Created.
- *                          bofferdn    09/13/2011  Support fapi->hb mapping
- *                          thi         01/28/2013  Add SPD CUSTOM attr
- *                          dedahle     06/20/2013  Add Bad DIMM DQ Bitmap attr
- *                          whs         08/15/2013  79615 Clock Mapping,
- *                                                  DIMM timing and TSYS
- */
-
 #ifndef FAPIPLATATTRIBUTESERVICE_H_
 #define FAPIPLATATTRIBUTESERVICE_H_
 
@@ -61,6 +49,7 @@
 #include <hwpf/hwp/mvpd_accessors/getMBvpdTermData.H>
 #include <hwpf/hwp/mvpd_accessors/getMBvpdSlopeInterceptData.H>
 #include <hwpf/hwp/mvpd_accessors/getMBvpdSpareDramData.H>
+#include <hwpf/hwp/spd_accessors/getSpdAttrAccessor.H>
 #include <vpd/spdenums.H>
 #include <dimmConsts.H>
 #include <util/singleton.H>
@@ -581,6 +570,23 @@ fapi::ReturnCode fapiPlatGetPllAttr(const fapi::AttributeId i_attrId,
                                     const fapi::Target * const i_pChipTarget,
                                     uint32_t (&o_pllRingLength));
 
+/**
+ * @brief This function is called by the FAPI_ATTR_GET macro when getting
+ *        DIMM SPD Attributes that are handled by an Accessor HWP
+ *        It should not be called directly.
+ *
+ *  @param[in]  i_pDimm DIMM target pointer
+ *  @param[in]  i_attr  Attribute ID
+ *  @param[out] o_pVal  Pointer to output variable
+ *  @param[in]  i_len   Size of o_pVal
+ *  @return     ReturnCode. Zero on success, else error
+ */
+fapi::ReturnCode fapiPlatGetSpdAttrAccessor (
+    const fapi::Target * i_pDimm,
+    const fapi::getSpdAttr::Attr i_attr,
+    void * o_pVal,
+    size_t i_len);
+
 } // namespace platAttrSvc
 
 } // namespace fapi
@@ -628,9 +634,6 @@ fapi::ReturnCode fapiPlatGetPllAttr(const fapi::AttributeId i_attrId,
 #define ATTR_SPD_MODULE_TYPE_GETMACRO(ID, PTARGET, VAL) \
     fapi::AttrOverrideSync::getAttrOverrideFunc(fapi::ID, PTARGET, &VAL) ? fapi::FAPI_RC_SUCCESS : \
     fapi::platAttrSvc::fapiPlatGetSpdAttr( PTARGET, SPD::MODULE_TYPE, &(VAL), sizeof(VAL) )
-#define ATTR_SPD_SDRAM_BANKS_GETMACRO(ID, PTARGET, VAL) \
-    fapi::AttrOverrideSync::getAttrOverrideFunc(fapi::ID, PTARGET, &VAL) ? fapi::FAPI_RC_SUCCESS : \
-    fapi::platAttrSvc::fapiPlatGetSpdAttr( PTARGET, SPD::BANK_ADDRESS_BITS, &(VAL), sizeof(VAL) )
 #define ATTR_SPD_SDRAM_DENSITY_GETMACRO(ID, PTARGET, VAL) \
     fapi::AttrOverrideSync::getAttrOverrideFunc(fapi::ID, PTARGET, &VAL) ? fapi::FAPI_RC_SUCCESS : \
     fapi::platAttrSvc::fapiPlatGetSpdAttr( PTARGET, SPD::DENSITY, &(VAL), sizeof(VAL) )
@@ -640,9 +643,6 @@ fapi::ReturnCode fapiPlatGetPllAttr(const fapi::AttributeId i_attrId,
 #define ATTR_SPD_SDRAM_COLUMNS_GETMACRO(ID, PTARGET, VAL) \
     fapi::AttrOverrideSync::getAttrOverrideFunc(fapi::ID, PTARGET, &VAL) ? fapi::FAPI_RC_SUCCESS : \
     fapi::platAttrSvc::fapiPlatGetSpdAttr( PTARGET, SPD::COL_ADDRESS, &(VAL), sizeof(VAL) )
-#define ATTR_SPD_MODULE_NOMINAL_VOLTAGE_GETMACRO(ID, PTARGET, VAL) \
-    fapi::AttrOverrideSync::getAttrOverrideFunc(fapi::ID, PTARGET, &VAL) ? fapi::FAPI_RC_SUCCESS : \
-    fapi::platAttrSvc::fapiPlatGetSpdAttr( PTARGET, SPD::MODULE_NOMINAL_VOLTAGE, &(VAL), sizeof(VAL) )
 #define ATTR_SPD_NUM_RANKS_GETMACRO(ID, PTARGET, VAL) \
     fapi::AttrOverrideSync::getAttrOverrideFunc(fapi::ID, PTARGET, &VAL) ? fapi::FAPI_RC_SUCCESS : \
     fapi::platAttrSvc::fapiPlatGetSpdAttr( PTARGET, SPD::MODULE_RANKS, &(VAL), sizeof(VAL) )
@@ -667,9 +667,6 @@ fapi::ReturnCode fapiPlatGetPllAttr(const fapi::AttributeId i_attrId,
 #define ATTR_SPD_TCKMIN_GETMACRO(ID, PTARGET, VAL) \
     fapi::AttrOverrideSync::getAttrOverrideFunc(fapi::ID, PTARGET, &VAL) ? fapi::FAPI_RC_SUCCESS : \
     fapi::platAttrSvc::fapiPlatGetSpdAttr( PTARGET,  SPD::TCK_MIN, &(VAL), sizeof(VAL) )
-#define ATTR_SPD_CAS_LATENCIES_SUPPORTED_GETMACRO(ID, PTARGET, VAL) \
-    fapi::AttrOverrideSync::getAttrOverrideFunc(fapi::ID, PTARGET, &VAL) ? fapi::FAPI_RC_SUCCESS : \
-    fapi::platAttrSvc::fapiPlatGetSpdAttr( PTARGET, SPD::CAS_LATENCIES_SUPPORTED, &(VAL), sizeof(VAL) )
 #define ATTR_SPD_TAAMIN_GETMACRO(ID, PTARGET, VAL) \
     fapi::AttrOverrideSync::getAttrOverrideFunc(fapi::ID, PTARGET, &VAL) ? fapi::FAPI_RC_SUCCESS : \
     fapi::platAttrSvc::fapiPlatGetSpdAttr( PTARGET, SPD::MIN_CAS_LATENCY, &(VAL), sizeof(VAL) )
@@ -763,9 +760,6 @@ fapi::ReturnCode fapiPlatGetPllAttr(const fapi::AttributeId i_attrId,
 #define ATTR_SPD_MODULE_PART_NUMBER_GETMACRO(ID, PTARGET, VAL) \
     fapi::AttrOverrideSync::getAttrOverrideFunc(fapi::ID, PTARGET, &VAL) ? fapi::FAPI_RC_SUCCESS : \
     fapi::platAttrSvc::fapiPlatGetSpdAttr( PTARGET, SPD::MODULE_PART_NUMBER, &(VAL), sizeof(VAL) )
-#define ATTR_SPD_MODULE_REVISION_CODE_GETMACRO(ID, PTARGET, VAL) \
-    fapi::AttrOverrideSync::getAttrOverrideFunc(fapi::ID, PTARGET, &VAL) ? fapi::FAPI_RC_SUCCESS : \
-    fapi::platAttrSvc::fapiPlatGetSpdAttr( PTARGET, SPD::MODULE_REVISION_CODE, &(VAL), sizeof(VAL) )
 #define ATTR_SPD_DRAM_MANUFACTURER_JEDEC_ID_CODE_GETMACRO(ID, PTARGET, VAL) \
     fapi::AttrOverrideSync::getAttrOverrideFunc(fapi::ID, PTARGET, &VAL) ? fapi::FAPI_RC_SUCCESS : \
     fapi::platAttrSvc::fapiPlatGetSpdAttr( PTARGET, SPD::DRAM_MANUFACTURER_ID, &(VAL), sizeof(VAL) )
@@ -847,6 +841,18 @@ fapi::ReturnCode fapiPlatGetPllAttr(const fapi::AttributeId i_attrId,
 #define ATTR_SPD_LR_MR12_FOR_1866_2133_GETMACRO(ID, PTARGET, VAL) \
     fapi::AttrOverrideSync::getAttrOverrideFunc(fapi::ID, PTARGET, &VAL) ? fapi::FAPI_RC_SUCCESS : \
     fapi::platAttrSvc::fapiPlatGetSpdAttr( PTARGET, SPD::LRMM_MR12_FOR_1866_2133, &(VAL), sizeof(VAL) )
+#define ATTR_SPD_SDRAM_BANKS_DDR3_GETMACRO(ID, PTARGET, VAL) \
+    fapi::AttrOverrideSync::getAttrOverrideFunc(fapi::ID, PTARGET, &VAL) ? fapi::FAPI_RC_SUCCESS : \
+    fapi::platAttrSvc::fapiPlatGetSpdAttr( PTARGET, SPD::BANK_ADDRESS_BITS, &(VAL), sizeof(VAL) )
+#define ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR3_GETMACRO(ID, PTARGET, VAL) \
+    fapi::AttrOverrideSync::getAttrOverrideFunc(fapi::ID, PTARGET, &VAL) ? fapi::FAPI_RC_SUCCESS : \
+    fapi::platAttrSvc::fapiPlatGetSpdAttr( PTARGET, SPD::CAS_LATENCIES_SUPPORTED, &(VAL), sizeof(VAL) )
+#define ATTR_SPD_MODULE_REVISION_CODE_DDR3_GETMACRO(ID, PTARGET, VAL) \
+    fapi::AttrOverrideSync::getAttrOverrideFunc(fapi::ID, PTARGET, &VAL) ? fapi::FAPI_RC_SUCCESS : \
+    fapi::platAttrSvc::fapiPlatGetSpdAttr( PTARGET, SPD::MODULE_REVISION_CODE, &(VAL), sizeof(VAL) )
+#define ATTR_SPD_MODULE_NOMINAL_VOLTAGE_DDR3_GETMACRO(ID, PTARGET, VAL) \
+    fapi::AttrOverrideSync::getAttrOverrideFunc(fapi::ID, PTARGET, &VAL) ? fapi::FAPI_RC_SUCCESS : \
+    fapi::platAttrSvc::fapiPlatGetSpdAttr( PTARGET, SPD::MODULE_NOMINAL_VOLTAGE, &(VAL), sizeof(VAL) )
 #define ATTR_SPD_SDRAM_BANKGROUPS_DDR4_GETMACRO(ID, PTARGET, VAL) \
     fapi::AttrOverrideSync::getAttrOverrideFunc(fapi::ID, PTARGET, &VAL) ? fapi::FAPI_RC_SUCCESS : \
     fapi::platAttrSvc::fapiPlatGetSpdAttr( PTARGET, SPD::BANK_GROUP_BITS, &(VAL), sizeof(VAL) )
@@ -1773,4 +1779,19 @@ fapi::ReturnCode fapiPlatGetPllAttr(const fapi::AttributeId i_attrId,
         ( fapi::platAttrSvc::fapiPlatGetPllAttr( \
           ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_LENGTH, PTARGET, VAL ))
 
+//------------------------------------------------------------------------------
+//  MACROs to support DIMM SPD Attributes that are handled by an Accessor HWP
+//------------------------------------------------------------------------------
+#define ATTR_SPD_SDRAM_BANKS_GETMACRO(ID, PTARGET, VAL) \
+    fapi::AttrOverrideSync::getAttrOverrideFunc(fapi::ID, PTARGET, &VAL) ? fapi::FAPI_RC_SUCCESS : \
+    fapi::platAttrSvc::fapiPlatGetSpdAttrAccessor(PTARGET, fapi::getSpdAttr::SPD_SDRAM_BANKS, &VAL, sizeof(VAL))
+#define ATTR_SPD_MODULE_NOMINAL_VOLTAGE_GETMACRO(ID, PTARGET, VAL) \
+    fapi::AttrOverrideSync::getAttrOverrideFunc(fapi::ID, PTARGET, &VAL) ? fapi::FAPI_RC_SUCCESS : \
+    fapi::platAttrSvc::fapiPlatGetSpdAttrAccessor(PTARGET, fapi::getSpdAttr::SPD_MODULE_NOMINAL_VOLTAGE, &VAL, sizeof(VAL))
+#define ATTR_SPD_CAS_LATENCIES_SUPPORTED_GETMACRO(ID, PTARGET, VAL) \
+    fapi::AttrOverrideSync::getAttrOverrideFunc(fapi::ID, PTARGET, &VAL) ? fapi::FAPI_RC_SUCCESS : \
+    fapi::platAttrSvc::fapiPlatGetSpdAttrAccessor(PTARGET, fapi::getSpdAttr::SPD_CAS_LATENCIES_SUPPORTED, &VAL, sizeof(VAL))
+#define ATTR_SPD_MODULE_REVISION_CODE_GETMACRO(ID, PTARGET, VAL) \
+    fapi::AttrOverrideSync::getAttrOverrideFunc(fapi::ID, PTARGET, &VAL) ? fapi::FAPI_RC_SUCCESS : \
+    fapi::platAttrSvc::fapiPlatGetSpdAttrAccessor(PTARGET, fapi::getSpdAttr::SPD_MODULE_REVISION_CODE, &VAL, sizeof(VAL))
 #endif // FAPIPLATATTRIBUTESERVICE_H_
diff --git a/src/usr/hwpf/hwp/dimm_spd_attributes.xml b/src/usr/hwpf/hwp/dimm_spd_attributes.xml
index 3e415a218..2aa368634 100644
--- a/src/usr/hwpf/hwp/dimm_spd_attributes.xml
+++ b/src/usr/hwpf/hwp/dimm_spd_attributes.xml
@@ -25,7 +25,9 @@
 <attributes>
 
 <!--
+*******************************************************************************
 The following attributes can be queried from both DDR3 and DDR4 DIMMs
+*******************************************************************************
 -->
 
 <attribute>
@@ -82,6 +84,22 @@ The following attributes can be queried from both DDR3 and DDR4 DIMMs
 </attribute>
 
 <attribute>
+    <id>ATTR_SPD_SDRAM_BANKS</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Number of banks.
+        Located in DDR3 SPD byte 4, bits 6-4.
+        Located in DDR4 SPD byte 4, bits 5-4.
+        The raw data has different meanings for DDR3 and DDR4.
+        HWPs must use this DDR neutral enumeration to decode.
+        Platform support must call an Accessor HWP.
+    </description>
+    <valueType>uint8</valueType>
+    <enum>B8 = 0x00, B16 = 0x01, B32 = 0x02, B64 = 0x03, B4 = 0x04, UNKNOWN = 0xff</enum>
+    <platInit/>
+</attribute>
+
+<attribute>
     <id>ATTR_SPD_SDRAM_ROWS</id>
     <targetType>TARGET_TYPE_DIMM</targetType>
     <description>
@@ -108,6 +126,28 @@ The following attributes can be queried from both DDR3 and DDR4 DIMMs
 </attribute>
 
 <attribute>
+    <id>ATTR_SPD_MODULE_NOMINAL_VOLTAGE</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Nominal voltage (bitmap).
+        Located in DDR3 SPD byte 6, bits 2-0.
+        Located in DDR4 SPD byte 11, bits 5-0.
+        The raw data has different meanings for DDR3 and DDR4.
+        HWPs must use this DDR neutral enumeration to decode.
+        Platform support must call an Accessor HWP.
+    </description>
+    <valueType>uint8</valueType>
+    <enum>
+         NOTOP1_5 = 0x01,
+         OP1_35 = 0x02,
+         OP1_2X = 0x04,
+         OP1_2V = 0x08,
+         END1_2V = 0x10
+    </enum>
+    <platInit/>
+</attribute>
+
+<attribute>
     <id>ATTR_SPD_NUM_RANKS</id>
     <targetType>TARGET_TYPE_DIMM</targetType>
     <description>
@@ -164,6 +204,44 @@ The following attributes can be queried from both DDR3 and DDR4 DIMMs
 </attribute>
 
 <attribute>
+    <id>ATTR_SPD_CAS_LATENCIES_SUPPORTED</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        CAS Latencies supported (bitmap).
+        Located in DDR3 SPD byte 14 (LSB) and byte 15.
+        Located in DDR4 SPD byte 20 (LSB) through byte 23
+        The raw data has different meanings for DDR3 and DDR4.
+        HWPs must use this DDR neutral enumeration to decode.
+        Platform support must call an Accessor HWP.
+    </description>
+    <valueType>uint32</valueType>
+    <enum>
+        CL_24 = 0x00100000,
+        CL_23 = 0x00080000,
+        CL_22 = 0x00040000,
+        CL_21 = 0x00020000,
+        CL_20 = 0x00010000,
+        CL_19 = 0x00008000,
+        CL_18 = 0x00004000,
+        CL_17 = 0x00002000,
+        CL_16 = 0x00001000,
+        CL_15 = 0x00000800,
+        CL_14 = 0x00000400,
+        CL_13 = 0x00000200,
+        CL_12 = 0x00000100,
+        CL_11 = 0x00000080,
+        CL_10 = 0x00000040,
+        CL_9  = 0x00000020,
+        CL_8  = 0x00000010,
+        CL_7  = 0x00000008,
+        CL_6  = 0x00000004,
+        CL_5  = 0x00000002,
+        CL_4  = 0x00000001
+    </enum>
+    <platInit/>
+</attribute>
+
+<attribute>
     <id>ATTR_SPD_TAAMIN</id>
     <targetType>TARGET_TYPE_DIMM</targetType>
     <description>
@@ -470,6 +548,21 @@ The following attributes can be queried from both DDR3 and DDR4 DIMMs
 </attribute>
 
 <attribute>
+    <id>ATTR_SPD_MODULE_REVISION_CODE</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Module Revision Code.
+        Located in DDR3 SPD bytes 146 (LSB) to 147.
+        Located in DDR4 SPD byte 349
+        The raw data has a different size for DDR3 and DDR4.
+        HWPs must use this DDR neutral attribute.
+        Platform support must call an Accessor HWP.
+    </description>
+    <valueType>uint32</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
     <id>ATTR_SPD_DRAM_MANUFACTURER_JEDEC_ID_CODE</id>
     <targetType>TARGET_TYPE_DIMM</targetType>
     <description>
@@ -498,35 +591,13 @@ The following attributes can be queried from both DDR3 and DDR4 DIMMs
 </attribute>
 
 <!--
+*******************************************************************************
 The following attributes can be queried from DDR3 DIMMs only
 Querying them from DDR4 DIMMs will result in an error
+*******************************************************************************
 -->
 
 <attribute>
-    <id>ATTR_SPD_SDRAM_BANKS</id>
-    <targetType>TARGET_TYPE_DIMM</targetType>
-    <description>
-        Number of banks.
-        Located in DDR3 SPD byte 4, bits 6-4.
-    </description>
-    <valueType>uint8</valueType>
-    <enum>B8 = 0x00, B16 = 0x01, B32 = 0x02, B64 = 0x03</enum>
-    <platInit/>
-</attribute>
-
-<attribute>
-    <id>ATTR_SPD_MODULE_NOMINAL_VOLTAGE</id>
-    <targetType>TARGET_TYPE_DIMM</targetType>
-    <description>
-        Nominal voltage (bitmap).
-        Located in DDR3 SPD byte 6, bits 2-0.
-    </description>
-    <valueType>uint8</valueType>
-    <enum>NOTOP1_5 = 0x01, OP1_35 = 0x02, OP1_2X = 0x04</enum>
-    <platInit/>
-</attribute>
-
-<attribute>
     <id>ATTR_SPD_FTB_DIVIDEND</id>
     <targetType>TARGET_TYPE_DIMM</targetType>
     <description>
@@ -571,34 +642,6 @@ Querying them from DDR4 DIMMs will result in an error
 </attribute>
 
 <attribute>
-    <id>ATTR_SPD_CAS_LATENCIES_SUPPORTED</id>
-    <targetType>TARGET_TYPE_DIMM</targetType>
-    <description>
-        CAS Latencies supported (bitmap).
-        Located in DDR3 SPD byte 14 (LSB) and byte 15.
-    </description>
-    <valueType>uint32</valueType>
-    <enum>
-        CL_18 = 0x00004000,
-        CL_17 = 0x00002000,
-        CL_16 = 0x00001000,
-        CL_15 = 0x00000800,
-        CL_14 = 0x00000400,
-        CL_13 = 0x00000200,
-        CL_12 = 0x00000100,
-        CL_11 = 0x00000080,
-        CL_10 = 0x00000040,
-        CL_9  = 0x00000020,
-        CL_8  = 0x00000010,
-        CL_7  = 0x00000008,
-        CL_6  = 0x00000004,
-        CL_5  = 0x00000002,
-        CL_4  = 0x00000001
-    </enum>
-    <platInit/>
-</attribute>
-
-<attribute>
     <id>ATTR_SPD_TWRMIN</id>
     <targetType>TARGET_TYPE_DIMM</targetType>
     <description>
@@ -654,17 +697,6 @@ Querying them from DDR4 DIMMs will result in an error
 </attribute>
 
 <attribute>
-    <id>ATTR_SPD_MODULE_REVISION_CODE</id>
-    <targetType>TARGET_TYPE_DIMM</targetType>
-    <description>
-        Module Revision Code.
-        Located in DDR3 SPD bytes 146 (LSB) to 147.
-    </description>
-    <valueType>uint32</valueType>
-    <platInit/>
-</attribute>
-
-<attribute>
     <id>ATTR_SPD_LR_ADDR_MIRRORING</id>
     <targetType>TARGET_TYPE_DIMM</targetType>
     <description>
@@ -956,8 +988,10 @@ Querying them from DDR4 DIMMs will result in an error
 </attribute>
 
 <!--
+*******************************************************************************
 The following attributes can be queried from DDR4 DIMMs only
 Querying them from DDR3 DIMMs will result in an error
+*******************************************************************************
 -->
 <attribute>
     <id>ATTR_SPD_SDRAM_BANKGROUPS_DDR4</id>
@@ -972,34 +1006,6 @@ Querying them from DDR3 DIMMs will result in an error
 </attribute>
 
 <attribute>
-    <id>ATTR_SPD_SDRAM_BANKS_DDR4</id>
-    <targetType>TARGET_TYPE_DIMM</targetType>
-    <description>
-        Number of banks.
-        Located in DDR4 SPD byte 4, bits 5-4.
-    </description>
-    <valueType>uint8</valueType>
-    <enum>B4 = 0x00, B8 = 0x01</enum>
-    <platInit/>
-</attribute>
-
-<attribute>
-    <id>ATTR_SPD_MODULE_NOMINAL_VOLTAGE_DDR4</id>
-    <targetType>TARGET_TYPE_DIMM</targetType>
-    <description>
-        Nominal voltage (bitmap).
-        Located in DDR4 SPD byte 11, bits 5-0.
-    </description>
-    <valueType>uint8</valueType>
-    <enum>
-        OP1_2V = 0x01, END1_2V = 0x02,
-        OPTBD1V = 0x04, ENDTBD1V = 0x08,
-        OPTBD2V = 0x10, ENDTBD2V = 0x20
-    </enum>
-    <platInit/>
-</attribute>
-
-<attribute>
     <id>ATTR_SPD_TIMEBASE_MTB_DDR4</id>
     <targetType>TARGET_TYPE_DIMM</targetType>
     <description>
@@ -1039,37 +1045,6 @@ Querying them from DDR3 DIMMs will result in an error
 </attribute>
 
 <attribute>
-    <id>ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR4</id>
-    <targetType>TARGET_TYPE_DIMM</targetType>
-    <description>
-        CAS Latencies supported (bitmap).
-        Located in DDR4 SPD byte 20 (LSB) through byte 23.
-    </description>
-    <valueType>uint32</valueType>
-    <enum>
-        CL_24 = 0x00020000,
-        CL_23 = 0x00010000,
-        CL_22 = 0x00008000,
-        CL_21 = 0x00004000,
-        CL_20 = 0x00002000,
-        CL_19 = 0x00001000,
-        CL_18 = 0x00000800,
-        CL_17 = 0x00000400,
-        CL_16 = 0x00000200,
-        CL_15 = 0x00000100,
-        CL_14 = 0x00000080,
-        CL_13 = 0x00000040,
-        CL_12 = 0x00000020,
-        CL_11 = 0x00000010,
-        CL_10 = 0x00000008,
-        CL_9  = 0x00000004,
-        CL_8  = 0x00000002,
-        CL_7  = 0x00000001
-    </enum>
-    <platInit/>
-</attribute>
-
-<attribute>
     <id>ATTR_SPD_TRFC1MIN_DDR4</id>
     <targetType>TARGET_TYPE_DIMM</targetType>
     <description>
@@ -1212,17 +1187,6 @@ Querying them from DDR3 DIMMs will result in an error
 </attribute>
 
 <attribute>
-    <id>ATTR_SPD_MODULE_REVISION_CODE_DDR4</id>
-    <targetType>TARGET_TYPE_DIMM</targetType>
-    <description>
-        Module Revision Code.
-        Located in DDR4 SPD byte 349
-    </description>
-    <valueType>uint8</valueType>
-    <platInit/>
-</attribute>
-
-<attribute>
     <id>ATTR_SPD_DRAM_STEPPING_DDR4</id>
     <targetType>TARGET_TYPE_DIMM</targetType>
     <description>
@@ -1261,8 +1225,174 @@ Querying them from DDR3 DIMMs will result in an error
 -->
 
 <!--
+*******************************************************************************
+The following attributes are DDR3 specific. Regular HWPs should query the DDR
+neutral attribute, these attributes should only be queried by the Accessor HWP
+that handles the DDR neutral attribute.
+*******************************************************************************
+-->
+<attribute>
+    <id>ATTR_SPD_SDRAM_BANKS_DDR3</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Number of banks.
+        Located in DDR3 SPD byte 4, bits 6-4.
+        This attribute must only be used by an Accessor HWP.
+        Regular HWPs must use ATTR_SPD_SDRAM_BANKS.
+    </description>
+    <valueType>uint8</valueType>
+    <enum>B8 = 0x00, B16 = 0x01, B32 = 0x02, B64 = 0x03</enum>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_MODULE_NOMINAL_VOLTAGE_DDR3</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Nominal voltage (bitmap).
+        Located in DDR3 SPD byte 6, bits 2-0.
+        This attribute must only be used by an Accessor HWP.
+        Regular HWPs must use ATTR_SPD_MODULE_NOMINAL_VOLTAGE.
+    </description>
+    <valueType>uint8</valueType>
+    <enum>NOTOP1_5 = 0x01, OP1_35 = 0x02, OP1_2X = 0x04</enum>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR3</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        CAS Latencies supported (bitmap).
+        Located in DDR3 SPD byte 14 (LSB) and byte 15.
+        This attribute must only be used by an Accessor HWP.
+        Regular HWPs must use ATTR_SPD_CAS_LATENCIES_SUPPORTED.
+    </description>
+    <valueType>uint32</valueType>
+    <enum>
+        CL_18 = 0x00004000,
+        CL_17 = 0x00002000,
+        CL_16 = 0x00001000,
+        CL_15 = 0x00000800,
+        CL_14 = 0x00000400,
+        CL_13 = 0x00000200,
+        CL_12 = 0x00000100,
+        CL_11 = 0x00000080,
+        CL_10 = 0x00000040,
+        CL_9  = 0x00000020,
+        CL_8  = 0x00000010,
+        CL_7  = 0x00000008,
+        CL_6  = 0x00000004,
+        CL_5  = 0x00000002,
+        CL_4  = 0x00000001
+    </enum>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_MODULE_REVISION_CODE_DDR3</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Module Revision Code.
+        Located in DDR3 SPD bytes 146 (LSB) to 147.
+        This attribute must only be used by an Accessor HWP.
+        Regular HWPs must use ATTR_SPD_MODULE_REVISION_CODE.
+    </description>
+    <valueType>uint32</valueType>
+    <platInit/>
+</attribute>
+
+<!--
+*******************************************************************************
+The following attributes are DDR4 specific. Regular HWPs should query the DDR
+neutral attribute, these attributes should only be queried by the Accessor HWP
+that handles the DDR neutral attribute.
+*******************************************************************************
+-->
+<attribute>
+    <id>ATTR_SPD_SDRAM_BANKS_DDR4</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Number of banks.
+        Located in DDR4 SPD byte 4, bits 5-4.
+        This attribute must only be used by an Accessor HWP.
+        Regular HWPs must use ATTR_SPD_SDRAM_BANKS.
+    </description>
+    <valueType>uint8</valueType>
+    <enum>B4 = 0x00, B8 = 0x01</enum>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_MODULE_NOMINAL_VOLTAGE_DDR4</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Nominal voltage (bitmap).
+        Located in DDR4 SPD byte 11, bits 5-0.
+        This attribute must only be used by an Accessor HWP.
+        Regular HWPs must use ATTR_SPD_MODULE_NOMINAL_VOLTAGE.
+    </description>
+    <valueType>uint8</valueType>
+    <!-- Note that current DDR4 spec has TBD for bits 2-5 -->
+    <enum>
+        OP1_2V = 0x01, END1_2V = 0x02,
+        OPTBD1V = 0x04, ENDTBD1V = 0x08,
+        OPTBD2V = 0x10, ENDTBD2V = 0x20
+    </enum>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR4</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        CAS Latencies supported (bitmap).
+        Located in DDR4 SPD byte 20 (LSB) through byte 23.
+        This attribute must only be used by an Accessor HWP.
+        Regular HWPs must use ATTR_SPD_CAS_LATENCIES_SUPPORTED.
+    </description>
+    <valueType>uint32</valueType>
+    <enum>
+        CL_24 = 0x00020000,
+        CL_23 = 0x00010000,
+        CL_22 = 0x00008000,
+        CL_21 = 0x00004000,
+        CL_20 = 0x00002000,
+        CL_19 = 0x00001000,
+        CL_18 = 0x00000800,
+        CL_17 = 0x00000400,
+        CL_16 = 0x00000200,
+        CL_15 = 0x00000100,
+        CL_14 = 0x00000080,
+        CL_13 = 0x00000040,
+        CL_12 = 0x00000020,
+        CL_11 = 0x00000010,
+        CL_10 = 0x00000008,
+        CL_9  = 0x00000004,
+        CL_8  = 0x00000002,
+        CL_7  = 0x00000001
+    </enum>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_MODULE_REVISION_CODE_DDR4</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Module Revision Code.
+        Located in DDR4 SPD byte 349
+        This attribute must only be used by an Accessor HWP.
+        Regular HWPs must use ATTR_SPD_MODULE_REVISION_CODE.
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+</attribute>
+
+<!--
+*******************************************************************************
 The following attributes are from Centaur VPD. Consider moving them from this
 file
+*******************************************************************************
 -->
 
 <attribute>
diff --git a/src/usr/hwpf/hwp/makefile b/src/usr/hwpf/hwp/makefile
index 22b7afb37..8b5504ffa 100644
--- a/src/usr/hwpf/hwp/makefile
+++ b/src/usr/hwpf/hwp/makefile
@@ -52,6 +52,7 @@ SUBDIRS	=   dmi_training.d  sbe_centaur_init.d mc_config.d \
             pstates.d
 
 include mvpd_accessors/mvpd.mk
+include spd_accessors/spd.mk
 include utility_procedures/utils.mk
 
 include ${ROOTPATH}/config.mk
diff --git a/src/usr/hwpf/hwp/spd_accessors/getSpdAttrAccessor.C b/src/usr/hwpf/hwp/spd_accessors/getSpdAttrAccessor.C
new file mode 100644
index 000000000..067aa8cd7
--- /dev/null
+++ b/src/usr/hwpf/hwp/spd_accessors/getSpdAttrAccessor.C
@@ -0,0 +1,587 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/usr/hwpf/hwp/spd_accessors/getSpdAttrAccessor.C $         */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* COPYRIGHT International Business Machines Corp. 2013                   */
+/*                                                                        */
+/* p1                                                                     */
+/*                                                                        */
+/* Object Code Only (OCO) source materials                                */
+/* Licensed Internal Code Source Materials                                */
+/* IBM HostBoot Licensed Internal Code                                    */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* Origin: 30                                                             */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/**
+ *  @file getSpdAttrAccessor.C
+ *
+ *  @brief Accessor HWP that gets DDR neutral DIMM SPD FAPI Attribute data
+ *
+ */
+
+#include <stdint.h>
+#include <fapi.H>
+#include <getSpdAttrAccessor.H>
+
+namespace fapi
+{
+    namespace getSpdAttr
+    {
+        enum DdrType
+        {
+            DDR3 = 1,
+            DDR4 = 2,
+        };
+    }
+}
+
+extern "C"
+{
+
+/**
+ * @brief Checks the user's buffer size
+ *
+ * @param[in] i_attr         Attribute ID (just used for tracing)
+ * @param[in] i_actualSize   Actual buffer size
+ * @param[in] i_expectedSize Expected buffer size
+ *
+ * @return fapi::ReturnCode Indicating success or error
+ */
+fapi::ReturnCode checkSize(const fapi::getSpdAttr::Attr i_attr,
+                           const size_t i_actualSize,
+                           const size_t i_expectedSize)
+{
+    fapi::ReturnCode l_rc;
+
+    if (i_actualSize != i_expectedSize)
+    {
+        FAPI_ERR("getSpdAttrAccessor: Incorrect Attribute output buffer size %d:%d:%d",
+                 i_attr, i_actualSize, i_expectedSize);
+        const fapi::getSpdAttr::Attr & ATTR_ID = i_attr;
+        const size_t & ACTUAL_SIZE = i_actualSize;
+        const size_t & EXPECTED_SIZE = i_expectedSize;
+        FAPI_SET_HWP_ERROR(l_rc, RC_GET_SPD_ACCESSOR_INVALID_OUTPUT_SIZE);
+    }
+
+    return l_rc;
+}
+
+/**
+ * @brief Returns the DIMM DDR Type
+ *
+ * This function only supports DDR3 and DDR4
+ *
+ * @param[in]  i_dimm Reference to DIMM fapi target.
+ * @param[out] o_type Filled in with the DIMM DDR Type.
+ *
+ * @return fapi::ReturnCode Indicating success or error
+ */
+fapi::ReturnCode getDdrType(const fapi::Target & i_dimm,
+                            fapi::ATTR_SPD_DRAM_DEVICE_TYPE_Type & o_type)
+{
+    fapi::ReturnCode l_rc = FAPI_ATTR_GET(ATTR_SPD_DRAM_DEVICE_TYPE, &i_dimm,
+                                          o_type);
+    if (l_rc)
+    {
+        FAPI_ERR("getSpdAttrAccessor: Error querying DDR type");
+    }
+    else if ((o_type != fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR3) &&
+             (o_type != fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR4))
+    {
+        FAPI_ERR("getSpdAttrAccessor: Invalid DIMM DDR Type 0x%02x", o_type);
+        const fapi::Target & DIMM = i_dimm;
+        const fapi::ATTR_SPD_DRAM_DEVICE_TYPE_Type & TYPE = o_type;
+        FAPI_SET_HWP_ERROR(l_rc, RC_GET_SPD_ACCESSOR_INVALID_DDR_TYPE);
+    }
+
+    return l_rc;
+}
+
+/**
+ * @brief Returns SPD_SDRAM_BANKS data
+ *
+ * The raw data has different meanings for DDR3 and DDR4, this HWP translates
+ * each to the enumeration in the common FAPI Attribute
+ *
+ * @param[in]  i_dimm Reference to DIMM fapi target
+ * @param[in]  i_attr The Attribute to get
+ * @param[out] o_pVal Pointer to data buffer filled in with attribute data
+ * @param[in]  i_len  Size of o_pVal
+ * @param[in]  i_type DDR Type
+ *
+ * @return fapi::ReturnCode Indicating success or error
+ */
+fapi::ReturnCode get_SPD_SDRAM_BANKS(const fapi::Target & i_dimm,
+    const fapi::getSpdAttr::Attr i_attr,
+    void * o_pVal,
+    const size_t i_len,
+    const fapi::ATTR_SPD_DRAM_DEVICE_TYPE_Type i_type)
+{
+    fapi::ATTR_SPD_SDRAM_BANKS_Type & o_val =
+        *(reinterpret_cast<fapi::ATTR_SPD_SDRAM_BANKS_Type *>(o_pVal));
+    o_val = 0;
+
+    fapi::ReturnCode l_rc = checkSize(i_attr, i_len, sizeof(o_val));
+
+    if (!l_rc)
+    {
+        if (i_type == fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR3)
+        {
+            fapi::ATTR_SPD_SDRAM_BANKS_DDR3_Type l_banks = 0;
+            l_rc = FAPI_ATTR_GET(ATTR_SPD_SDRAM_BANKS_DDR3, &i_dimm, l_banks);
+
+            if (l_rc)
+            {
+                FAPI_ERR("get_SPD_SDRAM_BANKS: Error getting DDR3 attr");
+            }
+            else
+            {
+                switch (l_banks)
+                {
+                case fapi::ENUM_ATTR_SPD_SDRAM_BANKS_DDR3_B8:
+                    o_val = fapi::ENUM_ATTR_SPD_SDRAM_BANKS_B8;
+                    break;
+                case fapi::ENUM_ATTR_SPD_SDRAM_BANKS_DDR3_B16:
+                    o_val = fapi::ENUM_ATTR_SPD_SDRAM_BANKS_B16;
+                    break;
+                case fapi::ENUM_ATTR_SPD_SDRAM_BANKS_DDR3_B32:
+                    o_val = fapi::ENUM_ATTR_SPD_SDRAM_BANKS_B32;
+                    break;
+                case fapi::ENUM_ATTR_SPD_SDRAM_BANKS_DDR3_B64:
+                    o_val = fapi::ENUM_ATTR_SPD_SDRAM_BANKS_B64;
+                    break;
+                default:
+                   FAPI_ERR("get_SPD_SDRAM_BANKS: Unrecognized DDR3 attr 0x%x",
+                            l_banks);
+                   o_val = fapi::ENUM_ATTR_SPD_SDRAM_BANKS_UNKNOWN;
+                }
+            }
+        }
+        else
+        {
+            fapi::ATTR_SPD_SDRAM_BANKS_DDR4_Type l_banks = 0;
+            l_rc = FAPI_ATTR_GET(ATTR_SPD_SDRAM_BANKS_DDR4, &i_dimm, l_banks);
+
+            if (l_rc)
+            {
+                FAPI_ERR("get_SPD_SDRAM_BANKS: Error getting DDR4 attr");
+            }
+            else
+            {
+                switch (l_banks)
+                {
+                case fapi::ENUM_ATTR_SPD_SDRAM_BANKS_DDR4_B4:
+                    o_val = fapi::ENUM_ATTR_SPD_SDRAM_BANKS_B4;
+                    break;
+                case fapi::ENUM_ATTR_SPD_SDRAM_BANKS_DDR4_B8:
+                    o_val = fapi::ENUM_ATTR_SPD_SDRAM_BANKS_B8;
+                    break;
+                   FAPI_ERR("get_SPD_SDRAM_BANKS: Unrecognized DDR4 attr 0x%x",
+                            l_banks);
+                   o_val = fapi::ENUM_ATTR_SPD_SDRAM_BANKS_UNKNOWN;
+                }
+            }
+        }
+    }
+
+    return l_rc;
+}
+
+/**
+ * @brief Returns SPD_MODULE_NOMINAL_VOLTAGE data
+ *
+ * The raw data has different meanings for DDR3 and DDR4, this HWP translates
+ * each to the enumeration in the common FAPI Attribute
+ *
+ * @param[in]  i_dimm Reference to DIMM fapi target
+ * @param[in]  i_attr The Attribute to get
+ * @param[out] o_pVal Pointer to data buffer filled in with attribute data
+ * @param[in]  i_len  Size of o_pVal
+ * @param[in]  i_type DDR Type
+ *
+ * @return fapi::ReturnCode Indicating success or error
+ */
+fapi::ReturnCode get_SPD_MODULE_NOMINAL_VOLTAGE(const fapi::Target & i_dimm,
+    const fapi::getSpdAttr::Attr i_attr,
+    void * o_pVal,
+    const size_t i_len,
+    const fapi::ATTR_SPD_DRAM_DEVICE_TYPE_Type i_type)
+{
+    fapi::ATTR_SPD_MODULE_NOMINAL_VOLTAGE_Type & o_val =
+        *(reinterpret_cast<fapi::ATTR_SPD_MODULE_NOMINAL_VOLTAGE_Type *>(
+            o_pVal));
+    o_val = 0;
+
+    fapi::ReturnCode l_rc = checkSize(i_attr, i_len, sizeof(o_val));
+
+    if (!l_rc)
+    {
+        if (i_type == fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR3)
+        {
+            fapi::ATTR_SPD_MODULE_NOMINAL_VOLTAGE_DDR3_Type l_voltage = 0;
+            l_rc = FAPI_ATTR_GET(ATTR_SPD_MODULE_NOMINAL_VOLTAGE_DDR3, &i_dimm,
+                                 l_voltage);
+
+            if (l_rc)
+            {
+                FAPI_ERR("get_SPD_MODULE_NOMINAL_VOLTAGE: Error getting DDR3 attr");
+            }
+            else
+            {
+                if (l_voltage &
+                    fapi::ENUM_ATTR_SPD_MODULE_NOMINAL_VOLTAGE_DDR3_NOTOP1_5)
+                {
+                    o_val |=
+                        fapi::ENUM_ATTR_SPD_MODULE_NOMINAL_VOLTAGE_NOTOP1_5;
+                }
+                if (l_voltage &
+                    fapi::ENUM_ATTR_SPD_MODULE_NOMINAL_VOLTAGE_DDR3_OP1_35)
+                {
+                    o_val |= fapi::ENUM_ATTR_SPD_MODULE_NOMINAL_VOLTAGE_OP1_35;
+                }
+                if (l_voltage &
+                    fapi::ENUM_ATTR_SPD_MODULE_NOMINAL_VOLTAGE_DDR3_OP1_2X)
+                {
+                    o_val |= fapi::ENUM_ATTR_SPD_MODULE_NOMINAL_VOLTAGE_OP1_2X;
+                }
+            }
+        }
+        else
+        {
+            fapi::ATTR_SPD_MODULE_NOMINAL_VOLTAGE_DDR4_Type l_voltage = 0;
+            l_rc = FAPI_ATTR_GET(ATTR_SPD_MODULE_NOMINAL_VOLTAGE_DDR4, &i_dimm,
+                                 l_voltage);
+
+            if (l_rc)
+            {
+                FAPI_ERR("get_SPD_MODULE_NOMINAL_VOLTAGE: Error getting DDR4 attr");
+            }
+            else
+            {
+                if (l_voltage &
+                    fapi::ENUM_ATTR_SPD_MODULE_NOMINAL_VOLTAGE_DDR4_OP1_2V)
+                {
+                    o_val |= fapi::ENUM_ATTR_SPD_MODULE_NOMINAL_VOLTAGE_OP1_2V;
+                }
+                if (l_voltage &
+                    fapi::ENUM_ATTR_SPD_MODULE_NOMINAL_VOLTAGE_DDR4_END1_2V)
+                {
+                    o_val |= fapi::ENUM_ATTR_SPD_MODULE_NOMINAL_VOLTAGE_END1_2V;
+                }
+            }
+        }
+    }
+
+    return l_rc;
+}
+
+/**
+ * @brief Returns SPD_CAS_LATENCIES_SUPPORTED data
+ *
+ * The raw data has different meanings for DDR3 and DDR4, this HWP translates
+ * each to the enumeration in the common FAPI Attribute
+ *
+ * @param[in]  i_dimm Reference to DIMM fapi target
+ * @param[in]  i_attr The Attribute to get
+ * @param[out] o_pVal Pointer to data buffer filled in with attribute data
+ * @param[in]  i_len  Size of o_pVal
+ * @param[in]  i_type DDR Type
+ *
+ * @return fapi::ReturnCode Indicating success or error
+ */
+fapi::ReturnCode get_SPD_CAS_LATENCIES_SUPPORTED(const fapi::Target & i_dimm,
+    const fapi::getSpdAttr::Attr i_attr,
+    void * o_pVal,
+    const size_t i_len,
+    const fapi::ATTR_SPD_DRAM_DEVICE_TYPE_Type i_type)
+{
+    fapi::ATTR_SPD_CAS_LATENCIES_SUPPORTED_Type & o_val =
+        *(reinterpret_cast<fapi::ATTR_SPD_CAS_LATENCIES_SUPPORTED_Type *>(
+            o_pVal));
+    o_val = 0;
+
+    fapi::ReturnCode l_rc = checkSize(i_attr, i_len, sizeof(o_val));
+
+    if (!l_rc)
+    {
+        if (i_type == fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR3)
+        {
+            fapi::ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR3_Type cl = 0;
+            l_rc = FAPI_ATTR_GET(ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR3, &i_dimm,
+                                 cl);
+            if (l_rc)
+            {
+                FAPI_ERR("get_SPD_CAS_LATENCIES_SUPPORTED: Error getting DDR3 attr");
+            }
+            else
+            {
+                if (cl & fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR3_CL_4)
+                {
+                    o_val |= fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_CL_4;
+                }
+                if (cl & fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR3_CL_5)
+                {
+                    o_val |= fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_CL_5;
+                }
+                if (cl & fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR3_CL_6)
+                {
+                    o_val |= fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_CL_6;
+                }
+                if (cl & fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR3_CL_7)
+                {
+                    o_val |= fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_CL_7;
+                }
+                if (cl & fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR3_CL_8)
+                {
+                    o_val |= fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_CL_8;
+                }
+                if (cl & fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR3_CL_9)
+                {
+                    o_val |= fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_CL_9;
+                }
+                if (cl & fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR3_CL_10)
+                {
+                    o_val |= fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_CL_10;
+                }
+                if (cl & fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR3_CL_11)
+                {
+                    o_val |= fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_CL_11;
+                }
+                if (cl & fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR3_CL_12)
+                {
+                    o_val |= fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_CL_12;
+                }
+                if (cl & fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR3_CL_13)
+                {
+                    o_val |= fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_CL_13;
+                }
+                if (cl & fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR3_CL_14)
+                {
+                    o_val |= fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_CL_14;
+                }
+                if (cl & fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR3_CL_15)
+                {
+                    o_val |= fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_CL_15;
+                }
+                if (cl & fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR3_CL_16)
+                {
+                    o_val |= fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_CL_16;
+                }
+                if (cl & fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR3_CL_17)
+                {
+                    o_val |= fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_CL_17;
+                }
+                if (cl & fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR3_CL_18)
+                {
+                    o_val |= fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_CL_18;
+                }
+            }
+        }
+        else
+        {
+            fapi::ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR4_Type cl = 0;
+            l_rc = FAPI_ATTR_GET(ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR4, &i_dimm,
+                                 cl);
+            if (l_rc)
+            {
+                FAPI_ERR("get_SPD_CAS_LATENCIES_SUPPORTED: Error getting DDR4 attr");
+            }
+            else
+            {
+                if (cl & fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR4_CL_7)
+                {
+                    o_val |= fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_CL_7;
+                }
+                if (cl & fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR4_CL_8)
+                {
+                    o_val |= fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_CL_8;
+                }
+                if (cl & fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR4_CL_9)
+                {
+                    o_val |= fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_CL_9;
+                }
+                if (cl & fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR4_CL_10)
+                {
+                    o_val |= fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_CL_10;
+                }
+                if (cl & fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR4_CL_11)
+                {
+                    o_val |= fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_CL_11;
+                }
+                if (cl & fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR4_CL_12)
+                {
+                    o_val |= fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_CL_12;
+                }
+                if (cl & fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR4_CL_13)
+                {
+                    o_val |= fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_CL_13;
+                }
+                if (cl & fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR4_CL_14)
+                {
+                    o_val |= fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_CL_14;
+                }
+                if (cl & fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR4_CL_15)
+                {
+                    o_val |= fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_CL_15;
+                }
+                if (cl & fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR4_CL_16)
+                {
+                    o_val |= fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_CL_16;
+                }
+                if (cl & fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR4_CL_17)
+                {
+                    o_val |= fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_CL_17;
+                }
+                if (cl & fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR4_CL_18)
+                {
+                    o_val |= fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_CL_18;
+                }
+                if (cl & fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR4_CL_19)
+                {
+                    o_val |= fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_CL_19;
+                }
+                if (cl & fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR4_CL_20)
+                {
+                    o_val |= fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_CL_20;
+                }
+                if (cl & fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR4_CL_21)
+                {
+                    o_val |= fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_CL_21;
+                }
+                if (cl & fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR4_CL_22)
+                {
+                    o_val |= fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_CL_22;
+                }
+                if (cl & fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR4_CL_23)
+                {
+                    o_val |= fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_CL_23;
+                }
+                if (cl & fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR4_CL_24)
+                {
+                    o_val |= fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_CL_24;
+                }
+            }
+        }
+    }
+
+    return l_rc;
+}
+
+/**
+ * @brief Returns SPD_MODULE_REVISION_CODE data
+ *
+ * The fields are different sizes for DDR3 and DDR4, this HWP copies the value
+ * to the attribute size in the common FAPI Attribute
+ *
+ * @param[in]  i_dimm Reference to DIMM fapi target
+ * @param[in]  i_attr The Attribute to get
+ * @param[out] o_pVal Pointer to data buffer filled in with attribute data
+ * @param[in]  i_len  Size of o_pVal
+ * @param[in]  i_type DDR Type
+ *
+ * @return fapi::ReturnCode Indicating success or error
+ */
+fapi::ReturnCode get_SPD_MODULE_REVISION_CODE(const fapi::Target & i_dimm,
+    const fapi::getSpdAttr::Attr i_attr,
+    void * o_pVal,
+    const size_t i_len,
+    const fapi::ATTR_SPD_DRAM_DEVICE_TYPE_Type i_type)
+{
+    fapi::ATTR_SPD_MODULE_REVISION_CODE_Type & o_val =
+        *(reinterpret_cast<fapi::ATTR_SPD_MODULE_REVISION_CODE_Type *>(o_pVal));
+    o_val = 0;
+
+    fapi::ReturnCode l_rc = checkSize(i_attr, i_len, sizeof(o_val));
+
+    if (!l_rc)
+    {
+        if (i_type == fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR3)
+        {
+            // Size of DDR3 data matches DDR neutral attribute (uint32_t)
+            l_rc = FAPI_ATTR_GET(ATTR_SPD_MODULE_REVISION_CODE_DDR3, &i_dimm,
+                                 o_val);
+
+            if (l_rc)
+            {
+                FAPI_ERR("get_SPD_MODULE_REVISION_CODE: Error getting DDR3 attr");
+            }
+        }
+        else
+        {
+            // Size of DDR4 data (uint8_t) is smaller than the DDR neutral
+            // attribute (uint32_t)
+            fapi::ATTR_SPD_MODULE_REVISION_CODE_DDR4_Type l_code = 0;
+            l_rc = FAPI_ATTR_GET(ATTR_SPD_MODULE_REVISION_CODE_DDR4, &i_dimm,
+                                 l_code);
+
+            if (l_rc)
+            {
+                FAPI_ERR("get_SPD_MODULE_NOMINAL_VOLTAGE: Error getting DDR4 attr");
+            }
+            else
+            {
+                o_val = static_cast<fapi::ATTR_SPD_MODULE_REVISION_CODE_Type>(
+                    l_code);
+            }
+        }
+    }
+
+    return l_rc;
+}
+
+//-----------------------------------------------------------------------------
+// getSpdAttrAccessor HWP - See header file for details
+//-----------------------------------------------------------------------------
+fapi::ReturnCode getSpdAttrAccessor(const fapi::Target & i_dimm,
+                                    const fapi::getSpdAttr::Attr i_attr,
+                                    void * o_pVal,
+                                    const size_t i_len)
+{
+    fapi::ReturnCode l_rc;
+
+    fapi::ATTR_SPD_DRAM_DEVICE_TYPE_Type l_type = 0;
+    l_rc = getDdrType(i_dimm, l_type);
+
+    if (l_rc)
+    {
+        FAPI_ERR("getSpdAttrAccessor: Error from getDdrType for Attr ID 0x%02x",
+                 i_attr);
+    }
+    else
+    {
+        switch (i_attr)
+        {
+        case fapi::getSpdAttr::SPD_SDRAM_BANKS:
+            l_rc = get_SPD_SDRAM_BANKS(i_dimm, i_attr, o_pVal, i_len, l_type);
+            break;
+        case fapi::getSpdAttr::SPD_MODULE_NOMINAL_VOLTAGE:
+            l_rc = get_SPD_MODULE_NOMINAL_VOLTAGE(i_dimm,  i_attr,o_pVal, i_len,
+                                                  l_type);
+            break;
+        case fapi::getSpdAttr::SPD_CAS_LATENCIES_SUPPORTED:
+            l_rc = get_SPD_CAS_LATENCIES_SUPPORTED(i_dimm, i_attr, o_pVal,
+                                                   i_len, l_type);
+            break;
+        case fapi::getSpdAttr::SPD_MODULE_REVISION_CODE:
+            l_rc = get_SPD_MODULE_REVISION_CODE(i_dimm,  i_attr, o_pVal, i_len,
+                                                l_type);
+            break;
+        default:
+            FAPI_ERR("getSpdAttrAccessor: Invalid Attribute ID 0x%02x", i_attr);
+            const fapi::getSpdAttr::Attr & ATTR_ID = i_attr;
+            FAPI_SET_HWP_ERROR(l_rc, RC_GET_SPD_ACCESSOR_INVALID_ATTRIBUTE_ID);
+        }
+    }
+
+    return l_rc;
+}
+
+}
diff --git a/src/usr/hwpf/hwp/spd_accessors/getSpdAttrAccessorErrors.xml b/src/usr/hwpf/hwp/spd_accessors/getSpdAttrAccessorErrors.xml
new file mode 100644
index 000000000..cb4e74802
--- /dev/null
+++ b/src/usr/hwpf/hwp/spd_accessors/getSpdAttrAccessorErrors.xml
@@ -0,0 +1,67 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: src/usr/hwpf/hwp/spd_accessors/getDimmSpdDataErrors.xml $     -->
+<!--                                                                        -->
+<!-- IBM CONFIDENTIAL                                                       -->
+<!--                                                                        -->
+<!-- COPYRIGHT International Business Machines Corp. 2013                   -->
+<!--                                                                        -->
+<!-- p1                                                                     -->
+<!--                                                                        -->
+<!-- Object Code Only (OCO) source materials                                -->
+<!-- Licensed Internal Code Source Materials                                -->
+<!-- IBM HostBoot Licensed Internal Code                                    -->
+<!--                                                                        -->
+<!-- The source code for this program is not published or otherwise         -->
+<!-- divested of its trade secrets, irrespective of what has been           -->
+<!-- deposited with the U.S. Copyright Office.                              -->
+<!--                                                                        -->
+<!-- Origin: 30                                                             -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<hwpErrors>
+  <!-- ********************************************************************* -->
+  <hwpError>
+    <rc>RC_GET_SPD_ACCESSOR_INVALID_ATTRIBUTE_ID</rc>
+    <description>
+      Request to get DIMM SPD field with invalid attribute ID. Code bug
+    </description>
+    <ffdc>ATTR_ID</ffdc>
+    <callout>
+      <procedure>CODE</procedure>
+      <priority>HIGH</priority>
+    </callout>
+  </hwpError>
+  <!-- ********************************************************************* -->
+  <hwpError>
+    <rc>RC_GET_SPD_ACCESSOR_INVALID_OUTPUT_SIZE</rc>
+    <description>
+      Request to get DIMM SPD field with invalid output buffer size. Code bug
+    </description>
+    <ffdc>ATTR_ID</ffdc>
+    <ffdc>ACTUAL_SIZE</ffdc>
+    <ffdc>EXPECTED_SIZE</ffdc>
+    <callout>
+      <procedure>CODE</procedure>
+      <priority>HIGH</priority>
+    </callout>
+  </hwpError>
+  <!-- ********************************************************************* -->
+  <hwpError>
+    <rc>RC_GET_SPD_ACCESSOR_INVALID_DDR_TYPE</rc>
+    <description>
+      Request to get DIMM SPD field from DIMM with incorrect DDR Type
+      Only DDR3 and DDR4 supported
+    </description>
+    <ffdc>DIMM</ffdc>
+    <ffdc>TYPE</ffdc>
+    <callout>
+      <target>DIMM</target>
+      <priority>HIGH</priority>
+    </callout>
+    <deconfigure>
+      <target>DIMM</target>
+    </deconfigure>
+  </hwpError>
+</hwpErrors>
diff --git a/src/usr/hwpf/hwp/spd_accessors/spd.mk b/src/usr/hwpf/hwp/spd_accessors/spd.mk
new file mode 100644
index 000000000..0e14d703a
--- /dev/null
+++ b/src/usr/hwpf/hwp/spd_accessors/spd.mk
@@ -0,0 +1,29 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: src/usr/hwpf/hwp/spd_accessors/spd.mk $
+#
+# IBM CONFIDENTIAL
+#
+# COPYRIGHT International Business Machines Corp. 2013
+#
+# p1
+#
+# Object Code Only (OCO) source materials
+# Licensed Internal Code Source Materials
+# IBM HostBoot Licensed Internal Code
+#
+# The source code for this program is not published or otherwise
+# divested of its trade secrets, irrespective of what has been
+# deposited with the U.S. Copyright Office.
+#
+# Origin: 30
+#
+# IBM_PROLOG_END_TAG
+EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/spd_accessors
+EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/hwp/spd_accessors
+
+VPATH += spd_accessors
+
+OBJS += getSpdAttrAccessor.o
+
diff --git a/src/usr/hwpf/makefile b/src/usr/hwpf/makefile
index ca9df5328..b286d5ab9 100644
--- a/src/usr/hwpf/makefile
+++ b/src/usr/hwpf/makefile
@@ -38,6 +38,7 @@ HWP_ERROR_XML_FILES = hwp/fapiHwpErrorInfo.xml   \
     hwp/nest_chiplets/proc_start_clocks_chiplets/proc_start_clocks_chiplets_errors.xml \
     hwp/edi_ei_initialization/proc_fab_iovalid/proc_fab_smp_errors.xml  \
     hwp/mvpd_accessors/mvpd_errors.xml \
+    hwp/spd_accessors/getSpdAttrAccessorErrors.xml \
     ../pore/fapiporeve/fapiPoreVe_errors.xml \
     hwp/dram_initialization/proc_setup_bars/proc_setup_bars_errors.xml  \
     hwp/nest_chiplets/proc_chiplet_scominit/proc_chiplet_scominit_errors.xml \
diff --git a/src/usr/hwpf/plat/fapiPlatAttributeService.C b/src/usr/hwpf/plat/fapiPlatAttributeService.C
index 37e0ce639..638163ec5 100644
--- a/src/usr/hwpf/plat/fapiPlatAttributeService.C
+++ b/src/usr/hwpf/plat/fapiPlatAttributeService.C
@@ -268,7 +268,8 @@ fapi::ReturnCode fapiPlatGetSpdAttr(const fapi::Target * i_pFapiTarget,
         if (l_err)
         {
             // Add the error log pointer as data to the ReturnCode
-            FAPI_ERR("fapiPlatGetSpdAttr: deviceRead() returns error");
+            FAPI_ERR("fapiPlatGetSpdAttr: Error from deviceRead, keyword 0x%04x, len %d",
+                     i_keyword, i_len);
             l_rc.setPlatError(reinterpret_cast<void *> (l_err));
         }
         else
@@ -316,7 +317,8 @@ fapi::ReturnCode fapiPlatSetSpdAttr(const fapi::Target * i_pFapiTarget,
         if (l_err)
         {
             // Add the error log pointer as data to the ReturnCode
-            FAPI_ERR("fapiPlatSetSpdAttr: deviceWrite() returns error");
+            FAPI_ERR("fapiPlatSetSpdAttr: Error from deviceWrite, keyword 0x%04x, len %d",
+                     i_keyword, i_len);
             l_rc.setPlatError(reinterpret_cast<void *> (l_err));
         }
     }
@@ -1560,6 +1562,17 @@ fapi::ReturnCode fapiPlatGetPllAttr(const fapi::AttributeId i_targAttrId,
     return l_rc;
 }
 
+//-----------------------------------------------------------------------------
+fapi::ReturnCode fapiPlatGetSpdAttrAccessor(
+    const fapi::Target * i_pDimm,
+    const fapi::getSpdAttr::Attr i_attr,
+    void  * o_pVal,
+    const size_t i_len)
+{
+    fapi::ReturnCode l_rc;
+    FAPI_EXEC_HWP(l_rc, getSpdAttrAccessor, *i_pDimm, i_attr, o_pVal, i_len);
+    return l_rc;
+}
 
 } // End platAttrSvc namespace