Add mem_size and misc attrs, unit tests enable

Consulting w/PRD (Zane), ATTR_EFF_DIMM_RANK_CONFIGED
is not required to be initialized early in the ipl flow.
So we move it from pre_eff_config to eff_config.
Added attr_derived_engine to set attrs derived
from other attrs or hardcodes. Updated unit tests.
Added attrs not set in exp_draminit implementation of
eff_config

Change-Id: I0bb5e1913160d2cd0224cbb8566b7548eabe46d4
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/75440
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Mark Pizzutillo <mark.pizzutillo@ibm.com>
Dev-Ready: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/75575
Reviewed-by: Zane C. Shelley <zshelle@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>

16 files changed, 1255 insertions, 660 deletions

diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/eff_config/explorer_attr_engine_traits.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/eff_config/explorer_attr_engine_traits.H
index a996dcef9..aa6328646 100644
--- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/eff_config/explorer_attr_engine_traits.H
+++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/eff_config/explorer_attr_engine_traits.H
@@ -48,10 +48,14 @@
 namespace mss
 {
 
+////////////////////////////////////////////////////////
+// Explorer specific traits for setTimingTraits
+////////////////////////////////////////////////////////
+
 ///
 /// @brief Forward declartion of traits for setTimingTraits
 /// @class setTimingTraits
-/// @note attr_eff_engine_fields, SPD_TAA_MIN
+/// @note exp::attr_eff_engine_fields, SPD_TAA_MIN
 ///
 template< >
 struct setTimingTraits< exp::attr_eff_engine_fields, exp::SPD_TAA_MIN >
@@ -62,6 +66,11 @@ struct setTimingTraits< exp::attr_eff_engine_fields, exp::SPD_TAA_MIN >
     static constexpr spd_facade_fptr get_timing_in_ftb = &spd::facade::fine_offset_min_taa;
 };
 
+////////////////////////////////////////////////////////
+// Traits for explorer specific attr_eff_engine_fields
+////////////////////////////////////////////////////////
+
+
 ///
 /// @brief Traits for attr_engine
 /// @class attrEngineTraits
@@ -93,7 +102,7 @@ struct attrEngineTraits<exp::attr_eff_engine_fields, exp::BYTE_ENABLES>
     static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target,
                                       attr_type& o_setting)
     {
-        return attr::get_byte_enables(i_target, o_setting);
+        return mss::attr::get_byte_enables(i_target, o_setting);
     }
 
     ///
@@ -105,7 +114,7 @@ struct attrEngineTraits<exp::attr_eff_engine_fields, exp::BYTE_ENABLES>
     static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target,
                                       attr_type& i_setting)
     {
-        return attr::set_byte_enables(i_target, i_setting);
+        return mss::attr::set_byte_enables(i_target, i_setting);
     }
 
     ///
@@ -143,7 +152,7 @@ struct attrEngineTraits<exp::attr_eff_engine_fields, exp::NIBBLE_ENABLES>
     static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target,
                                       attr_type& o_setting)
     {
-        return attr::get_nibble_enables(i_target, o_setting);
+        return mss::attr::get_nibble_enables(i_target, o_setting);
     }
 
     ///
@@ -155,7 +164,7 @@ struct attrEngineTraits<exp::attr_eff_engine_fields, exp::NIBBLE_ENABLES>
     static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target,
                                       attr_type& i_setting)
     {
-        return attr::set_nibble_enables(i_target, i_setting);
+        return mss::attr::set_nibble_enables(i_target, i_setting);
     }
 
     ///
@@ -193,7 +202,7 @@ struct attrEngineTraits<exp::attr_eff_engine_fields, exp::SPD_TAA_MIN>
     static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target,
                                       attr_type& o_setting)
     {
-        return attr::get_exp_spd_taa_min(i_target, o_setting);
+        return mss::attr::get_exp_spd_taa_min(i_target, o_setting);
     }
 
     ///
@@ -205,7 +214,7 @@ struct attrEngineTraits<exp::attr_eff_engine_fields, exp::SPD_TAA_MIN>
     static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target,
                                       attr_type& i_setting)
     {
-        return attr::set_exp_spd_taa_min(i_target, i_setting);
+        return mss::attr::set_exp_spd_taa_min(i_target, i_setting);
     }
 
     ///
@@ -243,7 +252,7 @@ struct attrEngineTraits<exp::attr_eff_engine_fields, exp::FOUR_RANK_MODE>
     static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target,
                                       attr_type& o_setting)
     {
-        return attr::get_four_rank_mode(i_target, o_setting);
+        return mss::attr::get_four_rank_mode(i_target, o_setting);
     }
 
     ///
@@ -255,7 +264,7 @@ struct attrEngineTraits<exp::attr_eff_engine_fields, exp::FOUR_RANK_MODE>
     static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target,
                                       attr_type& i_setting)
     {
-        return attr::set_four_rank_mode(i_target, i_setting);
+        return mss::attr::set_four_rank_mode(i_target, i_setting);
     }
 
     ///
@@ -268,7 +277,7 @@ struct attrEngineTraits<exp::attr_eff_engine_fields, exp::FOUR_RANK_MODE>
             attr_integral_type& o_setting)
     {
         constexpr auto FOUR_RANK_MODE_BIT = 7; // From SPEC
-        uint8_t l_spd_four_rank_mode = 0;
+        attr_integral_type l_spd_four_rank_mode = 0;
         FAPI_TRY(i_spd_data.compatabilty_modes(l_spd_four_rank_mode));
 
         o_setting = fapi2::buffer<uint8_t>(l_spd_four_rank_mode).getBit<FOUR_RANK_MODE_BIT>();
@@ -300,7 +309,7 @@ struct attrEngineTraits<exp::attr_eff_engine_fields, exp::DDP_COMPATIBILITY>
     static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target,
                                       attr_type& o_setting)
     {
-        return attr::get_ddp_compatibility(i_target, o_setting);
+        return mss::attr::get_ddp_compatibility(i_target, o_setting);
     }
 
     ///
@@ -312,7 +321,7 @@ struct attrEngineTraits<exp::attr_eff_engine_fields, exp::DDP_COMPATIBILITY>
     static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target,
                                       attr_type& i_setting)
     {
-        return attr::set_ddp_compatibility(i_target, i_setting);
+        return mss::attr::set_ddp_compatibility(i_target, i_setting);
     }
 
     ///
@@ -325,7 +334,7 @@ struct attrEngineTraits<exp::attr_eff_engine_fields, exp::DDP_COMPATIBILITY>
             attr_integral_type& o_setting)
     {
         constexpr auto DDP_COMPATIBILITY_BIT = 6; // From SPEC
-        uint8_t l_spd_ddp_compatibility = 0;
+        attr_integral_type l_spd_ddp_compatibility = 0;
         FAPI_TRY(i_spd_data.compatabilty_modes(l_spd_ddp_compatibility));
 
         o_setting = fapi2::buffer<uint8_t>(l_spd_ddp_compatibility).getBit<DDP_COMPATIBILITY_BIT>();
@@ -357,7 +366,7 @@ struct attrEngineTraits<exp::attr_eff_engine_fields, exp::TSV_8H_SUPPORT>
     static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target,
                                       attr_type& o_setting)
     {
-        return attr::get_tsv_8h_support(i_target, o_setting);
+        return mss::attr::get_tsv_8h_support(i_target, o_setting);
     }
 
     ///
@@ -369,7 +378,7 @@ struct attrEngineTraits<exp::attr_eff_engine_fields, exp::TSV_8H_SUPPORT>
     static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target,
                                       attr_type& i_setting)
     {
-        return attr::set_tsv_8h_support(i_target, i_setting);
+        return mss::attr::set_tsv_8h_support(i_target, i_setting);
     }
 
     ///
@@ -407,7 +416,7 @@ struct attrEngineTraits<exp::attr_eff_engine_fields, exp::PSTATES>
     static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target,
                                       attr_type& o_setting)
     {
-        return attr::get_pstates(i_target, o_setting);
+        return mss::attr::get_pstates(i_target, o_setting);
     }
 
     ///
@@ -419,7 +428,7 @@ struct attrEngineTraits<exp::attr_eff_engine_fields, exp::PSTATES>
     static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target,
                                       attr_type& i_setting)
     {
-        return attr::set_pstates(i_target, i_setting);
+        return mss::attr::set_pstates(i_target, i_setting);
     }
 
     ///
@@ -457,7 +466,7 @@ struct attrEngineTraits<exp::attr_eff_engine_fields, exp::MRAM_SUPPORT>
     static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target,
                                       attr_type& o_setting)
     {
-        return attr::get_mram_support(i_target, o_setting);
+        return mss::attr::get_mram_support(i_target, o_setting);
     }
 
     ///
@@ -469,7 +478,7 @@ struct attrEngineTraits<exp::attr_eff_engine_fields, exp::MRAM_SUPPORT>
     static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target,
                                       attr_type& i_setting)
     {
-        return attr::set_mram_support(i_target, i_setting);
+        return mss::attr::set_mram_support(i_target, i_setting);
     }
 
     ///
@@ -482,7 +491,7 @@ struct attrEngineTraits<exp::attr_eff_engine_fields, exp::MRAM_SUPPORT>
             attr_integral_type& o_setting)
     {
         constexpr auto MRAM_SUPPORT_BIT = 4; // From SPEC
-        uint8_t l_spd_ddp_compatibility = 0;
+        attr_integral_type l_spd_ddp_compatibility = 0;
         FAPI_TRY(i_spd_data.compatabilty_modes(l_spd_ddp_compatibility));
 
         o_setting = fapi2::buffer<uint8_t>(l_spd_ddp_compatibility).getBit<MRAM_SUPPORT_BIT>();
@@ -514,7 +523,7 @@ struct attrEngineTraits<exp::attr_eff_engine_fields, exp::HEIGHT_3DS>
     static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target,
                                       attr_type& o_setting)
     {
-        return attr::get_exp_3ds_height(i_target, o_setting);
+        return mss::attr::get_exp_3ds_height(i_target, o_setting);
     }
 
     ///
@@ -526,7 +535,7 @@ struct attrEngineTraits<exp::attr_eff_engine_fields, exp::HEIGHT_3DS>
     static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target,
                                       attr_type& i_setting)
     {
-        return attr::set_exp_3ds_height(i_target, i_setting);
+        return mss::attr::set_exp_3ds_height(i_target, i_setting);
     }
 
     ///
@@ -565,7 +574,7 @@ struct attrEngineTraits<exp::attr_eff_engine_fields, exp::SPD_CL_SUPPORTED>
     static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target,
                                       attr_type& o_setting)
     {
-        return attr::get_exp_spd_cl_supported(i_target, o_setting);
+        return mss::attr::get_exp_spd_cl_supported(i_target, o_setting);
     }
 
     ///
@@ -577,7 +586,7 @@ struct attrEngineTraits<exp::attr_eff_engine_fields, exp::SPD_CL_SUPPORTED>
     static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target,
                                       attr_type& i_setting)
     {
-        return attr::set_exp_spd_cl_supported(i_target, i_setting);
+        return mss::attr::set_exp_spd_cl_supported(i_target, i_setting);
     }
 
     ///
@@ -591,6 +600,7 @@ struct attrEngineTraits<exp::attr_eff_engine_fields, exp::SPD_CL_SUPPORTED>
     {
         uint64_t l_val = 0;
         FAPI_TRY(i_spd_data.supported_cas_latencies(l_val));
+
         o_setting = static_cast<attr_integral_type>(l_val);
 
     fapi_try_exit:
@@ -637,8 +647,8 @@ struct attrEngineTraits<generic_metadata_fields, DIMM_TYPE_METADATA>
 
     ///
     /// @brief Computes setting for attribute
-    /// @param[in] i_spd_data SPD data
-    /// @param[in] i_setting value we want to set attr with
+    /// @param[in] i_target the DIMM target
+    /// @param[out] o_setting value we want to set attr with
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
     static fapi2::ReturnCode get_value_to_set(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
@@ -721,8 +731,8 @@ struct attrEngineTraits<generic_metadata_fields, DRAM_GEN_METADATA>
 
     ///
     /// @brief Computes setting for attribute
-    /// @param[in] i_spd_data SPD data
-    /// @param[in] i_setting value we want to set attr with
+    /// @param[in] i_target the DIMM target
+    /// @param[out] o_setting value we want to set attr with
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
     static fapi2::ReturnCode get_value_to_set(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
@@ -771,8 +781,8 @@ struct attrEngineTraits<generic_metadata_fields, DIMM_POS_METADATA>
 
     ///
     /// @brief Computes setting for attribute
-    /// @param[in] i_spd_data SPD data
-    /// @param[in] i_setting value we want to set attr with
+    /// @param[in] i_target the DIMM target
+    /// @param[out] o_setting value we want to set attr with
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
     static fapi2::ReturnCode get_value_to_set(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
@@ -783,10 +793,15 @@ struct attrEngineTraits<generic_metadata_fields, DIMM_POS_METADATA>
     }
 };
 
+////////////////////////////////////////////////////////
+// Explorer specific traits for attrEnumTraits
+////////////////////////////////////////////////////////
+
+
 ///
 /// @brief Value traits for attr_eff_engine_fields
 /// @class attrEngineTraits
-/// @note attr_eff_engine_fields
+/// @note exp::attr_eff_engine_fields are exp DDIMM SPD fields
 ///
 template < >
 struct attrEnumTraits<exp::attr_eff_engine_fields>
@@ -797,7 +812,7 @@ struct attrEnumTraits<exp::attr_eff_engine_fields>
 ///
 /// @brief Value traits for attr_eff_engine_fields
 /// @class attrEngineTraits
-/// @note attr_eff_engine_fields
+/// @note generic_metadata_fields used for dimm pos setting
 ///
 template < >
 struct attrEnumTraits<generic_metadata_fields>
diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/shared/exp_consts.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/shared/exp_consts.H
index 4457ed3e7..d043e46f6 100644
--- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/shared/exp_consts.H
+++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/shared/exp_consts.H
@@ -47,7 +47,10 @@ namespace exp
 constexpr uint32_t OCMB_ADDR_SHIFT = 3;
 
 ///
-/// @brief enum list of explorer eff attributes to set
+/// @brief enum list of explorer SPD derived attributes to set
+/// @note these attrs are strictly derived from SPD
+/// @warning wrapped in exp namesapce to be distinguished from
+/// the generic attr_eff_engine_fields
 ///
 enum attr_eff_engine_fields
 {
diff --git a/src/import/chips/ocmb/explorer/procedures/xml/attribute_info/exp_attributes.xml b/src/import/chips/ocmb/explorer/procedures/xml/attribute_info/exp_attributes.xml
index e19cfe5be..c8a72cb0a 100644
--- a/src/import/chips/ocmb/explorer/procedures/xml/attribute_info/exp_attributes.xml
+++ b/src/import/chips/ocmb/explorer/procedures/xml/attribute_info/exp_attributes.xml
@@ -29,7 +29,6 @@
 <!-- -->
 <!-- *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> -->
 <!-- *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> -->
-<!-- *HWP FW Owner: Bill Hoffa <wghoffa@us.ibm.com> -->
 <!-- *HWP Team: Memory -->
 <!-- *HWP Level: 2 -->
 <!-- *HWP Consumed by: FSP:HB -->
diff --git a/src/import/chips/ocmb/explorer/procedures/xml/attribute_info/exp_omi_train.xml b/src/import/chips/ocmb/explorer/procedures/xml/attribute_info/exp_omi_train.xml
index e8880095e..fbb950259 100644
--- a/src/import/chips/ocmb/explorer/procedures/xml/attribute_info/exp_omi_train.xml
+++ b/src/import/chips/ocmb/explorer/procedures/xml/attribute_info/exp_omi_train.xml
@@ -5,7 +5,7 @@
 <!--                                                                        -->
 <!-- OpenPOWER HostBoot Project                                             -->
 <!--                                                                        -->
-<!-- Contributors Listed Below - COPYRIGHT 2018                             -->
+<!-- Contributors Listed Below - COPYRIGHT 2018,2019                        -->
 <!-- [+] International Business Machines Corp.                              -->
 <!--                                                                        -->
 <!--                                                                        -->
@@ -47,7 +47,8 @@
             MANUFACTURING_MODE = 1
         </enum>
         <initToZero/>
-        <writeable/>
+        <platInit/>
+        <overrideOnly/>
         <mssAccessorName>ocmb_exp_boot_config_fw_mode</mssAccessorName>
     </attribute>
 
@@ -63,7 +64,8 @@
             PERFORM_LOOPBACK_TESTING = 1
         </enum>
         <initToZero/>
-        <writeable/>
+        <platInit/>
+        <overrideOnly/>
         <mssAccessorName>ocmb_exp_boot_config_opencapi_loopback_test</mssAccessorName>
     </attribute>
 
@@ -80,7 +82,8 @@
             JTAG = 2
         </enum>
         <initToZero/>
-        <writeable/>
+        <platInit/>
+        <overrideOnly/>
         <mssAccessorName>ocmb_exp_boot_config_transport_layer</mssAccessorName>
     </attribute>
 
@@ -96,8 +99,9 @@
            BOOT_RIGHT_AFTER_CONFIG = 0,
            WAIT_FOR_HOST_CMD = 1
         </enum>
+        <platInit/>
         <initToZero/>
-        <writeable/>
+        <overrideOnly/>
         <mssAccessorName>ocmb_exp_boot_config_dl_layer_boot_mode</mssAccessorName>
     </attribute>
 
@@ -113,7 +117,8 @@
             STEP_BY_STEP_BOOT = 1
         </enum>
         <initToZero/>
-        <writeable/>
+        <platInit/>
+        <overrideOnly/>
         <mssAccessorName>ocmb_exp_boot_config_boot_mode</mssAccessorName>
     </attribute>
 
@@ -130,7 +135,6 @@
         </enum>
         <default>1</default>
         <platInit/>
-        <writeable/>
         <mssAccessorName>ocmb_exp_boot_config_lane_mode</mssAccessorName>
     </attribute>
 
@@ -148,7 +152,6 @@
         </enum>
         <default>3</default>
         <platInit/>
-        <writeable/>
         <mssAccessorName>ocmb_exp_boot_config_serdes_frequency</mssAccessorName>
     </attribute>
 
diff --git a/src/import/chips/ocmb/procedures/hwp/initfiles/explorer_scom.C b/src/import/chips/ocmb/procedures/hwp/initfiles/explorer_scom.C
index 764f38274..eb6eb8604 100644
--- a/src/import/chips/ocmb/procedures/hwp/initfiles/explorer_scom.C
+++ b/src/import/chips/ocmb/procedures/hwp/initfiles/explorer_scom.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2018                             */
+/* Contributors Listed Below - COPYRIGHT 2018,2019                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -172,10 +172,10 @@ fapi2::ReturnCode explorer_scom(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP
                                        l_TGT1_ATTR_MEM_EFF_NUM_MASTER_RANKS_PER_DIMM[literal_1]);
         uint64_t l_def_NUM_MRANKS_0 = ((l_TGT1_ATTR_MEM_EFF_NUM_MASTER_RANKS_PER_DIMM[literal_0] == literal_0x0) |
                                        l_TGT1_ATTR_MEM_EFF_NUM_MASTER_RANKS_PER_DIMM[literal_0]);
-        fapi2::ATTR_MEM_EFF_NUM_RANKS_PER_DIMM_Type l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM;
-        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MEM_EFF_NUM_RANKS_PER_DIMM, TGT1, l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM));
-        uint64_t l_def_NUM_SRANKS_1 = (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] / l_def_NUM_MRANKS_1);
-        uint64_t l_def_NUM_SRANKS_0 = (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] / l_def_NUM_MRANKS_0);
+        fapi2::ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM_Type l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM;
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM, TGT1, l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM));
+        uint64_t l_def_NUM_SRANKS_1 = (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] / l_def_NUM_MRANKS_1);
+        uint64_t l_def_NUM_SRANKS_0 = (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] / l_def_NUM_MRANKS_0);
         uint64_t l_def_disable_fast_act = ((((l_def_NUM_SRANKS_0 > literal_1) || (l_def_NUM_SRANKS_1 > literal_1))
                                             && ((l_def_NUM_MRANKS_0 == literal_4) || (l_def_NUM_MRANKS_1 == literal_4))) || l_def_half_dimm_mode);
         fapi2::ATTR_MSS_MRW_DRAM_2N_MODE_Type l_TGT2_ATTR_MSS_MRW_DRAM_2N_MODE;
@@ -186,16 +186,18 @@ fapi2::ReturnCode explorer_scom(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MEM_MRW_IS_PLANAR, TGT0, l_TGT0_ATTR_MEM_MRW_IS_PLANAR));
         uint64_t l_def_SLOT0_DENOMINATOR = ((l_TGT1_ATTR_MEM_EFF_NUM_MASTER_RANKS_PER_DIMM[literal_0] == literal_0x0) |
                                             l_TGT1_ATTR_MEM_EFF_NUM_MASTER_RANKS_PER_DIMM[literal_0]);
-        uint64_t l_def_SLOT0_DRAM_STACK_HEIGHT = (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] / l_def_SLOT0_DENOMINATOR);
+        uint64_t l_def_SLOT0_DRAM_STACK_HEIGHT = (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] /
+                l_def_SLOT0_DENOMINATOR);
         uint64_t l_def_SLOT1_DENOMINATOR = ((l_TGT1_ATTR_MEM_EFF_NUM_MASTER_RANKS_PER_DIMM[literal_1] == literal_0x0) |
                                             l_TGT1_ATTR_MEM_EFF_NUM_MASTER_RANKS_PER_DIMM[literal_1]);
-        uint64_t l_def_SLOT1_DRAM_STACK_HEIGHT = (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] / l_def_SLOT1_DENOMINATOR);
+        uint64_t l_def_SLOT1_DRAM_STACK_HEIGHT = (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] /
+                l_def_SLOT1_DENOMINATOR);
         fapi2::ATTR_MEM_SI_ODT_RD_Type l_TGT1_ATTR_MEM_SI_ODT_RD;
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_ODT_RD, TGT1, l_TGT1_ATTR_MEM_SI_ODT_RD));
         fapi2::ATTR_MEM_SI_ODT_WR_Type l_TGT1_ATTR_MEM_SI_ODT_WR;
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_ODT_WR, TGT1, l_TGT1_ATTR_MEM_SI_ODT_WR));
-        uint64_t l_def_NUM_RANKS = (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] +
-                                    l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1]);
+        uint64_t l_def_NUM_RANKS = (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] +
+                                    l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1]);
         uint64_t l_def_NUM_RANKS_DENOMINATOR = ((l_def_NUM_RANKS == literal_0x0) | l_def_NUM_RANKS);
         fapi2::ATTR_MEM_EFF_DRAM_TREFI_Type l_TGT1_ATTR_MEM_EFF_DRAM_TREFI;
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MEM_EFF_DRAM_TREFI, TGT1, l_TGT1_ATTR_MEM_EFF_DRAM_TREFI));
@@ -219,8 +221,8 @@ fapi2::ReturnCode explorer_scom(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP
         uint64_t l_def_row_bit16_val_1 = (l_TGT1_ATTR_MEM_EFF_DRAM_ROW_BITS[literal_1] >= literal_17);
         uint64_t l_def_row_bit17_val_0 = (l_TGT1_ATTR_MEM_EFF_DRAM_ROW_BITS[literal_0] >= literal_18);
         uint64_t l_def_row_bit17_val_1 = (l_TGT1_ATTR_MEM_EFF_DRAM_ROW_BITS[literal_1] >= literal_18);
-        uint64_t l_def_slot_val_0 = (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] > literal_0);
-        uint64_t l_def_slot_val_1 = (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] > literal_0);
+        uint64_t l_def_slot_val_0 = (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] > literal_0);
+        uint64_t l_def_slot_val_1 = (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] > literal_0);
         uint64_t l_def_m0_val_0 = (l_def_NUM_MRANKS_0 > literal_2);
         uint64_t l_def_m1_val_0 = (l_def_NUM_MRANKS_0 >= literal_2);
         uint64_t l_def_m0_val_1 = (l_def_NUM_MRANKS_1 > literal_2);
@@ -780,65 +782,65 @@ fapi2::ReturnCode explorer_scom(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP
         {
             FAPI_TRY(fapi2::getScom( TGT0, 0x801186full, l_scom_buffer ));
 
-            if (((l_def_half_dimm_mode == literal_1) && ((l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] == literal_1)
-                    || (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] == literal_1))))
+            if (((l_def_half_dimm_mode == literal_1) && ((l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] == literal_1)
+                    || (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] == literal_1))))
             {
                 l_scom_buffer.insert<59, 5, 59, uint64_t>(literal_0b01011 );
             }
-            else if ((((l_def_half_dimm_mode == literal_1) && (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] != literal_1))
-                      && (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] != literal_1)))
+            else if ((((l_def_half_dimm_mode == literal_1) && (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] != literal_1))
+                      && (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] != literal_1)))
             {
                 l_scom_buffer.insert<59, 5, 59, uint64_t>(literal_0b01100 );
             }
-            else if (((l_def_half_dimm_mode == literal_0) && ((l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] == literal_1)
-                      || (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] == literal_1))))
+            else if (((l_def_half_dimm_mode == literal_0) && ((l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] == literal_1)
+                      || (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] == literal_1))))
             {
                 l_scom_buffer.insert<59, 5, 59, uint64_t>(literal_0b01100 );
             }
-            else if ((((l_def_half_dimm_mode == literal_0) && (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] != literal_1))
-                      && (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] != literal_1)))
+            else if ((((l_def_half_dimm_mode == literal_0) && (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] != literal_1))
+                      && (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] != literal_1)))
             {
                 l_scom_buffer.insert<59, 5, 59, uint64_t>(literal_0b01101 );
             }
 
-            if (((l_def_half_dimm_mode == literal_1) && ((l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] == literal_1)
-                    || (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] == literal_1))))
+            if (((l_def_half_dimm_mode == literal_1) && ((l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] == literal_1)
+                    || (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] == literal_1))))
             {
                 l_scom_buffer.insert<54, 5, 59, uint64_t>(literal_0b01100 );
             }
-            else if ((((l_def_half_dimm_mode == literal_1) && (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] != literal_1))
-                      && (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] != literal_1)))
+            else if ((((l_def_half_dimm_mode == literal_1) && (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] != literal_1))
+                      && (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] != literal_1)))
             {
                 l_scom_buffer.insert<54, 5, 59, uint64_t>(literal_0b01101 );
             }
-            else if (((l_def_half_dimm_mode == literal_0) && ((l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] == literal_1)
-                      || (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] == literal_1))))
+            else if (((l_def_half_dimm_mode == literal_0) && ((l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] == literal_1)
+                      || (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] == literal_1))))
             {
                 l_scom_buffer.insert<54, 5, 59, uint64_t>(literal_0b01101 );
             }
-            else if ((((l_def_half_dimm_mode == literal_0) && (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] != literal_1))
-                      && (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] != literal_1)))
+            else if ((((l_def_half_dimm_mode == literal_0) && (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] != literal_1))
+                      && (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] != literal_1)))
             {
                 l_scom_buffer.insert<54, 5, 59, uint64_t>(literal_0b01110 );
             }
 
-            if (((l_def_half_dimm_mode == literal_1) && ((l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] == literal_1)
-                    || (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] == literal_1))))
+            if (((l_def_half_dimm_mode == literal_1) && ((l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] == literal_1)
+                    || (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] == literal_1))))
             {
                 l_scom_buffer.insert<49, 5, 59, uint64_t>(literal_0b01101 );
             }
-            else if ((((l_def_half_dimm_mode == literal_1) && (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] != literal_1))
-                      && (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] != literal_1)))
+            else if ((((l_def_half_dimm_mode == literal_1) && (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] != literal_1))
+                      && (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] != literal_1)))
             {
                 l_scom_buffer.insert<49, 5, 59, uint64_t>(literal_0b01110 );
             }
-            else if (((l_def_half_dimm_mode == literal_0) && ((l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] == literal_1)
-                      || (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] == literal_1))))
+            else if (((l_def_half_dimm_mode == literal_0) && ((l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] == literal_1)
+                      || (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] == literal_1))))
             {
                 l_scom_buffer.insert<49, 5, 59, uint64_t>(literal_0b01110 );
             }
-            else if ((((l_def_half_dimm_mode == literal_0) && (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] != literal_1))
-                      && (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] != literal_1)))
+            else if ((((l_def_half_dimm_mode == literal_0) && (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] != literal_1))
+                      && (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] != literal_1)))
             {
                 l_scom_buffer.insert<49, 5, 59, uint64_t>(literal_0b01111 );
             }
@@ -1298,92 +1300,92 @@ fapi2::ReturnCode explorer_scom(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP
                 l_scom_buffer.insert<38, 5, 59, uint64_t>(literal_0b10011 );
             }
 
-            if (((l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] < literal_2)
-                 && (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] < literal_2)))
+            if (((l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] < literal_2)
+                 && (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] < literal_2)))
             {
                 l_scom_buffer.insert<33, 5, 59, uint64_t>(literal_0b00110 );
             }
             else if (((l_def_half_dimm_mode == literal_1) && ((l_def_num_of_bitvals_0 == literal_1)
-                      && ((l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] >= literal_2)
-                          || (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] >= literal_2)))))
+                      && ((l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] >= literal_2)
+                          || (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] >= literal_2)))))
             {
                 l_scom_buffer.insert<33, 5, 59, uint64_t>(literal_0b01100 );
             }
             else if (((l_def_half_dimm_mode == literal_1) && ((l_def_num_of_bitvals_0 == literal_2)
-                      && ((l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] >= literal_2)
-                          || (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] >= literal_2)))))
+                      && ((l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] >= literal_2)
+                          || (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] >= literal_2)))))
             {
                 l_scom_buffer.insert<33, 5, 59, uint64_t>(literal_0b01101 );
             }
             else if (((l_def_half_dimm_mode == literal_1) && ((l_def_num_of_bitvals_0 == literal_3)
-                      && ((l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] >= literal_2)
-                          || (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] >= literal_2)))))
+                      && ((l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] >= literal_2)
+                          || (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] >= literal_2)))))
             {
                 l_scom_buffer.insert<33, 5, 59, uint64_t>(literal_0b01110 );
             }
             else if (((l_def_half_dimm_mode == literal_1) && ((l_def_num_of_bitvals_0 == literal_4)
-                      && ((l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] >= literal_2)
-                          || (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] >= literal_2)))))
+                      && ((l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] >= literal_2)
+                          || (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] >= literal_2)))))
             {
                 l_scom_buffer.insert<33, 5, 59, uint64_t>(literal_0b01111 );
             }
             else if (((l_def_half_dimm_mode == literal_1) && ((l_def_num_of_bitvals_0 == literal_5)
-                      && ((l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] >= literal_2)
-                          || (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] >= literal_2)))))
+                      && ((l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] >= literal_2)
+                          || (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] >= literal_2)))))
             {
                 l_scom_buffer.insert<33, 5, 59, uint64_t>(literal_0b10000 );
             }
             else if (((l_def_half_dimm_mode == literal_1) && ((l_def_num_of_bitvals_0 == literal_6)
-                      && ((l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] >= literal_2)
-                          || (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] >= literal_2)))))
+                      && ((l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] >= literal_2)
+                          || (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] >= literal_2)))))
             {
                 l_scom_buffer.insert<33, 5, 59, uint64_t>(literal_0b10001 );
             }
             else if (((l_def_half_dimm_mode == literal_1) && ((l_def_num_of_bitvals_0 == literal_7)
-                      && ((l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] >= literal_2)
-                          || (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] >= literal_2)))))
+                      && ((l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] >= literal_2)
+                          || (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] >= literal_2)))))
             {
                 l_scom_buffer.insert<33, 5, 59, uint64_t>(literal_0b10010 );
             }
             else if (((l_def_half_dimm_mode == literal_0) && ((l_def_num_of_bitvals_0 == literal_1)
-                      && ((l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] >= literal_2)
-                          || (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] >= literal_2)))))
+                      && ((l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] >= literal_2)
+                          || (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] >= literal_2)))))
             {
                 l_scom_buffer.insert<33, 5, 59, uint64_t>(literal_0b01101 );
             }
             else if (((l_def_half_dimm_mode == literal_0) && ((l_def_num_of_bitvals_0 == literal_2)
-                      && ((l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] >= literal_2)
-                          || (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] >= literal_2)))))
+                      && ((l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] >= literal_2)
+                          || (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] >= literal_2)))))
             {
                 l_scom_buffer.insert<33, 5, 59, uint64_t>(literal_0b01110 );
             }
             else if (((l_def_half_dimm_mode == literal_0) && ((l_def_num_of_bitvals_0 == literal_3)
-                      && ((l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] >= literal_2)
-                          || (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] >= literal_2)))))
+                      && ((l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] >= literal_2)
+                          || (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] >= literal_2)))))
             {
                 l_scom_buffer.insert<33, 5, 59, uint64_t>(literal_0b01111 );
             }
             else if (((l_def_half_dimm_mode == literal_0) && ((l_def_num_of_bitvals_0 == literal_4)
-                      && ((l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] >= literal_2)
-                          || (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] >= literal_2)))))
+                      && ((l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] >= literal_2)
+                          || (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] >= literal_2)))))
             {
                 l_scom_buffer.insert<33, 5, 59, uint64_t>(literal_0b10000 );
             }
             else if (((l_def_half_dimm_mode == literal_0) && ((l_def_num_of_bitvals_0 == literal_5)
-                      && ((l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] >= literal_2)
-                          || (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] >= literal_2)))))
+                      && ((l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] >= literal_2)
+                          || (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] >= literal_2)))))
             {
                 l_scom_buffer.insert<33, 5, 59, uint64_t>(literal_0b10001 );
             }
             else if (((l_def_half_dimm_mode == literal_0) && ((l_def_num_of_bitvals_0 == literal_6)
-                      && ((l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] >= literal_2)
-                          || (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] >= literal_2)))))
+                      && ((l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] >= literal_2)
+                          || (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] >= literal_2)))))
             {
                 l_scom_buffer.insert<33, 5, 59, uint64_t>(literal_0b10010 );
             }
             else if (((l_def_half_dimm_mode == literal_0) && ((l_def_num_of_bitvals_0 == literal_7)
-                      && ((l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] >= literal_2)
-                          || (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] >= literal_2)))))
+                      && ((l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] >= literal_2)
+                          || (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] >= literal_2)))))
             {
                 l_scom_buffer.insert<33, 5, 59, uint64_t>(literal_0b10011 );
             }
@@ -1429,76 +1431,76 @@ fapi2::ReturnCode explorer_scom(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP
             {
                 l_scom_buffer.insert<35, 5, 59, uint64_t>(literal_0b00101 );
             }
-            else if (((l_def_half_dimm_mode == literal_0) && ((l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] == literal_1)
-                      || (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] == literal_1))))
+            else if (((l_def_half_dimm_mode == literal_0) && ((l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] == literal_1)
+                      || (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] == literal_1))))
             {
                 l_scom_buffer.insert<35, 5, 59, uint64_t>(literal_0b00110 );
             }
-            else if ((((l_def_half_dimm_mode == literal_0) && (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] != literal_1))
-                      && (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] != literal_1)))
+            else if ((((l_def_half_dimm_mode == literal_0) && (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] != literal_1))
+                      && (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] != literal_1)))
             {
                 l_scom_buffer.insert<35, 5, 59, uint64_t>(literal_0b00111 );
             }
 
-            if (((l_def_half_dimm_mode == literal_1) && ((l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] == literal_1)
-                    || (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] == literal_1))))
+            if (((l_def_half_dimm_mode == literal_1) && ((l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] == literal_1)
+                    || (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] == literal_1))))
             {
                 l_scom_buffer.insert<43, 5, 59, uint64_t>(literal_0b00110 );
             }
-            else if ((((l_def_half_dimm_mode == literal_1) && (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] != literal_1))
-                      && (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] != literal_1)))
+            else if ((((l_def_half_dimm_mode == literal_1) && (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] != literal_1))
+                      && (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] != literal_1)))
             {
                 l_scom_buffer.insert<43, 5, 59, uint64_t>(literal_0b00111 );
             }
-            else if (((l_def_half_dimm_mode == literal_0) && ((l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] == literal_1)
-                      || (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] == literal_1))))
+            else if (((l_def_half_dimm_mode == literal_0) && ((l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] == literal_1)
+                      || (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] == literal_1))))
             {
                 l_scom_buffer.insert<43, 5, 59, uint64_t>(literal_0b00111 );
             }
-            else if ((((l_def_half_dimm_mode == literal_0) && (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] != literal_1))
-                      && (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] != literal_1)))
+            else if ((((l_def_half_dimm_mode == literal_0) && (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] != literal_1))
+                      && (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] != literal_1)))
             {
                 l_scom_buffer.insert<43, 5, 59, uint64_t>(literal_0b01000 );
             }
 
-            if (((l_def_half_dimm_mode == literal_1) && ((l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] == literal_1)
-                    || (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] == literal_1))))
+            if (((l_def_half_dimm_mode == literal_1) && ((l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] == literal_1)
+                    || (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] == literal_1))))
             {
                 l_scom_buffer.insert<51, 5, 59, uint64_t>(literal_0b00111 );
             }
-            else if ((((l_def_half_dimm_mode == literal_1) && (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] != literal_1))
-                      && (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] != literal_1)))
+            else if ((((l_def_half_dimm_mode == literal_1) && (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] != literal_1))
+                      && (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] != literal_1)))
             {
                 l_scom_buffer.insert<51, 5, 59, uint64_t>(literal_0b01000 );
             }
-            else if (((l_def_half_dimm_mode == literal_0) && ((l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] == literal_1)
-                      || (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] == literal_1))))
+            else if (((l_def_half_dimm_mode == literal_0) && ((l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] == literal_1)
+                      || (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] == literal_1))))
             {
                 l_scom_buffer.insert<51, 5, 59, uint64_t>(literal_0b01000 );
             }
-            else if ((((l_def_half_dimm_mode == literal_0) && (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] != literal_1))
-                      && (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] != literal_1)))
+            else if ((((l_def_half_dimm_mode == literal_0) && (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] != literal_1))
+                      && (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] != literal_1)))
             {
                 l_scom_buffer.insert<51, 5, 59, uint64_t>(literal_0b01001 );
             }
 
-            if (((l_def_half_dimm_mode == literal_1) && ((l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] == literal_1)
-                    || (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] == literal_1))))
+            if (((l_def_half_dimm_mode == literal_1) && ((l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] == literal_1)
+                    || (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] == literal_1))))
             {
                 l_scom_buffer.insert<59, 5, 59, uint64_t>(literal_0b01000 );
             }
-            else if ((((l_def_half_dimm_mode == literal_1) && (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] != literal_1))
-                      && (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] != literal_1)))
+            else if ((((l_def_half_dimm_mode == literal_1) && (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] != literal_1))
+                      && (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] != literal_1)))
             {
                 l_scom_buffer.insert<59, 5, 59, uint64_t>(literal_0b01001 );
             }
-            else if (((l_def_half_dimm_mode == literal_0) && ((l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] == literal_1)
-                      || (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] == literal_1))))
+            else if (((l_def_half_dimm_mode == literal_0) && ((l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] == literal_1)
+                      || (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] == literal_1))))
             {
                 l_scom_buffer.insert<59, 5, 59, uint64_t>(literal_0b01001 );
             }
-            else if ((((l_def_half_dimm_mode == literal_0) && (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] != literal_1))
-                      && (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] != literal_1)))
+            else if ((((l_def_half_dimm_mode == literal_0) && (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] != literal_1))
+                      && (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] != literal_1)))
             {
                 l_scom_buffer.insert<59, 5, 59, uint64_t>(literal_0b01010 );
             }
@@ -1646,44 +1648,44 @@ fapi2::ReturnCode explorer_scom(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP
                 l_scom_buffer.insert<19, 5, 59, uint64_t>(literal_0b00101 );
             }
 
-            if (((l_def_half_dimm_mode == literal_1) && ((l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] == literal_1)
-                    || (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] == literal_1))))
+            if (((l_def_half_dimm_mode == literal_1) && ((l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] == literal_1)
+                    || (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] == literal_1))))
             {
                 l_scom_buffer.insert<3, 5, 59, uint64_t>(literal_0b01001 );
             }
-            else if ((((l_def_half_dimm_mode == literal_1) && (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] != literal_1))
-                      && (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] != literal_1)))
+            else if ((((l_def_half_dimm_mode == literal_1) && (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] != literal_1))
+                      && (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] != literal_1)))
             {
                 l_scom_buffer.insert<3, 5, 59, uint64_t>(literal_0b01010 );
             }
-            else if (((l_def_half_dimm_mode == literal_0) && ((l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] == literal_1)
-                      || (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] == literal_1))))
+            else if (((l_def_half_dimm_mode == literal_0) && ((l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] == literal_1)
+                      || (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] == literal_1))))
             {
                 l_scom_buffer.insert<3, 5, 59, uint64_t>(literal_0b01010 );
             }
-            else if ((((l_def_half_dimm_mode == literal_0) && (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] != literal_1))
-                      && (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] != literal_1)))
+            else if ((((l_def_half_dimm_mode == literal_0) && (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] != literal_1))
+                      && (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] != literal_1)))
             {
                 l_scom_buffer.insert<3, 5, 59, uint64_t>(literal_0b01011 );
             }
 
-            if (((l_def_half_dimm_mode == literal_1) && ((l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] == literal_1)
-                    || (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] == literal_1))))
+            if (((l_def_half_dimm_mode == literal_1) && ((l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] == literal_1)
+                    || (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] == literal_1))))
             {
                 l_scom_buffer.insert<11, 5, 59, uint64_t>(literal_0b01010 );
             }
-            else if ((((l_def_half_dimm_mode == literal_1) && (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] != literal_1))
-                      && (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] != literal_1)))
+            else if ((((l_def_half_dimm_mode == literal_1) && (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] != literal_1))
+                      && (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] != literal_1)))
             {
                 l_scom_buffer.insert<11, 5, 59, uint64_t>(literal_0b01011 );
             }
-            else if (((l_def_half_dimm_mode == literal_0) && ((l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] == literal_1)
-                      || (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] == literal_1))))
+            else if (((l_def_half_dimm_mode == literal_0) && ((l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] == literal_1)
+                      || (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] == literal_1))))
             {
                 l_scom_buffer.insert<11, 5, 59, uint64_t>(literal_0b01011 );
             }
-            else if ((((l_def_half_dimm_mode == literal_0) && (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] != literal_1))
-                      && (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] != literal_1)))
+            else if ((((l_def_half_dimm_mode == literal_0) && (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] != literal_1))
+                      && (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] != literal_1)))
             {
                 l_scom_buffer.insert<11, 5, 59, uint64_t>(literal_0b01100 );
             }
diff --git a/src/import/generic/memory/lib/data_engine/attr_engine_traits.H b/src/import/generic/memory/lib/data_engine/attr_engine_traits.H
index 1d7388f65..cc61ea602 100644
--- a/src/import/generic/memory/lib/data_engine/attr_engine_traits.H
+++ b/src/import/generic/memory/lib/data_engine/attr_engine_traits.H
@@ -51,6 +51,283 @@ namespace mss
 ///
 /// @brief Traits for attr_engine
 /// @class attrEngineTraits
+/// @note attr_eff_engine_fields, PRIM_STACK_TYPE specialization
+///
+template<>
+struct attrEngineTraits<attr_eff_engine_fields, PRIM_STACK_TYPE>
+{
+    using attr_type = fapi2::ATTR_MEM_EFF_PRIM_STACK_TYPE_Type;
+    using attr_integral_type = std::remove_all_extents<attr_type>::type;
+    static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_PRIM_STACK_TYPE_TargetType;
+    static constexpr generic_ffdc_codes FFDC_CODE = SET_PRIM_STACK_TYPE;
+
+    ///
+    /// @brief attribute getter
+    /// @param[in] i_target the fapi2 target
+    /// @param[out] o_setting array to populate
+    /// @return FAPI2_RC_SUCCESS iff okay
+    ///
+    static inline fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target,
+            attr_type& o_setting)
+    {
+        return mss::attr::get_prim_stack_type(i_target, o_setting);
+    }
+
+    ///
+    /// @brief attribute setter
+    /// @param[in] i_target the fapi2 target
+    /// @param[in] i_setting array to set
+    /// @return FAPI2_RC_SUCCESS iff okay
+    ///
+    static inline fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target,
+            attr_type& i_setting)
+    {
+        return mss::attr::set_prim_stack_type(i_target, i_setting);
+    }
+
+    ///
+    /// @brief Computes setting for attribute
+    /// @param[in] i_efd_data EFD data
+    /// @param[out] o_setting value we want to set attr with
+    /// @return FAPI2_RC_SUCCESS iff okay
+    ///
+    static inline fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data,
+            attr_integral_type& o_setting)
+    {
+        return i_spd_data.prim_sdram_signal_loading(o_setting);
+    }
+};
+
+///
+/// @brief Traits for attr_engine
+/// @class attrEngineTraits
+/// @note attr_eff_engine_fields, PRIM_DIE_COUNT specialization
+///
+template<>
+struct attrEngineTraits<attr_eff_engine_fields, PRIMARY_DIE_COUNT>
+{
+    using attr_type = fapi2::ATTR_MEM_EFF_PRIM_DIE_COUNT_Type;
+    using attr_integral_type = std::remove_all_extents<attr_type>::type;
+    static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_PRIM_DIE_COUNT_TargetType;
+    static constexpr generic_ffdc_codes FFDC_CODE = SET_PRIM_DIE_COUNT;
+
+    ///
+    /// @brief attribute getter
+    /// @param[in] i_target the fapi2 target
+    /// @param[out] o_setting array to populate
+    /// @return FAPI2_RC_SUCCESS iff okay
+    ///
+    static inline fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target,
+            attr_type& o_setting)
+    {
+        return mss::attr::get_prim_die_count(i_target, o_setting);
+    }
+
+    ///
+    /// @brief attribute setter
+    /// @param[in] i_target the fapi2 target
+    /// @param[in] i_setting array to set
+    /// @return FAPI2_RC_SUCCESS iff okay
+    ///
+    static inline fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target,
+            attr_type& i_setting)
+    {
+        return mss::attr::set_prim_die_count(i_target, i_setting);
+    }
+
+    ///
+    /// @brief Computes setting for attribute
+    /// @param[in] i_efd_data EFD data
+    /// @param[out] o_setting value we want to set attr with
+    /// @return FAPI2_RC_SUCCESS iff okay
+    ///
+    static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data,
+            attr_integral_type& o_setting)
+    {
+        // =========================================================
+        // Byte 6 maps
+        // Item JC-45-2220.01x
+        // Page 19
+        // DDR4 SPD Document Release 3
+        // Byte 6 (0x006): Primary SDRAM Package Type
+        // =========================================================
+        static const std::vector<std::pair<uint8_t, uint8_t> > PRIM_DIE_COUNT_MAP =
+        {
+            // {key byte, number of die}
+            {0, fapi2::ENUM_ATTR_MEM_EFF_PRIM_DIE_COUNT_D1},
+            {1, fapi2::ENUM_ATTR_MEM_EFF_PRIM_DIE_COUNT_D2},
+            {2, fapi2::ENUM_ATTR_MEM_EFF_PRIM_DIE_COUNT_D3},
+            {3, fapi2::ENUM_ATTR_MEM_EFF_PRIM_DIE_COUNT_D4},
+            {4, fapi2::ENUM_ATTR_MEM_EFF_PRIM_DIE_COUNT_D5},
+            {5, fapi2::ENUM_ATTR_MEM_EFF_PRIM_DIE_COUNT_D6},
+            {6, fapi2::ENUM_ATTR_MEM_EFF_PRIM_DIE_COUNT_D7},
+            {7, fapi2::ENUM_ATTR_MEM_EFF_PRIM_DIE_COUNT_D8}
+        };
+
+        const auto l_dimm = i_spd_data.get_dimm_target();
+
+        attr_integral_type l_decoder_val = 0;
+        FAPI_TRY( i_spd_data.prim_sdram_die_count(l_decoder_val) );
+
+        // Map SPD value to desired setting
+        FAPI_TRY(lookup_table_check(l_dimm, PRIM_DIE_COUNT_MAP, FFDC_CODE, l_decoder_val, o_setting));
+
+    fapi_try_exit:
+        return fapi2::current_err;
+    }
+};
+
+///
+/// @brief Traits for pre_data_engine
+/// @class attrEngineTraits
+/// @note attr_eff_engine_fields, DRAM_DENSITY specialization
+///
+template<>
+struct attrEngineTraits<attr_eff_engine_fields, DRAM_DENSITY>
+{
+    using attr_type = fapi2::ATTR_MEM_EFF_DRAM_DENSITY_Type;
+    using attr_integral_type = std::remove_all_extents<attr_type>::type;
+    static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_DRAM_DENSITY_TargetType;
+    static constexpr generic_ffdc_codes FFDC_CODE = SET_DRAM_DENSITY;
+
+    ///
+    /// @brief attribute getter
+    /// @param[in] i_target the attr target
+    /// @param[out] o_setting array to populate
+    /// @return FAPI2_RC_SUCCESS iff okay
+    ///
+    static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target,
+                                      attr_type& o_setting)
+    {
+        return mss::attr::get_dram_density(i_target, o_setting);
+    }
+
+    ///
+    /// @brief attribute setter
+    /// @param[in] i_target the attr target
+    /// @param[in] i_setting array to set
+    /// @return FAPI2_RC_SUCCESS iff okay
+    ///
+    static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target,
+                                      attr_type& i_setting)
+    {
+        return mss::attr::set_dram_density(i_target, i_setting);
+    }
+
+    ///
+    /// @brief Computes setting for attribute
+    /// @param[in] i_spd_data SPD data
+    /// @param[in] i_setting value we want to set attr with
+    /// @return FAPI2_RC_SUCCESS iff okay
+    ///
+    static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data,
+            attr_integral_type& o_setting)
+    {
+        // =========================================================
+        // DDR4 SPD Document Release 4
+        // Byte 2 (0x002): Key Byte / DRAM Device Type
+        // =========================================================
+        static const std::vector< std::pair<uint8_t, uint8_t> > DRAM_DENSITY_MAP =
+        {
+            // {key byte, capacity in GBs}
+            {4, fapi2::ENUM_ATTR_MEM_EFF_DRAM_DENSITY_4G},
+            {5, fapi2::ENUM_ATTR_MEM_EFF_DRAM_DENSITY_8G},
+            {6, fapi2::ENUM_ATTR_MEM_EFF_DRAM_DENSITY_16G},
+        };
+
+        const auto l_dimm = i_spd_data.get_dimm_target();
+
+        attr_integral_type l_sdram_density = 0;
+        FAPI_TRY( i_spd_data.sdram_density(l_sdram_density),
+                  "%s failed to get device type from SPD", spd::c_str(l_dimm) );
+
+        FAPI_TRY( lookup_table_check(l_dimm, DRAM_DENSITY_MAP, FFDC_CODE, l_sdram_density, o_setting),
+                  "%s failed DRAM_DENSITY lookup check", spd::c_str(l_dimm) );
+
+    fapi_try_exit:
+        return fapi2::current_err;
+    }
+};
+
+///
+/// @brief Traits for attr_engine
+/// @class attrEngineTraits
+/// @note attr_engine_derived_fields, BUS_WIDTH specialization
+///
+template<>
+struct attrEngineTraits<attr_eff_engine_fields, PRIM_BUS_WIDTH>
+{
+    using attr_type = fapi2::ATTR_MEM_EFF_PRIM_BUS_WIDTH_Type;
+    using attr_integral_type = std::remove_all_extents<attr_type>::type;
+    static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_PRIM_BUS_WIDTH_TargetType;
+    static constexpr generic_ffdc_codes FFDC_CODE = SET_PRIM_BUS_WIDTH;
+
+    ///
+    /// @brief attribute getter
+    /// @param[in] i_target the fapi2 target
+    /// @param[out] o_setting array to populate
+    /// @return FAPI2_RC_SUCCESS iff okay
+    ///
+    static inline fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target,
+            attr_type& o_setting)
+    {
+        return mss::attr::get_prim_bus_width(i_target, o_setting);
+    }
+
+    ///
+    /// @brief attribute setter
+    /// @param[in] i_target the fapi2 target
+    /// @param[in] i_setting array to set
+    /// @return FAPI2_RC_SUCCESS iff okay
+    ///
+    static inline fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target,
+            attr_type& i_setting)
+    {
+        return mss::attr::set_prim_bus_width(i_target, i_setting);
+    }
+
+    ///
+    /// @brief Computes setting for attribute
+    /// @param[in] i_efd_data EFD data
+    /// @param[out] o_setting value we want to set attr with
+    /// @return FAPI2_RC_SUCCESS iff okay
+
+    static inline fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data,
+            attr_integral_type& o_setting)
+    {
+        // =========================================================
+        // Byte 13 maps
+        // Item JC-45-2220.01x
+        // Page 27
+        // DDR4 SPD Document Release 3
+        // Byte 13 (0x00D): Module Memory Bus Width
+        // =========================================================
+        const std::vector<std::pair<uint8_t, uint8_t> > BUS_WIDTH_MAP =
+        {
+            // {key byte, bus width (in bits)
+            {0, fapi2::ENUM_ATTR_MEM_EFF_PRIM_BUS_WIDTH_8_BITS},
+            {1, fapi2::ENUM_ATTR_MEM_EFF_PRIM_BUS_WIDTH_16_BITS},
+            {2, fapi2::ENUM_ATTR_MEM_EFF_PRIM_BUS_WIDTH_32_BITS},
+            {3, fapi2::ENUM_ATTR_MEM_EFF_PRIM_BUS_WIDTH_64_BITS}
+            // All others reserved
+        };
+
+        const auto l_dimm = i_spd_data.get_dimm_target();
+
+        attr_integral_type l_spd_bus_width = 0;
+        FAPI_TRY( i_spd_data.prim_bus_width(l_spd_bus_width) );
+
+        // Map SPD value to desired setting
+        FAPI_TRY(lookup_table_check(l_dimm, BUS_WIDTH_MAP, FFDC_CODE, l_spd_bus_width, o_setting));
+
+    fapi_try_exit:
+        return fapi2::current_err;
+    }
+};
+
+///
+/// @brief Traits for attr_engine
+/// @class attrEngineTraits
 /// @note attr_eff_engine_fields, DRAM_WIDTH specialization
 ///
 template<>
@@ -67,8 +344,8 @@ struct attrEngineTraits<attr_eff_engine_fields, DRAM_WIDTH>
     /// @param[out] o_setting array to populate
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
-    static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target,
-                                      attr_type& o_setting)
+    static inline fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target,
+            attr_type& o_setting)
     {
         return mss::attr::get_dram_width(i_target, o_setting);
     }
@@ -79,8 +356,8 @@ struct attrEngineTraits<attr_eff_engine_fields, DRAM_WIDTH>
     /// @param[in] i_setting array to set
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
-    static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target,
-                                      attr_type& i_setting)
+    static inline fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target,
+            attr_type& i_setting)
     {
         return mss::attr::set_dram_width(i_target, i_setting);
     }
@@ -88,13 +365,12 @@ struct attrEngineTraits<attr_eff_engine_fields, DRAM_WIDTH>
     ///
     /// @brief Computes setting for attribute
     /// @param[in] i_efd_data EFD data
-    /// @param[in] i_setting value we want to set attr with
+    /// @param[out] o_setting value we want to set attr with
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
     static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data,
             attr_integral_type& o_setting)
     {
-
         // =========================================================
         // Byte 12 maps
         // Item JC-45-2220.01x
@@ -113,11 +389,13 @@ struct attrEngineTraits<attr_eff_engine_fields, DRAM_WIDTH>
         };
 
         // Read SPD value
+        const auto l_dimm = i_spd_data.get_dimm_target();
+
         attr_integral_type l_value = 0;
         FAPI_TRY( i_spd_data.device_width(l_value) );
 
         // Map SPD value to desired setting
-        FAPI_TRY(lookup_table_check(i_spd_data.get_dimm_target(), DRAM_WIDTH_MAP, SET_DRAM_WIDTH, l_value, o_setting));
+        FAPI_TRY(lookup_table_check(l_dimm, DRAM_WIDTH_MAP, SET_DRAM_WIDTH, l_value, o_setting));
 
     fapi_try_exit:
         return fapi2::current_err;
@@ -155,8 +433,8 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_RCV_IMP_DQ_DQS>
     /// @param[out] o_setting array to populate
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
-    static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target,
-                                      attr_type& o_setting)
+    static inline fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target,
+            attr_type& o_setting)
     {
         return mss::attr::get_si_mc_rcv_imp_dq_dqs(i_target, o_setting);
     }
@@ -167,8 +445,8 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_RCV_IMP_DQ_DQS>
     /// @param[in] i_setting array to set
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
-    static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target,
-                                      attr_type& i_setting)
+    static inline fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target,
+            attr_type& i_setting)
     {
         return mss::attr::set_si_mc_rcv_imp_dq_dqs(i_target, i_setting);
     }
@@ -176,10 +454,10 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_RCV_IMP_DQ_DQS>
     ///
     /// @brief Computes setting for attribute
     /// @param[in] i_efd_data EFD data
-    /// @param[in] i_setting value we want to set attr with
+    /// @param[out] o_setting value we want to set attr with
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
-    static fapi2::ReturnCode get_value_to_set(const std::shared_ptr<efd::base_decoder>& i_efd_data,
+    static inline fapi2::ReturnCode get_value_to_set(const std::shared_ptr<efd::base_decoder>& i_efd_data,
             attr_integral_type& o_setting)
     {
         return i_efd_data->phy_odt_impedance(o_setting);
@@ -205,8 +483,8 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_DRV_IMP_DQ_DQS_PULL_UP>
     /// @param[out] o_setting array to populate
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
-    static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target,
-                                      attr_type& o_setting)
+    static inline fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target,
+            attr_type& o_setting)
     {
         return mss::attr::get_si_mc_drv_imp_dq_dqs_pull_up(i_target, o_setting);
     }
@@ -217,8 +495,8 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_DRV_IMP_DQ_DQS_PULL_UP>
     /// @param[in] i_setting array to set
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
-    static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target,
-                                      attr_type& i_setting)
+    static inline fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target,
+            attr_type& i_setting)
     {
         return mss::attr::set_si_mc_drv_imp_dq_dqs_pull_up(i_target, i_setting);
     }
@@ -226,10 +504,10 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_DRV_IMP_DQ_DQS_PULL_UP>
     ///
     /// @brief Computes setting for attribute
     /// @param[in] i_efd_data EFD data
-    /// @param[in] i_setting value we want to set attr with
+    /// @param[out] o_setting value we want to set attr with
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
-    static fapi2::ReturnCode get_value_to_set(const std::shared_ptr<efd::base_decoder>& i_efd_data,
+    static inline fapi2::ReturnCode get_value_to_set(const std::shared_ptr<efd::base_decoder>& i_efd_data,
             attr_integral_type& o_setting)
     {
         return i_efd_data->phy_drive_impedance_pull_up(o_setting);
@@ -255,8 +533,8 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_DRV_IMP_DQ_DQS_PULL_DOWN>
     /// @param[out] o_setting array to populate
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
-    static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target,
-                                      attr_type& o_setting)
+    static inline fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target,
+            attr_type& o_setting)
     {
         return mss::attr::get_si_mc_drv_imp_dq_dqs_pull_down(i_target, o_setting);
     }
@@ -267,8 +545,8 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_DRV_IMP_DQ_DQS_PULL_DOWN>
     /// @param[in] i_setting array to set
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
-    static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target,
-                                      attr_type& i_setting)
+    static inline fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target,
+            attr_type& i_setting)
     {
         return mss::attr::set_si_mc_drv_imp_dq_dqs_pull_down(i_target, i_setting);
     }
@@ -276,10 +554,10 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_DRV_IMP_DQ_DQS_PULL_DOWN>
     ///
     /// @brief Computes setting for attribute
     /// @param[in] i_efd_data EFD data
-    /// @param[in] i_setting value we want to set attr with
+    /// @param[out] o_setting value we want to set attr with
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
-    static fapi2::ReturnCode get_value_to_set(const std::shared_ptr<efd::base_decoder>& i_efd_data,
+    static inline fapi2::ReturnCode get_value_to_set(const std::shared_ptr<efd::base_decoder>& i_efd_data,
             attr_integral_type& o_setting)
     {
         return i_efd_data->phy_drive_impedance_pull_down(o_setting);
@@ -306,8 +584,8 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_DRV_SLEW_RATE_DQ_DQS>
     /// @param[out] o_setting array to populate
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
-    static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target,
-                                      attr_type& o_setting)
+    static inline fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target,
+            attr_type& o_setting)
     {
         return mss::attr::get_si_mc_drv_slew_rate_dq_dqs(i_target, o_setting);
     }
@@ -318,8 +596,8 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_DRV_SLEW_RATE_DQ_DQS>
     /// @param[in] i_setting array to set
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
-    static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target,
-                                      attr_type& i_setting)
+    static inline fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target,
+            attr_type& i_setting)
     {
         return mss::attr::set_si_mc_drv_slew_rate_dq_dqs(i_target, i_setting);
     }
@@ -327,10 +605,10 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_DRV_SLEW_RATE_DQ_DQS>
     ///
     /// @brief Computes setting for attribute
     /// @param[in] i_efd_data EFD data
-    /// @param[in] i_setting value we want to set attr with
+    /// @param[out] o_setting value we want to set attr with
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
-    static fapi2::ReturnCode get_value_to_set(const std::shared_ptr<efd::base_decoder>& i_efd_data,
+    static inline fapi2::ReturnCode get_value_to_set(const std::shared_ptr<efd::base_decoder>& i_efd_data,
             attr_integral_type& o_setting)
     {
         return i_efd_data->phy_slew_rate_dq_dqs(o_setting);
@@ -356,8 +634,8 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_DRV_IMP_CMD_ADDR>
     /// @param[out] o_setting array to populate
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
-    static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target,
-                                      attr_type& o_setting)
+    static inline fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target,
+            attr_type& o_setting)
     {
         return mss::attr::get_si_mc_drv_imp_cmd_addr(i_target, o_setting);
     }
@@ -368,8 +646,8 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_DRV_IMP_CMD_ADDR>
     /// @param[in] i_setting array to set
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
-    static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target,
-                                      attr_type& i_setting)
+    static inline fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target,
+            attr_type& i_setting)
     {
         return mss::attr::set_si_mc_drv_imp_cmd_addr(i_target, i_setting);
     }
@@ -377,10 +655,10 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_DRV_IMP_CMD_ADDR>
     ///
     /// @brief Computes setting for attribute
     /// @param[in] i_efd_data EFD data
-    /// @param[in] i_setting value we want to set attr with
+    /// @param[out] o_setting value we want to set attr with
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
-    static fapi2::ReturnCode get_value_to_set(const std::shared_ptr<efd::base_decoder>& i_efd_data,
+    static inline fapi2::ReturnCode get_value_to_set(const std::shared_ptr<efd::base_decoder>& i_efd_data,
             attr_integral_type& o_setting)
     {
         return i_efd_data->atx_impedance(o_setting);
@@ -406,8 +684,8 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_DRV_SLEW_RATE_CMD_ADDR>
     /// @param[out] o_setting array to populate
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
-    static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target,
-                                      attr_type& o_setting)
+    static inline fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target,
+            attr_type& o_setting)
     {
         return mss::attr::get_si_mc_drv_slew_rate_cmd_addr(i_target, o_setting);
     }
@@ -418,8 +696,8 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_DRV_SLEW_RATE_CMD_ADDR>
     /// @param[in] i_setting array to set
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
-    static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target,
-                                      attr_type& i_setting)
+    static inline fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target,
+            attr_type& i_setting)
     {
         return mss::attr::set_si_mc_drv_slew_rate_cmd_addr(i_target, i_setting);
     }
@@ -427,10 +705,10 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_DRV_SLEW_RATE_CMD_ADDR>
     ///
     /// @brief Computes setting for attribute
     /// @param[in] i_efd_data EFD data
-    /// @param[in] i_setting value we want to set attr with
+    /// @param[out] o_setting value we want to set attr with
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
-    static fapi2::ReturnCode get_value_to_set(const std::shared_ptr<efd::base_decoder>& i_efd_data,
+    static inline fapi2::ReturnCode get_value_to_set(const std::shared_ptr<efd::base_decoder>& i_efd_data,
             attr_integral_type& o_setting)
     {
         return i_efd_data->atx_slew_rate(o_setting);
@@ -456,8 +734,8 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_DRV_IMP_CLK>
     /// @param[out] o_setting array to populate
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
-    static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target,
-                                      attr_type& o_setting)
+    static inline fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target,
+            attr_type& o_setting)
     {
         return mss::attr::get_si_mc_drv_imp_clk(i_target, o_setting);
     }
@@ -468,8 +746,8 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_DRV_IMP_CLK>
     /// @param[in] i_setting array to set
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
-    static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target,
-                                      attr_type& i_setting)
+    static inline fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target,
+            attr_type& i_setting)
     {
         return mss::attr::set_si_mc_drv_imp_clk(i_target, i_setting);
     }
@@ -480,7 +758,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_DRV_IMP_CLK>
     /// @param[out] o_setting value we want to set attr with
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
-    static fapi2::ReturnCode get_value_to_set(const std::shared_ptr<efd::base_decoder>& i_efd_data,
+    static inline fapi2::ReturnCode get_value_to_set(const std::shared_ptr<efd::base_decoder>& i_efd_data,
             attr_integral_type& o_setting)
     {
         return i_efd_data->ck_impedance(o_setting);
@@ -506,8 +784,8 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_DRV_SLEW_RATE_CLK>
     /// @param[out] o_setting array to populate
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
-    static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target,
-                                      attr_type& o_setting)
+    static inline fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target,
+            attr_type& o_setting)
     {
         return mss::attr::get_si_mc_drv_slew_rate_clk(i_target, o_setting);
     }
@@ -518,8 +796,8 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_DRV_SLEW_RATE_CLK>
     /// @param[in] i_setting array to set
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
-    static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target,
-                                      attr_type& i_setting)
+    static inline fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target,
+            attr_type& i_setting)
     {
         return mss::attr::set_si_mc_drv_slew_rate_clk(i_target, i_setting);
     }
@@ -530,7 +808,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_DRV_SLEW_RATE_CLK>
     /// @param[out] o_setting value we want to set attr with
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
-    static fapi2::ReturnCode get_value_to_set(const std::shared_ptr<efd::base_decoder>& i_efd_data,
+    static inline fapi2::ReturnCode get_value_to_set(const std::shared_ptr<efd::base_decoder>& i_efd_data,
             attr_integral_type& o_setting)
     {
         return i_efd_data->ck_slew_rate(o_setting);
@@ -556,8 +834,8 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_RCV_IMP_ALERT_N>
     /// @param[out] o_setting array to populate
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
-    static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target,
-                                      attr_type& o_setting)
+    static inline fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target,
+            attr_type& o_setting)
     {
         return mss::attr::get_si_mc_rcv_imp_alert_n(i_target, o_setting);
     }
@@ -568,8 +846,8 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_RCV_IMP_ALERT_N>
     /// @param[in] i_setting array to set
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
-    static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target,
-                                      attr_type& i_setting)
+    static inline fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target,
+            attr_type& i_setting)
     {
         return mss::attr::set_si_mc_rcv_imp_alert_n(i_target, i_setting);
     }
@@ -580,7 +858,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_RCV_IMP_ALERT_N>
     /// @param[out] o_setting value we want to set attr with
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
-    static fapi2::ReturnCode get_value_to_set(const std::shared_ptr<efd::base_decoder>& i_efd_data,
+    static inline fapi2::ReturnCode get_value_to_set(const std::shared_ptr<efd::base_decoder>& i_efd_data,
             attr_integral_type& o_setting)
     {
         return i_efd_data->alert_odt_impedance(o_setting);
@@ -606,8 +884,8 @@ struct attrEngineTraits<attr_si_engine_fields, SI_DRAM_RTT_NOM>
     /// @param[out] o_setting array to populate
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
-    static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target,
-                                      attr_type& o_setting)
+    static inline fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target,
+            attr_type& o_setting)
     {
         return mss::attr::get_si_dram_rtt_nom(i_target, o_setting);
     }
@@ -618,8 +896,8 @@ struct attrEngineTraits<attr_si_engine_fields, SI_DRAM_RTT_NOM>
     /// @param[in] i_setting array to set
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
-    static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target,
-                                      attr_type& i_setting)
+    static inline fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target,
+            attr_type& i_setting)
     {
         return mss::attr::set_si_dram_rtt_nom(i_target, i_setting);
     }
@@ -630,7 +908,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_DRAM_RTT_NOM>
     /// @param[out] o_setting value we want to set attr with
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
-    static fapi2::ReturnCode get_value_to_set(const std::shared_ptr<efd::base_decoder>& i_efd_data,
+    static inline fapi2::ReturnCode get_value_to_set(const std::shared_ptr<efd::base_decoder>& i_efd_data,
             attr_integral_type& o_setting)
     {
         return i_efd_data->dram_rtt_nom(o_setting);
@@ -656,8 +934,8 @@ struct attrEngineTraits<attr_si_engine_fields, SI_DRAM_RTT_WR>
     /// @param[out] o_setting array to populate
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
-    static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target,
-                                      attr_type& o_setting)
+    static inline fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target,
+            attr_type& o_setting)
     {
         return mss::attr::get_si_dram_rtt_wr(i_target, o_setting);
     }
@@ -668,8 +946,8 @@ struct attrEngineTraits<attr_si_engine_fields, SI_DRAM_RTT_WR>
     /// @param[in] i_setting array to set
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
-    static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target,
-                                      attr_type& i_setting)
+    static inline fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target,
+            attr_type& i_setting)
     {
         return mss::attr::set_si_dram_rtt_wr(i_target, i_setting);
     }
@@ -680,7 +958,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_DRAM_RTT_WR>
     /// @param[out] o_setting value we want to set attr with
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
-    static fapi2::ReturnCode get_value_to_set(const std::shared_ptr<efd::base_decoder>& i_efd_data,
+    static inline fapi2::ReturnCode get_value_to_set(const std::shared_ptr<efd::base_decoder>& i_efd_data,
             attr_integral_type& o_setting)
     {
         return i_efd_data->dram_rtt_wr(o_setting);
@@ -706,8 +984,8 @@ struct attrEngineTraits<attr_si_engine_fields, SI_DRAM_RTT_PARK>
     /// @param[out] o_setting array to populate
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
-    static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target,
-                                      attr_type& o_setting)
+    static inline fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target,
+            attr_type& o_setting)
     {
         return mss::attr::get_si_dram_rtt_park(i_target, o_setting);
     }
@@ -718,8 +996,8 @@ struct attrEngineTraits<attr_si_engine_fields, SI_DRAM_RTT_PARK>
     /// @param[in] i_setting array to set
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
-    static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target,
-                                      attr_type& i_setting)
+    static inline fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target,
+            attr_type& i_setting)
     {
         return mss::attr::set_si_dram_rtt_park(i_target, i_setting);
     }
@@ -730,7 +1008,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_DRAM_RTT_PARK>
     /// @param[out] o_setting value we want to set attr with
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
-    static fapi2::ReturnCode get_value_to_set(const std::shared_ptr<efd::base_decoder>& i_efd_data,
+    static inline fapi2::ReturnCode get_value_to_set(const std::shared_ptr<efd::base_decoder>& i_efd_data,
             attr_integral_type& o_setting)
     {
         return i_efd_data->dram_rtt_park(o_setting);
@@ -756,8 +1034,8 @@ struct attrEngineTraits<attr_si_engine_fields, SI_DRAM_PREAMBLE>
     /// @param[out] o_setting array to populate
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
-    static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target,
-                                      attr_type& o_setting)
+    static inline fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target,
+            attr_type& o_setting)
     {
         return mss::attr::get_si_dram_preamble(i_target, o_setting);
     }
@@ -768,8 +1046,8 @@ struct attrEngineTraits<attr_si_engine_fields, SI_DRAM_PREAMBLE>
     /// @param[in] i_setting array to set
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
-    static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target,
-                                      attr_type& i_setting)
+    static inline fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target,
+            attr_type& i_setting)
     {
         return mss::attr::set_si_dram_preamble(i_target, i_setting);
     }
@@ -780,7 +1058,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_DRAM_PREAMBLE>
     /// @param[out] o_setting value we want to set attr with
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
-    static fapi2::ReturnCode get_value_to_set(const std::shared_ptr<efd::base_decoder>& i_efd_data,
+    static inline fapi2::ReturnCode get_value_to_set(const std::shared_ptr<efd::base_decoder>& i_efd_data,
             attr_integral_type& o_setting)
     {
         i_efd_data->write_preamble(o_setting);
@@ -807,8 +1085,8 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_DRV_EQ_DQ_DQS>
     /// @param[out] o_setting array to populate
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
-    static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target,
-                                      attr_type& o_setting)
+    static inline fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target,
+            attr_type& o_setting)
     {
         return mss::attr::get_si_mc_drv_eq_dq_dqs(i_target, o_setting);
     }
@@ -819,8 +1097,8 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_DRV_EQ_DQ_DQS>
     /// @param[in] i_setting array to set
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
-    static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target,
-                                      attr_type& i_setting)
+    static inline fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target,
+            attr_type& i_setting)
     {
         return mss::attr::set_si_mc_drv_eq_dq_dqs(i_target, i_setting);
     }
@@ -831,7 +1109,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_DRV_EQ_DQ_DQS>
     /// @param[out] o_setting value we want to set attr with
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
-    static fapi2::ReturnCode get_value_to_set(const std::shared_ptr<efd::base_decoder>& i_efd_data,
+    static inline fapi2::ReturnCode get_value_to_set(const std::shared_ptr<efd::base_decoder>& i_efd_data,
             attr_integral_type& o_setting)
     {
         return i_efd_data->phy_equalization(o_setting);
@@ -857,8 +1135,8 @@ struct attrEngineTraits<attr_si_engine_fields, SI_DRAM_DRV_IMP_DQ_DQS>
     /// @param[out] o_setting array to populate
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
-    static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target,
-                                      attr_type& o_setting)
+    static inline fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target,
+            attr_type& o_setting)
     {
         return mss::attr::get_si_dram_drv_imp_dq_dqs(i_target, o_setting);
     }
@@ -869,8 +1147,8 @@ struct attrEngineTraits<attr_si_engine_fields, SI_DRAM_DRV_IMP_DQ_DQS>
     /// @param[in] i_setting array to set
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
-    static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target,
-                                      attr_type& i_setting)
+    static inline fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target,
+            attr_type& i_setting)
     {
         return mss::attr::set_si_dram_drv_imp_dq_dqs(i_target, i_setting);
     }
@@ -881,7 +1159,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_DRAM_DRV_IMP_DQ_DQS>
     /// @param[out] o_setting value we want to set attr with
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
-    static fapi2::ReturnCode get_value_to_set(const std::shared_ptr<efd::base_decoder>& i_efd_data,
+    static inline fapi2::ReturnCode get_value_to_set(const std::shared_ptr<efd::base_decoder>& i_efd_data,
             attr_integral_type& o_setting)
     {
         return i_efd_data->dram_dic(o_setting);
@@ -907,8 +1185,8 @@ struct attrEngineTraits<attr_si_engine_fields, SI_VREF_DQ_TRAIN_RANGE>
     /// @param[out] o_setting array to populate
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
-    static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target,
-                                      attr_type& o_setting)
+    static inline fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target,
+            attr_type& o_setting)
     {
         return mss::attr::get_si_vref_dq_train_range(i_target, o_setting);
     }
@@ -919,8 +1197,8 @@ struct attrEngineTraits<attr_si_engine_fields, SI_VREF_DQ_TRAIN_RANGE>
     /// @param[in] i_setting array to set
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
-    static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target,
-                                      attr_type& i_setting)
+    static inline fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target,
+            attr_type& i_setting)
     {
         return mss::attr::set_si_vref_dq_train_range(i_target, i_setting);
     }
@@ -931,7 +1209,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_VREF_DQ_TRAIN_RANGE>
     /// @param[out] o_setting value we want to set attr with
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
-    static fapi2::ReturnCode get_value_to_set(const std::shared_ptr<efd::base_decoder>& i_efd_data,
+    static inline fapi2::ReturnCode get_value_to_set(const std::shared_ptr<efd::base_decoder>& i_efd_data,
             attr_integral_type& o_setting)
     {
         return i_efd_data->wr_vref_dq_range(o_setting);
@@ -957,8 +1235,8 @@ struct attrEngineTraits<attr_si_engine_fields, SI_VREF_DQ_TRAIN_VALUE>
     /// @param[out] o_setting array to populate
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
-    static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target,
-                                      attr_type& o_setting)
+    static inline fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target,
+            attr_type& o_setting)
     {
         return mss::attr::get_si_vref_dq_train_value(i_target, o_setting);
     }
@@ -969,8 +1247,8 @@ struct attrEngineTraits<attr_si_engine_fields, SI_VREF_DQ_TRAIN_VALUE>
     /// @param[out] o_setting array to populate
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
-    static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target,
-                                      attr_type& o_setting)
+    static inline fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target,
+            attr_type& o_setting)
     {
         return mss::attr::set_si_vref_dq_train_value(i_target, o_setting);
     }
@@ -981,7 +1259,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_VREF_DQ_TRAIN_VALUE>
     /// @param[out] o_setting value we want to set attr with
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
-    static fapi2::ReturnCode get_value_to_set(const std::shared_ptr<efd::base_decoder>& i_efd_data,
+    static inline fapi2::ReturnCode get_value_to_set(const std::shared_ptr<efd::base_decoder>& i_efd_data,
             attr_integral_type& o_setting)
     {
         return i_efd_data->wr_vref_dq_value(o_setting);
@@ -1007,8 +1285,8 @@ struct attrEngineTraits<attr_si_engine_fields, SI_ODT_WR>
     /// @param[out] o_setting array to populate
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
-    static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target,
-                                      attr_type& o_setting)
+    static inline fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target,
+            attr_type& o_setting)
     {
         return mss::attr::get_si_odt_wr(i_target, o_setting);
     }
@@ -1019,8 +1297,8 @@ struct attrEngineTraits<attr_si_engine_fields, SI_ODT_WR>
     /// @param[in] i_setting array to set
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
-    static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target,
-                                      attr_type& i_setting)
+    static inline fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target,
+            attr_type& i_setting)
     {
         return mss::attr::set_si_odt_wr(i_target, i_setting);
     }
@@ -1092,8 +1370,8 @@ struct attrEngineTraits<attr_si_engine_fields, SI_ODT_RD>
     /// @param[out] o_setting array to populate
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
-    static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target,
-                                      attr_type& o_setting)
+    static inline fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target,
+            attr_type& o_setting)
     {
         return mss::attr::get_si_odt_rd(i_target, o_setting);
     }
@@ -1104,8 +1382,8 @@ struct attrEngineTraits<attr_si_engine_fields, SI_ODT_RD>
     /// @param[in] i_setting array to set
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
-    static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target,
-                                      attr_type& i_setting)
+    static inline fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target,
+            attr_type& i_setting)
     {
         return mss::attr::set_si_odt_rd(i_target, i_setting);
     }
@@ -1176,8 +1454,8 @@ struct attrEngineTraits<attr_si_engine_fields, SI_GEARDOWN_MODE>
     /// @param[out] o_setting array to populate
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
-    static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target,
-                                      attr_type& o_setting)
+    static inline fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target,
+            attr_type& o_setting)
     {
         return mss::attr::get_si_geardown_mode(i_target, o_setting);
     }
@@ -1188,8 +1466,8 @@ struct attrEngineTraits<attr_si_engine_fields, SI_GEARDOWN_MODE>
     /// @param[in] i_setting array to set
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
-    static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target,
-                                      attr_type& i_setting)
+    static inline fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target,
+            attr_type& i_setting)
     {
         return mss::attr::set_si_geardown_mode(i_target, i_setting);
     }
@@ -1200,13 +1478,155 @@ struct attrEngineTraits<attr_si_engine_fields, SI_GEARDOWN_MODE>
     /// @param[out] o_setting value we want to set attr with
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
-    static fapi2::ReturnCode get_value_to_set(const std::shared_ptr<efd::base_decoder>& i_efd_data,
+    static inline fapi2::ReturnCode get_value_to_set(const std::shared_ptr<efd::base_decoder>& i_efd_data,
             attr_integral_type& o_setting)
     {
         return i_efd_data->geardown_during_training(o_setting);
     }
 };
 
+//
+// Derived attributes
+//
+///
+
+/// @brief Traits for attrEngineTraits
+/// @class attrEngineTraits
+/// @note attrEngineTraits, MRANKS specialization
+///
+template<>
+struct attrEngineTraits<attr_engine_derived_fields, LOGICAL_RANKS>
+{
+    using attr_type = fapi2::ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM_Type;
+    using attr_integral_type = std::remove_all_extents<attr_type>::type;
+    static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM_TargetType;
+    static constexpr generic_ffdc_codes FFDC_CODE = SET_LOGICAL_RANKS;
+
+    ///
+    /// @brief attribute getter
+    /// @param[in] i_target the attr target
+    /// @param[out] o_setting array to populate
+    /// @return FAPI2_RC_SUCCESS iff okay
+    ///
+    static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target,
+                                      attr_type& o_setting)
+    {
+        return mss::attr::get_logical_ranks_per_dimm(i_target, o_setting);
+    }
+
+    ///
+    /// @brief attribute setter
+    /// @param[in] i_target the attr target
+    /// @param[in] i_setting array to set
+    /// @return FAPI2_RC_SUCCESS iff okay
+    ///
+    static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target,
+                                      attr_type& i_setting)
+    {
+        return mss::attr::set_logical_ranks_per_dimm(i_target, i_setting);
+    }
+
+    ///
+    /// @brief Computes setting for attribute
+    /// @param[in] i_spd_data SPD data
+    /// @param[out] o_setting value we want to set attr with
+    /// @return FAPI2_RC_SUCCESS iff okay
+    ///
+    static fapi2::ReturnCode get_value_to_set(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+            attr_integral_type& o_setting)
+    {
+        uint8_t l_prim_stack_type = 0;
+        uint8_t l_master_ranks = 0;
+        uint8_t l_die_count = 0;
+
+        FAPI_TRY( mss::attr::get_num_master_ranks_per_dimm(i_target, l_master_ranks) );
+        FAPI_TRY( mss::attr::get_prim_die_count(i_target, l_die_count) );
+        FAPI_TRY( mss::attr::get_prim_stack_type(i_target, l_prim_stack_type) );
+
+        {
+            // For single-load-stack(3DS) the logical ranks per package ends up being the same as the die count.
+            // For MONOLITHIC & MULTI_LOAD_STACK
+            // The die count isn't guaranteed to be 1 (e.g. SDP - 1 die package, DDP - 2 die package).
+            // Value of 1 has no meaning and is used for calculation purposes as defined by the SPD spec.
+            const auto l_multiplier = (l_prim_stack_type == fapi2::ENUM_ATTR_MEM_EFF_PRIM_STACK_TYPE_3DS) ? l_die_count : 1;
+            o_setting = (l_master_ranks * l_multiplier);
+            FAPI_DBG("Num Logical Ranks %d", o_setting);
+        }
+
+    fapi_try_exit:
+        return fapi2::current_err;
+    }
+};
+
+///
+/// @brief Traits for attr_engine
+/// @class attrEngineTraits
+/// @note attr_engine_derived_fields, MEM_DIMM_SIZE specialization
+///
+template<>
+struct attrEngineTraits<attr_engine_derived_fields, MEM_DIMM_SIZE>
+{
+    using attr_type = fapi2::ATTR_MEM_EFF_DIMM_SIZE_Type;
+    using attr_integral_type = std::remove_all_extents<attr_type>::type;
+    static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_DIMM_SIZE_TargetType;
+    static constexpr generic_ffdc_codes FFDC_CODE = SET_DIMM_SIZE;
+
+    ///
+    /// @brief attribute getter
+    /// @param[in] i_target the fapi2 target
+    /// @param[out] o_setting array to populate
+    /// @return FAPI2_RC_SUCCESS iff okay
+    ///
+    static inline fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target,
+            attr_type& o_setting)
+    {
+        return mss::attr::get_dimm_size(i_target, o_setting);
+    }
+
+    ///
+    /// @brief attribute setter
+    /// @param[in] i_target the fapi2 target
+    /// @param[in] i_setting array to set
+    /// @return FAPI2_RC_SUCCESS iff okay
+    ///
+    static inline fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target,
+            attr_type& i_setting)
+    {
+        return mss::attr::set_dimm_size(i_target, i_setting);
+    }
+
+    ///
+    /// @brief Computes setting for attribute
+    /// @param[in] i_efd_data EFD data
+    /// @param[out] o_setting value we want to set attr with
+    /// @return FAPI2_RC_SUCCESS iff okay
+
+    static inline fapi2::ReturnCode get_value_to_set(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+            attr_integral_type& o_setting)
+    {
+        uint8_t l_dram_width = 0;
+        uint8_t l_dram_density = 0;
+        uint8_t l_logical_rank_per_dimm = 0;
+        uint8_t l_bus_width = 0;
+
+        FAPI_TRY( mss::attr::get_dram_width(i_target, l_dram_width) );
+        FAPI_TRY( mss::attr::get_dram_density(i_target, l_dram_density) );
+        FAPI_TRY( mss::attr::get_logical_ranks_per_dimm(i_target, l_logical_rank_per_dimm) );
+        FAPI_TRY( mss::attr::get_prim_bus_width(i_target, l_bus_width) );
+
+        // Calculate dimm size
+        // Formula from SPD Spec (seriously, they don't have parenthesis in the spec)
+        // Total = SDRAM Capacity / 8 * Primary Bus Width / SDRAM Width * Logical Ranks per DIMM
+        o_setting = (l_dram_density * l_bus_width * l_logical_rank_per_dimm) / (8 * l_dram_width);
+
+        FAPI_DBG("DIMM size = %d => (%d * %d * %d) / (8 * %d)",
+                 o_setting, l_dram_density, l_bus_width, l_logical_rank_per_dimm, l_dram_width);
+
+    fapi_try_exit:
+        return fapi2::current_err;
+    }
+};
+
 }//mss
 
 #endif
diff --git a/src/import/generic/memory/lib/data_engine/data_engine.H b/src/import/generic/memory/lib/data_engine/data_engine.H
index aa0fb5f0a..806fbf024 100644
--- a/src/import/generic/memory/lib/data_engine/data_engine.H
+++ b/src/import/generic/memory/lib/data_engine/data_engine.H
@@ -190,6 +190,16 @@ struct attrEnumTraits<pre_data_init_fields>
 };
 
 ///
+/// @brief Value traits for attrEnumTraits
+/// @class attrEnumTraits - attr_eff_engine_fields specialization
+///
+template < >
+struct attrEnumTraits<attr_engine_derived_fields>
+{
+    static constexpr size_t DISPATCHER = ATTR_DERIVED_DISPATCHER;
+};
+
+///
 /// @brief attribute signal integrity engine
 /// @class attr_si_engine
 /// @tparam ET field enumeration type
diff --git a/src/import/generic/memory/lib/data_engine/data_engine_traits_def.H b/src/import/generic/memory/lib/data_engine/data_engine_traits_def.H
index be55890ea..813abbe33 100644
--- a/src/import/generic/memory/lib/data_engine/data_engine_traits_def.H
+++ b/src/import/generic/memory/lib/data_engine/data_engine_traits_def.H
@@ -43,41 +43,45 @@ namespace mss
 {
 
 ///
-/// @brief enum list of preliminary data fields
+/// @brief enum list of preliminary data fields needed before eff_config
 ///
-enum generic_metadata_fields
+enum pre_data_init_fields
 {
     // Template recursive base case
-    ATTR_METADATA_BASE_CASE = 0,
+    ATTR_PRE_DATA_ENGINE_CASE = 0,
 
     // Attrs to set
-    DIMM_TYPE_METADATA = 1,
-    DRAM_GEN_METADATA = 2,
-    DIMM_POS_METADATA = 3,
+    DIMM_TYPE = 1,
+    DRAM_GEN = 2,
+    HYBRID = 3,
+    HYBRID_MEDIA = 4,
+    MRANKS = 5,
+    HOST_TO_DDR_SPEED_RATIO = 6,
+    DIMM_RANKS_CNFG = 7,
 
     // Dispatcher set to last enum value
-    ATTR_METADATA_DISPATCHER = DIMM_POS_METADATA,
+    ATTR_PRE_DATA_ENG_DISPATCHER = DIMM_RANKS_CNFG,
 };
 
 ///
 /// @brief enum list of preliminary data fields
+/// @note Separating these fields into their own special case
+/// since this is needed for reuse in incompatible code bases
+/// (e.g. Nimbus vs Axone)
+/// @warning these depend on pre_data_init_fields fields being set
 ///
-enum pre_data_init_fields
+enum generic_metadata_fields
 {
     // Template recursive base case
-    ATTR_PRE_DATA_ENGINE_CASE = 0,
+    ATTR_METADATA_BASE_CASE = 0,
 
     // Attrs to set
-    DIMM_TYPE = 1,
-    DRAM_GEN = 2,
-    HYBRID = 3,
-    HYBRID_MEDIA = 4,
-    MRANKS = 5,
-    DIMM_RANKS_CNFG = 6,
-    HOST_TO_DDR_SPEED_RATIO = 7,
+    DIMM_TYPE_METADATA = 1,
+    DRAM_GEN_METADATA = 2,
+    DIMM_POS_METADATA = 3,
 
     // Dispatcher set to last enum value
-    ATTR_PRE_DATA_ENG_DISPATCHER = HOST_TO_DDR_SPEED_RATIO,
+    ATTR_METADATA_DISPATCHER = DIMM_POS_METADATA,
 };
 
 ///
@@ -90,13 +94,17 @@ enum attr_eff_engine_fields
 
     // Attrs to set
     DRAM_WIDTH = 1,
+    PRIM_BUS_WIDTH = 2,
+    DRAM_DENSITY = 3,
+    PRIMARY_DIE_COUNT = 4,
+    PRIM_STACK_TYPE = 5,
 
     // Dispatcher set to last enum value
-    ATTR_EFF_DISPATCHER = DRAM_WIDTH,
+    ATTR_EFF_DISPATCHER = PRIM_STACK_TYPE,
 };
 
 ///
-/// @brief enum list of SI attr fields to set
+/// @brief enum list of SI attr fields to set from EFD
 ///
 enum attr_si_engine_fields
 {
@@ -130,6 +138,29 @@ enum attr_si_engine_fields
 };
 
 ///
+/// @brief enum list of derived attributes
+/// @note these are attributes that are derived from other
+/// attributes or other APIs.
+///
+enum attr_engine_derived_fields
+{
+    // Attributes are set recursively from the bottom up.
+    // When adding attrs that depend on other attrs
+    // being set first, they should be placed earlier in the enum list
+    // so that base level attrs are set first.
+
+    // Template recursive base case
+    ATTR_DERIVED_BASE_CASE = 0,
+
+    // Attrs to set
+    MEM_DIMM_SIZE = 1,
+    LOGICAL_RANKS = 2,
+
+    // Dispatcher set to last enum value
+    ATTR_DERIVED_DISPATCHER = LOGICAL_RANKS,
+};
+
+///
 /// @brief Forward declartion of traits for pre_data_engine
 /// @class preDataInitTraits
 /// @tparam T proc_type (e.g. Nimbus, Axone, etc.)
diff --git a/src/import/generic/memory/lib/data_engine/data_engine_utils.H b/src/import/generic/memory/lib/data_engine/data_engine_utils.H
index aaf9a0485..cea9c7369 100644
--- a/src/import/generic/memory/lib/data_engine/data_engine_utils.H
+++ b/src/import/generic/memory/lib/data_engine/data_engine_utils.H
@@ -47,88 +47,6 @@ namespace mss
 {
 
 ///
-/// @class DataSetterTraits2D
-/// @brief Traits for setting eff_config data
-/// @tparam P proc_type
-/// @tparam X size of 1st array index
-/// @tparam Y size of 2nd array index
-///
-template < proc_type, size_t X, size_t Y >
-struct DataSetterTraits2D;
-
-///
-/// @class DataSetterTraits - Nimbus, [PORT][DIMM] array specialization
-/// @brief Traits for setting eff_config data
-///
-template < >
-struct DataSetterTraits2D < proc_type::NIMBUS,
-           mcTypeTraits<mc_type::NIMBUS>::PORTS_PER_MCS,
-           mcTypeTraits<mc_type::NIMBUS>::DIMMS_PER_PORT
-           >
-{
-    static constexpr fapi2::TargetType TARGET = fapi2::TARGET_TYPE_MCA;
-};
-
-///
-/// @brief Helper function to update a 2D array output
-/// @tparam P proc_type
-/// @tparam X size of 1st array index
-/// @tparam Y size of 2nd array index
-/// @tparam T Input/output data type
-/// @tparam TT defaulted to DataSetterTraits2D<P, X, Y>
-/// @param[in] i_target the DIMM target
-/// @param[in] i_setting array to set
-/// @param[in] i_ffdc_code FFDC function code
-/// @param[out] o_data attribute data structure to set
-/// @warning This is Nimbus specific until MCA alias to MEM_PORT
-///
-template < proc_type P,
-           size_t X,
-           size_t Y,
-           typename T,
-           typename TT = DataSetterTraits2D<P, X, Y>
-           >
-fapi2::ReturnCode update_data(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
-                              const T i_setting,
-                              const generic_ffdc_codes i_ffdc_code,
-                              T (&o_data)[X][Y])
-{
-    // Currenlty only valid for a DIMM target, for Nimbus, traits enforces this at compile time
-    // Use case is currently for pre_eff_config which is supported in both Axone and Nimbus
-    const auto l_port_index = mss::index( find_target<TT::TARGET>(i_target) );
-    const auto l_dimm_index = mss::index(i_target);
-
-    FAPI_ASSERT( l_port_index < X,
-                 fapi2::MSS_OUT_OF_BOUNDS_INDEXING()
-                 .set_INDEX(l_port_index)
-                 .set_LIST_SIZE(X)
-                 .set_FUNCTION(i_ffdc_code)
-                 .set_TARGET(i_target),
-                 "Port index (%d) was larger than max (%d) on %s",
-                 l_port_index,
-                 X,
-                 mss::spd::c_str(i_target) );
-
-    FAPI_ASSERT( l_dimm_index < Y,
-                 fapi2::MSS_OUT_OF_BOUNDS_INDEXING()
-                 .set_INDEX(l_dimm_index)
-                 .set_LIST_SIZE(Y)
-                 .set_FUNCTION(i_ffdc_code)
-                 .set_TARGET(i_target),
-                 "DIMM index (%d) was larger than max (%d) on %s",
-                 l_dimm_index,
-                 Y,
-                 mss::spd::c_str(i_target) );
-
-    o_data[l_port_index][l_dimm_index] = i_setting;
-
-    return fapi2::FAPI2_RC_SUCCESS;
-
-fapi_try_exit:
-    return fapi2::current_err;
-}
-
-///
 /// @brief Mapping boilerplate check
 /// @tparam T FAPI2 target type
 /// @tparam IT map key type
@@ -162,41 +80,13 @@ fapi_try_exit:
     return fapi2::current_err;
 }
 
-///
-/// @brief Sets attr data fields
-/// @tparam P proc_type
-/// @tparam TT data engine class traits (e.g. preDataInitTraits, etc.)
-/// @tparam T FAPI2 target type
-/// @tparam IT Input data type
-/// @param[in] i_target the FAPI target
-/// @param[in] i_setting value we want to set attr with
-/// @return FAPI2_RC_SUCCESS iff okay
-///
-template< proc_type P,
-          typename TT,
-          fapi2::TargetType T,
-          typename IT >
-inline fapi2::ReturnCode set_field(const fapi2::Target<T>& i_target,
-                                   const IT i_setting)
-{
-    const auto l_attr_target = mss::find_target<TT::TARGET_TYPE>(i_target);
-    typename TT::attr_type l_attr_list = {};
-    FAPI_TRY( TT::get_attr(l_attr_target, l_attr_list) );
-
-    FAPI_TRY( update_data<P>(i_target, i_setting, TT::FFDC_CODE, l_attr_list) );
-    FAPI_TRY( TT::set_attr(l_attr_target, l_attr_list) );
-
-fapi_try_exit:
-    return fapi2::current_err;
-}
-
 // Controller agnostic functions
 
 namespace gen
 {
 
 ///
-/// @brief Get the target associated with the SPD facade
+/// @brief Helper to get the target associated with the SPD facade
 /// @param[in] i_data the SPD data
 /// return a fapi2 DIMM target
 ///
@@ -206,7 +96,7 @@ static inline fapi2::Target<fapi2::TARGET_TYPE_DIMM> get_target(const spd::facad
 }
 
 ///
-/// @brief Get the target associated with the EFD decoder
+/// @brief Helper to get the target associated with the EFD decoder
 /// @param[in] i_data the EFD data
 /// return a fapi2 DIMM target
 ///
@@ -216,6 +106,32 @@ static inline fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP> get_target(const std::
 }
 
 ///
+/// @brief Helper function to get the target associated with generic attribute setting
+/// @param[in] i_target
+/// return a fapi2 MEM_PORT target
+///
+static inline fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT> get_attr_target(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>&
+        i_target)
+{
+    return mss::find_target<fapi2::TARGET_TYPE_MEM_PORT>(i_target);
+}
+
+///
+/// @brief Helper function to get the target associated with generic attribute setting
+/// @param[in] i_target
+/// return a fapi2 MEM_PORT target
+///
+inline fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT> get_attr_target(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>&
+        i_target)
+{
+    // Explorer has only one MEM_PORT per OCMB, so we are looking for the 0th pos relative to the OCMB
+    // Will need to update to take into account a mem_channel index in VPDinfo if we ever support this.
+    // Per FW, for the DDIMM case we can't support unique settings per channel because the SPD
+    // doesn't know about anything outside of the DDIMM itself.
+    return mss::find_targets<fapi2::TARGET_TYPE_MEM_PORT>(i_target)[0];
+}
+
+///
 /// @brief Helper function to update the structure that holds attr data
 /// @tparam X size of 1st array index
 /// @tparam Y size of 2nd array index
@@ -294,9 +210,8 @@ inline fapi2::ReturnCode update_data( const spd::facade& i_spd_data,
                                       const FFDC i_ffdc_code,
                                       T (&o_data)[X])
 {
-    // TK remove hard-code to DIMM0, use REL_POS attr
     const auto l_dimm = i_spd_data.get_dimm_target();
-    const size_t l_dimm_index = 0;
+    const size_t l_dimm_index = mss::index(l_dimm);
 
     FAPI_ASSERT( l_dimm_index < X,
                  fapi2::MSS_OUT_OF_BOUNDS_INDEXING()
@@ -321,6 +236,49 @@ fapi_try_exit:
 ///
 /// @brief Helper function to update the structure that holds attr data
 /// @tparam T the FAPI2 TargetType
+/// @tparam IT Input/Output data type
+/// @tparam FFDC the FFDC type
+/// @tparam X size of 1st array index
+/// @param[in] i_target the FAPI2 target
+/// @param[in] i_setting array to set
+/// @param[in] i_ffdc_code FFDC function code
+/// @param[out] o_data attribute data structure to set
+/// @return FAPI2_RC_SUCCESS iff okay
+///
+template < fapi2::TargetType T,
+           typename IT,
+           typename FFDC,
+           size_t X >
+inline fapi2::ReturnCode update_data( const fapi2::Target<T>& i_target,
+                                      const IT i_setting,
+                                      const FFDC i_ffdc_code,
+                                      IT (&o_data)[X])
+{
+    const size_t l_dimm_index = mss::index(i_target);
+
+    FAPI_ASSERT( l_dimm_index < X,
+                 fapi2::MSS_OUT_OF_BOUNDS_INDEXING()
+                 .set_INDEX(l_dimm_index)
+                 .set_LIST_SIZE(X)
+                 .set_FUNCTION(i_ffdc_code)
+                 .set_TARGET(i_target),
+                 "Dimm index (%d) was larger than max (%d) on %s",
+                 l_dimm_index,
+                 X,
+                 mss::spd::c_str(i_target) );
+
+    FAPI_DBG("Updating data[%d] with %d for %s", l_dimm_index, i_setting, spd::c_str(i_target));
+    o_data[l_dimm_index] = i_setting;
+
+    return fapi2::FAPI2_RC_SUCCESS;
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
+/// @brief Helper function to update the structure that holds attr data
+/// @tparam T the FAPI2 TargetType
 /// @tparam IT Input data type
 /// @tparam FFDC type
 /// @tparam OT Output data type
@@ -396,32 +354,6 @@ fapi_try_exit:
 }
 
 ///
-/// @brief Helper function to get the target associated with generic attribute setting
-/// @param[in] i_target
-/// return a fapi2 MEM_PORT target
-///
-static inline fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT> get_attr_target(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>&
-        i_target)
-{
-    return mss::find_target<fapi2::TARGET_TYPE_MEM_PORT>(i_target);
-}
-
-///
-/// @brief Helper function to get the target associated with generic attribute setting
-/// @param[in] i_target
-/// return a fapi2 MEM_PORT target
-///
-inline fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT> get_attr_target(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>&
-        i_target)
-{
-    // Explorer has only one MEM_PORT per OCMB, so we are looking for the 0th pos relative to the OCMB
-    // Will need to update to take into account a mem_channel index in VPDinfo if we ever support this.
-    // Per FW, for the DDIMM case we can't support unique settings per channel because the SPD
-    // doesn't know about anything outside of the DDIMM itself.
-    return mss::find_targets<fapi2::TARGET_TYPE_MEM_PORT>(i_target)[0];
-}
-
-///
 /// @brief Sets attr data fields
 /// @tparam TT data engine class traits (e.g. preDataInitTraits, etc.)
 /// @tparam DT the data type
@@ -472,55 +404,17 @@ struct attr_engine
 {
     ///
     /// @brief Sets attributes fields F in ET
-    /// @tparam T the fapi2 target type
-    /// @param[in] i_target the fapi2 target
-    /// @return FAPI2_RC_SUCCESS iff oka
-    ///
-    template < fapi2::TargetType T >
-    static fapi2::ReturnCode single_set(const fapi2::Target<T>& i_target)
-    {
-        typename TT::attr_integral_type l_value = 0;
-        FAPI_TRY( TT::get_value_to_set(i_target, l_value) );
-
-        FAPI_TRY( set_field<TT>(i_target, l_value) );
-
-    fapi_try_exit:
-        return fapi2::current_err;
-    }
-
-    ///
-    /// @brief Sets attributes fields F in ET
-    /// @tparam DT the data type
-    /// @param[in] i_data the data (efd_decoder, spd_facade, etc.)
+    /// @tparam IT the input type
+    /// @param[in] i_input input (efd_decoder, spd_facade, fapi2 target)
     /// @return FAPI2_RC_SUCCESS iff ok
     ///
-    template < typename DT >
-    static fapi2::ReturnCode single_set(const DT& i_data)
+    template < typename IT >
+    static fapi2::ReturnCode single_set(const IT& i_input)
     {
         typename TT::attr_integral_type l_value = 0;
-        FAPI_TRY( TT::get_value_to_set(i_data, l_value) );
-
-        FAPI_TRY( set_field<TT>(i_data, l_value) );
-
-    fapi_try_exit:
-        return fapi2::current_err;
-    }
-
-    ///
-    /// @brief Sets attributes fields F in ET
-    /// @tparam DT the data type
-    /// @param[in] i_data the data (efd_decoder, spd_facade, etc.)
-    /// @return FAPI2_RC_SUCCESS iff ok
-    ///
-    template < typename DT >
-    static fapi2::ReturnCode set(const DT& i_data)
-    {
-        FAPI_TRY( (attr_engine<ET, F>::single_set(i_data)) );
+        FAPI_TRY( TT::get_value_to_set(i_input, l_value) );
 
-        // Compiler isn't smart enough to deduce F - 1u (decrementing the enum values by 1)
-        // Cast needed to help the compiler deduce this value is an ET type
-        // This does the recursive call to unroll a compile-time looping of a enum list of attrs to set
-        FAPI_TRY( (attr_engine < ET, static_cast<ET>(F - 1u) >::set(i_data)) );
+        FAPI_TRY( set_field<TT>(i_input, l_value) );
 
     fapi_try_exit:
         return fapi2::current_err;
@@ -528,19 +422,19 @@ struct attr_engine
 
     ///
     /// @brief Sets attributes fields F in ET
-    /// @tparam T the fapi2 target type
-    /// @param[in] i_target the fapi2 target
+    /// @tparam IT the input type
+    /// @param[in] i_input input (efd_decoder, spd_facade, fapi2 target)
     /// @return FAPI2_RC_SUCCESS iff ok
     ///
-    template < fapi2::TargetType T >
-    static fapi2::ReturnCode set(const fapi2::Target<T>& i_target)
+    template < typename IT >
+    static fapi2::ReturnCode set(const IT& i_input)
     {
-        FAPI_TRY( (attr_engine<ET, F>::single_set(i_target)) );
+        FAPI_TRY( (attr_engine<ET, F>::single_set(i_input)) );
 
         // Compiler isn't smart enough to deduce F - 1u (decrementing the enum values by 1)
         // Cast needed to help the compiler deduce this value is an ET type
         // This does the recursive call to unroll a compile-time looping of a enum list of attrs to set
-        FAPI_TRY( (attr_engine < ET, static_cast<ET>(F - 1u) >::set(i_target)) );
+        FAPI_TRY( (attr_engine < ET, static_cast<ET>(F - 1u) >::set(i_input)) );
 
     fapi_try_exit:
         return fapi2::current_err;
@@ -562,24 +456,12 @@ struct attr_engine< ET,
 {
     ///
     /// @brief Sets attributes fields F in ET
-    /// @tparam T the fapi2 target type
-    /// @param[in] i_target the fapi2 target
-    /// @return FAPI2_RC_SUCCESS iff ok
-    ///
-    template < fapi2::TargetType T >
-    static fapi2::ReturnCode set(const fapi2::Target<T>& i_target)
-    {
-        return fapi2::FAPI2_RC_SUCCESS;
-    }
-
-    ///
-    /// @brief Sets attributes fields F in ET
-    /// @tparam DT the data type
-    /// @param[in] i_data the data (efd_decoder, spd_facade, etc.)
+    /// @tparam IT the input type
+    /// @param[in] i_input input (efd_decoder, spd_facade, fapi2 target)
     /// @return FAPI2_RC_SUCCESS iff ok
     ///
-    template < typename DT >
-    static fapi2::ReturnCode set(const DT& i_data)
+    template < typename IT >
+    static fapi2::ReturnCode set(const IT& i_input)
     {
         return fapi2::FAPI2_RC_SUCCESS;
     }
diff --git a/src/import/generic/memory/lib/data_engine/p9a/p9a_data_init_traits.H b/src/import/generic/memory/lib/data_engine/p9a/p9a_data_init_traits.H
index d0f00d6f0..9122c12da 100644
--- a/src/import/generic/memory/lib/data_engine/p9a/p9a_data_init_traits.H
+++ b/src/import/generic/memory/lib/data_engine/p9a/p9a_data_init_traits.H
@@ -46,66 +46,6 @@ namespace mss
 {
 
 ///
-/// @brief Helper function to get dimm_type from SPD
-/// @param[in] i_spd_data SPD data
-/// @param[in] i_setting value we want to set attr with
-/// @return FAPI2_RC_SUCCESS iff okay
-///
-static fapi2::ReturnCode get_dimm_type(const spd::facade& i_spd_data,
-                                       uint8_t& o_setting)
-{
-    // =========================================================
-    // DDR4 SPD Document Release 4
-    // Byte 3 (0x003): Key Byte / Module Type
-    // =========================================================
-    static const std::vector< std::pair<uint8_t, uint8_t> > BASE_MODULE_TYPE_MAP =
-    {
-        //{key byte, dimm type}
-        {1, fapi2::ENUM_ATTR_MEM_EFF_DIMM_TYPE_RDIMM},
-        {2, fapi2::ENUM_ATTR_MEM_EFF_DIMM_TYPE_UDIMM},
-        {10, fapi2::ENUM_ATTR_MEM_EFF_DIMM_TYPE_DDIMM},
-        // All others reserved or not supported
-    };
-
-    const auto l_dimm = i_spd_data.get_dimm_target();
-    uint8_t l_base_module_type = 0;
-    FAPI_TRY(i_spd_data.base_module(l_base_module_type));
-    FAPI_TRY(lookup_table_check(l_dimm, BASE_MODULE_TYPE_MAP, SET_ATTR_DIMM_TYPE, l_base_module_type, o_setting));
-
-fapi_try_exit:
-    return fapi2::current_err;
-}
-
-///
-/// @brief Helper function to get dram_gen from SPD
-/// @param[in] i_spd_data SPD data
-/// @param[in] i_setting value we want to set attr with
-/// @return FAPI2_RC_SUCCESS iff okay
-///
-static fapi2::ReturnCode get_dram_gen(const spd::facade& i_spd_data,
-                                      uint8_t& o_setting)
-{
-    // =========================================================
-    // DDR4 SPD Document Release 4
-    // Byte 2 (0x002): Key Byte / DRAM Device Type
-    // =========================================================
-    static const std::vector< std::pair<uint8_t, uint8_t> > DRAM_GEN_MAP =
-    {
-        //{key value, dram gen}
-        {0x0C, fapi2::ENUM_ATTR_MEM_EFF_DRAM_GEN_DDR4}
-        // Other key bytes reserved or not supported
-    };
-
-    const auto l_dimm = i_spd_data.get_dimm_target();
-    uint8_t l_device_type = 0;
-    FAPI_TRY(i_spd_data.device_type(l_device_type));
-    FAPI_TRY(lookup_table_check(l_dimm, DRAM_GEN_MAP, SET_ATTR_DRAM_GEN, l_device_type, o_setting));
-
-fapi_try_exit:
-    return fapi2::current_err;
-}
-
-///
 /// @brief Traits for pre_data_engine
 /// @class attrEngineTraits
 /// @note pre_data_init_fields, DIMM_TYPE specialization
@@ -145,13 +85,36 @@ struct attrEngineTraits<pre_data_init_fields, DIMM_TYPE>
     ///
     /// @brief Computes setting for attribute
     /// @param[in] i_spd_data SPD data
-    /// @param[in] i_setting value we want to set attr with
+    /// @param[out] o_setting value we want to set attr with
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
     static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data,
             attr_integral_type& o_setting)
     {
-        return get_dimm_type(i_spd_data, o_setting);
+        // =========================================================
+        // DDR4 SPD Document Release 4
+        // Byte 3 (0x003): Key Byte / Module Type
+        // =========================================================
+        static const std::vector< std::pair<uint8_t, uint8_t> > BASE_MODULE_TYPE_MAP =
+        {
+            //{key byte, dimm type}
+            {1, fapi2::ENUM_ATTR_MEM_EFF_DIMM_TYPE_RDIMM},
+            {2, fapi2::ENUM_ATTR_MEM_EFF_DIMM_TYPE_UDIMM},
+            {10, fapi2::ENUM_ATTR_MEM_EFF_DIMM_TYPE_DDIMM},
+            // All others reserved or not supported
+        };
+
+        const auto l_dimm = i_spd_data.get_dimm_target();
+
+        attr_integral_type l_base_module_type = 0;
+        FAPI_TRY( i_spd_data.base_module(l_base_module_type),
+                  "%s failed to get base module from SPD", spd::c_str(l_dimm) );
+
+        FAPI_TRY( lookup_table_check(l_dimm, BASE_MODULE_TYPE_MAP, FFDC_CODE, l_base_module_type, o_setting),
+                  "%s failed DIMM_TYPE lookup check", spd::c_str(l_dimm) );
+
+    fapi_try_exit:
+        return fapi2::current_err;
     }
 };
 
@@ -195,13 +158,34 @@ struct attrEngineTraits<pre_data_init_fields, DRAM_GEN>
     ///
     /// @brief Computes setting for attribute
     /// @param[in] i_spd_data SPD data
-    /// @param[in] i_setting value we want to set attr with
+    /// @param[out] o_setting value we want to set attr with
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
     static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data,
             attr_integral_type& o_setting)
     {
-        return get_dram_gen(i_spd_data, o_setting);
+        // =========================================================
+        // DDR4 SPD Document Release 4
+        // Byte 2 (0x002): Key Byte / DRAM Device Type
+        // =========================================================
+        static const std::vector< std::pair<uint8_t, uint8_t> > DRAM_GEN_MAP =
+        {
+            //{key value, dram gen}
+            {0x0C, fapi2::ENUM_ATTR_MEM_EFF_DRAM_GEN_DDR4}
+            // Other key bytes reserved or not supported
+        };
+
+        const auto l_dimm = i_spd_data.get_dimm_target();
+
+        attr_integral_type l_device_type = 0;
+        FAPI_TRY( i_spd_data.device_type(l_device_type),
+                  "%s failed to get device type from SPD", spd::c_str(l_dimm) );
+
+        FAPI_TRY( lookup_table_check(l_dimm, DRAM_GEN_MAP, FFDC_CODE, l_device_type, o_setting),
+                  "%s failed DRAM_GEN lookup check", spd::c_str(l_dimm) );
+
+    fapi_try_exit:
+        return fapi2::current_err;
     }
 };
 
@@ -245,7 +229,7 @@ struct attrEngineTraits<pre_data_init_fields, HOST_TO_DDR_SPEED_RATIO>
     ///
     /// @brief Computes setting for attribute
     /// @param[in] i_spd_data SPD data
-    /// @param[in] i_setting value we want to set attr with
+    /// @param[out] o_setting value we want to set attr with
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
     static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data,
@@ -323,7 +307,7 @@ struct attrEngineTraits<pre_data_init_fields, HYBRID>
     ///
     /// @brief Computes setting for attribute
     /// @param[in] i_spd_data SPD data
-    /// @param[in] i_setting value we want to set attr with
+    /// @param[out] o_setting value we want to set attr with
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
     static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data,
@@ -341,9 +325,14 @@ struct attrEngineTraits<pre_data_init_fields, HYBRID>
             // All others reserved or not supported
         };
 
-        uint8_t l_spd_hybrid_type = 0;
-        FAPI_TRY(i_spd_data.hybrid(l_spd_hybrid_type));
-        FAPI_TRY(lookup_table_check(i_spd_data.get_dimm_target(), HYBRID_MAP, SET_ATTR_HYBRID, l_spd_hybrid_type, o_setting));
+        const auto l_dimm = i_spd_data.get_dimm_target();
+
+        attr_integral_type l_spd_hybrid_type = 0;
+        FAPI_TRY(i_spd_data.hybrid(l_spd_hybrid_type),
+                 "%s failed to get hybrid from SPD", spd::c_str(l_dimm) );
+
+        FAPI_TRY(lookup_table_check(l_dimm, HYBRID_MAP, FFDC_CODE, l_spd_hybrid_type, o_setting),
+                 "%s failed HYBRID lookup check", spd::c_str(l_dimm) );
 
     fapi_try_exit:
         return fapi2::current_err;
@@ -390,7 +379,7 @@ struct attrEngineTraits<pre_data_init_fields, HYBRID_MEDIA>
     ///
     /// @brief Computes setting for attribute
     /// @param[in] i_spd_data SPD data
-    /// @param[in] i_setting value we want to set attr with
+    /// @param[out] o_setting value we want to set attr with
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
     static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data,
@@ -408,11 +397,14 @@ struct attrEngineTraits<pre_data_init_fields, HYBRID_MEDIA>
             {1, fapi2::ENUM_ATTR_MEM_EFF_HYBRID_MEMORY_TYPE_NVDIMM},
             // All others reserved or not supported
         };
+        const auto l_dimm = i_spd_data.get_dimm_target();
+        attr_integral_type l_spd_hybrid_media = 0;
+
+        FAPI_TRY( i_spd_data.hybrid_media(l_spd_hybrid_media),
+                  "%s failed to get hybrid media from SPD", spd::c_str(l_dimm) );
 
-        uint8_t l_spd_hybrid_media = 0;
-        FAPI_TRY(i_spd_data.hybrid_media(l_spd_hybrid_media));
-        FAPI_TRY(lookup_table_check(i_spd_data.get_dimm_target(), HYBRID_MEMORY_TYPE_MAP, SET_ATTR_HYBRID_MEDIA,
-                                    l_spd_hybrid_media, o_setting));
+        FAPI_TRY( lookup_table_check(l_dimm, HYBRID_MEMORY_TYPE_MAP, FFDC_CODE, l_spd_hybrid_media, o_setting),
+                  "%s failed HYBRID_MEMORY_TYPE lookup check", spd::c_str(l_dimm) );
 
     fapi_try_exit:
         return fapi2::current_err;
@@ -420,39 +412,6 @@ struct attrEngineTraits<pre_data_init_fields, HYBRID_MEDIA>
 };
 
 ///
-/// @brief Gets master ranks from SPD
-/// @param[out] o_output num package ranks per DIMM
-/// @return FAPI2_RC_SUCCESS iff ok
-///
-static fapi2::ReturnCode get_master_ranks(const spd::facade& i_spd_data,
-        const generic_ffdc_codes i_ffdc,
-        uint8_t& o_output)
-{
-    // =========================================================
-    // DDR4 SPD Document Release 4
-    // Byte 12 (0x00C): Module Organization
-    // =========================================================
-    static const std::vector< std::pair<uint8_t, uint8_t> > NUM_PACKAGE_RANKS_MAP =
-    {
-        // {key byte, num of package ranks per DIMM (package ranks)}
-        {0, fapi2::ENUM_ATTR_MEM_EFF_NUM_MASTER_RANKS_PER_DIMM_1R},
-        {1, fapi2::ENUM_ATTR_MEM_EFF_NUM_MASTER_RANKS_PER_DIMM_2R},
-        {3, fapi2::ENUM_ATTR_MEM_EFF_NUM_MASTER_RANKS_PER_DIMM_4R},
-    };
-
-    const auto l_dimm = i_spd_data.get_dimm_target();
-    uint8_t l_master_ranks_spd = 0;
-    FAPI_TRY(i_spd_data.num_package_ranks_per_dimm(l_master_ranks_spd),
-             "%s failed to get number of package ranks from SPD", spd::c_str(l_dimm));
-
-    FAPI_TRY(lookup_table_check(l_dimm, NUM_PACKAGE_RANKS_MAP, i_ffdc, l_master_ranks_spd,
-                                o_output), "%s failed MASTER_RANKS lookup check", spd::c_str(l_dimm));
-
-fapi_try_exit:
-    return fapi2::current_err;
-}
-
-///
 /// @brief Traits for pre_data_engine
 /// @class attrEngineTraits
 /// @note pre_data_init_fields, MRANKS specialization
@@ -467,7 +426,7 @@ struct attrEngineTraits<pre_data_init_fields, MRANKS>
 
     ///
     /// @brief attribute getter
-    /// @param[in] i_target the attr target
+    /// @param[in] i_target the attribute associated target
     /// @param[out] o_setting array to populate
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
@@ -479,7 +438,7 @@ struct attrEngineTraits<pre_data_init_fields, MRANKS>
 
     ///
     /// @brief attribute setter
-    /// @param[in] i_target the attr target
+    /// @param[in] i_target the attribute associated target
     /// @param[in] i_setting array to set
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
@@ -492,13 +451,32 @@ struct attrEngineTraits<pre_data_init_fields, MRANKS>
     ///
     /// @brief Computes setting for attribute
     /// @param[in] i_spd_data SPD data
-    /// @param[in] i_setting value we want to set attr with
+    /// @param[out] o_setting value we want to set attr with
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
     static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data,
             attr_integral_type& o_setting)
     {
-        FAPI_TRY( get_master_ranks(i_spd_data, SET_ATTR_MASTER_RANKS, o_setting) );
+        // =========================================================
+        // DDR4 SPD Document Release 4
+        // Byte 12 (0x00C): Module Organization
+        // =========================================================
+        static const std::vector< std::pair<uint8_t, uint8_t> > NUM_PACKAGE_RANKS_MAP =
+        {
+            // {key byte, num of package ranks per DIMM (package ranks)}
+            {0, fapi2::ENUM_ATTR_MEM_EFF_NUM_MASTER_RANKS_PER_DIMM_1R},
+            {1, fapi2::ENUM_ATTR_MEM_EFF_NUM_MASTER_RANKS_PER_DIMM_2R},
+            {3, fapi2::ENUM_ATTR_MEM_EFF_NUM_MASTER_RANKS_PER_DIMM_4R},
+        };
+
+        const auto l_dimm = i_spd_data.get_dimm_target();
+
+        attr_integral_type l_master_ranks_spd = 0;
+        FAPI_TRY( i_spd_data.num_package_ranks_per_dimm(l_master_ranks_spd),
+                  "%s failed to get number of package ranks from SPD", spd::c_str(l_dimm) );
+
+        FAPI_TRY( lookup_table_check(l_dimm, NUM_PACKAGE_RANKS_MAP, FFDC_CODE, l_master_ranks_spd, o_setting),
+                  "%s failed MASTER_RANKS lookup check", spd::c_str(l_dimm) );
 
     fapi_try_exit:
         return fapi2::current_err;
@@ -508,36 +486,37 @@ struct attrEngineTraits<pre_data_init_fields, MRANKS>
 ///
 /// @brief Traits for pre_data_engine
 /// @class attrEngineTraits
-/// @note pre_data_init_fields, DIMM_RANKS_CNFG specialization
+/// @note DIMM_RANKS_CNFG specialization
 ///
 template<>
 struct attrEngineTraits<pre_data_init_fields, DIMM_RANKS_CNFG>
 {
+
     using attr_type = fapi2::ATTR_MEM_EFF_DIMM_RANKS_CONFIGED_Type;
     using attr_integral_type = std::remove_all_extents<attr_type>::type;
-    static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_DIMM_RANKS_CONFIGED_TargetType;
+    static const fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_DIMM_RANKS_CONFIGED_TargetType;
     static constexpr generic_ffdc_codes FFDC_CODE = SET_DIMM_RANKS_CNFG;
 
     ///
     /// @brief attribute getter
-    /// @param[in] i_target the attr target
+    /// @param[in] i_target the fapi2 target
     /// @param[out] o_setting array to populate
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
-    static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target,
-                                      attr_type& o_setting)
+    static inline fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target,
+            attr_type& o_setting)
     {
         return mss::attr::get_dimm_ranks_configed(i_target, o_setting);
     }
 
     ///
     /// @brief attribute setter
-    /// @param[in] i_target the attr target
+    /// @param[in] i_target the fapi2 target
     /// @param[in] i_setting array to set
     /// @return FAPI2_RC_SUCCESS iff okay
     ///
-    static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target,
-                                      attr_type& i_setting)
+    static inline fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target,
+            attr_type& i_setting)
     {
         return mss::attr::set_dimm_ranks_configed(i_target, i_setting);
     }
@@ -545,9 +524,9 @@ struct attrEngineTraits<pre_data_init_fields, DIMM_RANKS_CNFG>
     ///
     /// @brief Computes setting for attribute
     /// @param[in] i_spd_data SPD data
-    /// @param[in] i_setting value we want to set attr with
+    /// @param[out] o_setting value we want to set attr with
     /// @return FAPI2_RC_SUCCESS iff okay
-    ///
+
     static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data,
             attr_integral_type& o_setting)
     {
@@ -555,8 +534,9 @@ struct attrEngineTraits<pre_data_init_fields, DIMM_RANKS_CNFG>
         // a 4R DIMM would be 0b11110000 (0xF0). This is used by PRD.
         fapi2::buffer<uint8_t> l_ranks_configed;
 
+        // Make sure the number of master ranks is setup
         uint8_t l_master_ranks = 0;
-        FAPI_TRY( get_master_ranks(i_spd_data, SET_ATTR_RANKS_CONFIGED, l_master_ranks) );
+        FAPI_TRY( (attrEngineTraits<pre_data_init_fields, MRANKS>::get_value_to_set(i_spd_data, l_master_ranks)) );
 
         FAPI_TRY( l_ranks_configed.setBit(0, l_master_ranks),
                   "%s. Failed to setBit", spd::c_str(i_spd_data.get_dimm_target()) );
diff --git a/src/import/generic/memory/lib/data_engine/p9n/p9n_data_init_traits.H b/src/import/generic/memory/lib/data_engine/p9n/p9n_data_init_traits.H
index 5f0207b14..cf520c148 100644
--- a/src/import/generic/memory/lib/data_engine/p9n/p9n_data_init_traits.H
+++ b/src/import/generic/memory/lib/data_engine/p9n/p9n_data_init_traits.H
@@ -255,39 +255,35 @@ class preDataInitTraits<mss::proc_type::NIMBUS, MRANKS>
 /// @note NIMBUS, DIMM_RANKS_CNFG specialization
 ///
 template<>
-class preDataInitTraits<mss::proc_type::NIMBUS, DIMM_RANKS_CNFG>
+struct preDataInitTraits<mss::proc_type::NIMBUS, DIMM_RANKS_CNFG>
 {
-    public:
-        using attr_type = fapi2::ATTR_EFF_DIMM_RANKS_CONFIGED_Type;
-        static const fapi2::TargetType TARGET_TYPE = fapi2::ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_TargetType;
-        static constexpr generic_ffdc_codes FFDC_CODE = SET_DIMM_RANKS_CNFG;
-
-        ///
-        /// @brief attribute getter
-        /// @param[in] i_target the MCS target
-        /// @param[out] o_setting array to populate
-        /// @return FAPI2_RC_SUCCESS iff okay
-        ///
-        static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target,
-                                          attr_type& o_setting)
-        {
-            FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_EFF_DIMM_RANKS_CONFIGED, i_target, o_setting) );
+    using attr_type = fapi2::ATTR_EFF_DIMM_RANKS_CONFIGED_Type;
+    static const fapi2::TargetType TARGET_TYPE = fapi2::ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_TargetType;
+    static constexpr generic_ffdc_codes FFDC_CODE = SET_DIMM_RANKS_CNFG;
 
-        fapi_try_exit:
-            return fapi2::current_err;
-        }
+    ///
+    /// @brief attribute getter
+    /// @param[in] i_target the MCS target
+    /// @param[out] o_setting array to populate
+    /// @return FAPI2_RC_SUCCESS iff okay
+    ///
+    static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target,
+                                      attr_type& o_setting)
+    {
+        return FAPI_ATTR_GET(fapi2::ATTR_EFF_DIMM_RANKS_CONFIGED, i_target, o_setting);
+    }
 
-        ///
-        /// @brief attribute setter
-        /// @param[in] i_target the MCS target
-        /// @param[in] i_setting array to set
-        /// @return FAPI2_RC_SUCCESS iff okay
-        ///
-        static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target,
-                                          attr_type& i_setting)
-        {
-            return FAPI_ATTR_SET(fapi2::ATTR_EFF_DIMM_RANKS_CONFIGED, i_target, i_setting);
-        }
+    ///
+    /// @brief attribute setter
+    /// @param[in] i_target the MCS target
+    /// @param[in] i_setting array to set
+    /// @return FAPI2_RC_SUCCESS iff okay
+    ///
+    static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target,
+                                      attr_type& i_setting)
+    {
+        return FAPI_ATTR_SET(fapi2::ATTR_EFF_DIMM_RANKS_CONFIGED, i_target, i_setting);
+    }
 };
 
 ///
diff --git a/src/import/generic/memory/lib/data_engine/pre_data_init.H b/src/import/generic/memory/lib/data_engine/pre_data_init.H
index df19a86ef..307c08aa1 100644
--- a/src/import/generic/memory/lib/data_engine/pre_data_init.H
+++ b/src/import/generic/memory/lib/data_engine/pre_data_init.H
@@ -46,6 +46,117 @@
 
 namespace mss
 {
+// TK - Remove generalizations since this is dubbed Nimbus specific implementation
+
+///
+/// @class DataSetterTraits2D
+/// @brief Traits for setting eff_config data
+/// @tparam P proc_type
+/// @tparam X size of 1st array index
+/// @tparam Y size of 2nd array index
+///
+template < proc_type P, size_t X, size_t Y >
+struct DataSetterTraits2D;
+
+///
+/// @class DataSetterTraits - Nimbus, [PORT][DIMM] array specialization
+/// @brief Traits for setting eff_config data
+///
+template < >
+struct DataSetterTraits2D < proc_type::NIMBUS,
+           mcTypeTraits<mc_type::NIMBUS>::PORTS_PER_MCS,
+           mcTypeTraits<mc_type::NIMBUS>::DIMMS_PER_PORT
+           >
+{
+    static constexpr fapi2::TargetType TARGET = fapi2::TARGET_TYPE_MCA;
+};
+
+///
+/// @brief Helper function to update a 2D array output
+/// @tparam P proc_type
+/// @tparam X size of 1st array index
+/// @tparam Y size of 2nd array index
+/// @tparam T Input/output data type
+/// @tparam TT defaulted to DataSetterTraits2D<P, X, Y>
+/// @param[in] i_target the DIMM target
+/// @param[in] i_setting array to set
+/// @param[in] i_ffdc_code FFDC function code
+/// @param[out] o_data attribute data structure to set
+/// @warning This is Nimbus specific until MCA alias to MEM_PORT
+///
+template < proc_type P,
+           size_t X,
+           size_t Y,
+           typename T,
+           typename TT = DataSetterTraits2D<P, X, Y>
+           >
+fapi2::ReturnCode update_data(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+                              const T i_setting,
+                              const generic_ffdc_codes i_ffdc_code,
+                              T (&o_data)[X][Y])
+{
+    // Currenlty only valid for a DIMM target, for Nimbus, traits enforces this at compile time
+    // Use case is currently for pre_eff_config which is supported in both Axone and Nimbus
+    const auto l_port_index = mss::index( find_target<TT::TARGET>(i_target) );
+    const auto l_dimm_index = mss::index(i_target);
+
+    FAPI_ASSERT( l_port_index < X,
+                 fapi2::MSS_OUT_OF_BOUNDS_INDEXING()
+                 .set_INDEX(l_port_index)
+                 .set_LIST_SIZE(X)
+                 .set_FUNCTION(i_ffdc_code)
+                 .set_TARGET(i_target),
+                 "Port index (%d) was larger than max (%d) on %s",
+                 l_port_index,
+                 X,
+                 mss::spd::c_str(i_target) );
+
+    FAPI_ASSERT( l_dimm_index < Y,
+                 fapi2::MSS_OUT_OF_BOUNDS_INDEXING()
+                 .set_INDEX(l_dimm_index)
+                 .set_LIST_SIZE(Y)
+                 .set_FUNCTION(i_ffdc_code)
+                 .set_TARGET(i_target),
+                 "DIMM index (%d) was larger than max (%d) on %s",
+                 l_dimm_index,
+                 Y,
+                 mss::spd::c_str(i_target) );
+
+    o_data[l_port_index][l_dimm_index] = i_setting;
+
+    return fapi2::FAPI2_RC_SUCCESS;
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
+/// @brief Sets attr data fields
+/// @tparam P proc_type
+/// @tparam TT data engine class traits (e.g. preDataInitTraits, etc.)
+/// @tparam T FAPI2 target type
+/// @tparam IT Input data type
+/// @param[in] i_target the FAPI target
+/// @param[in] i_setting value we want to set attr with
+/// @return FAPI2_RC_SUCCESS iff okay
+///
+template< proc_type P,
+          typename TT,
+          fapi2::TargetType T,
+          typename IT >
+inline fapi2::ReturnCode set_field(const fapi2::Target<T>& i_target,
+                                   const IT i_setting)
+{
+    const auto l_attr_target = mss::find_target<TT::TARGET_TYPE>(i_target);
+    typename TT::attr_type l_attr_list = {};
+    FAPI_TRY( TT::get_attr(l_attr_target, l_attr_list) );
+
+    FAPI_TRY( update_data<P>(i_target, i_setting, TT::FFDC_CODE, l_attr_list) );
+    FAPI_TRY( TT::set_attr(l_attr_target, l_attr_list) );
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
 
 ///
 /// @brief Sets preliminary data fields
@@ -277,11 +388,13 @@ inline fapi2::ReturnCode set_pre_init_attrs<mss::proc_type::NIMBUS>( const fapi2
     FAPI_TRY(l_data_engine.set_hybrid_media(), "Failed to set Hybrid Media %s", mss::spd::c_str(i_target) );
 
     // Number of master ranks needed for VPD decoding
-    // and dimm_ranks_configured is a PRD attr...
     FAPI_TRY(l_data_engine.set_master_ranks(), "Failed to set Master ranks %s", mss::spd::c_str(i_target) );
+
+    // and dimm_ranks_configured is a PRD attr...
     FAPI_TRY(l_data_engine.set_dimm_ranks_configured(), "Failed to set DIMM ranks configured %s",
              mss::spd::c_str(i_target) );
 
+    // Adding metadata c-str fields derived from attrs set above
     FAPI_TRY( mss::attr_derived_engine<mss::generic_metadata_fields>::set(i_target) );
 
 fapi_try_exit:
diff --git a/src/import/generic/memory/lib/mss_generic_attribute_getters.H b/src/import/generic/memory/lib/mss_generic_attribute_getters.H
index f16829f3b..c8fd30b63 100644
--- a/src/import/generic/memory/lib/mss_generic_attribute_getters.H
+++ b/src/import/generic/memory/lib/mss_generic_attribute_getters.H
@@ -1464,14 +1464,60 @@ fapi_try_exit:
 }
 
 ///
+/// @brief ATTR_MEM_EFF_PRIM_DIE_COUNT getter
+/// @param[in] const ref to the TARGET_TYPE_DIMM
+/// @param[out] uint8_t& reference to store the value
+/// @note Generated by gen_accessors.pl generate_mc_port_params
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  ARRAY[DIMM] Primary SDRAM Die Count. Decodes Byte 6 (bits 6~4).
+///
+inline fapi2::ReturnCode get_prim_die_count(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value)
+{
+    uint8_t l_value[2] = {};
+    const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>();
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_EFF_PRIM_DIE_COUNT, l_port, l_value) );
+    o_value = l_value[mss::index(i_target)];
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed getting ATTR_MEM_EFF_PRIM_DIE_COUNT: 0x%lx (target: %s)",
+             uint64_t(fapi2::current_err), mss::c_str(i_target));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_MEM_EFF_PRIM_DIE_COUNT getter
+/// @param[in] const ref to the TARGET_TYPE_MEM_PORT
+/// @param[out] uint8_t&[] array reference to store the value
+/// @note Generated by gen_accessors.pl generate_mc_port_params
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  ARRAY[DIMM] Primary SDRAM Die Count. Decodes Byte 6 (bits 6~4).
+///
+inline fapi2::ReturnCode get_prim_die_count(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target,
+        uint8_t (&o_array)[2])
+{
+    uint8_t l_value[2] = {};
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_EFF_PRIM_DIE_COUNT, i_target, l_value) );
+    memcpy(o_array, &l_value, 2);
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed getting ATTR_MEM_EFF_PRIM_DIE_COUNT: 0x%lx (target: %s)",
+             uint64_t(fapi2::current_err), mss::c_str(i_target));
+    return fapi2::current_err;
+}
+
+///
 /// @brief ATTR_MEM_EFF_PRIM_STACK_TYPE getter
 /// @param[in] const ref to the TARGET_TYPE_DIMM
 /// @param[out] uint8_t& reference to store the value
 /// @note Generated by gen_accessors.pl generate_mc_port_params
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  ARRAY[DIMM] Primary SDRAM Package Type. Decodes Byte 6. This byte defines the primary
-/// set of SDRAMs. Monolithic = SPD, Multi-load stack = DDP/QDP, Single-load stack =
-/// 3DS
+/// @note  ARRAY[DIMM] Primary SDRAM Package Type (bits 1~0). Decodes Byte 6. This byte defines
+/// the primary set of SDRAMs. Monolithic = SPD, Multi-load stack = DDP/QDP, Single-load
+/// stack = 3DS
 ///
 inline fapi2::ReturnCode get_prim_stack_type(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value)
 {
@@ -1494,9 +1540,9 @@ fapi_try_exit:
 /// @param[out] uint8_t&[] array reference to store the value
 /// @note Generated by gen_accessors.pl generate_mc_port_params
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  ARRAY[DIMM] Primary SDRAM Package Type. Decodes Byte 6. This byte defines the primary
-/// set of SDRAMs. Monolithic = SPD, Multi-load stack = DDP/QDP, Single-load stack =
-/// 3DS
+/// @note  ARRAY[DIMM] Primary SDRAM Package Type (bits 1~0). Decodes Byte 6. This byte defines
+/// the primary set of SDRAMs. Monolithic = SPD, Multi-load stack = DDP/QDP, Single-load
+/// stack = 3DS
 ///
 inline fapi2::ReturnCode get_prim_stack_type(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target,
         uint8_t (&o_array)[2])
@@ -1514,6 +1560,52 @@ fapi_try_exit:
 }
 
 ///
+/// @brief ATTR_MEM_EFF_PRIM_BUS_WIDTH getter
+/// @param[in] const ref to the TARGET_TYPE_DIMM
+/// @param[out] uint8_t& reference to store the value
+/// @note Generated by gen_accessors.pl generate_mc_port_params
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  ARRAY[DIMM] Primary bus with (bits 1~0). Decodes Byte 13.
+///
+inline fapi2::ReturnCode get_prim_bus_width(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value)
+{
+    uint8_t l_value[2] = {};
+    const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>();
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_EFF_PRIM_BUS_WIDTH, l_port, l_value) );
+    o_value = l_value[mss::index(i_target)];
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed getting ATTR_MEM_EFF_PRIM_BUS_WIDTH: 0x%lx (target: %s)",
+             uint64_t(fapi2::current_err), mss::c_str(i_target));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_MEM_EFF_PRIM_BUS_WIDTH getter
+/// @param[in] const ref to the TARGET_TYPE_MEM_PORT
+/// @param[out] uint8_t&[] array reference to store the value
+/// @note Generated by gen_accessors.pl generate_mc_port_params
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  ARRAY[DIMM] Primary bus with (bits 1~0). Decodes Byte 13.
+///
+inline fapi2::ReturnCode get_prim_bus_width(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target,
+        uint8_t (&o_array)[2])
+{
+    uint8_t l_value[2] = {};
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_EFF_PRIM_BUS_WIDTH, i_target, l_value) );
+    memcpy(o_array, &l_value, 2);
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed getting ATTR_MEM_EFF_PRIM_BUS_WIDTH: 0x%lx (target: %s)",
+             uint64_t(fapi2::current_err), mss::c_str(i_target));
+    return fapi2::current_err;
+}
+
+///
 /// @brief ATTR_MEM_EFF_DRAM_PPR getter
 /// @param[in] const ref to the TARGET_TYPE_DIMM
 /// @param[out] uint8_t& reference to store the value
@@ -1968,7 +2060,7 @@ fapi_try_exit:
 }
 
 ///
-/// @brief ATTR_MEM_EFF_NUM_RANKS_PER_DIMM getter
+/// @brief ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM getter
 /// @param[in] const ref to the TARGET_TYPE_DIMM
 /// @param[out] uint8_t& reference to store the value
 /// @note Generated by gen_accessors.pl generate_mc_port_params
@@ -1979,24 +2071,24 @@ fapi_try_exit:
 /// number of logical ranks per DIMM. Logical rank refers the individually addressable
 /// die in a 3DS stack and has no meaning for monolithic or multi-load stacked SDRAMs.
 ///
-inline fapi2::ReturnCode get_num_ranks_per_dimm(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode get_logical_ranks_per_dimm(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2] = {};
     const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>();
 
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_EFF_NUM_RANKS_PER_DIMM, l_port, l_value) );
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM, l_port, l_value) );
     o_value = l_value[mss::index(i_target)];
     return fapi2::current_err;
 
 fapi_try_exit:
-    FAPI_ERR("failed getting ATTR_MEM_EFF_NUM_RANKS_PER_DIMM: 0x%lx (target: %s)",
+    FAPI_ERR("failed getting ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM: 0x%lx (target: %s)",
              uint64_t(fapi2::current_err), mss::c_str(i_target));
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MEM_EFF_NUM_RANKS_PER_DIMM getter
+/// @brief ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM getter
 /// @param[in] const ref to the TARGET_TYPE_MEM_PORT
 /// @param[out] uint8_t&[] array reference to store the value
 /// @note Generated by gen_accessors.pl generate_mc_port_params
@@ -2007,17 +2099,17 @@ fapi_try_exit:
 /// number of logical ranks per DIMM. Logical rank refers the individually addressable
 /// die in a 3DS stack and has no meaning for monolithic or multi-load stacked SDRAMs.
 ///
-inline fapi2::ReturnCode get_num_ranks_per_dimm(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target,
+inline fapi2::ReturnCode get_logical_ranks_per_dimm(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target,
         uint8_t (&o_array)[2])
 {
     uint8_t l_value[2] = {};
 
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_EFF_NUM_RANKS_PER_DIMM, i_target, l_value) );
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM, i_target, l_value) );
     memcpy(o_array, &l_value, 2);
     return fapi2::current_err;
 
 fapi_try_exit:
-    FAPI_ERR("failed getting ATTR_MEM_EFF_NUM_RANKS_PER_DIMM: 0x%lx (target: %s)",
+    FAPI_ERR("failed getting ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM: 0x%lx (target: %s)",
              uint64_t(fapi2::current_err), mss::c_str(i_target));
     return fapi2::current_err;
 }
diff --git a/src/import/generic/memory/lib/utils/shared/mss_generic_consts.H b/src/import/generic/memory/lib/utils/shared/mss_generic_consts.H
index 4d7f8afe7..2dee8fa53 100644
--- a/src/import/generic/memory/lib/utils/shared/mss_generic_consts.H
+++ b/src/import/generic/memory/lib/utils/shared/mss_generic_consts.H
@@ -194,6 +194,12 @@ enum generic_ffdc_codes
     SET_DRAM_GEN_METADATA = 0x1063,
     SET_DIMM_TYPE_METADATA = 0x1064,
     SET_DIMM_POS_METADATA = 0x1065,
+    SET_LOGICAL_RANKS = 0x1066,
+    SET_PRIM_STACK_TYPE = 0x1067,
+    SET_DIMM_SIZE = 0x1068,
+    SET_PRIM_BUS_WIDTH = 0x1069,
+    SET_PRIM_DIE_COUNT = 0x1070,
+    SET_DRAM_DENSITY = 0x1071,
 };
 
 ///
diff --git a/src/import/generic/procedures/xml/attribute_info/generic_memory_eff_attributes.xml b/src/import/generic/procedures/xml/attribute_info/generic_memory_eff_attributes.xml
index 8890a447b..1b2e69ea4 100644
--- a/src/import/generic/procedures/xml/attribute_info/generic_memory_eff_attributes.xml
+++ b/src/import/generic/procedures/xml/attribute_info/generic_memory_eff_attributes.xml
@@ -212,11 +212,36 @@
   </attribute>
 
   <attribute>
+    <id>ATTR_MEM_EFF_PRIM_DIE_COUNT</id>
+    <targetType>TARGET_TYPE_MEM_PORT</targetType>
+    <description>
+      ARRAY[DIMM]
+      Primary SDRAM Die Count.
+      Decodes Byte 6 (bits 6~4).
+    </description>
+    <initToZero></initToZero>
+    <valueType>uint8</valueType>
+    <enum>
+      D1 = 1,
+      D2 = 2,
+      D3 = 3,
+      D4 = 4,
+      D5 = 5,
+      D6 = 6,
+      D7 = 7,
+      D8 = 8
+    </enum>
+    <writeable/>
+    <array>2</array>
+    <mssAccessorName>prim_die_count</mssAccessorName>
+  </attribute>
+
+  <attribute>
     <id>ATTR_MEM_EFF_PRIM_STACK_TYPE</id>
     <targetType>TARGET_TYPE_MEM_PORT</targetType>
     <description>
       ARRAY[DIMM]
-      Primary SDRAM Package Type.
+      Primary SDRAM Package Type (bits 1~0).
       Decodes Byte 6.
       This byte defines the primary set of SDRAMs.
       Monolithic = SPD, Multi-load stack = DDP/QDP, Single-load stack = 3DS
@@ -230,6 +255,24 @@
   </attribute>
 
   <attribute>
+    <id>ATTR_MEM_EFF_PRIM_BUS_WIDTH</id>
+    <targetType>TARGET_TYPE_MEM_PORT</targetType>
+    <description>
+      ARRAY[DIMM]
+      Primary bus with (bits 1~0).
+      Decodes Byte 13.
+    </description>
+    <initToZero></initToZero>
+    <valueType>uint8</valueType>
+    <enum>
+      8_BITS = 8, 16_BITS = 16, 32_BITS = 32, 64_BITS = 64
+    </enum>
+    <writeable/>
+    <array>2</array>
+    <mssAccessorName>prim_bus_width</mssAccessorName>
+  </attribute>
+
+  <attribute>
     <id>ATTR_MEM_EFF_DRAM_PPR</id>
     <targetType>TARGET_TYPE_MEM_PORT</targetType>
     <description>
@@ -522,7 +565,7 @@
   </attribute>
 
   <attribute>
-    <id>ATTR_MEM_EFF_NUM_RANKS_PER_DIMM</id>
+    <id>ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM</id>
     <targetType>TARGET_TYPE_MEM_PORT</targetType>
     <description>
       ARRAY[DIMM]
@@ -542,7 +585,7 @@
     </enum>
     <writeable/>
     <array>2</array>
-    <mssAccessorName>num_ranks_per_dimm</mssAccessorName>
+    <mssAccessorName>logical_ranks_per_dimm</mssAccessorName>
   </attribute>
 
   <attribute>
diff --git a/src/usr/diag/prdf/common/plat/prdfTargetServices.C b/src/usr/diag/prdf/common/plat/prdfTargetServices.C
index 65f8b9cdc..fce6dee9e 100755
--- a/src/usr/diag/prdf/common/plat/prdfTargetServices.C
+++ b/src/usr/diag/prdf/common/plat/prdfTargetServices.C
@@ -1822,10 +1822,10 @@ uint8_t __getNumRanksPerDimm( TargetHandle_t i_trgt,
     }
     else if ( MODEL_AXONE == l_procModel )
     {
-        ATTR_MEM_EFF_NUM_RANKS_PER_DIMM_type attr;
-        if ( !i_trgt->tryGetAttr<ATTR_MEM_EFF_NUM_RANKS_PER_DIMM>(attr) )
+        ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM_type attr;
+        if ( !i_trgt->tryGetAttr<ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM>(attr) )
         {
-            PRDF_ERR( PRDF_FUNC "tryGetAttr<ATTR_MEM_EFF_NUM_RANKS_PER_DIMM> "
+            PRDF_ERR( PRDF_FUNC "tryGetAttr<ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM> "
                       "failed: i_trgt=0x%08x", getHuid(i_trgt) );
             PRDF_ASSERT( false ); // attribute does not exist for target
         }