Clean up some comments and refactor how we determine new cache entry

While code was added to handle detecting new OCMB parts a new check
was added to make sure an entry was newly added to cache to make it so
we didnt do new part validation on entries that had not been cached yet.
This commit removes what was added and leverages existing information we
had earlier on in the caching algorith. Also in this commit a few minor
comments were addressed related to tracing and doxygen comments.

Change-Id: Ie3454181449320a6a570c15692cc1f71c819ba22
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/77814
Reviewed-by: Matthew Raybuck <matthew.raybuck@ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Chen Du <duchen@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

4 files changed, 18 insertions, 24 deletions

diff --git a/src/include/usr/vpd/vpd_if.H b/src/include/usr/vpd/vpd_if.H
index a995fe06c..b649b46ab 100644
--- a/src/include/usr/vpd/vpd_if.H
+++ b/src/include/usr/vpd/vpd_if.H
@@ -112,13 +112,9 @@ namespace VPD
      *        sync with hardware and returns the result in o_isInSync.
      *
      * @param[in]   i_target      Target device
-     *
-     *
      * @param[in]   i_eepromType  Eeprom content type of target device
-     *
      * @param[out]  o_isInSync    true if part and serial numbers in cache match
      *                            hardware. Otherwise, false.
-     *
      * @return errlHndl_t - NULL if successful, otherwise a pointer to the
      *      error log.
      */
diff --git a/src/usr/i2c/eepromCache.C b/src/usr/i2c/eepromCache.C
index 7fa2b9861..8eb858883 100644
--- a/src/usr/i2c/eepromCache.C
+++ b/src/usr/i2c/eepromCache.C
@@ -358,6 +358,9 @@ errlHndl_t cacheEeprom(TARGETING::Target* i_target,
                 // to be the current "end of cache" offset in the toc.
                 l_eepromRecordHeader.completeRecord.internal_offset = l_eecacheSectionHeaderPtr->end_of_cache;
                 l_eecacheSectionHeaderPtr->end_of_cache += l_eepromLen;
+
+                // Set cached_copy_valid to 0 until the cache contents actually gets loaded
+                l_recordHeaderToUpdate->completeRecord.cached_copy_valid = 0;
                 l_updateContents = i_present;
                 break;
             }
@@ -444,29 +447,14 @@ errlHndl_t cacheEeprom(TARGETING::Target* i_target,
         }
 
 
-        uint64_t l_eepromCacheVaddr = lookupEepromAddr(l_eepromRecordHeader);
-        const uint64_t l_invalidAddress = 0xFFFFFFFFFFFFFFFF;
-
-        // If the virtual address of the eeprom record header is an invalid
-        // address then this is the first time this target's eeprom is being
-        // cached.
-        bool l_isNewCacheEntry = false;
-        if (memcmp(
-                reinterpret_cast<void *>(l_eepromCacheVaddr),
-                &l_invalidAddress, sizeof(uint64_t)) == 0)
-        {
-            l_isNewCacheEntry = true;
-        }
-
-        // At this point we have found a match in the PNOR but we need
-        // to decide what all needs an update.
-        //
         // Only check if the cache is in sync with HARDWARE if there is an
         // existing EECACHE section. Otherwise, the code after this logic will
         // take care of adding a new eeprom cache section for the target.
-        if (   l_recordHeaderToUpdate->completeRecord.cached_copy_valid
-            && !l_isNewCacheEntry)
+        if (l_recordHeaderToUpdate->completeRecord.cached_copy_valid)
         {
+            // At this point we have found a match in the PNOR but we need
+            // to decide what all needs an update.
+
             // Create namespace alias for targeting to reduce number of
             // new lines required to be within line character limit.
             namespace T = TARGETING;
@@ -622,6 +610,13 @@ errlHndl_t cacheEeprom(TARGETING::Target* i_target,
                 break;
             }
 
+            // If cache copy was not valid before, it is now valid, we must update the header
+            if (!l_recordHeaderToUpdate->completeRecord.cached_copy_valid)
+            {
+                  l_eepromRecordHeader.completeRecord.cached_copy_valid = 0x01;
+                  l_updateHeader = true;
+            }
+
         }
 
         // Above we have determined whether the header entry for the eeprom at
diff --git a/src/usr/vpd/spd.C b/src/usr/vpd/spd.C
index 09db1c497..52f603310 100644
--- a/src/usr/vpd/spd.C
+++ b/src/usr/vpd/spd.C
@@ -2392,6 +2392,7 @@ errlHndl_t cmpEecacheToEeprom(TARGETING::Target * i_target,
 
         if (!isValidDimmType(memTypeCache, i_eepromType))
         {
+            TRACFCOMP(g_trac_spd, ERR_MRK"cmpEecacheToEeprom() Invalid DIMM type found in cache copy of eeprom");
             break;
         }
 
@@ -2409,6 +2410,7 @@ errlHndl_t cmpEecacheToEeprom(TARGETING::Target * i_target,
         if (!isValidDimmType(memTypeHardware, i_eepromType))
         {
             // Leave o_match == false and exit.
+            TRACFCOMP(g_trac_spd, ERR_MRK"cmpEecacheToEeprom() Invalid DIMM type found in hw copy of eeprom");
             break;
         }
 
diff --git a/src/usr/vpd/vpd.C b/src/usr/vpd/vpd.C
index a9883eb37..aa85a3ed6 100755
--- a/src/usr/vpd/vpd.C
+++ b/src/usr/vpd/vpd.C
@@ -727,7 +727,8 @@ errlHndl_t cmpEecacheToEeprom(TARGETING::Target *            i_target,
     }
     else
     {
-        assert(false, "Error, invalid EEPROM type passed to cmpEecacheToEeprom");
+        assert(false, "Error, invalid EEPROM type 0x%x for target HUID 0x%X passed to cmpEecacheToEeprom",
+               i_eepromType, get_huid(i_target));
     }
 
     return l_err;