SW427193 / HW461448: Enable memory controller wat

Change-Id: I2fc4cf0dda43d4eba543024605c8f358e22e1bae
CQ:SW427193
CQ:HW461448
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/65476
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: Adam S. Hale <adam.samuel.hale@ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/65510
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>

5 files changed, 100 insertions, 0 deletions

diff --git a/src/build/citest/etc/workarounds.postsimsetup b/src/build/citest/etc/workarounds.postsimsetup
index 32523a5a9..bab36d991 100755
--- a/src/build/citest/etc/workarounds.postsimsetup
+++ b/src/build/citest/etc/workarounds.postsimsetup
@@ -33,5 +33,8 @@
 #cp $BACKING_BUILD/src/simu/data/cec-chip/base_cec_chip_file $sb/simu/data/cec-chip
 #patch -p0 $sb/simu/data/cec-chip/base_cec_chip_file $PROJECT_ROOT/src/build/citest/etc/patches/my_patch_File
 
+#echo "+++ Adding reg 501081D to p9c.chip +++"
+mkdir -p $sb/simu/data/cec-chip/
+sbex -t 1067370 -f aix@auscmvc1.austin.ibm.com@2035 -r fips921 -d $sb/../
 
 ##########################################################################
diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9c_dmi_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9c_dmi_scom.C
index 5f0397cc9..1b61f1644 100644
--- a/src/import/chips/p9/procedures/hwp/initfiles/p9c_dmi_scom.C
+++ b/src/import/chips/p9/procedures/hwp/initfiles/p9c_dmi_scom.C
@@ -51,6 +51,8 @@ constexpr uint64_t literal_6 = 6;
 constexpr uint64_t literal_0x26 = 0x26;
 constexpr uint64_t literal_0x33 = 0x33;
 constexpr uint64_t literal_0x40 = 0x40;
+constexpr uint64_t literal_0b01111 = 0b01111;
+constexpr uint64_t literal_0b00001 = 0b00001;
 constexpr uint64_t literal_3 = 3;
 constexpr uint64_t literal_1167 = 1167;
 constexpr uint64_t literal_1000 = 1000;
@@ -263,6 +265,13 @@ fapi2::ReturnCode p9c_dmi_scom(const fapi2::Target<fapi2::TARGET_TYPE_DMI>& TGT0
             FAPI_TRY(fapi2::putScom(TGT0, 0x5010827ull, l_scom_buffer));
         }
         {
+            FAPI_TRY(fapi2::getScom( TGT0, 0x501082aull, l_scom_buffer ));
+
+            l_scom_buffer.insert<12, 5, 59, uint64_t>(literal_0b01111 );
+            l_scom_buffer.insert<17, 5, 59, uint64_t>(literal_0b00001 );
+            FAPI_TRY(fapi2::putScom(TGT0, 0x501082aull, l_scom_buffer));
+        }
+        {
             FAPI_TRY(fapi2::getScom( TGT0, 0x501082bull, l_scom_buffer ));
 
             if (l_def_ENABLE_AMO_CACHING)
@@ -505,6 +514,15 @@ fapi2::ReturnCode p9c_dmi_scom(const fapi2::Target<fapi2::TARGET_TYPE_DMI>& TGT0
 
             FAPI_TRY(fapi2::putScom(TGT0, 0x7012348ull, l_scom_buffer));
         }
+        {
+            FAPI_TRY(fapi2::getScom( TGT0, 0x701234bull, l_scom_buffer ));
+
+            constexpr auto l_MCP_CHAN0_WRITE_NEST_DBG_SEL_WRT_ON = 0x1;
+            l_scom_buffer.insert<1, 1, 63, uint64_t>(l_MCP_CHAN0_WRITE_NEST_DBG_SEL_WRT_ON );
+            constexpr auto l_MCP_CHAN0_WRITE_WBMGR_DBG_0_SELECT_ON = 0x1;
+            l_scom_buffer.insert<2, 1, 63, uint64_t>(l_MCP_CHAN0_WRITE_WBMGR_DBG_0_SELECT_ON );
+            FAPI_TRY(fapi2::putScom(TGT0, 0x701234bull, l_scom_buffer));
+        }
 
     };
 fapi_try_exit:
diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9c_mi_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9c_mi_scom.C
index 8b526c36e..977fe9103 100644
--- a/src/import/chips/p9/procedures/hwp/initfiles/p9c_mi_scom.C
+++ b/src/import/chips/p9/procedures/hwp/initfiles/p9c_mi_scom.C
@@ -47,6 +47,8 @@ constexpr uint64_t literal_0b0000000000001000 = 0b0000000000001000;
 constexpr uint64_t literal_0b10 = 0b10;
 constexpr uint64_t literal_0b01 = 0b01;
 constexpr uint64_t literal_5 = 5;
+constexpr uint64_t literal_0xE = 0xE;
+constexpr uint64_t literal_0b100 = 0b100;
 
 fapi2::ReturnCode p9c_mi_scom(const fapi2::Target<fapi2::TARGET_TYPE_MI>& TGT0,
                               const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& TGT1, const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& TGT2)
@@ -346,6 +348,13 @@ fapi2::ReturnCode p9c_mi_scom(const fapi2::Target<fapi2::TARGET_TYPE_MI>& TGT0,
 
             FAPI_TRY(fapi2::putScom(TGT0, 0x501081bull, l_scom_buffer));
         }
+        {
+            FAPI_TRY(fapi2::getScom( TGT0, 0x501081cull, l_scom_buffer ));
+
+            l_scom_buffer.insert<32, 4, 60, uint64_t>(literal_0xE );
+            l_scom_buffer.insert<16, 3, 61, uint64_t>(literal_0b100 );
+            FAPI_TRY(fapi2::putScom(TGT0, 0x501081cull, l_scom_buffer));
+        }
 
     };
 fapi_try_exit:
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_chiplet_scominit.C b/src/import/chips/p9/procedures/hwp/nest/p9_chiplet_scominit.C
index 77563c44b..ab9f19f8c 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_chiplet_scominit.C
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_chiplet_scominit.C
@@ -53,6 +53,7 @@
 #include <p9_vas_scom.H>
 #include <p9_fbc_smp_utils.H>
 #include <p9_mc_scom_addresses.H>
+#include <p9_mc_scom_addresses_fld.H>
 #include <p9_xbus_scom_addresses.H>
 #include <p9_xbus_scom_addresses_fld.H>
 #include <p9_obus_scom_addresses.H>
@@ -82,6 +83,14 @@ static const uint64_t MCBIST_FIR_ACTION0 = 0x0000000000000000ULL;
 static const uint64_t MCBIST_FIR_ACTION1 = 0x2000000000000000ULL;
 static const uint64_t MCBIST_FIR_MASK    = 0xDC00000000000000ULL;
 
+// HW461448 MC WAT
+static const uint8_t  MCWAT_SELECT0 = 0x0;
+static const uint8_t  MCWAT_SELECT3 = 0x3;
+static const uint8_t  MCWAT_SELECT9 = 0x9;
+static const uint64_t MCWAT_DATA0   = 0x02EC001000000000ULL; // 75 counts
+static const uint64_t MCWAT_DATA3   = 0x100003BFFFF00000ULL; // 16 entries
+static const uint64_t MCWAT_DATA9   = 0x8000000001010800ULL;
+
 //------------------------------------------------------------------------------
 // Function definitions
 //------------------------------------------------------------------------------
@@ -107,6 +116,7 @@ fapi2::ReturnCode p9_chiplet_scominit(const fapi2::Target<fapi2::TARGET_TYPE_PRO
     uint32_t l_eps_write_cycles_t1 = 0;
     uint32_t l_eps_write_cycles_t2 = 0;
     uint8_t l_npu_enabled = 0;
+    uint8_t l_hw461448 = 0;
 
     FAPI_DBG("Start");
 
@@ -208,6 +218,45 @@ fapi2::ReturnCode p9_chiplet_scominit(const fapi2::Target<fapi2::TARGET_TYPE_PRO
                 fapi2::current_err = l_rc;
                 goto fapi_try_exit;
             }
+
+            // HW461448 Configure MC WAT for Cumulus using indirect scoms
+            FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_HW461448, i_target, l_hw461448),
+                     "Error from FAPI_ATTR_GET(ATTR_CHIP_EC_FEATURE_HW461448)");
+
+            if (l_hw461448)
+            {
+                FAPI_TRY(fapi2::getScom(l_mi_target, MCS_MCWATCNTL, l_scom_data),
+                         "Error from getScom (MCS_MCWATCNTL)");
+
+                // MCWATDATA0
+                l_scom_data.insertFromRight<MCS_MCWATCNTL_WAT_CNTL_REG_SEL, MCS_MCWATCNTL_WAT_CNTL_REG_SEL_LEN>
+                (MCWAT_SELECT0);
+                FAPI_TRY(fapi2::putScom(l_mi_target, MCS_MCWATCNTL, l_scom_data),
+                         "Error from putScom (MCS_MCWATCNTL)");
+                FAPI_TRY(fapi2::putScom(l_mi_target, MCS_MCWATDATA, MCWAT_DATA0),
+                         "Error from putScom (MCS_MCWATDATA)");
+
+                // MCWATDATA3
+                l_scom_data.insertFromRight<MCS_MCWATCNTL_WAT_CNTL_REG_SEL, MCS_MCWATCNTL_WAT_CNTL_REG_SEL_LEN>
+                (MCWAT_SELECT3);
+                FAPI_TRY(fapi2::putScom(l_mi_target, MCS_MCWATCNTL, l_scom_data),
+                         "Error from putScom (MCS_MCWATCNTL)");
+                FAPI_TRY(fapi2::putScom(l_mi_target, MCS_MCWATDATA, MCWAT_DATA3),
+                         "Error from putScom (MCS_MCWATDATA)");
+
+                // MCWATDATA9
+                l_scom_data.insertFromRight<MCS_MCWATCNTL_WAT_CNTL_REG_SEL, MCS_MCWATCNTL_WAT_CNTL_REG_SEL_LEN>
+                (MCWAT_SELECT9);
+                FAPI_TRY(fapi2::putScom(l_mi_target, MCS_MCWATCNTL, l_scom_data),
+                         "Error from putScom (MCS_MCWATCNTL)");
+                FAPI_TRY(fapi2::putScom(l_mi_target, MCS_MCWATDATA, MCWAT_DATA9),
+                         "Error from putScom (MCS_MCWATDATA)");
+
+                // Enable MC WAT
+                l_scom_data.setBit<MCS_MCWATCNTL_ENABLE_WAT>();
+                FAPI_TRY(fapi2::putScom(l_mi_target, MCS_MCWATCNTL, l_scom_data),
+                         "Error from putScom (MCS_MCWATCNTL)");
+            }
         }
 
         for (auto l_dmi_target : l_dmi_targets)
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
index b371d5f96..f01bfda93 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
@@ -7842,6 +7842,27 @@
   </attribute>
   <!-- ******************************************************************** -->
   <attribute>
+    <id>ATTR_CHIP_EC_FEATURE_HW461448</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+        Enable MC WAT to hold off incoming commands to the memory controller after
+        a certain fullness level. Currently configured to hold off for 75 counts
+        after reaching 16 entries in the write buffers. This will allow existing
+        entries in queue to make forward progress before commiting more into the
+        queues.
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_CUMULUS</name>
+        <ec>
+          <value>0x10</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+  <!-- ******************************************************************** -->
+  <attribute>
     <id>ATTR_CHIP_EC_FEATURE_SYNC_SS_PLL_SPREAD</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>