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authorPatrick Williams <iawillia@us.ibm.com>2012-08-20 15:52:07 -0500
committerA. Patrick Williams III <iawillia@us.ibm.com>2012-09-05 15:42:19 -0500
commit1c6e1a4cddde411b6219b9e881039ffbda0deb4f (patch)
tree1e1ff02f7e51c0f7667ae30154e3bb326838fca4 /src
parentc07b8bb150f1464e17ebf3672460564ec3e8947c (diff)
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Set "high" thread priority as 2 rather than 3.
The Power processor has instructions of the form 'or a,a,a' that allow code to change the priority of a hw-thread relative to the others. We initially used 'or 1,1,1' as low priority and 'or 3,3,3' as high priority. This is used in, for instance, spinlocks to reduce the priority of a hw-thread while waiting for another thread to perform an activity. This code originally came from HAL. In reading the Power ISA closer I realized that 'or 3,3,3' has no effect when in user-space code, which means that a spinlock-like effect in user code is going to end up with the thread stuck at low priority until the next context switch. To prevent this we are going to change from 1/3 to 1/2 as the priority levels. Change-Id: I60ee866cde37499106f5e1e1d68a0b5ddeedf403 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1569 Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src')
-rw-r--r--src/include/arch/ppc.H47
-rw-r--r--src/kernel/shutdown.S8
-rw-r--r--src/kernel/start.S8
3 files changed, 30 insertions, 33 deletions
diff --git a/src/include/arch/ppc.H b/src/include/arch/ppc.H
index 4e6add553..42ec52db4 100644
--- a/src/include/arch/ppc.H
+++ b/src/include/arch/ppc.H
@@ -1,26 +1,25 @@
-/* IBM_PROLOG_BEGIN_TAG
- * This is an automatically generated prolog.
- *
- * $Source: src/include/arch/ppc.H $
- *
- * IBM CONFIDENTIAL
- *
- * COPYRIGHT International Business Machines Corp. 2011-2012
- *
- * p1
- *
- * Object Code Only (OCO) source materials
- * Licensed Internal Code Source Materials
- * IBM HostBoot Licensed Internal Code
- *
- * The source code for this program is not published or other-
- * wise divested of its trade secrets, irrespective of what has
- * been deposited with the U.S. Copyright Office.
- *
- * Origin: 30
- *
- * IBM_PROLOG_END_TAG
- */
+/* IBM_PROLOG_BEGIN_TAG */
+/* This is an automatically generated prolog. */
+/* */
+/* $Source: src/include/arch/ppc.H $ */
+/* */
+/* IBM CONFIDENTIAL */
+/* */
+/* COPYRIGHT International Business Machines Corp. 2011,2012 */
+/* */
+/* p1 */
+/* */
+/* Object Code Only (OCO) source materials */
+/* Licensed Internal Code Source Materials */
+/* IBM HostBoot Licensed Internal Code */
+/* */
+/* The source code for this program is not published or otherwise */
+/* divested of its trade secrets, irrespective of what has been */
+/* deposited with the U.S. Copyright Office. */
+/* */
+/* Origin: 30 */
+/* */
+/* IBM_PROLOG_END_TAG */
#ifndef __KERNEL_PPCARCH_H
#define __KERNEL_PPCARCH_H
@@ -255,7 +254,7 @@ inline void setThreadPriorityLow()
ALWAYS_INLINE
inline void setThreadPriorityHigh()
{
- asm volatile("or 3,3,3");
+ asm volatile("or 2,2,2");
}
ALWAYS_INLINE
diff --git a/src/kernel/shutdown.S b/src/kernel/shutdown.S
index 2e03a58a7..bb7657318 100644
--- a/src/kernel/shutdown.S
+++ b/src/kernel/shutdown.S
@@ -38,7 +38,7 @@
bne 1b; \
/* Instruction barrier to ensure exit. */ \
isync; \
- or 3,3,3; /* Increase thread priority */
+ or 2,2,2; /* Increase thread priority */
.section .text
@@ -89,8 +89,7 @@ kernel_shutdown:
kernel_shutdown_ea0_1_mode:
;// Perform barrier - 1
KERNEL_BARRIER(r8, r3, r11)
- isync
- or 3,3,3 ;// Increase thread priority
+
;// Update HRMOR on master.
mfspr r10, PIR
andi. r10, r10, 7
@@ -153,13 +152,12 @@ kernel_shutdown_ea0_1_mode:
bdnz 1b
isync
;// Raise thread priority and leave ourselves.
- or 3,3,3
+ or 2,2,2
;// Clear "Hostboot active" scratch register.
li r3, (0x40 + 0x38) ;// See sys/mmio.h
mtspr SPRC, r3
li r3, 0x0
mtspr SPRD, r3
-
b 2b
.section .data
diff --git a/src/kernel/start.S b/src/kernel/start.S
index d7d4ec202..a97fd484f 100644
--- a/src/kernel/start.S
+++ b/src/kernel/start.S
@@ -50,7 +50,7 @@
.global _start
_start:
;// Set thread priority high.
- or 3,3,3
+ or 2,2,2
;// Clear MSR[TA] (bit 63).
mfmsr r2
@@ -146,7 +146,7 @@ finished_relocate:
#define STD_INTERRUPT_NOADDR(name) \
intvect_##name: \
- or 3,3,3; /* Ensure thread priority is high. */ \
+ or 2,2,2; /* Ensure thread priority is high. */ \
mtsprg1 r1; /* Save GPR1 */ \
;/* Retrieve processing address for interrupt. */ \
lis r1, intvect_##name##_finish_save@h; \
@@ -299,7 +299,7 @@ _other_thread_spinlock:
b 1b
;// Now released by primary thread.
_other_thread_spinlock_complete:
- or 3,3,3 ;// Raise thread priority.
+ or 2,2,2 ;// Raise thread priority.
isync
;// Get CPU object from thread ID.
mfspr r1, PIR
@@ -574,7 +574,7 @@ intvect_system_reset:
;// - IPI wake-up from winkle of slave core.
;// Raise priority to high.
- or 3,3,3
+ or 2,2,2
;// Free up two registers temporarily.
mtsprg0 r1
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