diff options
author | Brian Silver <bsilver@us.ibm.com> | 2015-12-28 11:26:59 -0600 |
---|---|---|
committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2016-02-22 09:42:21 -0600 |
commit | 13cadbe07510f7e7896c5c7c3cfd191a7075491e (patch) | |
tree | ee27b4cbf2f73575ab62d0c65a9faa5030a655b0 /src | |
parent | f6700762b490d9caf3a62f5d078859ca242701b6 (diff) | |
download | blackbird-hostboot-13cadbe07510f7e7896c5c7c3cfd191a7075491e.tar.gz blackbird-hostboot-13cadbe07510f7e7896c5c7c3cfd191a7075491e.zip |
Initial commit of memory subsystem
Change-Id: I6b63d2c4eec5d77585c91d905a464962a6153a0a
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/22978
Tested-by: Jenkins Server
Reviewed-by: Craig C. Hamilton <cchamilt@us.ibm.com>
Reviewed-by: Brian Silver <bsilver@us.ibm.com>
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/24518
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src')
32 files changed, 492 insertions, 86 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_attr_update.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_attr_update.C index 990ba1bf3..55c994354 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_attr_update.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_attr_update.C @@ -22,8 +22,7 @@ /// @brief Programatic over-rides related to effective config /// // *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> -// *HWP HWP Backup: Luke Mulkey <lwmulkey@us.ibm.com> -// *HWP FW Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com> // *HWP Team: Memory // *HWP Level: 1 // *HWP Consumed by: FSP:HB diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_attr_update.H b/src/import/chips/p9/procedures/hwp/memory/p9_mss_attr_update.H index b3f9c8726..3af07d6c7 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_attr_update.H +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_attr_update.H @@ -22,7 +22,6 @@ /// @brief Programatic over-rides related to effective config /// // *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> -// *HWP HWP Backup: Luke Mulkey <lwmulkey@us.ibm.com> // *HWP FW Owner: Brian Silver <bsilver@us.ibm.com> // *HWP Team: Memory // *HWP Level: 1 @@ -32,7 +31,6 @@ #define __P9_MSS_ATTR_UPDATE__ #include <fapi2.H> - typedef fapi2::ReturnCode (*p9_mss_attr_update_FP_t) (const fapi2::Target<fapi2::TARGET_TYPE_MCS>&); extern "C" diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.C index 5fe40ed53..f1cebe600 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.C @@ -19,31 +19,100 @@ /// /// @file p9_mss_ddr_phy_reset.C -/// @brief Initialize dram +/// @brief Reset the DDR PHY /// // *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> -// *HWP FW Owner: Brian Silver <bsilver@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 1 +// *HWP Level: 2 // *HWP Consumed by: FSP:HB +#include <stdint.h> +#include <string.h> + #include <fapi2.H> +#include <mss.H> + + #include "p9_mss_ddr_phy_reset.H" using fapi2::TARGET_TYPE_MCBIST; extern "C" { + /// -/// @brief Reset the DDR PHY -/// @param[in] i_target, the McBIST of the ports of the dram you're training -/// @return FAPI2_RC_SUCCESS iff ok +/// @brief Perform a phy reset on all the PHY related to this half-chip (mcbist) +/// @param[in] the mcbist representing the PHY +/// @return FAPI2_RC_SUCCESS iff OK /// - fapi2::ReturnCode p9_mss_ddr_phy_reset( const fapi2::Target<TARGET_TYPE_MCBIST>& i_target ) + fapi2::ReturnCode p9_mss_ddr_phy_reset(const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target) { - FAPI_INF("Start ddr phy reset"); - FAPI_INF("End ddr phy reset"); - return fapi2::FAPI2_RC_SUCCESS; + // Cache the name of our target. We can't just keep the pointer from c_str as + // it points to thread-local space and anything we call might change the string. + char l_name[fapi2::MAX_ECMD_STRING_LEN]; + strncpy(l_name, mss::c_str(i_target), fapi2::MAX_ECMD_STRING_LEN); + + FAPI_INF("********* %s start *********", __func__); + + // Initialize via scoms. Could be put in to p9_mss_scominit.C if that ever exists BRS. + FAPI_TRY( mss::phy_scominit(i_target) ); + + FAPI_TRY(mss::change_force_mclk_low(i_target, mss::HIGH), + "force_mclk_low (set high) Failed rc = 0x%08X", uint64_t(fapi2::current_err) ); + + // + // 1. Drive all control signals to the PHY to their inactive state, idle state, or inactive value. + FAPI_TRY( mss::dp16::setup_sysclk(i_target) ); + + // (Note: The chip should already be in this state.) + FAPI_DBG("All control signals to the PHYs should already be set to their inactive state, idle state, or inactive values"); + + // 2. Assert reset to PHY for 32 memory clocks + FAPI_TRY( mss::change_resetn(i_target, mss::HIGH), "change_resetn for %s failed", l_name ); + fapi2::delay(mss::cycles_to_ns(i_target, 32), mss::cycles_to_simcycles(32)); + + // 3. Deassert reset_n + FAPI_TRY( mss::change_resetn(i_target, mss::LOW), "change_resetn for %s failed", l_name ); + + // 4, 5, 6. + FAPI_TRY( mss::toggle_zctl(i_target), "toggle_zctl for %s failed", l_name ); + + // 7, 8. + FAPI_TRY( mss::deassert_pll_reset(i_target), "deassert_pll_reset failed for %s", l_name ); + + // 9, 10, 11, 12 & 13. Lock dphy_gckn and sysclk + FAPI_TRY( mss::bang_bang_lock(i_target) ); + + // 14? + + // + // + // + //FIXME: Need to code.. FAPI_TRY(mss_slew_cal(i_target), + // "mss_slew_cal Failed rc = 0x%08X", uint64_t(fapi2::current_err) ); + // slew cal successful +// FAPI_TRY( mss::slew_cal(i_target), "slew_cal for %s failed", l_name); + + FAPI_TRY( mss::ddr_phy_flush(i_target), "ddr_phy_flush failed for %s", l_name ); + +#ifdef LEAVES_OUTPUT_TO_DIMM_TRISTATE + // Per J. Bialas, force_mclk_low can be dasserted. + FAPI_TRY(mss::change_force_mclk_low(i_target, mss::LOW), + "force_mclk_low (set low) Failed rc = 0x%08X", uint64_t(fapi2::current_err) ); +#endif + + // If mss_unmask_ddrphy_errors gets it's own bad rc, + // it will commit the passed in rc (if non-zero), and return it's own bad rc. + // Else if mss_unmask_ddrphy_errors runs clean, + // it will just return the passed in rc. + //FIXME: Need to code.. FAPI_TRY(mss_unmask_ddrphy_errors(i_target, rc)); + + FAPI_INF("********* %s complete *********", __func__); + + fapi_try_exit: + return fapi2::current_err; + } + } diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.H b/src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.H index b10f472c6..12726b632 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.H +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.H @@ -19,21 +19,20 @@ /// /// @file p9_mss_ddr_phy_reset.H -/// @brief Perform reset of the DDR PHY +/// @brief Reset and initialize the DDR PHY /// -// *HWP HWP Owner: Luke Mulkey <lwmulkey@us.ibm.com> +// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> -// *HWP FW Owner: Brian Silver <bsilver@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 1 +// *HWP Level: 2 // *HWP Consumed by: FSP:HB -#ifndef __P9_MSS_DDR_PHY_RESET__ -#define __P9_MSS_DDR_PHY_RESET__ +#ifndef P9_MSS_DDR_PHY_RESET_H_ +#define P9_MSS_DDR_PHY_RESET_H_ #include <fapi2.H> -typedef fapi2::ReturnCode (*p9_mss_ddr_phy_reset_FP_t) (const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>&); +typedef fapi2::ReturnCode (*p9_mss_ddr_phy_reset_FP_t)(const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target); extern "C" { @@ -47,4 +46,3 @@ extern "C" } #endif - diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.mk b/src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.mk index 4241bd2d1..8f27a0743 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.mk +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.mk @@ -17,5 +17,9 @@ # # IBM_PROLOG_END_TAG +# Include the macros and things for MSS procedures +-include 00common.mk + PROCEDURE=p9_mss_ddr_phy_reset +$(eval $(call ADD_MEMORY_INCDIRS,$(PROCEDURE))) $(call BUILD_PROCEDURE) diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit.C index 2c96e96dd..fef042c24 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit.C @@ -23,27 +23,116 @@ /// // *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> -// *HWP FW Owner: Brian Silver <bsilver@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 1 +// *HWP Level: 2 // *HWP Consumed by: FSP:HB #include <fapi2.H> +#include <mss.H> + #include "p9_mss_draminit.H" using fapi2::TARGET_TYPE_MCBIST; +using fapi2::TARGET_TYPE_MCA; +using fapi2::FAPI2_RC_SUCCESS; extern "C" { /// /// @brief Initialize dram -/// @param[in] i_target, the McBIST of the ports of the dram you're training +/// @param[in] i_target, the McBIST of the ports of the dram you're initializing /// @return FAPI2_RC_SUCCESS iff ok /// fapi2::ReturnCode p9_mss_draminit( const fapi2::Target<TARGET_TYPE_MCBIST>& i_target ) { - FAPI_INF("Start draminit"); - FAPI_INF("End draminit"); - return fapi2::FAPI2_RC_SUCCESS; + fapi2::buffer<uint64_t> l_data; + + mss::ccs::instruction_t<TARGET_TYPE_MCBIST> l_inst; + mss::ccs::instruction_t<TARGET_TYPE_MCBIST> l_des = mss::ccs::des_command<TARGET_TYPE_MCBIST>(); + + mss::ccs::program<TARGET_TYPE_MCBIST> l_program; + + static const uint64_t PCLK_INITIAL_VALUE = 0x02; + static const uint64_t NCLK_INITIAL_VALUE = 0x01; + + auto l_mca = i_target.getChildren<TARGET_TYPE_MCA>(); + + FAPI_INF("Start draminit: %s", mss::c_str(i_target)); + + // If we don't have any ports, lets go. + if (l_mca.size() == 0) + { + FAPI_INF("No ports? %s", mss::c_str(i_target)); + return fapi2::FAPI2_RC_SUCCESS; + } + + // Configure the CCS engine. Since this is a chunk of McBIST logic, we don't want + // to do it for every port. If we ever break this code out so f/w can call draminit + // per-port (separate threads) we'll need to proved them a way to set this up before + // sapwning per-port threads. + { + fapi2::buffer<uint64_t> l_ccs_config; + + FAPI_TRY( mss::ccs::read_mode(i_target, l_ccs_config) ); + + // It's unclear if we want to run with this true or false. Right now (10/15) this + // has to be false. Shelton was unclear if this should be on or off in general BRS + mss::ccs::stop_on_err(i_target, l_ccs_config, mss::LOW); + mss::ccs::ue_disable(i_target, l_ccs_config, mss::LOW); + mss::ccs::copy_cke_to_spare_cke(i_target, l_ccs_config, mss::HIGH); + +#ifndef JIM_SAYS_TURN_OFF_ECC + mss::ccs::disable_ecc(i_target, l_ccs_config); +#endif + FAPI_TRY( mss::ccs::write_mode(i_target, l_ccs_config) ); + } + + // We initialize dram by iterating over the (ungarded) ports. We could allow the caller + // to initialize each port's dram on a separate thread if we could synchronize access + // to the MCBIST (CCS engine.) Right now we can't, so we'll do it this way. + + // + // We expect to come in to draminit with the following setup: + // 1. ENABLE_RESET_N (FARB5Q(6)) 0 + // 2. RESET_N (FARB5Q(4)) 0 - driving reset + // 3. CCS_ADDR_MUX_SEL (FARB5Q(5)) - 1 + // 4. CKE out of high impedence + // + for (auto p : l_mca) + { + FAPI_TRY( mss::draminit_entry_invariant(p) ); + FAPI_TRY( mss::ddr_resetn(p, mss::HIGH) ); + + // Begin driving mem clks, and wait 10ns (we'll do this outside the loop) + FAPI_TRY( mss::drive_mem_clks(p, PCLK_INITIAL_VALUE, NCLK_INITIAL_VALUE) ); + } + + // Clocks need to be started and stable for 10ns before CKE goes active. + // Not 100% clear what cycle count to use here. We'll assume 2400 for now. 10ns is 13 cycles freq 2400. + FAPI_TRY( fapi2::delay(mss::DELAY_10NS, mss::cycles_to_simcycles(13)) ); + + // Register DES instruction, which pulls CKE high. Idle 400 cycles, and then begin RCD loading + // Note: This only is sent to one of the MCA as we still have the mux_addr_sel bit set, meaning + // we'll PDE/DES all DIMM at the same time. + l_des.arr1.insertFromRight<MCBIST_CCS_INST_ARR1_00_IDLES, MCBIST_CCS_INST_ARR1_00_IDLES_LEN>(400); + l_program.iv_instructions.push_back(l_des); + FAPI_TRY( mss::ccs::execute(i_target, l_program, l_mca[0]) ); + + // Per conversation with Shelton and Steve 10/9/15, turn off addr_mux_sel after the CKE CCS but + // before the RCD/MRS CCSs + for (auto p : l_mca) + { + FAPI_TRY( change_addr_mux_sel(p, mss::LOW) ); + } + + // Load RCD control words + FAPI_TRY( mss::rcd_load(i_target) ); + + // Load MRS + FAPI_TRY( mss::mrs_load(i_target) ); + + fapi_try_exit: + FAPI_INF("End draminit: %s (0x%lx)", mss::c_str(i_target), uint64_t(fapi2::current_err)); + return fapi2::current_err; } } diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit.H b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit.H index 5edf9ec5b..99224df38 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit.H +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit.H @@ -21,11 +21,10 @@ /// @file p9_mss_draminit.H /// @brief Reset and initialze DRAM /// -// *HWP HWP Owner: Luke Mulkey <lwmulkey@us.ibm.com> +// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> -// *HWP FW Owner: Brian Silver <bsilver@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 1 +// *HWP Level: 2 // *HWP Consumed by: FSP:HB #ifndef __P9_MSS_DRAMINIT__ @@ -39,8 +38,8 @@ extern "C" { /// -/// @brief Initialize dram -/// @param[in] i_target, the McBIST of the ports of the dram you're training +/// @brief Initialize dram, assumes effective config has run +/// @param[in] i_target, the McBIST of the ports of the dram you're initializing /// @return FAPI2_RC_SUCCESS iff ok /// fapi2::ReturnCode p9_mss_draminit( const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target ); diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit.mk b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit.mk index 2ab354c8f..652f8d419 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit.mk +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit.mk @@ -17,5 +17,9 @@ # # IBM_PROLOG_END_TAG +# Include the macros and things for MSS procedures +-include 00common.mk + PROCEDURE=p9_mss_draminit +$(eval $(call ADD_MEMORY_INCDIRS,$(PROCEDURE))) $(call BUILD_PROCEDURE) diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.C index 1d62c4b0b..0d9c7342e 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.C @@ -23,27 +23,72 @@ /// // *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> -// *HWP FW Owner: Brian Silver <bsilver@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 1 +// *HWP Level: 2 // *HWP Consumed by: FSP:HB #include <fapi2.H> +#include <mss.H> + #include "p9_mss_draminit_mc.H" using fapi2::TARGET_TYPE_MCBIST; +using fapi2::TARGET_TYPE_MCA; extern "C" { /// /// @brief Initialize the MC now that DRAM is up -/// @param[in] i_target, the McBIST of the ports of the dram you're training +/// @param[in] i_target, the McBIST of the ports /// @return FAPI2_RC_SUCCESS iff ok /// fapi2::ReturnCode p9_mss_draminit_mc( const fapi2::Target<TARGET_TYPE_MCBIST>& i_target ) { + auto l_mca = i_target.getChildren<TARGET_TYPE_MCA>(); + FAPI_INF("Start draminit MC"); + + // If we don't have any ports, lets go. + if (l_mca.size() == 0) + { + FAPI_INF("No ports? %s", mss::c_str(i_target)); + return fapi2::FAPI2_RC_SUCCESS; + } + + for (auto p : l_mca) + { + // Set the IML Complete bit MBSSQ(3) (SCOM Addr: 0x02011417) to indicate that IML has completed + // Can't find MBSSQ or the iml_complete bit - asked Steve BRS. + + // Reset addr_mux_sel to “0” to allow the MBA to take control of the DDR interface over from CCS. + // (Note: this step must remain in this procedure to ensure that data path is placed into mainline + // mode prior to running memory diagnostics. When Advanced DRAM Training executes, this step + // becomes superfluous but not harmful. However, it's not guaranteed that Advanced DRAM Training + // will be executed on every system configuration.) + // Note: addr_mux_sel is set low in p9_mss_draminit(), however that might be a work-around so we + // set it low here kind of like belt-and-suspenders. BRS + FAPI_TRY( mss::change_addr_mux_sel(p, mss::LOW) ); + + // Step Two.1: Check RCD protect time on RDIMM and LRDIMM + // Step Two.2: Enable address inversion on each MBA for ALL CARDS + + // Start the refresh engines by setting MBAREF0Q(0) = “1”. Note that the remaining bits in + // MBAREF0Q should retain their initialization values. + FAPI_TRY( mss::change_refresh_enable(p, mss::HIGH) ); + + // Power management is handled in the init file. (or should be BRS) + + // Enabling periodic calibration + FAPI_TRY( mss::enable_periodic_cal(p) ); + + // Step Six: Setup Control Bit ECC + FAPI_TRY( mss::enable_read_ecc(p) ); + + // At this point the DDR interface must be monitored for memory errors. Memory related FIRs should be unmasked. + } + + fapi_try_exit: FAPI_INF("End draminit MC"); - return fapi2::FAPI2_RC_SUCCESS; + return fapi2::current_err; } } diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.H b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.H index f32c74796..82d00e879 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.H +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.H @@ -22,9 +22,8 @@ /// // *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> -// *HWP FW Owner: Brian Silver <bsilver@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 1 +// *HWP Level: 2 // *HWP Consumed by: FSP:HB #ifndef __P9_MSS_DRAMINIT_MC__ @@ -38,7 +37,7 @@ extern "C" { /// /// @brief Initialize the MC now that DRAM is up -/// @param[in] i_target, the McBIST of the ports of the dram you're training +/// @param[in] i_target, the McBIST of the ports /// @return FAPI2_RC_SUCCESS iff ok /// fapi2::ReturnCode p9_mss_draminit_mc( const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target ); diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.mk b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.mk index b18ee7c30..da27d668f 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.mk +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.mk @@ -17,5 +17,9 @@ # # IBM_PROLOG_END_TAG +# Include the macros and things for MSS procedures +-include 00common.mk + PROCEDURE=p9_mss_draminit_mc +$(eval $(call ADD_MEMORY_INCDIRS,$(PROCEDURE))) $(call BUILD_PROCEDURE) diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C index 12385454f..c8941c98f 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C @@ -23,15 +23,17 @@ /// // *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> -// *HWP FW Owner: Brian Silver <bsilver@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 1 +// *HWP Level: 2 // *HWP Consumed by: FSP:HB #include <fapi2.H> +#include <mss.H> + #include "p9_mss_draminit_training.H" using fapi2::TARGET_TYPE_MCBIST; +using fapi2::TARGET_TYPE_MCA; extern "C" { @@ -42,8 +44,132 @@ extern "C" /// fapi2::ReturnCode p9_mss_draminit_training( const fapi2::Target<TARGET_TYPE_MCBIST>& i_target ) { + fapi2::buffer<uint16_t> l_cal_steps_enabled; + FAPI_INF("Start draminit training"); + + uint8_t l_reset_disable = 0; + FAPI_TRY( mss::draminit_reset_disable(l_reset_disable) ); + + // Configure the CCS engine. + { + fapi2::buffer<uint64_t> l_ccs_config; + + FAPI_TRY( mss::ccs::read_mode(i_target, l_ccs_config) ); + + // It's unclear if we want to run with this true or false. Right now (10/15) this + // has to be false. Shelton was unclear if this should be on or off in general BRS + mss::ccs::stop_on_err(i_target, l_ccs_config, false); + mss::ccs::ue_disable(i_target, l_ccs_config, false); + mss::ccs::copy_cke_to_spare_cke(i_target, l_ccs_config, true); + + // Hm. Centaur sets this up for the longest duration possible. Can we do better? + mss::ccs::cal_count(i_target, l_ccs_config, ~0, ~0); + +#ifndef JIM_SAYS_TURN_OFF_ECC + mss::ccs::disable_ecc(i_target, l_ccs_config); +#endif + FAPI_TRY( mss::ccs::write_mode(i_target, l_ccs_config) ); + } + + // Clean out any previous calibration results, set bad-bits and configure the ranks. + FAPI_DBG("MCA's on this McBIST: %d", i_target.getChildren<TARGET_TYPE_MCA>().size()); + + for( auto p : i_target.getChildren<TARGET_TYPE_MCA>()) + { + mss::ccs::program<TARGET_TYPE_MCBIST> l_program; + + // Delays in the CCS instruction ARR1 for training are supposed to be 0xFFFF, + // and we're supposed to poll for the done or timeout bit. But we don't want + // to wait 0xFFFF cycles before we start polling - that's too long. So we put + // in a best-guess of how long to wait. This, in a perfect world, would be the + // time it takes one rank to train one training algorithm times the number of + // ranks we're going to train. We fail-safe as worst-case we simply poll the + // register too much - so we can tune this as we learn more. + l_program.iv_poll.iv_initial_sim_delay = mss::DELAY_100US; + l_program.iv_poll.iv_initial_sim_delay = 200; + l_program.iv_poll.iv_poll_count = 0xFFFF; + + // Returned from set_rank_pairs, it tells us how many rank pairs + // we configured on this port. + std::vector<uint64_t> l_pairs; + +#ifdef CAL_STATUS_DOESNT_REPORT_COMPLETE + // This isn't correct - shouldn't be setting + static const uint64_t CLEAR_CAL_COMPLETE = 0x000000000000F000; + FAPI_TRY( fapi2::putScom(p, MCA_DDRPHY_PC_INIT_CAL_STATUS_P0, CLEAR_CAL_COMPLETE) ); +#endif + FAPI_TRY( fapi2::putScom(p, MCA_DDRPHY_PC_INIT_CAL_ERROR_P0, 0) ); + FAPI_TRY( fapi2::putScom(p, MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0, 0) ); + + // Hit the reset button for wr_lvl values. These won't reset until the next run of wr_lvl + FAPI_TRY( mss::reset_wc_config0(p) ); + FAPI_TRY( mss::reset_wc_config1(p) ); + FAPI_TRY( mss::reset_wc_config2(p) ); + + // The following registers must be configured to the correct operating environment: + + // Unclear, can probably be 0's for sim BRS + // • Section 5.2.5.10 SEQ ODT Write Configuration {0-3} on page 422 + + FAPI_TRY( mss::reset_seq_config0(p) ); + FAPI_TRY( mss::reset_seq_rd_wr_data(p) ); + + FAPI_TRY( mss::reset_odt_config(p) ); + + // These are reset in phy_scominit + // • Section 5.2.6.1 WC Configuration 0 Register on page 434 + // • Section 5.2.6.2 WC Configuration 1 Register on page 436 + // • Section 5.2.6.3 WC Configuration 2 Register on page 438 + + // Get our rank pairs. + FAPI_TRY( mss::get_rank_pairs(p, l_pairs) ); + + // Setup the config register + // + // Grab the attribute which contains the information on what cal steps we should run + FAPI_TRY( mss::cal_step_enable(p, l_cal_steps_enabled) ); + + // Check to see if we're supposed to reset the delay values before starting training + if (l_reset_disable == fapi2::ENUM_ATTR_MSS_DRAMINIT_RESET_DISABLE_ENABLE) + { + FAPI_TRY( mss::dp16::reset_delay_values(p, l_pairs) ); + } + + FAPI_TRY( mss::dump_cal_registers(p) ); + + FAPI_DBG("generating calibration CCS instructions: %d rank-pairs", l_pairs.size()); + + // For each rank pair we need to calibrate, pop a ccs instruction in an array and execute it. + // NOTE: IF YOU CALIBRATE MORE THAN ONE RANK PAIR PER CCS PROGRAM, MAKE SURE TO CHANGE + // THE PROCESSING OF THE ERRORS. (it's hard to figure out which DIMM failed, too) BRS. + for (auto rp : l_pairs) + { + auto l_inst = mss::ccs::initial_cal_command<TARGET_TYPE_MCBIST>(rp); + + FAPI_DBG("exeecuting training CCS instruction: 0x%llx, 0x%llx", l_inst.arr0, l_inst.arr1); + l_program.iv_instructions.push_back(l_inst); + + // We need to figure out how long to wait before we start polling. Each cal step has an expected + // duration, so for each cal step which was enabled, we update the CCS program. + FAPI_TRY( mss::cal_timer_setup(p, l_program.iv_poll, l_cal_steps_enabled) ); + + FAPI_TRY( mss::setup_cal_config(p, rp, l_cal_steps_enabled) ); + + // In the event of an init cal hang, CCS_STATQ(2) will assert and CCS_STATQ(3:5) = “001” to indicate a + // timeout. Otherwise, if calibration completes, FW should inspect DDRPHY_FIR_REG bits (50) and (58) + // for signs of a calibration error. If either bit is on, then the DDRPHY_PC_INIT_CAL_ERROR register + // should be polled to determine which calibration step failed. + + // If we got a cal timeout, or another CCS error just leave now. If we got success, check the error + // bits for a cal failure. We'll return the proper ReturnCode so all we need to do is FAPI_TRY. + FAPI_TRY( mss::ccs::execute(i_target, l_program, p) ); + FAPI_TRY( mss::process_initial_cal_errors(p) ); + } + } + + fapi_try_exit: FAPI_INF("End draminit training"); - return fapi2::FAPI2_RC_SUCCESS; + return fapi2::current_err; } } diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.H b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.H index 4594a8df5..35e2f6cc8 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.H +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.H @@ -22,9 +22,8 @@ /// // *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> -// *HWP FW Owner: Brian Silver <bsilver@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 1 +// *HWP Level: 2 // *HWP Consumed by: FSP:HB #ifndef __P9_MSS_DRAMINIT_TRAINING__ @@ -36,12 +35,14 @@ typedef fapi2::ReturnCode (*p9_mss_draminit_training_FP_t) (const fapi2::Target< extern "C" { + /// -/// @brief Train dram +/// @brief Train dram, assumes effective config has run /// @param[in] i_target, the McBIST of the ports of the dram you're training /// @return FAPI2_RC_SUCCESS iff ok /// fapi2::ReturnCode p9_mss_draminit_training( const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target ); } + #endif diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.mk b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.mk index ce3f35c2a..23336582f 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.mk +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.mk @@ -17,5 +17,10 @@ # # IBM_PROLOG_END_TAG +# Include the macros and things for MSS procedures +-include 00common.mk + PROCEDURE=p9_mss_draminit_training +$(eval $(call ADD_MEMORY_INCDIRS,$(PROCEDURE))) +lib$(PROCEDURE)_DEPLIBS+=mss $(call BUILD_PROCEDURE) diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.C index 385900efa..88ec74266 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.C @@ -21,9 +21,8 @@ /// @file p9_mss_eff_config.C /// @brief Command and Control for the memory subsystem - populate attributes /// -// *HWP HWP Owner: Luke Mulkey <lwmulkey@us.ibm.com> -// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> -// *HWP FW Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> +// *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com> // *HWP Team: Memory // *HWP Level: 1 // *HWP Consumed by: FSP:HB @@ -31,17 +30,15 @@ #include <fapi2.H> #include "p9_mss_eff_config.H" -using fapi2::TARGET_TYPE_MCS; -using fapi2::FAPI2_RC_SUCCESS; /// /// @brief Configure the attributes for each controller /// @param[in] i_target, the controller (e.g., MCS) /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode p9_mss_eff_config( const fapi2::Target<TARGET_TYPE_MCS>& i_target ) +fapi2::ReturnCode p9_mss_eff_config( const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target ) { FAPI_INF("Start effective config"); FAPI_INF("End effective config"); - return FAPI2_RC_SUCCESS; + return fapi2::FAPI2_RC_SUCCESS; } diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.H b/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.H index 976876a46..b8a39d5a1 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.H +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.H @@ -21,9 +21,8 @@ /// @file p9_mss_eff_config.H /// @brief Command and Control for the memory subsystem - populate attributes /// -// *HWP HWP Owner: Luke Mulkey <lwmulkey@us.ibm.com> -// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> -// *HWP FW Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> +// *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com> // *HWP Team: Memory // *HWP Level: 1 // *HWP Consumed by: FSP:HB diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config_thermal.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config_thermal.C index 91681919e..1d9aeaed8 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config_thermal.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config_thermal.C @@ -21,9 +21,8 @@ /// @file p9_mss_eff_config_thermal.C /// @brief Perform thermal calculations as part of the effective configuration /// -// *HWP HWP Owner: Luke Mulkey <lwmulkey@us.ibm.com> -// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> -// *HWP FW Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> +// *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com> // *HWP Team: Memory // *HWP Level: 1 // *HWP Consumed by: FSP:HB @@ -31,17 +30,14 @@ #include <fapi2.H> #include "p9_mss_eff_config_thermal.H" -using fapi2::TARGET_TYPE_MCS; -using fapi2::FAPI2_RC_SUCCESS; - /// /// @brief Perform thermal calculations as part of the effective configuration /// @param[in] i_target, the controller (e.g., MCS) /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode p9_mss_eff_config_thermal( const fapi2::Target<TARGET_TYPE_MCS>& i_target ) +fapi2::ReturnCode p9_mss_eff_config_thermal( const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target ) { FAPI_INF("Start effective config thermal"); FAPI_INF("End effective config thermal"); - return FAPI2_RC_SUCCESS; + return fapi2::FAPI2_RC_SUCCESS; } diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config_thermal.H b/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config_thermal.H index 47367eb80..e6736f466 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config_thermal.H +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config_thermal.H @@ -21,9 +21,8 @@ /// @file p9_mss_eff_config_thermal.H /// @brief Perform thermal calculations as part of the effective configuration /// -// *HWP HWP Owner: Luke Mulkey <lwmulkey@us.ibm.com> -// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> -// *HWP FW Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> +// *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com> // *HWP Team: Memory // *HWP Level: 1 // *HWP Consumed by: FSP:HB diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_freq.H b/src/import/chips/p9/procedures/hwp/memory/p9_mss_freq.H index 1ca65a1b2..f18b29341 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_freq.H +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_freq.H @@ -22,10 +22,9 @@ /// @brief Calculate and save off DIMM frequencies /// // *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> -// *HWP HWP Backup: Luke Mulkey <lwmulkey@us.ibm.com> -// *HWP FW Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 1 +// *HWP Level: 2 // *HWP Consumed by: FSP:HB #ifndef __P9_MSS_FREQ__ @@ -33,6 +32,83 @@ #include <fapi2.H> +namespace mss +{ + +enum constants : std::uint64_t +{ + TAA_MAX_DDR4 = 18000, + TWO_MHZ = 2000000, + DMI_9_6GB = 0x01, + DMI_16_0GB = 0x02, + LR_MIN_DDR4_CL = 7, + LR_MAX_DDR4_CL = 36, + HR_MIN_DDR4_CL = 23, + HR_MAX_DDR4_CL = 52, +}; + +enum frequencies : std::uint64_t +{ + FREQ_2667 = 2667, + FREQ_2400 = 2400, + FREQ_2133 = 2133, + FREQ_1867 = 1867, + FREQ_1600 = 1600, +}; + + +/// +/// @brief Calculate frequency +/// @tparam T input +/// @param[in] T i_clock +/// @return T (frequency) +/// +template<typename T> +inline T calc_freq(T i_clock) +{ + // Casted so compiler performs operations on equivalent data types + T frequency = TWO_MHZ / i_clock; + // Round-up if division leaves remainder + frequency += ( (TWO_MHZ % i_clock) == 0 ? 0 : 1 ); + + return frequency; +} + +/// +/// @brief Calculate timing value (e.g.tCK, tAA, etc.) +/// @tparam T input +/// @param[in] T i_freq +/// @return T (timing) +/// +template<typename T> +inline T calc_clock (T i_freq) +{ + T timing = TWO_MHZ / i_freq; + // Round-up if division leaves remainder + timing += ( (TWO_MHZ % i_freq) == 0 ? 0 : 1 ); + + return timing; +} + +/// +/// @brief Calculate CAS latency +/// @tparam[in] T tAA_max, +/// T tCKmax +/// @return T cas_latency +/// +template<typename T> +inline T calc_cas_latency(T tAA_max, T tCKmax) +{ + T cas_latency = tAA_max / tCKmax; + // Increment if division leaves remainder + cas_latency += ( (tAA_max % tCKmax) == 0 ? 0 : 1 ); + + return cas_latency; +} + + +}// mss namespace + typedef fapi2::ReturnCode (*p9_mss_freq_FP_t) (const fapi2::Target<fapi2::TARGET_TYPE_MCS>&); extern "C" diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_freq.mk b/src/import/chips/p9/procedures/hwp/memory/p9_mss_freq.mk index 8b065eeda..5681e6b64 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_freq.mk +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_freq.mk @@ -17,5 +17,10 @@ # # IBM_PROLOG_END_TAG +# Include the macros and things for MSS procedures +-include 00common.mk + PROCEDURE=p9_mss_freq +$(eval $(call ADD_MEMORY_INCDIRS,$(PROCEDURE))) +lib$(PROCEDURE)_DEPLIBS+=mss $(call BUILD_PROCEDURE) diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_memdiag.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_memdiag.C index 0e73f894b..e7bb3b974 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_memdiag.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_memdiag.C @@ -23,7 +23,6 @@ /// // *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> -// *HWP FW Owner: Brian Silver <bsilver@us.ibm.com> // *HWP Team: Memory // *HWP Level: 1 // *HWP Consumed by: FSP:HB diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_memdiag.H b/src/import/chips/p9/procedures/hwp/memory/p9_mss_memdiag.H index d64913495..df17ba84c 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_memdiag.H +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_memdiag.H @@ -22,7 +22,6 @@ /// // *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> -// *HWP FW Owner: Brian Silver <bsilver@us.ibm.com> // *HWP Team: Memory // *HWP Level: 1 // *HWP Consumed by: FSP:HB diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_power_cleanup.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_power_cleanup.C index 8ef0c8c6f..286a0632a 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_power_cleanup.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_power_cleanup.C @@ -23,7 +23,6 @@ /// // *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> -// *HWP FW Owner: Brian Silver <bsilver@us.ibm.com> // *HWP Team: Memory // *HWP Level: 1 // *HWP Consumed by: FSP:HB diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_power_cleanup.H b/src/import/chips/p9/procedures/hwp/memory/p9_mss_power_cleanup.H index 94f932b77..33141d8fa 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_power_cleanup.H +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_power_cleanup.H @@ -22,7 +22,6 @@ /// // *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> -// *HWP FW Owner: Brian Silver <bsilver@us.ibm.com> // *HWP Team: Memory // *HWP Level: 1 // *HWP Consumed by: FSP:HB diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_scominit.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_scominit.C index d7634db9e..073f11fd5 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_scominit.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_scominit.C @@ -23,7 +23,6 @@ /// // *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> // *HWP HWP Backup: Craig Hamilton <cchamilt@us.ibm.com> -// *HWP FW Owner: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory // *HWP Level: 1 // *HWP Consumed by: FSP:HB diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_scominit.H b/src/import/chips/p9/procedures/hwp/memory/p9_mss_scominit.H index b59076254..c0ee61a64 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_scominit.H +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_scominit.H @@ -23,7 +23,6 @@ /// // *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> // *HWP HWP Backup: Craig Hamilton <cchamilt@us.ibm.com> -// *HWP FW Owner: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory // *HWP Level: 1 // *HWP Consumed by: FSP:HB diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_scrub.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_scrub.C index ba8b81592..a79a22d69 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_scrub.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_scrub.C @@ -22,8 +22,7 @@ /// @brief Begin background scrub /// // *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> -// *HWP HWP Backup: Luke Mulkey <lwmulkey@us.ibm.com> -// *HWP FW Owner: Andre Marin <aamarin@us.ibm.com> +// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory // *HWP Level: 1 // *HWP Consumed by: FSP:HB diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_scrub.H b/src/import/chips/p9/procedures/hwp/memory/p9_mss_scrub.H index 395d5d3b9..9a9752c89 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_scrub.H +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_scrub.H @@ -22,7 +22,6 @@ /// @brief Begin background scrub /// // *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> -// *HWP HWP Backup: Luke Mulkey <lwmulkey@us.ibm.com> // *HWP FW Owner: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory // *HWP Level: 1 diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_thermal_init.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_thermal_init.C index dc6f68391..a19c072c2 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_thermal_init.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_thermal_init.C @@ -23,7 +23,6 @@ /// // *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> -// *HWP FW Owner: Brian Silver <bsilver@us.ibm.com> // *HWP Team: Memory // *HWP Level: 1 // *HWP Consumed by: FSP:HB diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_thermal_init.H b/src/import/chips/p9/procedures/hwp/memory/p9_mss_thermal_init.H index 0969db97c..8322503ae 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_thermal_init.H +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_thermal_init.H @@ -22,7 +22,6 @@ /// // *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> -// *HWP FW Owner: Brian Silver <bsilver@us.ibm.com> // *HWP Team: Memory // *HWP Level: 1 // *HWP Consumed by: FSP:HB diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_volt.H b/src/import/chips/p9/procedures/hwp/memory/p9_mss_volt.H index 7c94ad5c0..55988fcc7 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_volt.H +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_volt.H @@ -22,14 +22,13 @@ /// @brief Calculate and save off rail voltages /// // *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> -// *HWP HWP Backup: Luke Mulkey <lwmulkey@us.ibm.com> -// *HWP FW Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 1 +// *HWP Level: 2 // *HWP Consumed by: FSP:HB -#ifndef __P9_MSS_VOLT__ -#define __P9_MSS_VOLT__ +#ifndef MSS_VOLT_H_ +#define MSS_VOLT_H_ #include <fapi2.H> diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_volt.mk b/src/import/chips/p9/procedures/hwp/memory/p9_mss_volt.mk index d895c10c0..c668a7cc7 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_volt.mk +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_volt.mk @@ -17,5 +17,10 @@ # # IBM_PROLOG_END_TAG +# Include the macros and things for MSS procedures +-include 00common.mk + PROCEDURE=p9_mss_volt +$(eval $(call ADD_MEMORY_INCDIRS,$(PROCEDURE))) +lib$(PROCEDURE)_DEPLIBS+=mss $(call BUILD_PROCEDURE) |