Update p9_setup_bars for 3 NPU's on Axone

- The PHY0/1 BARS were dropped.  The MMIO bar's 16M space
includes both 2M PHY spaces.
- Added Private Register Interface configuration registers
setup by attributes.

Change-Id: I7c4b6a23f2f46a8f6417b40201eafac57dd50945
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/77769
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/77777
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

3 files changed, 394 insertions, 8 deletions

diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_setup_bars.C b/src/import/chips/p9/procedures/hwp/nest/p9_setup_bars.C
index 844899466..31a20244d 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_setup_bars.C
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_setup_bars.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015,2018                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2019                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -743,6 +743,160 @@ fapi_try_exit:
 }
 
 
+/// @brief Configure an NPU instance
+///
+/// @param[in] i_target Processor chip target
+/// @param[in] i_attr_bar_enable Enable the NPU MMIO bar
+/// @param[in] i_attr_bar The BAR for the NPU instance
+/// @param[in] i_mmio_offset The MMIO offset for the chip
+/// @param[in] i_attr_pri The private reg interface settings for each NDL
+/// @param[in] i_npu_regs The registers for this NPU
+/// @param[in] i_chip_info Structure describing chip properties/base addresses
+///
+/// @return FAPI_RC_SUCCESS if all calls are successful, else error
+fapi2::ReturnCode
+p9a_setup_bars_npuX(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+                    const uint8_t& i_attr_bar_enable,
+                    fapi2::buffer<uint64_t> i_attr_bar,
+                    const uint64_t& i_mmio_offset,
+                    const uint8_t i_attr_pri[],
+                    p9_setup_bars_p9a_npu_regs& i_npu_regs,
+                    p9_setup_bars_chip_info& i_chip_info)
+{
+    FAPI_DBG("Start");
+
+    if (i_attr_bar_enable)
+    {
+        p9_setup_bars_addr_range l_mmio_range;
+        FAPI_ASSERT((i_attr_bar & P9_SETUP_BARS_OFFSET_MASK_16_MB) == 0,
+                    fapi2::P9_SETUP_BARS_NPU_MMIO_BAR_ATTR_ERR()
+                    .set_TARGET(i_target)
+                    .set_BAR_OFFSET(i_attr_bar)
+                    .set_BAR_OFFSET_MASK(P9_SETUP_BARS_OFFSET_MASK_16_MB)
+                    .set_BAR_OVERLAP(i_attr_bar & P9_SETUP_BARS_OFFSET_MASK_2_MB),
+                    "NPU MMIO BAR offset attribute is not aligned to HW implementation");
+
+        i_attr_bar &= NPU_BAR_BASE_ADDR_MASK;
+        i_attr_bar += i_mmio_offset;
+        i_attr_bar = i_attr_bar << NPU_BAR_ADDR_SHIFT;
+        i_attr_bar = NPU_BAR_REG_MASK & i_attr_bar;
+        i_attr_bar.setBit<PU_NPU0_SM0_PHY_BAR_CONFIG_ENABLE>();
+
+        for (uint8_t ll = 0; ll < NPU_NUM_BAR_SHADOWS; ll++)
+        {
+            FAPI_TRY(fapi2::putScom(i_target, i_npu_regs.bar_regs[ll], i_attr_bar),
+                     "Error from putScom (0x08X)", i_npu_regs.bar_regs[ll]);
+        }
+
+        l_mmio_range.base_addr = i_attr_bar;
+        l_mmio_range.size = P9_SETUP_BARS_SIZE_16_MB;
+        l_mmio_range.enabled = true;
+        i_chip_info.ranges.push_back(l_mmio_range);
+        i_chip_info.ranges.back().print();
+    }
+
+    for (uint8_t ll = 0; ll < NPU_NUM_BAR_SHADOWS; ll++)
+    {
+        uint64_t l_pri_val = static_cast<uint64_t>(i_attr_pri[ll]) << (64 - 8);
+        FAPI_TRY(fapi2::putScom(i_target, i_npu_regs.pri_regs[ll], l_pri_val),
+                 "Error from putScom (0x08X)", i_npu_regs.pri_regs[ll]);
+    }
+
+fapi_try_exit:
+    FAPI_DBG("End");
+    return fapi2::current_err;
+}
+
+/// @brief Configure p9a NPU MMIO access
+///
+/// @param[in] i_target Processor chip target
+/// @param[in] i_target_sys System target
+/// @param[in] i_chip_info Structure describing chip properties/base addresses
+///
+/// @return FAPI_RC_SUCCESS if all calls are successful, else error
+fapi2::ReturnCode
+p9a_setup_bars_npu(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+                   const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& i_target_sys,
+                   p9_setup_bars_chip_info& i_chip_info)
+
+{
+    FAPI_DBG("Start");
+
+    fapi2::buffer<uint64_t> l_mmio_bar = i_chip_info.base_address_mmio;
+
+    //NPU0
+    {
+        fapi2::ATTR_PROC_NPU0_MMIO_BAR_ENABLE_Type l_mmio_enable;
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_NPU0_MMIO_BAR_ENABLE, i_target, l_mmio_enable),
+                 "Error from FAPI_ATTR_GET (ATTR_PROC_NPU0_MMIO_BAR_ENABLE)");
+
+        fapi2::ATTR_PROC_NPU0_MMIO_BAR_BASE_ADDR_OFFSET_Type l_mmio_offset;
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_NPU0_MMIO_BAR_BASE_ADDR_OFFSET, i_target_sys, l_mmio_offset),
+                 "Error from FAPI_ATTR_GET (ATTR_PROC_NPU0_MMIO_BAR_BASE_ADDR_OFFSET)");
+
+        fapi2::ATTR_PROC_NPU0_PRI_CONFIG_Type l_pri_config;
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_NPU0_PRI_CONFIG, i_target, l_pri_config),
+                 "Error from FAPI_ATTR_GET (ATTR_PROC_NPU0_PRI_CONFIG)");
+
+        FAPI_TRY(p9a_setup_bars_npuX(i_target,
+                                     l_mmio_enable,
+                                     l_mmio_offset,
+                                     l_mmio_bar,
+                                     l_pri_config,
+                                     p9_setup_bars_p9a_npu0_regs,
+                                     i_chip_info));
+    }
+    //NPU1
+    {
+        fapi2::ATTR_PROC_NPU1_MMIO_BAR_ENABLE_Type l_mmio_enable;
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_NPU1_MMIO_BAR_ENABLE, i_target, l_mmio_enable),
+                 "Error from FAPI_ATTR_GET (ATTR_PROC_NPU1_MMIO_BAR_ENABLE)");
+
+        fapi2::ATTR_PROC_NPU1_MMIO_BAR_BASE_ADDR_OFFSET_Type l_mmio_offset;
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_NPU1_MMIO_BAR_BASE_ADDR_OFFSET, i_target_sys, l_mmio_offset),
+                 "Error from FAPI_ATTR_GET (ATTR_PROC_NPU1_MMIO_BAR_BASE_ADDR_OFFSET)");
+
+        fapi2::ATTR_PROC_NPU1_PRI_CONFIG_Type l_pri_config;
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_NPU1_PRI_CONFIG, i_target, l_pri_config),
+                 "Error from FAPI_ATTR_GET (ATTR_PROC_NPU1_PRI_CONFIG)");
+
+        FAPI_TRY(p9a_setup_bars_npuX(i_target,
+                                     l_mmio_enable,
+                                     l_mmio_offset,
+                                     l_mmio_bar,
+                                     l_pri_config,
+                                     p9_setup_bars_p9a_npu1_regs,
+                                     i_chip_info));
+    }
+    //NPU2
+    {
+        fapi2::ATTR_PROC_NPU2_MMIO_BAR_ENABLE_Type l_mmio_enable;
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_NPU2_MMIO_BAR_ENABLE, i_target, l_mmio_enable),
+                 "Error from FAPI_ATTR_GET (ATTR_PROC_NPU2_MMIO_BAR_ENABLE)");
+
+        fapi2::ATTR_PROC_NPU2_MMIO_BAR_BASE_ADDR_OFFSET_Type l_mmio_offset;
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_NPU2_MMIO_BAR_BASE_ADDR_OFFSET, i_target_sys, l_mmio_offset),
+                 "Error from FAPI_ATTR_GET (ATTR_PROC_NPU2_MMIO_BAR_BASE_ADDR_OFFSET)");
+
+        fapi2::ATTR_PROC_NPU2_PRI_CONFIG_Type l_pri_config;
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_NPU2_PRI_CONFIG, i_target, l_pri_config),
+                 "Error from FAPI_ATTR_GET (ATTR_PROC_NPU2_PRI_CONFIG)");
+
+        FAPI_TRY(p9a_setup_bars_npuX(i_target,
+                                     l_mmio_enable,
+                                     l_mmio_offset,
+                                     l_mmio_bar,
+                                     l_pri_config,
+                                     p9_setup_bars_p9a_npu2_regs,
+                                     i_chip_info));
+    }
+
+fapi_try_exit:
+    FAPI_DBG("End");
+    return fapi2::current_err;
+}
+
+
 /// @brief Configure NPU MMIO access
 ///
 /// @param[in] i_target Processor chip target
@@ -1237,7 +1391,12 @@ p9_setup_bars_check_overlap(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i
                             .set_BASE_ADDR2(i_chip_info.ranges[jj].base_addr)
                             .set_END_ADDR2(i_chip_info.ranges[jj].end_addr())
                             .set_ENABLED2(i_chip_info.ranges[jj].enabled),
-                            "Overlapping address regions detected!");
+                            "Overlapping address regions detected %llx->%llx  %llx->%llx!",
+                            i_chip_info.ranges[ii].base_addr,
+                            i_chip_info.ranges[ii].end_addr(),
+                            i_chip_info.ranges[jj].base_addr,
+                            i_chip_info.ranges[jj].end_addr()
+                           );
             }
         }
     }
@@ -1255,6 +1414,10 @@ p9_setup_bars(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
     FAPI_INF("Start");
     fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM;
     p9_setup_bars_chip_info l_chip_info;
+    fapi2::ATTR_CHIP_EC_FEATURE_ONE_NPU_TOP_Type l_one_npu;
+
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_ONE_NPU_TOP, i_target, l_one_npu),
+             "Error from FAPI_ATTR_GET (ATTR_CHIP_EC_FEATURE_ONE_NPU_TOP)");
 
     // process chip information
     FAPI_TRY(p9_setup_bars_build_chip_info(i_target,
@@ -1268,9 +1431,18 @@ p9_setup_bars(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
     // PSI
     FAPI_TRY(p9_setup_bars_psi(i_target, FAPI_SYSTEM, l_chip_info),
              "Error from p9_setup_bars_psi");
+
     // NPU
-    FAPI_TRY(p9_setup_bars_npu(i_target, FAPI_SYSTEM, l_chip_info),
-             "Error from p9_setup_bars_npu");
+    if (l_one_npu)
+    {
+        FAPI_TRY(p9_setup_bars_npu(i_target, FAPI_SYSTEM, l_chip_info),
+                 "Error from p9_setup_bars_npu");
+    }
+    else
+    {
+        FAPI_TRY(p9a_setup_bars_npu(i_target, FAPI_SYSTEM, l_chip_info),
+                 "Error from p9a_setup_bars_npu");
+    }
 
     // MCD
     if (!l_chip_info.hw423589_option1)
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_setup_bars_defs.H b/src/import/chips/p9/procedures/hwp/nest/p9_setup_bars_defs.H
index ebf4682af..19a04873e 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_setup_bars_defs.H
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_setup_bars_defs.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2016,2017                        */
+/* Contributors Listed Below - COPYRIGHT 2016,2019                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -344,6 +344,13 @@ const uint8_t NPU_NUM_BAR_SHADOWS = 4;
 const uint64_t NPU_BAR_BASE_ADDR_MASK = 0x0001FFFFFFFFFFFFULL;
 const uint64_t NPU_BAR_ADDR_SHIFT = 12;
 
+// The NPU BAR does not include the Memory Select bits.
+// This mask ensures after shifting the attribute bar value
+// we only set the relivant BAR bits.
+//                                  0001122233444556
+//                                  0482604826048260
+const uint64_t NPU_BAR_REG_MASK = 0x1FFFFFF000000000ULL;
+
 const uint64_t NPU_PHY0_BAR_REGS_NDD1[NPU_NUM_BAR_SHADOWS] =
 {
     PU_NPU0_SM0_PHY_BAR,
@@ -360,6 +367,14 @@ const uint64_t NPU_PHY0_BAR_REGS[NPU_NUM_BAR_SHADOWS] =
     0x05011496
 };
 
+const uint64_t NPU_PHY0_BAR_REGS_ADD1[NPU_NUM_BAR_SHADOWS] =
+{
+    0x05011406,
+    0x05011436,
+    0x05011466,
+    0x05011496
+};
+
 const uint64_t NPU_PHY1_BAR_REGS_NDD1[NPU_NUM_BAR_SHADOWS] =
 {
     PU_NPU1_SM0_PHY_BAR,
@@ -392,4 +407,29 @@ const uint64_t NPU_MMIO_BAR_REGS[NPU_NUM_BAR_SHADOWS] =
     0x05011096
 };
 
+// P9A Npu instances
+struct p9_setup_bars_p9a_npu_regs
+{
+    uint64_t bar_regs[NPU_NUM_BAR_SHADOWS];
+    uint64_t pri_regs[NPU_NUM_BAR_SHADOWS];
+};
+
+p9_setup_bars_p9a_npu_regs  p9_setup_bars_p9a_npu0_regs =
+{
+    { 0x501103C, 0x501109C, 0x50110FC, 0x501115C },
+    { 0x50111F6, 0x5011216, 0x50113D6, 0x50113F6 }
+};
+
+p9_setup_bars_p9a_npu_regs  p9_setup_bars_p9a_npu1_regs =
+{
+    { 0x501143C, 0x501149C, 0x50114FC, 0x501155C },
+    { 0x50115F6, 0x5011616, 0x50117D6, 0x50117F6 }
+};
+
+p9_setup_bars_p9a_npu_regs  p9_setup_bars_p9a_npu2_regs =
+{
+    { 0x3011C3C, 0x3011C9C, 0x3011CFC, 0x3011D5C },
+    { 0x3011DF6, 0x3011E16, 0x3011FD6, 0x3011FF6 }
+};
+
 #endif //_P9_SETUP_BARS_DEFS_H_
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/p9_setup_bars_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/p9_setup_bars_attributes.xml
index 920e0dcf1..88bd4192b 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/p9_setup_bars_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/p9_setup_bars_attributes.xml
@@ -5,7 +5,7 @@
 <!--                                                                        -->
 <!-- OpenPOWER HostBoot Project                                             -->
 <!--                                                                        -->
-<!-- Contributors Listed Below - COPYRIGHT 2015,2018                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2015,2019                        -->
 <!-- [+] International Business Machines Corp.                              -->
 <!--                                                                        -->
 <!--                                                                        -->
@@ -167,6 +167,20 @@
     <mrwHide/>
   </attribute>
   <!-- ********************************************************************* -->
+   <attribute>
+    <id>ATTR_PROC_NPU_MMIO_BAR_ENABLE</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>NPU MMIO (stack2) BAR enable
+      creator: platform
+      consumer: p9_setup_bars
+      firmware notes: none
+    </description>
+    <valueType>uint8</valueType>
+    <enum>DISABLE = 0x0, ENABLE = 0x1</enum>
+    <platInit/>
+    <mrwHide/>
+  </attribute>
+  <!-- ********************************************************************* -->
   <attribute>
     <id>ATTR_PROC_NPU_MMIO_BAR_BASE_ADDR_OFFSET</id>
     <targetType>TARGET_TYPE_SYSTEM</targetType>
@@ -185,9 +199,71 @@
   </attribute>
   <!-- ********************************************************************* -->
    <attribute>
-    <id>ATTR_PROC_NPU_MMIO_BAR_ENABLE</id>
+    <id>ATTR_PROC_NPU0_MMIO_BAR_ENABLE</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
-    <description>NPU MMIO (stack2) BAR enable
+    <description>NPU0 MMIO BAR enable
+      creator: platform
+      consumer: p9_setup_bars
+      firmware notes: none
+    </description>
+    <valueType>uint8</valueType>
+    <enum>DISABLE = 0x0, ENABLE = 0x1</enum>
+    <platInit/>
+    <mrwHide/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PROC_NPU0_MMIO_BAR_BASE_ADDR_OFFSET</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>NPU MMIO BAR
+      creator: platform
+      consumer: p9_setup_bars
+      firmware notes:
+        Defines 16MB range mapped to NPU0 registers
+        Attribute holds offset (relative to chip MMIO origin) to program into
+        chip address range field of BAR -- Bits 15:39 of the RA
+        (excludes system/memory select/group/chip fields)
+    </description>
+    <valueType>uint64</valueType>
+    <platInit/>
+    <mrwHide/>
+  </attribute>
+  <!-- ********************************************************************* -->
+   <attribute>
+    <id>ATTR_PROC_NPU1_MMIO_BAR_ENABLE</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>NPU1 MMIO BAR enable
+      creator: platform
+      consumer: p9_setup_bars
+      firmware notes: none
+    </description>
+    <valueType>uint8</valueType>
+    <enum>DISABLE = 0x0, ENABLE = 0x1</enum>
+    <platInit/>
+    <mrwHide/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PROC_NPU1_MMIO_BAR_BASE_ADDR_OFFSET</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>NPU1 MMIO BAR
+      creator: platform
+      consumer: p9_setup_bars
+      firmware notes:
+        Defines 16MB range mapped to NPU1 registers
+        Attribute holds offset (relative to chip MMIO origin) to program into
+        chip address range field of BAR -- Bits 15:39 of the RA
+        (excludes system/memory select/group/chip fields)
+    </description>
+    <valueType>uint64</valueType>
+    <platInit/>
+    <mrwHide/>
+  </attribute>
+  <!-- ********************************************************************* -->
+   <attribute>
+    <id>ATTR_PROC_NPU2_MMIO_BAR_ENABLE</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>NPU2 MMIO BAR enable
       creator: platform
       consumer: p9_setup_bars
       firmware notes: none
@@ -199,6 +275,104 @@
   </attribute>
   <!-- ********************************************************************* -->
   <attribute>
+    <id>ATTR_PROC_NPU2_MMIO_BAR_BASE_ADDR_OFFSET</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>NPU2 MMIO BAR
+      creator: platform
+      consumer: p9_setup_bars
+      firmware notes:
+        Defines 16MB range mapped to NPU2 registers
+        Attribute holds offset (relative to chip MMIO origin) to program into
+        chip address range field of BAR -- Bits 15:39 of the RA
+        (excludes system/memory select/group/chip fields)
+    </description>
+    <valueType>uint64</valueType>
+    <platInit/>
+    <mrwHide/>
+  </attribute>
+  <!-- ********************************************************************** -->
+  <attribute>
+    <id>ATTR_PROC_NPU0_PRI_CONFIG</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description> 
+      NPU0 NTL Private Register Interface (PRI) Configuration register settings
+      Array 0 = SM0 value
+            1 = SM1 value
+            2 = SM2 value
+            3 = SM3 value
+      Bits of values:
+      0    PRI_CONFIG_DISABLE: Disable
+      1    Disable (this will disable NTL from decoding the NDL register space)
+      1:2  PRI_CONFIG_NDL: NDL indication sent in the PRI Read/Write access
+            00 = NDL 0
+            01 = NDL 1
+            10 = NDL 2
+            11 = NDL 3
+      3:4 PRI_CONFIG_PHY: Indicates if NTL should decode a PHY register space
+            00 = Decode PHY0 register space
+            01 = Decode PHY1 register space
+            1- = Do not decode any PHY register space
+    </description>
+    <valueType>uint8</valueType>
+    <array>4</array>
+    <platInit/>
+  </attribute>
+  <!-- ********************************************************************** -->
+  <attribute>
+    <id>ATTR_PROC_NPU1_PRI_CONFIG</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description> 
+      NPU1 NTL Private Register Interface (PRI) Configuration register settings
+      Array 0 = SM0 value
+            1 = SM1 value
+            2 = SM2 value
+            3 = SM3 value
+      Bits of values:
+      0    PRI_CONFIG_DISABLE: Disable
+      1    Disable (this will disable NTL from decoding the NDL register space)
+      1:2  PRI_CONFIG_NDL: NDL indication sent in the PRI Read/Write access
+            00 = NDL 0
+            01 = NDL 1
+            10 = NDL 2
+            11 = NDL 3
+      3:4 PRI_CONFIG_PHY: Indicates if NTL should decode a PHY register space
+            00 = Decode PHY0 register space
+            01 = Decode PHY1 register space
+            1- = Do not decode any PHY register space
+    </description>
+    <valueType>uint8</valueType>
+    <array>4</array>
+    <platInit/>
+  </attribute>
+  <!-- ********************************************************************** -->
+  <attribute>
+    <id>ATTR_PROC_NPU2_PRI_CONFIG</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description> 
+      NPU2 NTL Private Register Interface (PRI) Configuration register settings
+      Array 0 = SM0 value
+            1 = SM1 value
+            2 = SM2 value
+            3 = SM3 value
+      Bits of values:
+      0    PRI_CONFIG_DISABLE: Disable
+      1    Disable (this will disable NTL from decoding the NDL register space)
+      1:2  PRI_CONFIG_NDL: NDL indication sent in the PRI Read/Write access
+            00 = NDL 0
+            01 = NDL 1
+            10 = NDL 2
+            11 = NDL 3
+      3:4 PRI_CONFIG_PHY: Indicates if NTL should decode a PHY register space
+            00 = Decode PHY0 register space
+            01 = Decode PHY1 register space
+            1- = Do not decode any PHY register space
+    </description>
+    <valueType>uint8</valueType>
+    <array>4</array>
+    <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
     <id>ATTR_PROC_PSI_BRIDGE_BAR_ENABLE</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>PSI Bridge BAR enable