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| author | Andre Marin <aamarin@us.ibm.com> | 2017-05-11 11:28:21 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-05-25 15:40:26 -0400 |
| commit | c00a806435284d3ffd4eb1e6e1142ac8723a8ab2 (patch) | |
| tree | f9bcc5b5a2975558553371a1fb3f7d6652858194 /src/usr | |
| parent | 4d9e5a4a231d2a4a14231bc5a01d4590cb88d96d (diff) | |
| download | blackbird-hostboot-c00a806435284d3ffd4eb1e6e1142ac8723a8ab2.tar.gz blackbird-hostboot-c00a806435284d3ffd4eb1e6e1142ac8723a8ab2.zip | |
Remove ZQCAL redundant CCS inst, move to draminit_training
Lab requested to move ZQCL to draminit_training to control
(with granularity) all enabled cal steps from an attribute in
training. Also removing redundant ZQCAL being sent out for both
a-side/b-side and addr_mirroring since this only applies to MRS cmds.
Added new attribute proposal for CAL_STEPS_ENABLE to
account for LRDIMM training steps and more control bits
such as INITIAL_PAT_WR and WR_VRE_LATCH
Change-Id: Ibb758af74966a5dd659bf3dda86f283f73956bca
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38648
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38650
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Diffstat (limited to 'src/usr')
| -rw-r--r-- | src/usr/targeting/common/xmltohb/attribute_types.xml | 46 |
1 files changed, 31 insertions, 15 deletions
diff --git a/src/usr/targeting/common/xmltohb/attribute_types.xml b/src/usr/targeting/common/xmltohb/attribute_types.xml index c777158a9..5dc44fb3f 100644 --- a/src/usr/targeting/common/xmltohb/attribute_types.xml +++ b/src/usr/targeting/common/xmltohb/attribute_types.xml @@ -10315,23 +10315,39 @@ firmware notes: Used as override attribute for pstate procedure <attribute> <id>MSS_CAL_STEP_ENABLE</id> <description> - A bit map ofvector denoting valid cal steps to run (0 is left most bit) - [0] EXT_ZQCAL - [1] WR_LEVEL - [2] DQS_ALIGN - [3] RDCLK_ALIGN - [4] READ_CTR - [5] READ_CTR_2D_VREF - [6] WRITE_CTR - [7] WRITE_CTR_2D_VREF - [8] COARSE_WR - [9] COARSE_RD - [10]:[15] Reserved for future use - COARSE_WR and COARSE_RD will be consumed together to form COARSE_LVL. + A bit map of vector denoting valid steps to run (0 is left most bit) + [0] DRAM_ZQCAL + [1] DB_ZQCAL (LRDIMM) + [2] MREP (LRDIMM) + [3] MRD - Coarse (LRDIMM) + [4] MRD - Fine (LRDIMM) + [5] WR_LEVEL + [6] INITIAL_PAT_WR + [7] WR_VREF_LATCH + [8] DWL (LRDIMM) + [9] MWD - Coarse (LRDIMM) + [10] MWD - Fine (LRDIMM) + [11] HWL (LRDIMM) + [12] DQS_ALIGN + [13] RDCLK_ALIGN + [14] READ_CTR_2D_VREF + [15] READ_CTR + [16] WRITE_CTR_2D_VREF + [17] WRITE_CTR + [18] COARSE_WR + [19] COARSE_RD + [20]:[31] Reserved for future use + + COARSE_WR and COARSE_RD will be consumed together to form COARSE_LVL. + + WRITE_CTR will be run, even if only WRITE_CTR_2D_VREF is enabled, + as the WR 2D VREF HW cal depends upon WRITE_CTR 1D to function. + + Note: LRDIMM steps will only be enabled for LRDIMMs and won't run on RDIMMs. </description> <simpleType> - <uint16_t> - </uint16_t> + <uint32_t> + </uint32_t> <array>2</array> </simpleType> <persistency>volatile-zeroed</persistency> |
