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| author | Matt Derksen <mderkse1@us.ibm.com> | 2018-12-10 16:38:11 -0600 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2019-02-28 10:24:21 -0600 |
| commit | 37e67698be56632c6505990dc3375136494d2a67 (patch) | |
| tree | a23967962c1e31f9a2a8b7430fff1b10232241b2 /src/usr/vpd | |
| parent | 80cea86add7ba742181cd272b16e10185b5e9a4d (diff) | |
| download | blackbird-hostboot-37e67698be56632c6505990dc3375136494d2a67.tar.gz blackbird-hostboot-37e67698be56632c6505990dc3375136494d2a67.zip | |
Framework for NVDIMM update
This includes framework to update the firmware
running on the NV controller. The controller requires
12V power to update, so this function in inside hostboot.
Change-Id: I0733d83ff6ba2fc3f026d49c72784b1295bd3eed
RTC:201197
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/69879
Reviewed-by: Roland Veloz <rveloz@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/usr/vpd')
| -rwxr-xr-x | src/usr/vpd/spdDDR4.H | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/usr/vpd/spdDDR4.H b/src/usr/vpd/spdDDR4.H index bf4d0dfc8..8e03a0f0d 100755 --- a/src/usr/vpd/spdDDR4.H +++ b/src/usr/vpd/spdDDR4.H @@ -47,7 +47,7 @@ namespace SPD const KeywordData ddr4Data[] = { // ---------------------------------------------------------------------------------- - // NOTE: This list must remain an ordered list! The Keyword must be in numerical + // NOTE: This list must remain an ordered list! The Keyword must be in numerical // order (values defined in spdenums.H) to allow efficient searching, a unit // test enforces this. // ---------------------------------------------------------------------------------- @@ -136,6 +136,8 @@ const KeywordData ddr4Data[] = { DRAM_STEPPING, 0x160, 0x01, 0x00, 0x00, false, false, NA }, { MANUFACTURING_SECTION_CRC, 0x17f, 0x02, 0x00, 0x00, true, false, NA }, { NVM_INIT_TIME, 0xCB, 0x01, 0x00, 0x00, false, false, NA }, + { RAW_MODULE_PRODUCT_ID, 0xc0, 0x02, 0x00, 0x00, false, false, NA }, + { RAW_MODULE_MANUFACTURER_ID, 0x140, 0x02, 0x00, 0x00, false, false, NA }, // Module Specific fields supported on both DDR3 and DDR4 { MODSPEC_COM_NOM_HEIGHT_MAX, 0x80, 0x01, 0x1f, 0x00, false, false, ALL }, { MODSPEC_COM_MAX_THICK_BACK, 0x81, 0x01, 0xf0, 0x04, false, false, ALL }, |
