Add new common attributes for PRD thresholds

The new attributes will be for the system target and backed by MRW.

Change-Id: I2b71657aefea1a63e25db91137b1c1530021ca1f
CMVC-Prereq: 945073
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/14559
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

3 files changed, 279 insertions, 0 deletions

diff --git a/src/usr/targeting/common/genHwsvMrwXml.pl b/src/usr/targeting/common/genHwsvMrwXml.pl
index b63d4db9a..9c9320595 100755
--- a/src/usr/targeting/common/genHwsvMrwXml.pl
+++ b/src/usr/targeting/common/genHwsvMrwXml.pl
@@ -239,6 +239,25 @@ push @systemAttr,
     "REDUNDANT_CLOCKS", $reqPol->{'redundant-clocks'},
     "MSS_DRAMINIT_RESET_DISABLE", $reqPol->{'mss_draminit_reset_disable'},
     "MRW_POWER_CONTROL_REQUESTED", (uc $reqPol->{'mem_power_control_usage'}),
+    "MNFG_TH_P8EX_L2_CACHE_CES", $reqPol->{'mnfg_th_p8ex_l2_cache_ces'},
+    "MNFG_TH_P8EX_L2_DIR_CES", $reqPol->{'mnfg_th_p8ex_l2_dir_ces'},
+    "MNFG_TH_P8EX_L3_CACHE_CES", $reqPol->{'mnfg_th_p8ex_l3_cache_ces'},
+    "MNFG_TH_P8EX_L3_DIR_CES", $reqPol->{'mnfg_th_p8ex_l3_dir_ces'},
+    "FIELD_TH_P8EX_L2_LINE_DELETES", $reqPol->{'field_th_p8ex_l2_line_deletes'},
+    "FIELD_TH_P8EX_L3_LINE_DELETES", $reqPol->{'field_th_p8ex_l3_line_deletes'},
+    "FIELD_TH_P8EX_L2_COL_REPAIRS", $reqPol->{'field_th_p8ex_l2_col_repairs'},
+    "FIELD_TH_P8EX_L3_COL_REPAIRS", $reqPol->{'field_th_p8ex_l3_col_repairs'},
+    "MNFG_TH_P8EX_L2_LINE_DELETES", $reqPol->{'mnfg_th_p8ex_l2_line_deletes'},
+    "MNFG_TH_P8EX_L3_LINE_DELETES", $reqPol->{'mnfg_th_p8ex_l3_line_deletes'},
+    "MNFG_TH_P8EX_L2_COL_REPAIRS", $reqPol->{'mnfg_th_p8ex_l2_col_repairs'},
+    "MNFG_TH_P8EX_L3_COL_REPAIRS", $reqPol->{'mnfg_th_p8ex_l3_col_repairs'},
+    "MNFG_TH_CEN_MBA_RT_SOFT_CE_TH_ALGO",
+                                $reqPol->{'mnfg_th_cen_mba_rt_soft_ce_th_algo'},
+    "MNFG_TH_CEN_MBA_IPL_SOFT_CE_TH_ALGO",
+                               $reqPol->{'mnfg_th_cen_mba_ipl_soft_ce_th_algo'},
+    "MNFG_TH_CEN_MBA_RT_RCE_PER_RANK",
+                                   $reqPol->{'mnfg_th_cen_mba_rt_rce_per_rank'},
+    "MNFG_TH_CEN_L4_CACHE_CES", $reqPol->{'mnfg_th_cen_l4_cache_ces'},
 ];
 
 if ($reqPol->{'mba_cacheline_interleave_mode_control'} eq 'required')
diff --git a/src/usr/targeting/common/xmltohb/attribute_types.xml b/src/usr/targeting/common/xmltohb/attribute_types.xml
index 0301b682e..2cb33bf71 100644
--- a/src/usr/targeting/common/xmltohb/attribute_types.xml
+++ b/src/usr/targeting/common/xmltohb/attribute_types.xml
@@ -15106,4 +15106,247 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript
     </hwpfToHbAttrMap>
 </attribute>
 
+<!-- === Manufacturing threshold Attributes of PRD === -->
+
+<attribute>
+    <id>MNFG_TH_P8EX_L2_CACHE_CES</id>
+    <description>
+      This attribute represents the Maximum number of L2 Cache CEs allowed
+      during Manufacturing.
+      creator: platform (generated based on MRW data)
+    </description>
+    <simpleType>
+      <uint8_t>
+      </uint8_t>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+</attribute>
+
+<attribute>
+    <id>MNFG_TH_P8EX_L2_DIR_CES</id>
+    <description>
+      This attribute represents the Maximum number of L2 Directory CEs allowed
+      during Manufacturing.
+      creator: platform (generated based on MRW data)
+    </description>
+    <simpleType>
+      <uint8_t>
+      </uint8_t>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+</attribute>
+
+<attribute>
+    <id>MNFG_TH_P8EX_L3_CACHE_CES</id>
+    <description>
+      This attribute represents the Maximum number of L3 Cache CEs allowed
+      during Manufacturing.
+      creator: platform (generated based on MRW data)
+    </description>
+    <simpleType>
+      <uint8_t>
+      </uint8_t>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+</attribute>
+
+<attribute>
+    <id>MNFG_TH_P8EX_L3_DIR_CES</id>
+    <description>
+      This attribute represents the Maximum number of L3 Directory CEs allowed
+      during Manufacturing.
+      creator: platform (generated based on MRW data)
+    </description>
+    <simpleType>
+      <uint8_t>
+      </uint8_t>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+</attribute>
+
+<attribute>
+    <id>FIELD_TH_P8EX_L2_LINE_DELETES</id>
+    <description>
+      This attribute represents the Maximum number of L2 Line Deletes allowed
+      in the Field.
+      creator: platform (generated based on MRW data)
+    </description>
+    <simpleType>
+      <uint8_t>
+      </uint8_t>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+</attribute>
+
+<attribute>
+    <id>FIELD_TH_P8EX_L3_LINE_DELETES</id>
+    <description>
+      This attribute represents the Maximum number of L3 Line Deletes allowed
+      in the Field.
+      creator: platform (generated based on MRW data)
+    </description>
+    <simpleType>
+      <uint8_t>
+      </uint8_t>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+</attribute>
+
+<attribute>
+    <id>FIELD_TH_P8EX_L2_COL_REPAIRS</id>
+    <description>
+      This attribute represents the Maximum number of L2 Column Repairs allowed
+      in the Field.
+      creator: platform (generated based on MRW data)
+    </description>
+    <simpleType>
+      <uint8_t>
+      </uint8_t>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+</attribute>
+
+<attribute>
+    <id>FIELD_TH_P8EX_L3_COL_REPAIRS</id>
+    <description>
+      This attribute represents the Maximum number of L3 Column Repairs allowed
+      in the Field.
+      creator: platform (generated based on MRW data)
+    </description>
+    <simpleType>
+      <uint8_t>
+      </uint8_t>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+</attribute>
+
+<attribute>
+    <id>MNFG_TH_P8EX_L2_LINE_DELETES</id>
+    <description>
+      This attribute represents the Maximum number of L2 Line Deletes allowed
+      during Manufacturing.
+      creator: platform (generated based on MRW data)
+    </description>
+    <simpleType>
+      <uint8_t>
+      </uint8_t>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+</attribute>
+
+<attribute>
+    <id>MNFG_TH_P8EX_L3_LINE_DELETES</id>
+    <description>
+      This attribute represents the Maximum number of L3 Line Deletes allowed
+      during Manufacturing.
+      creator: platform (generated based on MRW data)
+    </description>
+    <simpleType>
+      <uint8_t>
+      </uint8_t>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+</attribute>
+
+<attribute>
+    <id>MNFG_TH_P8EX_L2_COL_REPAIRS</id>
+    <description>
+      This attribute represents the Maximum number of L2 Column Repairs allowed
+      during Manufacturing.
+      creator: platform (generated based on MRW data)
+    </description>
+    <simpleType>
+      <uint8_t>
+      </uint8_t>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+</attribute>
+
+<attribute>
+    <id>MNFG_TH_P8EX_L3_COL_REPAIRS</id>
+    <description>
+      This attribute represents the Maximum number of L3 Column Repairs allowed
+      during Manufacturing.
+      creator: platform (generated based on MRW data)
+    </description>
+    <simpleType>
+      <uint8_t>
+      </uint8_t>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+</attribute>
+
+<attribute>
+    <id>MNFG_TH_CEN_MBA_RT_SOFT_CE_TH_ALGO</id>
+    <description>
+      This attribute represents the Base threshold (for 2GB DRAM ) of
+      Memory CEs allowed during runtime.
+      creator: platform (generated based on MRW data)
+    </description>
+    <simpleType>
+      <uint8_t>
+      </uint8_t>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+</attribute>
+
+<attribute>
+    <id>MNFG_TH_CEN_MBA_IPL_SOFT_CE_TH_ALGO</id>
+    <description>
+      This attribute represents the Base threshold (for 2GB DRAM ) of
+      Memory CEs allowed during IPL.
+      creator: platform (generated based on MRW data)
+    </description>
+    <simpleType>
+      <uint8_t>
+      </uint8_t>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+</attribute>
+
+<attribute>
+    <id>MNFG_TH_CEN_MBA_RT_RCE_PER_RANK</id>
+    <description>
+      This attribute represents the maximum number of Memory RCEs
+      allowed per Rank during runtime.
+      creator: platform (generated based on MRW data)
+    </description>
+    <simpleType>
+      <uint8_t>
+      </uint8_t>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+</attribute>
+
+<attribute>
+    <id>MNFG_TH_CEN_L4_CACHE_CES</id>
+    <description>
+      This attribute represents the maximum number of L4 Cache CEs allowed.
+      creator: platform (generated based on MRW data)
+    </description>
+    <simpleType>
+      <uint8_t>
+      </uint8_t>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+</attribute>
+
+<!-- === Manufacturing threshold Attributes of PRD === -->
+
 </attributes>
diff --git a/src/usr/targeting/common/xmltohb/target_types.xml b/src/usr/targeting/common/xmltohb/target_types.xml
index 6d641059f..cf6d06302 100644
--- a/src/usr/targeting/common/xmltohb/target_types.xml
+++ b/src/usr/targeting/common/xmltohb/target_types.xml
@@ -287,6 +287,23 @@
     <attribute><id>ISTEP_PAUSE_CONFIG</id></attribute>
     <!-- IPMI Sensor numbers for reporting system status and info to the BMC -->
     <attribute><id>IPMI_SENSORS</id></attribute>
+    <!-- Manufacturing threshold Attributes of PRD -->
+    <attribute><id>MNFG_TH_P8EX_L2_CACHE_CES</id></attribute>
+    <attribute><id>MNFG_TH_P8EX_L2_DIR_CES</id></attribute>
+    <attribute><id>MNFG_TH_P8EX_L3_CACHE_CES</id></attribute>
+    <attribute><id>MNFG_TH_P8EX_L3_DIR_CES</id></attribute>
+    <attribute><id>FIELD_TH_P8EX_L2_LINE_DELETES</id></attribute>
+    <attribute><id>FIELD_TH_P8EX_L2_COL_REPAIRS</id></attribute>
+    <attribute><id>FIELD_TH_P8EX_L3_LINE_DELETES</id></attribute>
+    <attribute><id>FIELD_TH_P8EX_L3_COL_REPAIRS</id></attribute>
+    <attribute><id>MNFG_TH_P8EX_L2_LINE_DELETES</id></attribute>
+    <attribute><id>MNFG_TH_P8EX_L2_COL_REPAIRS</id></attribute>
+    <attribute><id>MNFG_TH_P8EX_L3_LINE_DELETES</id></attribute>
+    <attribute><id>MNFG_TH_P8EX_L3_COL_REPAIRS</id></attribute>
+    <attribute><id>MNFG_TH_CEN_MBA_RT_SOFT_CE_TH_ALGO</id></attribute>
+    <attribute><id>MNFG_TH_CEN_MBA_IPL_SOFT_CE_TH_ALGO</id></attribute>
+    <attribute><id>MNFG_TH_CEN_MBA_RT_RCE_PER_RANK</id></attribute>
+    <attribute><id>MNFG_TH_CEN_L4_CACHE_CES</id></attribute>
 </targetType>
 
 <targetType>