Full support for Scom Translate

Includes Xbus, Abus support and all indirect scom address ranges known to date.
Task 36903 - Scom Translate for A and X Bus
Task 37697 - Code updates for Scom Translate Abus/Xbus
Task 38765 - fix for Indirect Scom/Scom translate for MBA targets currently not yet supported
Added Murano XML targets for Xbus and Abus
Final Merge with Murano/Venice on 810 verified

Change-Id: I75d9e642efc4e020e39a2b87ab541cfa5ecd56ba
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/761
Tested-by: Jenkins Server
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: ADAM R. MUHLE <armuhle@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

1 files changed, 581 insertions, 73 deletions

diff --git a/src/usr/scom/test/scomtest.H b/src/usr/scom/test/scomtest.H
index 7d88b0da0..65ddd78ef 100644
--- a/src/usr/scom/test/scomtest.H
+++ b/src/usr/scom/test/scomtest.H
@@ -34,7 +34,7 @@
 #include <errl/errlentry.H>
 #include <devicefw/userif.H>
 #include <fsi/fsiif.H>
-#include    <sys/time.h>  //mc99 remove
+#include <targeting/util.H>
 
 
 extern trace_desc_t* g_trac_scom;
@@ -92,18 +92,18 @@ public:
           else if((TARGETING::MASTER_PROCESSOR_CHIP_TARGET_SENTINEL == scom_targets[x]) ||
                   (scom_targets[x]->getAttr<TARGETING::ATTR_SCOM_SWITCHES>().useXscom))
           {
-              TRACFCOMP( g_trac_scom, "ScomTest::test_FSISCOMreadWrite_proc> Target %d is the MASTER Sentinal or is set to use Xscom, exiting test", x );
+              TRACDCOMP( g_trac_scom, "ScomTest::test_FSISCOMreadWrite_proc> Target %d is the MASTER Sentinal or is set to use Xscom, exiting test", x );
               scom_targets[x] = NULL; //remove from our list
           }
           // skip if fsi scom is not enabled
           else if(0 == scom_targets[x]->getAttr<TARGETING::ATTR_SCOM_SWITCHES>().useFsiScom)
           {
-              TRACFCOMP( g_trac_scom, "ScomTest::test_FSISCOMreadWrite_proc> useFsiScom set to zero on target %d", x );
+              TRACDCOMP( g_trac_scom, "ScomTest::test_FSISCOMreadWrite_proc> useFsiScom set to zero on target %d", x );
               scom_targets[x] = NULL; //remove from our list
           }
           else if( !FSI::isSlavePresent(scom_targets[x]) )
           {
-              TRACFCOMP( g_trac_scom, "ScomTest::test_FSISCOMreadWrite_proc> Target %d is not present", x );
+              TRACDCOMP( g_trac_scom, "ScomTest::test_FSISCOMreadWrite_proc> Target %d is not present", x );
               scom_targets[x] = NULL; //remove from our list
           }
       }
@@ -235,17 +235,17 @@ public:
                   (scom_targets[x]->getAttr<TARGETING::ATTR_SCOM_SWITCHES>().useXscom) ||
                   (scom_targets[x]->getAttr<TARGETING::ATTR_SCOM_SWITCHES>().useInbandScom))
           {
-              TRACFCOMP( g_trac_scom, "ScomTest::test_FSISCOMreadWrite_centaur> Target %d is the MASTER Sentinal or is set to use Xscom or Inband Scom, exiting test", x );
+              TRACDCOMP( g_trac_scom, "ScomTest::test_FSISCOMreadWrite_centaur> Target %d is the MASTER Sentinal or is set to use Xscom or Inband Scom, exiting test", x );
               scom_targets[x] = NULL; //remove from our list
           }
           else if(0 == scom_targets[x]->getAttr<TARGETING::ATTR_SCOM_SWITCHES>().useFsiScom)
           {
-              TRACFCOMP( g_trac_scom, "ScomTest::test_FSISCOMreadWrite_centaur> useFsiScom set to zero on target %d", x );
+              TRACDCOMP( g_trac_scom, "ScomTest::test_FSISCOMreadWrite_centaur> useFsiScom set to zero on target %d", x );
               scom_targets[x] = NULL; //remove from our list
           }
           else if( !FSI::isSlavePresent(scom_targets[x]) )
           {
-              TRACFCOMP( g_trac_scom, "ScomTest::test_FSISCOMreadWrite_centaur> Target %d is not present", x );
+              TRACDCOMP( g_trac_scom, "ScomTest::test_FSISCOMreadWrite_centaur> Target %d is not present", x );
               scom_targets[x] = NULL; //remove from our list
           }
       }
@@ -271,7 +271,7 @@ public:
       // write all the test registers
       for( uint64_t x = 0; x < NUM_ADDRS; x++ )
       {
-          TRACFCOMP(g_trac_scom, "ScomTest::test_FSISCOMreadWrite_centaur> x=%d, addr=%.8X, target=%p", x,  test_data[x].addr, test_data[x].target );
+          TRACDCOMP(g_trac_scom, "ScomTest::test_FSISCOMreadWrite_centaur> x=%d, addr=%.8X, target=%p", x,  test_data[x].addr, test_data[x].target );
 
           //only run if the target exists
           if(test_data[x].target == NULL)
@@ -298,7 +298,7 @@ public:
       // read all the test registers
       for( uint64_t x = 0; x < NUM_ADDRS; x++ )
       {
-          TRACFCOMP(g_trac_scom, "ScomTest::test_FSISCOMreadWrite_centaur> x=%d, addr=%.8X, target=%p", x,  test_data[x].addr, test_data[x].target );
+          TRACDCOMP(g_trac_scom, "ScomTest::test_FSISCOMreadWrite_centaur> x=%d, addr=%.8X, target=%p", x,  test_data[x].addr, test_data[x].target );
 
           //only run if the target exists
           if(test_data[x].target == NULL)
@@ -349,18 +349,11 @@ public:
       //@VBU workaround - Disable Indirect SCOM test case o
       //Test case read/writes to valid addresses and is
       //potentially destructive on VBU
-      TARGETING::EntityPath syspath(TARGETING::EntityPath::PATH_PHYSICAL);
-      syspath.addLast(TARGETING::TYPE_SYS,0);
-      TARGETING::Target* sys = TARGETING::targetService().toTarget(syspath);
-      uint8_t vpo_mode = 0;
-      if( sys
-          && sys->tryGetAttr<TARGETING::ATTR_IS_SIMULATION>(vpo_mode)
-          && (vpo_mode == 1) )
+      if (TARGETING::is_vpo())
       {
-          return;
+           return;
       }
 
-
       // Setup some targets to use
       enum {
           myPROC9,
@@ -386,15 +379,15 @@ public:
           //only run if the target exists
           if(scom_targets[x] == NULL)
           {
-              TRACFCOMP( g_trac_scom, "ScomTest - TARGET = NULL - 1 x = %d", x);
+              TRACDCOMP( g_trac_scom, "ScomTest - TARGET = NULL - 1 x = %d", x);
               continue;
           }
           else if ((scom_targets[x]->getAttr<TARGETING::ATTR_SCOM_SWITCHES>().useXscom == 0) &&
                    (scom_targets[x]->getAttr<TARGETING::ATTR_SCOM_SWITCHES>().useFsiScom == 0))
 	  {
-            // If both FSI and XSCOM are not enabled.. then ignore..
-            TRACFCOMP(g_trac_scom, "INDIRECT SCOM>> SKIPPING ");
-            scom_targets[x] = NULL; //remove from our list
+              // If both FSI and XSCOM are not enabled.. then ignore..
+              TRACDCOMP(g_trac_scom, "INDIRECT SCOM>> SKIPPING ");
+              scom_targets[x] = NULL; //remove from our list
 	  }
 
       }
@@ -500,15 +493,9 @@ public:
       //@VBU workaround - Disable Indirect SCOM test case o
       //Test case read/writes to valid addresses and is
       //potentially destructive on VBU
-      TARGETING::EntityPath syspath(TARGETING::EntityPath::PATH_PHYSICAL);
-      syspath.addLast(TARGETING::TYPE_SYS,0);
-      TARGETING::Target* sys = TARGETING::targetService().toTarget(syspath);
-      uint8_t vpo_mode = 0;
-      if( sys
-          && sys->tryGetAttr<TARGETING::ATTR_IS_SIMULATION>(vpo_mode)
-          && (vpo_mode == 1) )
+      if (TARGETING::is_vpo())
       {
-          return;
+           return;
       }
 
       // Setup some targets to use
@@ -539,7 +526,7 @@ public:
           (scom_targets[myProc0]->getAttr<TARGETING::ATTR_SCOM_SWITCHES>().useFsiScom == 0))
       {
             // If both FSI and XSCOM are not enabled.. then ignore..
-            TRACFCOMP(g_trac_scom, "TRANSLATE SCOM>> SKIPPING ");
+            TRACDCOMP(g_trac_scom, "TRANSLATE SCOM>> SKIPPING ");
             scom_targets[myProc0] = NULL; //remove from our list
       }
 
@@ -566,9 +553,9 @@ public:
           uint64_t addr;
           uint64_t data;
       } test_data[] = {
-          { scom_targets[myEX1], 0x100F0120 ,0x7676767676767676},
-          { scom_targets[myEX5], 0x100F0166, 0x9191919191919191},
-          { scom_targets[myEX5], 0x130F0166, 0xabcdabcdabcdabcd},   // invalid unit 0 address
+          { scom_targets[myEX1], 0x10040000 ,0x7676767676767676},
+          { scom_targets[myEX5], 0x10040002, 0x9191919191919191},
+          { scom_targets[myEX5], 0x13040002, 0xabcdabcdabcdabcd},   // invalid unit 0 address
           { scom_targets[myEX1], 0x000F0166, 0xabcdabcdabcdabcd},   // invalid address range for target
       };
       const uint64_t NUM_ADDRS = sizeof(test_data)/sizeof(test_data[0]);
@@ -668,15 +655,9 @@ public:
       //@VBU workaround - Disable Indirect SCOM test case o
       //Test case read/writes to valid addresses and is
       //potentially destructive on VBU
-      TARGETING::EntityPath syspath(TARGETING::EntityPath::PATH_PHYSICAL);
-      syspath.addLast(TARGETING::TYPE_SYS,0);
-      TARGETING::Target* sys = TARGETING::targetService().toTarget(syspath);
-      uint8_t vpo_mode = 0;
-      if( sys
-          && sys->tryGetAttr<TARGETING::ATTR_IS_SIMULATION>(vpo_mode)
-          && (vpo_mode == 1) )
+      if (TARGETING::is_vpo())
       {
-          return;
+           return;
       }
 
       // Setup some targets to use
@@ -709,7 +690,7 @@ public:
           (scom_targets[myProc0]->getAttr<TARGETING::ATTR_SCOM_SWITCHES>().useFsiScom == 0))
       {
             // If both FSI and XSCOM are not enabled.. then ignore..
-            TRACFCOMP(g_trac_scom, "TRANSLATE_SCOM_MCS>> SKIPPING ");
+            TRACDCOMP(g_trac_scom, "TRANSLATE_SCOM_MCS>> SKIPPING ");
             scom_targets[myProc0] = NULL; //remove from our list
       }
 
@@ -754,10 +735,6 @@ public:
           { scom_targets[myMCS4], 0x0201184A, 0x3333333344444444},
           { scom_targets[myMCS2], 0x0201184A, 0x5555555566666666},
           { scom_targets[myMCS7], 0x0201184A, 0x7777777788888888},
-//	  { scom_targets[myMCS4], 0x02011C4A, 0x0101010101010101},  // invalid
-                                                                    // Unit for
-                                                                    // the
-                                                                    // target
 	  { scom_targets[myMCS4], 0x0601184A, 0x0101010101010101},  // invalid address range
 	  { scom_targets[myMCS4], 0x0200184A, 0x2323232323232323},  // Invalid address range for target
       };
@@ -842,6 +819,184 @@ public:
  }
 
 
+ void test_TranslateScom_MCS_DMI(void)
+{
+
+      TRACFCOMP( g_trac_scom, "ScomTest::test_TranslateScom_MCS_DMI Start" );
+      errlHndl_t l_err = NULL;
+
+      uint64_t fails = 0;
+      uint64_t total = 0;
+
+
+
+      //@VBU workaround - Disable Indirect SCOM test case o
+      //Test case read/writes to valid addresses and is
+      //potentially destructive on VBU
+      if (TARGETING::is_vpo())
+      {
+           return;
+      }
+
+      // Setup some targets to use
+      enum {
+          myProc0,
+          myMCS1,
+          myMCS2,
+          myMCS7,
+          myMCS4,
+          NUM_TARGETS
+      };
+
+      TARGETING::Target* scom_targets[NUM_TARGETS];
+      for( uint64_t x = 0; x < NUM_TARGETS; x++ )
+      {
+          scom_targets[x] = NULL;
+      }
+
+      // Target Proc 0 - to make sure we have XSCOM and FSISCOM attributes
+      TARGETING::EntityPath epath(TARGETING::EntityPath::PATH_PHYSICAL);
+      epath.addLast(TARGETING::TYPE_SYS,0);
+      epath.addLast(TARGETING::TYPE_NODE,0);
+      epath.addLast(TARGETING::TYPE_PROC,0);
+
+      scom_targets[myProc0] = TARGETING::targetService().toTarget(epath);
+
+      // Only check the Proc or Membuf targets to look at the SCOM attributes
+      if ((scom_targets[myProc0] != NULL) &&
+          (scom_targets[myProc0]->getAttr<TARGETING::ATTR_SCOM_SWITCHES>().useXscom == 0) &&
+          (scom_targets[myProc0]->getAttr<TARGETING::ATTR_SCOM_SWITCHES>().useFsiScom == 0))
+      {
+            // If both FSI and XSCOM are not enabled.. then ignore..
+            TRACDCOMP(g_trac_scom, "TRANSLATE_SCOM_MCS_DMI>> SKIPPING ");
+            scom_targets[myProc0] = NULL; //remove from our list
+      }
+
+
+      if (scom_targets[myProc0] != NULL)
+      {
+          // Add the MCS(1) to the path and  create new target
+          epath.addLast(TARGETING::TYPE_MCS,1);
+          scom_targets[myMCS1] = TARGETING::targetService().toTarget(epath);
+
+          // remote MCS(1) (off of sys-0/node-0/proc-0/MCS1)
+          epath.removeLast();
+
+          // add MCS4 target.
+          epath.addLast(TARGETING::TYPE_MCS,4);
+          scom_targets[myMCS4] = TARGETING::targetService().toTarget(epath);
+
+          // remote MCS4 target (off of sys-0/node-0/proc-0/MCS4)
+          epath.removeLast();
+
+          // add MCS2 target.
+          epath.addLast(TARGETING::TYPE_MCS,2);
+          scom_targets[myMCS2] = TARGETING::targetService().toTarget(epath);
+
+          // remove MCS2 target (off of sys-0/node-0/proc-0/MCS4)
+          epath.removeLast();
+
+          // add MCS7 target.
+          epath.addLast(TARGETING::TYPE_MCS,7);
+          scom_targets[myMCS7] = TARGETING::targetService().toTarget(epath);
+      }
+
+      // scratch data to use
+      //@fixme: Need to either fabricate some fake registers to use or save off data before modifying SCOMs to avoid
+      //   corrupting the HW.
+      struct {
+          TARGETING::Target* target;
+          uint64_t addr;
+          uint64_t data;
+      } test_data[] = {
+          { scom_targets[myMCS1], 0x800EAC0002011A3F ,0x1111111122222222},
+          { scom_targets[myMCS4], 0x800EAC0002011A3F, 0x3333333344444444},
+          { scom_targets[myMCS2], 0x800EAC0002011A3F, 0x5555555566666666},
+          { scom_targets[myMCS7], 0x800EAC0002011A3F, 0x7777777788888888},
+	  { scom_targets[myMCS4], 0x800EAC2002011A3F, 0x0101010101010101},  // invalid address range
+	  { scom_targets[myMCS4], 0x800EAC4002011E3F, 0x2323232323232323},  // Invalid address range for target
+      };
+      const uint64_t NUM_ADDRS = sizeof(test_data)/sizeof(test_data[0]);
+
+      size_t op_size = sizeof(uint32_t);
+
+      // write all the test registers
+      for( uint64_t x = 0; x < NUM_ADDRS; x++ )
+      {
+          //only run if the target exists
+          if(test_data[x].target == NULL)
+	  {
+              continue;
+          }
+
+          op_size = sizeof(uint64_t);
+
+          total++;
+          l_err = deviceWrite( test_data[x].target,
+                               &(test_data[x].data),
+                               op_size,
+                               DEVICE_SCOM_ADDRESS(test_data[x].addr) );
+          if( l_err )
+          {
+            if ((x == NUM_ADDRS-1) || (x==NUM_ADDRS-2))
+            {
+                TRACDCOMP( g_trac_scom, "ScomTest::test_translate MCS_DMI.. Expected Error log returned> x = %d", x );
+            }
+            else
+            {
+              TRACFCOMP(g_trac_scom, "ScomTest::test_translate_Scom_MCS_DMI> [%d] Write: Error from device : addr=0x%X, RC=%X", x,  test_data[x].addr, l_err->reasonCode() );
+              TS_FAIL( "ScomTest::test_Translate_SCOM_mcs_DMI> ERROR : Unexpected error log from write1" );
+              fails++;
+              errlCommit(l_err,SCOM_COMP_ID);
+             }
+
+              delete l_err;
+          }
+      }
+
+      // allocate space for read data
+      uint64_t read_data[NUM_ADDRS];
+
+      memset(read_data, 0, sizeof read_data);
+
+      // read all the test registers
+      for( uint64_t x = 0; x < NUM_ADDRS-2; x++ )
+      {
+          //only run if the target exists
+          if(test_data[x].target == NULL)
+          {
+              continue;
+          }
+
+          op_size = sizeof(uint64_t);
+
+          total++;
+          l_err = deviceRead( test_data[x].target,
+                              &(read_data[x]),
+                              op_size,
+                              DEVICE_SCOM_ADDRESS(test_data[x].addr) );
+
+          if( l_err )
+          {
+              TRACFCOMP(g_trac_scom, "ScomTest::test_TranslateScom_MCS_DMI> [%d] Read: Error from device : addr=0x%X, RC=%X", x,  test_data[x].addr, l_err->reasonCode() );
+              TS_FAIL( "ScomTest::test_TranslateScom_MCS_DMI> ERROR : Unexpected error log from write1" );
+              fails++;
+              errlCommit(l_err,SCOM_COMP_ID);
+              delete l_err;
+          }
+          else if((read_data[x] & 0x000000000000FFFF) != (test_data[x].data & 0x000000000000FFFF))
+       //   else if((read_data[x]) != (test_data[x].data))
+          {
+              TRACFCOMP(g_trac_scom, "ScomTest::test_TranslateScom_MCS_DMI> [%d] Read: Data miss-match : addr=0x%X, read_data=0x%llx, write_data=0x%llx", x, test_data[x].addr, read_data[x], test_data[x].data);
+              TS_FAIL( "ScomTest::test_TranslateScom_MCS_DMI> ERROR : Data miss-match between read and expected data" );
+              fails++;
+          }
+
+      }
+
+      TRACFCOMP( g_trac_scom, "ScomTest::test_translateScom_MCS_DMI> %d/%d fails", fails, total );
+
+ }
 
  void test_TranslateScom_MBA_MBS(void)
   {
@@ -854,15 +1009,9 @@ public:
       //@VBU workaround - Disable Indirect SCOM test case o
       //Test case read/writes to valid addresses and is
       //potentially destructive on VBU
-      TARGETING::EntityPath syspath(TARGETING::EntityPath::PATH_PHYSICAL);
-      syspath.addLast(TARGETING::TYPE_SYS,0);
-      TARGETING::Target* sys = TARGETING::targetService().toTarget(syspath);
-      uint8_t vpo_mode = 0;
-      if( sys
-          && sys->tryGetAttr<TARGETING::ATTR_IS_SIMULATION>(vpo_mode)
-          && (vpo_mode == 1) )
+      if (TARGETING::is_vpo())
       {
-          return;
+           return;
       }
 
       // Setup some targets to use
@@ -894,7 +1043,7 @@ public:
           (scom_targets[myMembuf0]->getAttr<TARGETING::ATTR_SCOM_SWITCHES>().useFsiScom == 0))
       {
             // If both FSI and XSCOM are not enabled.. then ignore..
-            TRACFCOMP(g_trac_scom, "TRANSLATE_SCOM_MBA_MBS>> SKIPPING ");
+            TRACDCOMP(g_trac_scom, "TRANSLATE_SCOM_MBA_MBS>> SKIPPING ");
             scom_targets[myMembuf0] = NULL; //remove from our list
       }
 
@@ -923,10 +1072,13 @@ public:
           uint64_t addr;
           uint64_t data;
       } test_data[] = {
-          { scom_targets[myMBA0], 0x03010655 ,0x1111111122222222},
-          { scom_targets[myMBA1], 0x03010655, 0x3333333344444444},
-          { scom_targets[myMBS],  0x02011417, 0x1231231231231231},
-	  { scom_targets[myMBA0], 0x03010E55, 0x0101010101010101},  // invalid passing in a non-0 unit address
+          { scom_targets[myMBA0], 0x03010655 ,0x111111111111DDDD},
+          { scom_targets[myMBA1], 0x03010655, 0x333333334444EEEE},
+          { scom_targets[myMBA0], 0x8000C0140301143F,0x1111111111111212},
+          { scom_targets[myMBA1], 0x8000C0140301143F, 0x333333334444abcd},
+          { scom_targets[myMBS],  0x02011417, 0x123123123123FFFF},
+          { scom_targets[myMBA0], 0x8000C0140301183F,0x111111111111ccee}, // invalid non zero indirect address
+	  { scom_targets[myMBA0], 0x03010E55, 0x010101010101CCCC},  // invalid passing in a non-0 unit address
       };
       const uint64_t NUM_ADDRS = sizeof(test_data)/sizeof(test_data[0]);
 
@@ -950,18 +1102,18 @@ public:
                                DEVICE_SCOM_ADDRESS(test_data[x].addr) );
           if( l_err )
           {
-              // checking the read of NUM_ADDRs - 1 because the last entry written above failed as expected.
-              if (x == (NUM_ADDRS-1))
-              {
-                  TRACDCOMP( g_trac_scom, "ScomTest::test_translate MCS.. Expected Errorlog Returned> x = %d", x );
-              }
-              else
-              {
-                  TRACFCOMP(g_trac_scom, "ScomTest::test_translate_Scom_MBA_MBS> [%d] Write: Error from device : addr=0x%X, RC=%X", x,  test_data[x].addr, l_err->reasonCode() );
-                  TS_FAIL( "ScomTest::test_Translate_SCOM_MBA_MBS> ERROR : Unexpected error log from write1" );
-                  fails++;
-                  errlCommit(l_err,SCOM_COMP_ID);
-              }
+            // checking the read of NUM_ADDRs - 1 because the last entry written above failed as expected.
+            if ((x == NUM_ADDRS-1) || (x==NUM_ADDRS-2))
+            {
+                TRACDCOMP( g_trac_scom, "ScomTest::test_translate MCS.. Expected Errorlog Returned> x = %d", x );
+            }
+            else
+	    {
+              TRACFCOMP(g_trac_scom, "ScomTest::test_translate_Scom_MBA_MBS> [%d] Write: Error from device : addr=0x%X, RC=%X", x,  test_data[x].addr, l_err->reasonCode() );
+              TS_FAIL( "ScomTest::test_Translate_SCOM_MBA_MBS> ERROR : Unexpected error log from write1" );
+              fails++;
+              errlCommit(l_err,SCOM_COMP_ID);
+             }
 
               delete l_err;
           }
@@ -971,7 +1123,7 @@ public:
       uint64_t read_data[NUM_ADDRS];
 
       // read all the test registers
-      for( uint64_t x = 0; x < NUM_ADDRS-1; x++ )
+      for( uint64_t x = 0; x < NUM_ADDRS-2; x++ )
       {
           memset(read_data, 0, sizeof read_data);
 
@@ -997,6 +1149,16 @@ public:
               fails++;
               errlCommit(l_err,SCOM_COMP_ID);
           }
+          else if ((x == 2) || (x==3))
+          {
+              if((read_data[x] & 0x000000000000FFFF) != (test_data[x].data & 0x000000000000FFFF))
+
+              {
+                  TRACFCOMP(g_trac_scom, "ScomTest::test_TranslateScom_ABUS> [%d] Read: Data miss-match : addr=0x%X, read_data=0x%llx, write_data=0x%llx", x, test_data[x].addr, read_data[x], test_data[x].data);
+                  TS_FAIL( "ScomTest::test_TranslateScom_ABUS> ERROR : Data miss-match between read and expected data" );
+                  fails++;
+              }
+          }
           else if((read_data[x]) != (test_data[x].data))
           {
               TRACFCOMP(g_trac_scom, "ScomTest::test_TranslateScom_MBA_MBS> [%d] Read: Data miss-match : addr=0x%X, read_data=0x%llx, write_data=0x%llx", x, test_data[x].addr, read_data[x], test_data[x].data);
@@ -1011,8 +1173,354 @@ public:
  }
 
 
+ void test_TranslateScom_ABUS(void)
+{
+
+      TRACFCOMP( g_trac_scom, "ScomTest::test_TranslateScom_ABUS Start" );
+      errlHndl_t l_err = NULL;
+
+      uint64_t fails = 0;
+      uint64_t total = 0;
+
+      //@VBU workaround - Disable Indirect SCOM test case o
+      //Test case read/writes to valid addresses and is
+      //potentially destructive on VBU
+      if (TARGETING::is_vpo())
+      {
+           return;
+      }
+
+      // Setup some targets to use
+      enum {
+          myProc0,
+          myABUS0,
+          myABUS1,
+          myABUS2,
+          NUM_TARGETS
+      };
+
+      TARGETING::Target* scom_targets[NUM_TARGETS];
+      for( uint64_t x = 0; x < NUM_TARGETS; x++ )
+      {
+          scom_targets[x] = NULL;
+      }
+
+      // Target Proc 0 - to make sure we have XSCOM and FSISCOM attributes
+      TARGETING::EntityPath epath(TARGETING::EntityPath::PATH_PHYSICAL);
+      epath.addLast(TARGETING::TYPE_SYS,0);
+      epath.addLast(TARGETING::TYPE_NODE,0);
+      epath.addLast(TARGETING::TYPE_PROC,0);
+
+      scom_targets[myProc0] = TARGETING::targetService().toTarget(epath);
+
+      // Only check the Proc or Membuf targets to look at the SCOM attributes
+      if ((scom_targets[myProc0] != NULL) &&
+          (scom_targets[myProc0]->getAttr<TARGETING::ATTR_SCOM_SWITCHES>().useXscom == 0) &&
+          (scom_targets[myProc0]->getAttr<TARGETING::ATTR_SCOM_SWITCHES>().useFsiScom == 0))
+      {
+            // If both FSI and XSCOM are not enabled.. then ignore..
+            TRACDCOMP(g_trac_scom, "TRANSLATE_SCOM_ABUS>> SKIPPING ");
+            scom_targets[myProc0] = NULL; //remove from our list
+      }
+
+
+      if (scom_targets[myProc0] != NULL)
+      {
+          // Add the ABUS 0 to the path and  create new target
+          epath.addLast(TARGETING::TYPE_ABUS,0);
+          scom_targets[myABUS0] = TARGETING::targetService().toTarget(epath);
+
+          // remote ABUS 0 (off of sys-0/node-0/proc-0/ABUS0)
+          epath.removeLast();
+
+          // add ABUS 1 target.
+          epath.addLast(TARGETING::TYPE_ABUS,1);
+          scom_targets[myABUS1] = TARGETING::targetService().toTarget(epath);
+
+          // remote ABUS1 target (off of sys-0/node-0/proc-0/ABUS1)
+          epath.removeLast();
 
+          // add ABUS2 target.
+          epath.addLast(TARGETING::TYPE_ABUS,2);
+          scom_targets[myABUS2] = TARGETING::targetService().toTarget(epath);
 
+      }
+
+      // scratch data to use
+      //@fixme: Need to either fabricate some fake registers to use or save off data before modifying SCOMs to avoid
+      //   corrupting the HW.
+      struct {
+          TARGETING::Target* target;
+          uint64_t addr;
+          uint64_t data;
+      } test_data[] = {
+
+          { scom_targets[myABUS0], 0x800C4C0008010C3F ,0x1111111101010101},
+          { scom_targets[myABUS1], 0x800C4C0008010C3F, 0x3333333311111111},
+          { scom_targets[myABUS2], 0x800C4C0008010C3F, 0x5555555521212121},
+	  { scom_targets[myABUS0], 0x800C4C0208010C3F, 0x0101010101010101},  // invalid address range - non zero
+	  { scom_targets[myABUS2], 0x800C4C0004010C3F, 0x2323232323232323},  // Invalid address range for target
+      };
+      const uint64_t NUM_ADDRS = sizeof(test_data)/sizeof(test_data[0]);
+
+      size_t op_size = sizeof(uint32_t);
+
+      // write all the test registers
+      for( uint64_t x = 0; x < NUM_ADDRS; x++ )
+      {
+          //only run if the target exists
+          if(test_data[x].target == NULL)
+	  {
+              continue;
+          }
+
+          op_size = sizeof(uint64_t);
+
+          total++;
+          l_err = deviceWrite( test_data[x].target,
+                               &(test_data[x].data),
+                               op_size,
+                               DEVICE_SCOM_ADDRESS(test_data[x].addr) );
+          if( l_err )
+          {
+              if ((x == NUM_ADDRS-1) || (x==NUM_ADDRS-2))
+              {
+                  TRACDCOMP( g_trac_scom, "ScomTest::test_translate ABUS.. Expected Error log returned> x = %d", x );
+              }
+              else
+              {
+                  TRACFCOMP(g_trac_scom, "ScomTest::test_translate_Scom_ABUS> [%d] Write: Error from device : addr=0x%X, RC=%X", x,  test_data[x].addr, l_err->reasonCode() );
+                  TS_FAIL( "ScomTest::test_Translate_SCOM_ABUS> ERROR : Unexpected error log from write1" );
+                  fails++;
+                  errlCommit(l_err,SCOM_COMP_ID);
+              }
+
+              delete l_err;
+          }
+      }
+
+      // allocate space for read data
+      uint64_t read_data[NUM_ADDRS];
+
+      memset(read_data, 0, sizeof read_data);
+
+      // read all the test registers
+      for( uint64_t x = 0; x < NUM_ADDRS-2; x++ )
+      {
+          //only run if the target exists
+          if(test_data[x].target == NULL)
+          {
+              continue;
+          }
+
+          op_size = sizeof(uint64_t);
+
+          total++;
+          l_err = deviceRead( test_data[x].target,
+                              &(read_data[x]),
+                              op_size,
+                              DEVICE_SCOM_ADDRESS(test_data[x].addr) );
+
+          if( l_err )
+          {
+              TRACFCOMP(g_trac_scom, "ScomTest::test_TranslateScom_ABUS> [%d] Read: Error from device : addr=0x%X, RC=%X", x,  test_data[x].addr, l_err->reasonCode() );
+              TS_FAIL( "ScomTest::test_TranslateScom_ABUS> ERROR : Unexpected error log from write1" );
+              fails++;
+              errlCommit(l_err,SCOM_COMP_ID);
+              delete l_err;
+          }
+          else if((read_data[x] & 0x000000000000FFFF) != (test_data[x].data & 0x000000000000FFFF))
+          {
+              TRACFCOMP(g_trac_scom, "ScomTest::test_TranslateScom_ABUS> [%d] Read: Data miss-match : addr=0x%X, read_data=0x%llx, write_data=0x%llx", x, test_data[x].addr, read_data[x], test_data[x].data);
+              TS_FAIL( "ScomTest::test_TranslateScom_ABUS> ERROR : Data miss-match between read and expected data" );
+              fails++;
+          }
+
+      }
+
+      TRACFCOMP( g_trac_scom, "ScomTest::test_translateScom_ABUS> %d/%d fails", fails, total );
+
+ }
+
+
+ void test_TranslateScom_XBUS(void)
+{
+
+      TRACFCOMP( g_trac_scom, "ScomTest::test_TranslateScom_XBUS Start" );
+      errlHndl_t l_err = NULL;
+
+      uint64_t fails = 0;
+      uint64_t total = 0;
+
+      //@VBU workaround - Disable Indirect SCOM test case o
+      //Test case read/writes to valid addresses and is
+      //potentially destructive on VBU
+      if (TARGETING::is_vpo())
+      {
+           return;
+      }
+
+
+      // Setup some targets to use
+      enum {
+          myProc0,
+          myXBUS0,
+          myXBUS1,
+          myXBUS2,
+          myXBUS3,
+          NUM_TARGETS
+      };
+
+      TARGETING::Target* scom_targets[NUM_TARGETS];
+      for( uint64_t x = 0; x < NUM_TARGETS; x++ )
+      {
+          scom_targets[x] = NULL;
+      }
+
+      // Target Proc 0 - to make sure we have XSCOM and FSISCOM attributes
+      TARGETING::EntityPath epath(TARGETING::EntityPath::PATH_PHYSICAL);
+      epath.addLast(TARGETING::TYPE_SYS,0);
+      epath.addLast(TARGETING::TYPE_NODE,0);
+      epath.addLast(TARGETING::TYPE_PROC,0);
+
+      scom_targets[myProc0] = TARGETING::targetService().toTarget(epath);
+
+      // Only check the Proc or Membuf targets to look at the SCOM attributes
+      if ((scom_targets[myProc0] != NULL) &&
+          (scom_targets[myProc0]->getAttr<TARGETING::ATTR_SCOM_SWITCHES>().useXscom == 0) &&
+          (scom_targets[myProc0]->getAttr<TARGETING::ATTR_SCOM_SWITCHES>().useFsiScom == 0))
+      {
+            // If both FSI and XSCOM are not enabled.. then ignore..
+            TRACDCOMP(g_trac_scom, "TRANSLATE_SCOM_XBUS>> SKIPPING ");
+            scom_targets[myProc0] = NULL; //remove from our list
+      }
+
+
+      if (scom_targets[myProc0] != NULL)
+      {
+          // Add the XBUS 0 to the path and  create new target
+          epath.addLast(TARGETING::TYPE_XBUS,0);
+          scom_targets[myXBUS0] = TARGETING::targetService().toTarget(epath);
+
+          // remove XBUS 0 (off of sys-0/node-0/proc-0/XBUS0)
+          epath.removeLast();
+
+          // add XBUS 1 target.
+          epath.addLast(TARGETING::TYPE_XBUS,1);
+          scom_targets[myXBUS1] = TARGETING::targetService().toTarget(epath);
+
+          // remove XBUS1 target (off of sys-0/node-0/proc-0/XBUS1)
+          epath.removeLast();
+
+          // add XBUS2 target.
+          epath.addLast(TARGETING::TYPE_XBUS,2);
+          scom_targets[myXBUS2] = TARGETING::targetService().toTarget(epath);
+
+          // remove XBUS2 target (off of sys-0/node-0/proc-0/XBUS2)
+          epath.removeLast();
+
+          // add XBUS3 target.
+          epath.addLast(TARGETING::TYPE_XBUS,3);
+          scom_targets[myXBUS3] = TARGETING::targetService().toTarget(epath);
+
+      }
+
+      // scratch data to use
+      //@fixme: Need to either fabricate some fake registers to use or save off data before modifying SCOMs to avoid
+      //   corrupting the HW.
+      struct {
+          TARGETING::Target* target;
+          uint64_t addr;
+          uint64_t data;
+      } test_data[] = {
+
+          { scom_targets[myXBUS0], 0x800000200401103F ,0x1111111101010101},
+          { scom_targets[myXBUS1], 0x800000200401103F, 0x3333333311111111},
+          { scom_targets[myXBUS2], 0x800000200401103F, 0x555555552121aaaa},
+          { scom_targets[myXBUS3], 0x800000200401103F, 0x555555552121bbbb},
+	  { scom_targets[myXBUS0], 0x8000002004011C3F, 0x0101010101010101},  // invalid address range - non zero
+	  { scom_targets[myXBUS2], 0x800000200401003F, 0x2323232323232323},  // Invalid address range for target
+      };
+      const uint64_t NUM_ADDRS = sizeof(test_data)/sizeof(test_data[0]);
+
+      size_t op_size = sizeof(uint32_t);
+
+      // write all the test registers
+      for( uint64_t x = 0; x < NUM_ADDRS; x++ )
+      {
+          //only run if the target exists
+          if(test_data[x].target == NULL)
+	  {
+              continue;
+          }
+
+          op_size = sizeof(uint64_t);
+
+          total++;
+          l_err = deviceWrite( test_data[x].target,
+                               &(test_data[x].data),
+                               op_size,
+                               DEVICE_SCOM_ADDRESS(test_data[x].addr) );
+          if( l_err )
+          {
+            if ((x == NUM_ADDRS-1) || (x==NUM_ADDRS-2))
+            {
+                TRACDCOMP( g_trac_scom, "ScomTest::test_translate XBUS.. Expected Error log returned> x = %d", x );
+            }
+            else
+            {
+              TRACFCOMP(g_trac_scom, "ScomTest::test_translate_Scom_XBUS> [%d] Write: Error from device : addr=0x%X, RC=%X", x,  test_data[x].addr, l_err->reasonCode() );
+              TS_FAIL( "ScomTest::test_Translate_SCOM_XBUS> ERROR : Unexpected error log from write1" );
+              fails++;
+              errlCommit(l_err,SCOM_COMP_ID);
+             }
+
+              delete l_err;
+          }
+      }
+
+      // allocate space for read data
+      uint64_t read_data[NUM_ADDRS];
+
+      memset(read_data, 0, sizeof read_data);
+
+      // read all the test registers
+      for( uint64_t x = 0; x < NUM_ADDRS-2; x++ )
+      {
+          //only run if the target exists
+          if(test_data[x].target == NULL)
+          {
+              continue;
+          }
+
+          op_size = sizeof(uint64_t);
+
+          total++;
+          l_err = deviceRead( test_data[x].target,
+                              &(read_data[x]),
+                              op_size,
+                              DEVICE_SCOM_ADDRESS(test_data[x].addr) );
+
+          if( l_err )
+          {
+              TRACFCOMP(g_trac_scom, "ScomTest::test_TranslateScom_XBUS> [%d] Read: Error from device : addr=0x%X, RC=%X", x,  test_data[x].addr, l_err->reasonCode() );
+              TS_FAIL( "ScomTest::test_TranslateScom_XBUS> ERROR : Unexpected error log from write1" );
+              fails++;
+              errlCommit(l_err,SCOM_COMP_ID);
+              delete l_err;
+          }
+          else if((read_data[x] & 0x000000000000FFFF) != (test_data[x].data & 0x000000000000FFFF))
+          {
+              TRACFCOMP(g_trac_scom, "ScomTest::test_TranslateScom_XBUS> [%d] Read: Data miss-match : addr=0x%X, read_data=0x%llx, write_data=0x%llx", x, test_data[x].addr, read_data[x], test_data[x].data);
+              TS_FAIL( "ScomTest::test_TranslateScom_XBUS> ERROR : Data miss-match between read and expected data" );
+              fails++;
+          }
+
+      }
+
+      TRACFCOMP( g_trac_scom, "ScomTest::test_translateScom_XBUS> %d/%d fails", fails, total );
+
+ }
   //@todo - write tests to verify connection between XSCOM and FSISCOM
 
   //@todo - write error path testcase for FSI scom using bad address