Remove is_master conditional from getVersionInfo in sbe_update

Previously we were having issues reading from the slave proc's
SBE while we were in cache containment. We have re-order the IPL
steps to reset the memory bars later on in the boot. This allows
us to perform the reads now. We had issues running chipOps on simics.
I am opening up a defect to look into this problem but for now we will
only do i2c reads on simics.

Change-Id: I177082d9c443d83ee750c57cde9a16c09844807f
RTC: 182266
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52040
Reviewed-by: Martin Gloff <mgloff@us.ibm.com>
Reviewed-by: Roland Veloz <rveloz@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

1 files changed, 15 insertions, 20 deletions

diff --git a/src/usr/sbe/sbe_update.C b/src/usr/sbe/sbe_update.C
index ea05f20ca..af032a07f 100644
--- a/src/usr/sbe/sbe_update.C
+++ b/src/usr/sbe/sbe_update.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2013,2017                        */
+/* Contributors Listed Below - COPYRIGHT 2013,2018                        */
 /* [+] Google Inc.                                                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
@@ -1885,11 +1885,9 @@ namespace SBE
             /*  Get SEEPROM 0 SBE Version Information  */
             /*******************************************/
 
-            // If the current seeprom is side 0 and is on master proc,
-            // then attempt read via chipOp
-            // TODO RTC: 182266 Remove is_master conditional once we figure out
-            //      how we can write to master cache from slave SBE
-            if (l_sideZeroIsActive && io_sbeState.target_is_master)
+            // If the current seeprom is side 0 then attempt read via chipOp
+            // TODO RTC:186269 Remove forced I2C path when simics issue is resolved
+            if (l_sideZeroIsActive && !Util::isSimicsRunning())
             {
                 err = getSeepromSideVersionViaChipOp(io_sbeState.target,
                                             io_sbeState.seeprom_0_ver,
@@ -1923,12 +1921,11 @@ namespace SBE
                 }
             }
 
-            //If side 0 is not active, or this is a slave proc, or there was
-            //an error trying to read the primary via chipOp, then try reading via I2C
-            // TODO RTC: 182266 Remove is_master conditional once we figure out
-            //      how we can write to master cache from slave SBE
+            //If side 0 is not active or there was an error trying to read
+            //the primary via chipOp, then try reading via I2C
+            // TODO RTC:186269 Remove forced I2C path when simics issue is resolved
             if(!l_sideZeroIsActive || !l_sbeSupportedSeepromReadOp ||
-                l_errFoundDuringChipOp|| !io_sbeState.target_is_master)
+                l_errFoundDuringChipOp || Util::isSimicsRunning())
             {
 
                 err = getSeepromSideVersionViaI2c(io_sbeState.target,
@@ -1956,13 +1953,12 @@ namespace SBE
             /*  Get SEEPROM 1 SBE Version Information  */
             /*******************************************/
 
-            //If side 1 is active and this is master, then attempt read via chipOp
+            //If side 1 is active, then attempt read via chipOp
             //Note that there is no reason to attempt chipOp on backup if it failed
             //on the primary.
-            // TODO RTC: 182266 Remove is_master conditional once we figure out
-            //      how we can write to master cache from slave SBE
+            // TODO RTC:186269 Remove forced I2C path when simics issue is resolved
             if (!l_sideZeroIsActive && l_sbeSupportedSeepromReadOp &&
-                !l_errFoundDuringChipOp && io_sbeState.target_is_master)
+                !l_errFoundDuringChipOp && !Util::isSimicsRunning() )
             {
                 err = getSeepromSideVersionViaChipOp(io_sbeState.target,
                                                   io_sbeState.seeprom_1_ver,
@@ -1996,12 +1992,11 @@ namespace SBE
                 }
             }
 
-            //If side 1 is not active, or this is a slave proc,  or there was
-            //an error trying to read the primary via chipOp, then try reading via I2C
-            // TODO RTC: 182266 Remove is_master conditional once we figure out
-            //      how we can write to master cache from slave SBE
+            //If side 1 is not active, or there was an error trying to read
+            //the primary via chipOp, then try reading via I2C
+            // TODO RTC:186269 Remove forced I2C path when simics issue is resolved
             if(l_sideZeroIsActive || !l_sbeSupportedSeepromReadOp ||
-                l_errFoundDuringChipOp || !io_sbeState.target_is_master)
+                l_errFoundDuringChipOp || Util::isSimicsRunning() )
             {
                 err = getSeepromSideVersionViaI2c(io_sbeState.target,
                                             EEPROM::SBE_BACKUP,