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| author | Thi Tran <thi@us.ibm.com> | 2013-12-01 09:39:35 -0600 |
|---|---|---|
| committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2013-12-06 10:13:01 -0600 |
| commit | 7615414ee5ffc83a9c2c9d65770c57f69d37fc4e (patch) | |
| tree | 08ca9d4762f9be95609973b95c59efda1b1bca22 /src/usr/pore/poreve/model | |
| parent | 1e00a3c8a448fccb7b0afa65aa78692a3d7e3c68 (diff) | |
| download | blackbird-hostboot-7615414ee5ffc83a9c2c9d65770c57f69d37fc4e.tar.gz blackbird-hostboot-7615414ee5ffc83a9c2c9d65770c57f69d37fc4e.zip | |
VSBE update SW213552
Change-Id: I1e8d075ace452816183c584561fe948d338ea756
CQ:SW213552
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/7468
Tested-by: Jenkins Server
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src/usr/pore/poreve/model')
| -rw-r--r-- | src/usr/pore/poreve/model/poremodel.C | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/usr/pore/poreve/model/poremodel.C b/src/usr/pore/poreve/model/poremodel.C index eeefe779f..5bd38dde1 100644 --- a/src/usr/pore/poreve/model/poremodel.C +++ b/src/usr/pore/poreve/model/poremodel.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: poremodel.C,v 1.24 2012/08/06 15:11:06 jeshua Exp $ +// $Id: poremodel.C,v 1.25 2013/05/30 00:30:43 bcbrock Exp $ /// \file poremodel.C /// \brief The PORE hardware engine model and interface to the virtual @@ -132,26 +132,26 @@ PoreModel::run(const uint64_t i_instructions, uint64_t& o_ran) ModelError me = ME_SUCCESS; bool stepped; bool writeControl = false; - int iv_status; + int status; do { o_ran = 0; iv_stopCode = 0; - iv_status = getStatus(); + status = getStatus(); - if (iv_status & (PORE_STATUS_ERROR_HALT | PORE_STATUS_MODEL_ERROR)) { + if (status & (PORE_STATUS_ERROR_HALT | PORE_STATUS_MODEL_ERROR)) { break; } me = registerRead(PORE_CONTROL, control); if (me != 0) break; - if (iv_status & PORE_STATUS_HARDWARE_STOP) { + if (status & PORE_STATUS_HARDWARE_STOP) { control &= ~BE64_BIT(0); writeControl = true; } - if (iv_status & (PORE_STATUS_BREAKPOINT | PORE_STATUS_TRAP)) { + if (status & (PORE_STATUS_BREAKPOINT | PORE_STATUS_TRAP)) { control |= BE64_BIT(1); writeControl = true; } |
