Set hostboot_mode bit on P3PC interrupt scom reg during intrrp init

The interrupt resource provider is expecting hostboot to set this
bit in the P3PC register to notify the interrupt logic that we
are running hostboot. Setting this allows the interrupt code to
allow thread contexts to be enabled w/o NVT data structures, also
complex store operations to thread context are considered invalid
and are dropped. This bit gets cleared in the shutdown path when
we reset the interrupt logic.

Change-Id: I41430c836633796d6841a965ef634f26939c6eb5
CQ: SW410032
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50598
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Martin Gloff <mgloff@us.ibm.com>
Reviewed-by: Matt Derksen <mderkse1@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>

1 files changed, 48 insertions, 1 deletions

diff --git a/src/usr/intr/intrrp.C b/src/usr/intr/intrrp.C
index f54577f98..7396e5009 100644
--- a/src/usr/intr/intrrp.C
+++ b/src/usr/intr/intrrp.C
@@ -54,6 +54,7 @@
 #include <arch/pvrformat.H>
 #include <config.h>
 #include <p9_misc_scom_addresses.H>
+#include <p9n2_misc_scom_addresses_fld.H>
 #include <util/utilmbox_scratch.H>
 
 #define INTR_TRACE_NAME INTR_COMP_NAME
@@ -204,9 +205,46 @@ errlHndl_t IntrRp::resetIntpForMpipl()
     return err;
 }
 
+
+errlHndl_t setHbModeOnP3PCReg()
+{
+    errlHndl_t l_err = nullptr;
+    do{
+        TARGETING::TargetHandleList l_funcProcs;
+        getAllChips(l_funcProcs, TYPE_PROC);
+        uint64_t  HOSTBOOT_MODE_MASK = 0x8000000000000000ull >> P9N2_PU_INT_PC_GLOBAL_CFG_HOSTBOOT_MODE;
+        uint64_t scom_data = 0;
+        size_t    DATA_SIZE          = sizeof(scom_data);
+        //Need to set this bit on all functional processors
+        for(const auto & l_procChip : l_funcProcs)
+        {
+            l_err = deviceRead(l_procChip,
+                                &scom_data,
+                                DATA_SIZE,
+                                DEVICE_SCOM_ADDRESS(PU_INT_PC_GLOBAL_CFG));
+            if( l_err)
+            {
+                break;
+            }
+
+            scom_data |= HOSTBOOT_MODE_MASK;
+            l_err = deviceWrite(l_procChip,
+                                &scom_data,
+                                DATA_SIZE,
+                                DEVICE_SCOM_ADDRESS(PU_INT_PC_GLOBAL_CFG));
+            if( l_err)
+            {
+                break;
+            }
+        }
+    }while(0);
+
+    return l_err;
+}
+
 errlHndl_t IntrRp::_init()
 {
-    errlHndl_t l_err = NULL;
+    errlHndl_t l_err = nullptr;
 
     // get the PIR
     // Which ever cpu core this is running on is the MASTER cpu
@@ -262,6 +300,15 @@ errlHndl_t IntrRp::_init()
             break;
         }
 
+        l_err = setHbModeOnP3PCReg();
+
+        if (l_err)
+        {
+            TRACFCOMP(g_trac_intr,
+                      "IntrRp::_init() Error setting Hostboot Mode bit on in P3PC registers");
+            break;
+        }
+
         uint8_t is_mpipl = 0;
         TARGETING::Target * sys = NULL;
         TARGETING::targetService().getTopLevelTarget(sys);