diff options
| author | dgilbert <dgilbert@us.ibm.com> | 2012-11-27 11:41:04 -0600 |
|---|---|---|
| committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2012-12-19 16:02:43 -0600 |
| commit | f5ae894024733fe3fb5ae26aaaa67cc8df0d0a3c (patch) | |
| tree | 7bcc9aa241f64758736e88d4f1bc9c4bf72db252 /src/usr/intr/test | |
| parent | 9458535739acca481800bbda1b59d4f1b213d2c2 (diff) | |
| download | blackbird-hostboot-f5ae894024733fe3fb5ae26aaaa67cc8df0d0a3c.tar.gz blackbird-hostboot-f5ae894024733fe3fb5ae26aaaa67cc8df0d0a3c.zip | |
Initialize the PIB hardware layer for interrupts
RTC: 47105
Change-Id: Iba893e65ee468b56e9e929a26d2888a67a4788af
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/2433
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src/usr/intr/test')
| -rw-r--r-- | src/usr/intr/test/intrtest.H | 76 |
1 files changed, 50 insertions, 26 deletions
diff --git a/src/usr/intr/test/intrtest.H b/src/usr/intr/test/intrtest.H index 93c2d235a..c12835d77 100644 --- a/src/usr/intr/test/intrtest.H +++ b/src/usr/intr/test/intrtest.H @@ -1,25 +1,25 @@ -// IBM_PROLOG_BEGIN_TAG -// This is an automatically generated prolog. -// -// $Source: src/usr/intr/test/intrtest.H $ -// -// IBM CONFIDENTIAL -// -// COPYRIGHT International Business Machines Corp. 2011 -// -// p1 -// -// Object Code Only (OCO) source materials -// Licensed Internal Code Source Materials -// IBM HostBoot Licensed Internal Code -// -// The source code for this program is not published or other- -// wise divested of its trade secrets, irrespective of what has -// been deposited with the U.S. Copyright Office. -// -// Origin: 30 -// -// IBM_PROLOG_END +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/intr/test/intrtest.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2011,2012 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ #ifndef __INTRTEST_H #define __INTRTEST_H @@ -139,7 +139,7 @@ class IntrTest: public CxxTest::TestSuite // Need to register a msgq msg_q_t msgQ = msg_q_create(); - err = INTR::registerMsgQ(msgQ,0,INTR::INTERPROC); + err = INTR::registerMsgQ(msgQ,0,INTR::ISN_INTERPROC); if(err) { TS_FAIL("Errl from INTR::registerMsgQ()"); @@ -151,16 +151,17 @@ class IntrTest: public CxxTest::TestSuite volatile uint8_t * mfrr = reinterpret_cast<uint8_t *>(iv_masterAddr+12); *(mfrr) = 0x55; - + + TRACFCOMP(g_trac_intr,"Waiting for IPI interrupt"); msg_t* msg = msg_wait(msgQ); // wait for interrupt msg TRACFCOMP(g_trac_intr,"Interrupt handled! Type=%lx",msg->data[0]); - if(msg->data[0] != INTR::INTERPROC) + if(msg->data[0] != INTR::INTERPROC_XISR) { TS_FAIL("INTR::unexpected interrupt type %lx",msg->data[0]); } msg_respond(msgQ,msg); - msgQ = INTR::unRegisterMsgQ(INTR::INTERPROC); + msgQ = INTR::unRegisterMsgQ(INTR::ISN_INTERPROC); if(msgQ) { msg_q_destroy(msgQ); @@ -171,6 +172,29 @@ class IntrTest: public CxxTest::TestSuite } } + // This checks the enablePsiIntr. Even though the master proc + // is already configured it does not use this interface + // and there are no other processor currently configured in simics + // to test with. + void test_enablePsi( void ) + { + errlHndl_t err = NULL; + if( TARGETING::is_vpo() ) + { + return; + } + + TARGETING::Target* target = NULL; + TARGETING::targetService().masterProcChipTargetHandle( target ); + + err = INTR::enablePsiIntr(target); + if(err) + { + TS_FAIL("Errl from INTER::enablePsiIntr"); + errlCommit(err,INTR_COMP_ID); + } + } + IntrTest() : CxxTest::TestSuite() { |
