INITPROC: Hostboot SW251725 DMI/ABUS/XBUS Power down state

Change-Id: I8e8773304dfab9b924d4915def18a3d10ad93451
CQ:SW251725
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/9642
Tested-by: Jenkins Server
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

5 files changed, 673 insertions, 10 deletions

diff --git a/src/usr/hwpf/hwp/dmi_training/proc_dmi_scominit/proc_dmi_scominit.C b/src/usr/hwpf/hwp/dmi_training/proc_dmi_scominit/proc_dmi_scominit.C
index 2a5e07146..c57d91f5e 100644
--- a/src/usr/hwpf/hwp/dmi_training/proc_dmi_scominit/proc_dmi_scominit.C
+++ b/src/usr/hwpf/hwp/dmi_training/proc_dmi_scominit/proc_dmi_scominit.C
@@ -1,11 +1,11 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dmi_training/proc_dmi_scominit/proc_dmi_scominit.C $ */
+/* $Source: src/usr/hwpf/hwp/dmi_training/proc_dmi_scominit/proc_dmi_scominit.C $      */
 /*                                                                        */
 /* IBM CONFIDENTIAL                                                       */
 /*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2013                   */
+/* COPYRIGHT International Business Machines Corp. 2012,2014              */
 /*                                                                        */
 /* p1                                                                     */
 /*                                                                        */
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_dmi_scominit.C,v 1.8 2013/11/09 18:37:40 jmcgill Exp $
+// $Id: proc_dmi_scominit.C,v 1.9 2014/03/12 18:56:56 jmcgill Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_dmi_scominit.C,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2012
@@ -39,6 +39,7 @@
 //------------------------------------------------------------------------------
 //  Version     Date        Owner       Description
 //------------------------------------------------------------------------------
+//    1.9       03/10/14    jmcgill     Add endpoint power up
 //    1.8       10/08/13    jmcgill     Updates for RAS review
 //    1.7       05/14/13    jmcgill     Address review comments
 //    1.6       05/01/13    jgrell      Added proc chip target
@@ -68,6 +69,17 @@
 //------------------------------------------------------------------------------
 #include <fapiHwpExecInitFile.H>
 #include <proc_dmi_scominit.H>
+#include <p8_scom_addresses.H>
+
+
+//------------------------------------------------------------------------------
+//  Constant definitions
+//------------------------------------------------------------------------------
+
+// map MCS chiplet ID -> associated bus IORESET bit in IOMC SCOM_MODE_PB
+// register
+const uint8_t IOMC_SCOM_MODE_PB_IORESET_BIT[8] = { 5,4,2,3,5,4,2,3 };
+
 
 extern "C" {
 
@@ -78,11 +90,15 @@ extern "C" {
 // HWP entry point, comments in header
 fapi::ReturnCode proc_dmi_scominit(const fapi::Target & i_target)
 {
-
     fapi::ReturnCode rc;
+    uint32_t rc_ecmd = 0x0;
+
     fapi::Target this_pu_target;
     std::vector<fapi::Target> targets;
 
+    uint8_t mcs_pos;
+    ecmdDataBufferBase data(64);
+
     // mark HWP entry
     FAPI_INF("proc_dmi_scominit: Start");
 
@@ -92,6 +108,42 @@ fapi::ReturnCode proc_dmi_scominit(const fapi::Target & i_target)
         // to execute
         if (i_target.getType() == fapi::TARGET_TYPE_MCS_CHIPLET)
         {
+            // assert IO reset to power-up bus endpoint logic
+            rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target, mcs_pos);
+            if (!rc.ok())
+            {
+                FAPI_ERR("proc_dmi_scominit: Error from FAPI_ATTR_GET (ATTR_CHIP_UNIT_POS) on %s",
+                         i_target.toEcmdString());
+                break;
+            }
+
+            // read-modify-write, set single reset bit (HW auto-clears)
+            // on writeback
+            rc = fapiGetScom(i_target, IOMC_SCOM_MODE_PB_0x02011A20, data);
+            if (!rc.ok())
+            {
+                FAPI_ERR("proc_dmi_scominit: Error from fapiGetScom (IOMC_SCOM_MODE_PB_0x02011A20) on %s",
+                         i_target.toEcmdString());
+                break;
+            }
+
+            rc_ecmd |= data.setBit(IOMC_SCOM_MODE_PB_IORESET_BIT[mcs_pos]);
+            if (rc_ecmd)
+            {
+                FAPI_ERR("proc_dmi_scominit: Error 0x%x forming IOMC SCOM Mode PB register data buffer on %s",
+                         rc_ecmd, i_target.toEcmdString());
+                rc.setEcmdError(rc_ecmd);
+                break;
+            }
+
+            rc = fapiPutScom(i_target, IOMC_SCOM_MODE_PB_0x02011A20, data);
+            if (!rc.ok())
+            {
+                FAPI_ERR("proc_dmi_scominit: Error from fapiPutScom (IOMC_SCOM_MODE_PB_0x02011A20) on %s",
+                         i_target.toEcmdString());
+                break;
+            }
+
             // get parent chip target
             rc = fapiGetParentChip(i_target, this_pu_target);
             if (!rc.ok())
diff --git a/src/usr/hwpf/hwp/include/p8_scom_addresses.H b/src/usr/hwpf/hwp/include/p8_scom_addresses.H
index 2a372d984..2477d938d 100755
--- a/src/usr/hwpf/hwp/include/p8_scom_addresses.H
+++ b/src/usr/hwpf/hwp/include/p8_scom_addresses.H
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: p8_scom_addresses.H,v 1.177 2014/03/05 00:13:59 belldi Exp $
+// $Id: p8_scom_addresses.H,v 1.178 2014/03/12 18:55:47 jmcgill Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/p8_scom_addresses.H,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
@@ -997,6 +997,8 @@ CONST_UINT64_T( MCS_MCICFG_0x0201184A                 , ULL(0x0201184A) );
 CONST_UINT64_T( MCS_MCISTAT_0x0201184B                , ULL(0x0201184B) );
 CONST_UINT64_T( MCS_MCICRCSYN_0x0201184C              , ULL(0x0201184C) );
 
+CONST_UINT64_T( IOMC_SCOM_MODE_PB_0x02011A20          , ULL(0x02011A20) );
+
 CONST_UINT64_T( MC1_BUSCNTL_FIR_0x02011E00            , ULL(0x02011E00) );
 CONST_UINT64_T( MC1_BUSCNTL_FIR_AND_0x02011E01        , ULL(0x02011E01) );
 
@@ -1267,6 +1269,8 @@ CONST_UINT64_T( X_PERV_LFIR_ACT1_0x04040011           , ULL(0x04040011) );
 CONST_UINT64_T( X_XBUS1_BUSCNTL_FIR_0x04011400        , ULL(0x04011400) );
 CONST_UINT64_T( X_XBUS1_BUSCNTL_FIR_AND_0x04011401    , ULL(0x04011401) );
 
+CONST_UINT64_T( X_XBUS_SCOM_MODE_PB_0x04011020        , ULL(0x04011020) );
+
 //------------------------------------------------------------------------------
 //      X-BUS THERMAL
 //------------------------------------------------------------------------------
@@ -1359,6 +1363,8 @@ CONST_UINT64_T( A_PERV_LFIR_ACT1_0x08040011           , ULL(0x08040011) );
 CONST_UINT64_T( A_ABUS_BUSCNTL_FIR_0x08010C00         , ULL(0x08010C00) );
 CONST_UINT64_T( A_ABUS_BUSCNTL_FIR_AND_0x08010C01     , ULL(0x08010C01) );
 
+CONST_UINT64_T( A_ABUS_SCOM_MODE_PB_0x08010C20        , ULL(0x08010C20) );
+
 //------------------------------------------------------------------------------
 //      PLL LOCK
 //------------------------------------------------------------------------------
@@ -2077,6 +2083,9 @@ This section is automatically updated by CVS when you check in this file.
 Be sure to create CVS comments when you commit so that they can be included here.
 
 $Log: p8_scom_addresses.H,v $
+Revision 1.178  2014/03/12 18:55:47  jmcgill
+add IO SCOM_MODE_PB register constant definitions (DMI/XBUS/ABUS)
+
 Revision 1.177  2014/03/05 00:13:59  belldi
 
 Added following CAPP Error Reporting and Handling regs. FFDC is collected from them in proc_suspend_io.
diff --git a/src/usr/hwpf/hwp/initfiles/p8.a_x_pci_dmi_fir.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.a_x_pci_dmi_fir.scom.initfile
index ba018573f..6f6096846 100644
--- a/src/usr/hwpf/hwp/initfiles/p8.a_x_pci_dmi_fir.scom.initfile
+++ b/src/usr/hwpf/hwp/initfiles/p8.a_x_pci_dmi_fir.scom.initfile
@@ -1,4 +1,4 @@
-#-- $Id: p8.a_x_pci_dmi_fir.scom.initfile,v 1.6 2014/02/11 23:26:33 jmcgill Exp $
+#-- $Id: p8.a_x_pci_dmi_fir.scom.initfile,v 1.7 2014/03/12 19:00:28 jmcgill Exp $
 #-------------------------------------------------------------------------------
 #--
 #-- (C) Copyright International Business Machines Corp. 2011
@@ -29,6 +29,7 @@ define pcie_enabled = (ATTR_PROC_PCIE_ENABLE == ENUM_ATTR_PROC_PCIE_ENABLE_ENABL
 define trace_on_scom = (ATTR_CHIP_EC_FEATURE_TRACE_CONTROL_ON_SCOM != 0);
 define is_venice     = (ATTR_CHIP_EC_FEATURE_VENICE_SPECIFIC != 0);
 
+
 #--------------------------------------------------------------------------------
 #-- SCOM initializations
 #--------------------------------------------------------------------------------
@@ -73,6 +74,211 @@ scom 0x02011E03 {
     0:63, 0xDFFFFFFFFFFFC000, (mcr_enabled);
 }
 
+#-- IOMC0 bus initialization/powerdown settings
+#-- IOMC0.TX_WRAP.TX3.TXCTL.TX_CTL_REGS.TX_ID1_PG
+scom 0x800C946002011A3F {
+    bits,  scom_data,         expr;
+    48:53, 0b000000,          (mcl_enabled);
+} 
+
+#-- IOMC0.RX3.RXCTL.RX_CTL_REGS.RX_ID1_PG
+scom 0x8008506002011A3F {
+    bits,  scom_data,         expr;
+    48:53, 0b000000,          (mcl_enabled);
+} 
+
+#-- IOMC0.TX_WRAP.TX2.TXCTL.TX_CTL_REGS.TX_ID1_PG
+scom 0x800C944002011A3F {
+    bits,  scom_data,         expr;
+    48:53, 0b000001,          (mcl_enabled);
+} 
+
+#-- IOMC0.RX2.RXCTL.RX_CTL_REGS.RX_ID1_PG
+scom 0x8008504002011A3F {
+    bits,  scom_data,         expr;
+    48:53, 0b000001,          (mcl_enabled);
+}
+
+#-- IOMC0.TX_WRAP.TX0.TXCTL.TX_CTL_REGS.TX_ID1_PG
+scom 0x800C940002011A3F {
+    bits,  scom_data,         expr;
+    48:53, 0b000010,          (mcl_enabled);
+} 
+
+#-- IOMC0.RX0.RXCTL.RX_CTL_REGS.RX_ID1_PG
+scom 0x8008500002011A3F {
+    bits,  scom_data,         expr;
+    48:53, 0b000010,          (mcl_enabled);
+} 
+
+#-- IOMC0.TX_WRAP.TX1.TXCTL.TX_CTL_REGS.TX_ID1_PG
+scom 0x800C942002011A3F {
+    bits,  scom_data,         expr;
+    48:53, 0b000011,          (mcl_enabled);
+} 
+
+#-- IOMC0.RX1.RXCTL.RX_CTL_REGS.RX_ID1_PG
+scom 0x8008502002011A3F {
+    bits,  scom_data,         expr;
+    48:53, 0b000011,          (mcl_enabled);
+}
+
+#-- IOMC0 RX_MODE_PL (broadcast to all groups/lanes), set RX_LANE_PDWN
+scom 0x800001FF02011A3F {
+    bits, scom_data,          expr;
+    0:63, 0x0000000000008000, (mcl_enabled);
+}
+
+#-- IOMC0 TX_MODE_PL (broadcast to all groups/lanes), set TX_LANE_PDWN
+scom 0x800405FF02011A3F {
+    bits, scom_data,          expr;
+    0:63, 0x0000000000008000, (mcl_enabled);
+}
+
+#-- IOMC0 RX_LANE_DISABLED_VEC_0_15_PG (broadcast to all groups), disable all
+scom 0x800929E002011A3F {
+    bits, scom_data,          expr;
+    0:63, 0x000000000000FFFF, (mcl_enabled);
+}
+
+#-- IOMC0 RX_LANE_DISABLED_VEC_16_31_PG (broadcast to all groups), disable all
+scom 0x800931E002011A3F {
+    bits, scom_data,          expr;
+    0:63, 0x000000000000FFFF, (mcl_enabled);
+}
+
+#-- IOMC0 RX_CLK_MODE_PG (broadcast to all groups), set RX_CLK_PDWN
+scom 0x800801E002011A3F {
+    bits, scom_data,          expr;
+    0:63, 0x0000000000008000, (mcl_enabled);
+}
+
+#-- IOMC0 TX_LANE_DISABLED_VEC_0_15_PG (broadcast to all groups), disable all
+scom 0x800D1DE002011A3F {
+    bits, scom_data,          expr;
+    0:63, 0x000000000000FFFF, (mcl_enabled);
+}
+
+#-- IOMC0 TX_LANE_DISABLED_VEC_16_31_PG (broadcast to all groups), disable all
+scom 0x800D25E002011A3F {
+    bits, scom_data,          expr;
+    0:63, 0x000000000000FFFF, (mcl_enabled);
+}
+
+#-- IOMC0 TX_CLK_MODE_PG (broadcast to all groups), set TX_CLK_PDWN
+scom 0x800C05E002011A3F {
+    bits, scom_data,          expr;
+    0:63, 0x0000000000008000, (mcl_enabled);
+}
+
+#-- IOMC0 RX_FENCE_PG (broadcast to all groups), set RX_FENCE
+scom 0x8009A9E002011A3F {
+    bits, scom_data,          expr;
+    0:63, 0x0000000000008000, (mcl_enabled);
+}
+
+#-- IOMC1 bus initialization/powerdown settings
+#-- IOMC1.TX_WRAP.TX3.TXCTL.TX_CTL_REGS.TX_ID1_PG
+scom 0x800C946002011E3F {
+    bits,  scom_data,         expr;
+    48:53, 0b000000,          (mcr_enabled);
+} 
+
+#-- IOMC1.RX3.RXCTL.RX_CTL_REGS.RX_ID1_PG
+scom 0x8008506002011E3F {
+    bits,  scom_data,         expr;
+    48:53, 0b000000,          (mcr_enabled);
+} 
+
+#-- IOMC1.TX_WRAP.TX2.TXCTL.TX_CTL_REGS.TX_ID1_PG
+scom 0x800C944002011E3F {
+    bits,  scom_data,         expr;
+    48:53, 0b000001,          (mcr_enabled);
+} 
+
+#-- IOMC1.RX2.RXCTL.RX_CTL_REGS.RX_ID1_PG
+scom 0x8008504002011E3F {
+    bits,  scom_data,         expr;
+    48:53, 0b000001,          (mcr_enabled);
+}
+
+#-- IOMC1.TX_WRAP.TX0.TXCTL.TX_CTL_REGS.TX_ID1_PG
+scom 0x800C940002011E3F {
+    bits,  scom_data,         expr;
+    48:53, 0b000010,          (mcr_enabled);
+} 
+
+#-- IOMC1.RX0.RXCTL.RX_CTL_REGS.RX_ID1_PG
+scom 0x8008500002011E3F {
+    bits,  scom_data,         expr;
+    48:53, 0b000010,          (mcr_enabled);
+} 
+
+#-- IOMC1.TX_WRAP.TX1.TXCTL.TX_CTL_REGS.TX_ID1_PG
+scom 0x800C942002011E3F {
+    bits,  scom_data,         expr;
+    48:53, 0b000011,          (mcr_enabled);
+} 
+
+#-- IOMC1.RX1.RXCTL.RX_CTL_REGS.RX_ID1_PG
+scom 0x8008502002011E3F {
+    bits,  scom_data,         expr;
+    48:53, 0b000011,          (mcr_enabled);
+}
+
+#-- IOMC1 RX_MODE_PL (broadcast to all groups/lanes), set RX_LANE_PDWN
+scom 0x800001FF02011E3F {
+    bits, scom_data,          expr;
+    0:63, 0x0000000000008000, (mcr_enabled);
+}
+
+#-- IOMC1 TX_MODE_PL (broadcast to all groups/lanes), set TX_LANE_PDWN
+scom 0x800405FF02011E3F {
+    bits, scom_data,          expr;
+    0:63, 0x0000000000008000, (mcr_enabled);
+}
+
+#-- IOMC1 RX_LANE_DISABLED_VEC_0_15_PG (broadcast to all groups), disable all
+scom 0x800929E002011E3F {
+    bits, scom_data,          expr;
+    0:63, 0x000000000000FFFF, (mcr_enabled);
+}
+
+#-- IOMC1 RX_LANE_DISABLED_VEC_16_31_PG (broadcast to all groups), disable all
+scom 0x800931E002011E3F {
+    bits, scom_data,          expr;
+    0:63, 0x000000000000FFFF, (mcr_enabled);
+}
+
+#-- IOMC1 RX_CLK_MODE_PG (broadcast to all groups), set RX_CLK_PDWN
+scom 0x800801E002011E3F {
+    bits, scom_data,          expr;
+    0:63, 0x0000000000008000, (mcr_enabled);
+}
+
+#-- IOMC1 TX_LANE_DISABLED_VEC_0_15_PG (broadcast to all groups), disable all
+scom 0x800D1DE002011E3F {
+    bits, scom_data,          expr;
+    0:63, 0x000000000000FFFF, (mcr_enabled);
+}
+
+#-- IOMC1 TX_LANE_DISABLED_VEC_16_31_PG (broadcast to all groups), disable all
+scom 0x800D25E002011E3F {
+    bits, scom_data,          expr;
+    0:63, 0x000000000000FFFF, (mcr_enabled);
+}
+
+#-- IOMC1 TX_CLK_MODE_PG (broadcast to all groups), set TX_CLK_PDWN
+scom 0x800C05E002011E3F {
+    bits, scom_data,          expr;
+    0:63, 0x0000000000008000, (mcr_enabled);
+}
+
+#-- IOMC1 RX_FENCE_PG (broadcast to all groups), set RX_FENCE
+scom 0x8009A9E002011E3F {
+    bits, scom_data,          expr;
+    0:63, 0x0000000000008000, (mcr_enabled);
+}
 
 
 #-- XBUS IO (EI4)
@@ -158,6 +364,223 @@ scom 0x04011C03 {
     0:63, 0xDFFFFFFFFFFFC000, ((xbus_enabled) && (is_venice));
 }
 
+#-- bus powerdown settings
+#-- X0 RX_MODE_PL (broadcast to all groups/lanes), set RX_LANE_PDWN
+scom 0x800001FF0401103F {
+    bits, scom_data,          expr;
+    0:63, 0x0000000000008000, ((xbus_enabled) && (is_venice));
+}
+
+#-- X0 TX_MODE_PL (broadcast to all groups/lanes), set TX_LANE_PDWN
+scom 0x800405FF0401103F {
+    bits, scom_data,          expr;
+    0:63, 0x0000000000008000, ((xbus_enabled) && (is_venice));
+}
+
+#-- X0 RX_LANE_DISABLED_VEC_0_15_PG (broadcast to all groups), disable all
+scom 0x800929E00401103F {
+    bits, scom_data,          expr;
+    0:63, 0x000000000000FFFF, ((xbus_enabled) && (is_venice));
+}
+
+#-- X0 RX_LANE_DISABLED_VEC_16_31_PG (broadcast to all groups), disable all
+scom 0x800931E00401103F {
+    bits, scom_data,          expr;
+    0:63, 0x000000000000FFFF, ((xbus_enabled) && (is_venice));
+}
+
+#-- X0 RX_CLK_MODE_PG (broadcast to all groups), set RX_CLK_PDWN
+scom 0x800801E00401103F {
+    bits, scom_data,          expr;
+    0:63, 0x0000000000008000, ((xbus_enabled) && (is_venice));
+}
+
+#-- X0 TX_LANE_DISABLED_VEC_0_15_PG (broadcast to all groups), disable all
+scom 0x800D1DE00401103F {
+    bits, scom_data,          expr;
+    0:63, 0x000000000000FFFF, ((xbus_enabled) && (is_venice));
+}
+
+#-- X0 TX_LANE_DISABLED_VEC_16_31_PG (broadcast to all groups), disable all
+scom 0x800D25E00401103F {
+    bits, scom_data,          expr;
+    0:63, 0x000000000000FFFF, ((xbus_enabled) && (is_venice));
+}
+
+#-- X0 TX_CLK_MODE_PG (broadcast to all groups), set TX_CLK_PDWN
+scom 0x800C05E00401103F {
+    bits, scom_data,          expr;
+    0:63, 0x0000000000008000, ((xbus_enabled) && (is_venice));
+}
+
+#-- X0 RX_FENCE_PG (broadcast to all groups), set RX_FENCE
+scom 0x8009A9E00401103F {
+    bits, scom_data,          expr;
+    0:63, 0x0000000000008000, ((xbus_enabled) && (is_venice));
+}
+
+#-- X1 RX_MODE_PL (broadcast to all groups/lanes), set RX_LANE_PDWN
+scom 0x800001FF0401143F {
+    bits, scom_data,          expr;
+    0:63, 0x0000000000008000, (xbus_enabled);
+}
+
+#-- X1 TX_MODE_PL (broadcast to all groups/lanes), set TX_LANE_PDWN
+scom 0x800405FF0401143F {
+    bits, scom_data,          expr;
+    0:63, 0x0000000000008000, (xbus_enabled);
+}
+
+#-- X1 RX_LANE_DISABLED_VEC_0_15_PG (broadcast to all groups), disable all
+scom 0x800929E00401143F {
+    bits, scom_data,          expr;
+    0:63, 0x000000000000FFFF, (xbus_enabled);
+}
+
+#-- X1 RX_LANE_DISABLED_VEC_16_31_PG (broadcast to all groups), disable all
+scom 0x800931E00401143F {
+    bits, scom_data,          expr;
+    0:63, 0x000000000000FFFF, (xbus_enabled);
+}
+
+#-- X1 RX_CLK_MODE_PG (broadcast to all groups), set RX_CLK_PDWN
+scom 0x800801E00401143F {
+    bits, scom_data,          expr;
+    0:63, 0x0000000000008000, (xbus_enabled);
+}
+
+#-- X1 TX_LANE_DISABLED_VEC_0_15_PG (broadcast to all groups), disable all
+scom 0x800D1DE00401143F {
+    bits, scom_data,          expr;
+    0:63, 0x000000000000FFFF, (xbus_enabled);
+}
+
+#-- X1 TX_LANE_DISABLED_VEC_16_31_PG (broadcast to all groups), disable all
+scom 0x800D25E00401143F {
+    bits, scom_data,          expr;
+    0:63, 0x000000000000FFFF, (xbus_enabled);
+}
+
+#-- X1 TX_CLK_MODE_PG (broadcast to all groups), set TX_CLK_PDWN
+scom 0x800C05E00401143F {
+    bits, scom_data,          expr;
+    0:63, 0x0000000000008000, (xbus_enabled);
+}
+
+#-- X1 RX_FENCE_PG (broadcast to all groups), set RX_FENCE
+scom 0x8009A9E00401143F {
+    bits, scom_data,          expr;
+    0:63, 0x0000000000008000, (xbus_enabled);
+}
+
+#-- X2 RX_MODE_PL (broadcast to all groups/lanes), set RX_LANE_PDWN
+scom 0x800001FF04011C3F {
+    bits, scom_data,          expr;
+    0:63, 0x0000000000008000, ((xbus_enabled) && (is_venice));
+}
+
+#-- X2 TX_MODE_PL (broadcast to all groups/lanes), set TX_LANE_PDWN
+scom 0x800405FF04011C3F {
+    bits, scom_data,          expr;
+    0:63, 0x0000000000008000, ((xbus_enabled) && (is_venice));
+}
+
+#-- X2 RX_LANE_DISABLED_VEC_0_15_PG (broadcast to all groups), disable all
+scom 0x800929E004011C3F {
+    bits, scom_data,          expr;
+    0:63, 0x000000000000FFFF, ((xbus_enabled) && (is_venice));
+}
+
+#-- X2 RX_LANE_DISABLED_VEC_16_31_PG (broadcast to all groups), disable all
+scom 0x800931E004011C3F {
+    bits, scom_data,          expr;
+    0:63, 0x000000000000FFFF, ((xbus_enabled) && (is_venice));
+}
+
+#-- X2 RX_CLK_MODE_PG (broadcast to all groups), set RX_CLK_PDWN
+scom 0x800801E004011C3F {
+    bits, scom_data,          expr;
+    0:63, 0x0000000000008000, ((xbus_enabled) && (is_venice));
+}
+
+#-- X2 TX_LANE_DISABLED_VEC_0_15_PG (broadcast to all groups), disable all
+scom 0x800D1DE004011C3F {
+    bits, scom_data,          expr;
+    0:63, 0x000000000000FFFF, ((xbus_enabled) && (is_venice));
+}
+
+#-- X2 TX_LANE_DISABLED_VEC_16_31_PG (broadcast to all groups), disable all
+scom 0x800D25E004011C3F {
+    bits, scom_data,          expr;
+    0:63, 0x000000000000FFFF, ((xbus_enabled) && (is_venice));
+}
+
+#-- X2 TX_CLK_MODE_PG (broadcast to all groups), set TX_CLK_PDWN
+scom 0x800C05E004011C3F {
+    bits, scom_data,          expr;
+    0:63, 0x0000000000008000, ((xbus_enabled) && (is_venice));
+}
+
+#-- X2 RX_FENCE_PG (broadcast to all groups), set RX_FENCE
+scom 0x8009A9E004011C3F {
+    bits, scom_data,          expr;
+    0:63, 0x0000000000008000, ((xbus_enabled) && (is_venice));
+}
+
+#-- X3 RX_MODE_PL (broadcast to all groups/lanes), set RX_LANE_PDWN
+scom 0x800001FF0401183F {
+    bits, scom_data,          expr;
+    0:63, 0x0000000000008000, ((xbus_enabled)  && (is_venice));
+}
+
+#-- X3 TX_MODE_PL (broadcast to all groups/lanes), set TX_LANE_PDWN
+scom 0x800405FF0401183F {
+    bits, scom_data,          expr;
+    0:63, 0x0000000000008000, ((xbus_enabled) && (is_venice));
+}
+
+#-- X3 RX_LANE_DISABLED_VEC_0_15_PG (broadcast to all groups), disable all
+scom 0x800929E00401183F {
+    bits, scom_data,          expr;
+    0:63, 0x000000000000FFFF, ((xbus_enabled) && (is_venice));
+}
+
+#-- X3 RX_LANE_DISABLED_VEC_16_31_PG (broadcast to all groups), disable all
+scom 0x800931E00401183F {
+    bits, scom_data,          expr;
+    0:63, 0x000000000000FFFF, ((xbus_enabled) && (is_venice));
+}
+
+#-- X3 RX_CLK_MODE_PG (broadcast to all groups), set RX_CLK_PDWN
+scom 0x800801E00401183F {
+    bits, scom_data,          expr;
+    0:63, 0x0000000000008000, ((xbus_enabled) && (is_venice));
+}
+
+#-- X3 TX_LANE_DISABLED_VEC_0_15_PG (broadcast to all groups), disable all
+scom 0x800D1DE00401183F {
+    bits, scom_data,          expr;
+    0:63, 0x000000000000FFFF, ((xbus_enabled) && (is_venice));
+}
+
+#-- X3 TX_LANE_DISABLED_VEC_16_31_PG (broadcast to all groups), disable all
+scom 0x800D25E00401183F {
+    bits, scom_data,          expr;
+    0:63, 0x000000000000FFFF, ((xbus_enabled) && (is_venice));
+}
+
+#-- X3 TX_CLK_MODE_PG (broadcast to all groups), set TX_CLK_PDWN
+scom 0x800C05E00401183F {
+    bits, scom_data,          expr;
+    0:63, 0x0000000000008000, ((xbus_enabled) && (is_venice));
+}
+
+#-- X3 RX_FENCE_PG (broadcast to all groups), set RX_FENCE
+scom 0x8009A9E00401183F {
+    bits, scom_data,          expr;
+    0:63, 0x0000000000008000, ((xbus_enabled) && (is_venice));
+}
+
 
 #-- XBUS PB (PBEN)
 #-- set base configuration for FIR, leaving link specific FIR bits *masked*
@@ -239,6 +662,97 @@ scom 0x08010C03 {
     0:63, 0xDFFFFFFFFFFFC000, (abus_enabled);
 }
 
+#-- ABUS bus initialization/powerdown settings
+#-- ABUS.TX_WRAP.TX0.TXCTL.TX_CTL_REGS.TX_ID1_PG
+scom 0x800C940008010C3F {
+    bits,  scom_data,         expr;
+    48:53, 0b000001,          (abus_enabled);
+}
+
+#-- ABUS.RX0.RXCTL.RX_CTL_REGS.RX_ID1_PG
+scom 0x8008500008010C3F {
+    bits,  scom_data,         expr;
+    48:53, 0b000001,          (abus_enabled);
+}
+
+#-- ABUS.TX_WRAP.TX1.TXCTL.TX_CTL_REGS.TX_ID1_PG
+scom 0x800C942008010C3F {
+    bits,  scom_data,         expr;
+    48:53, 0b000010,          (abus_enabled);
+}
+
+#-- ABUS.RX1.RXCTL.RX_CTL_REGS.RX_ID1_PG
+scom 0x8008502008010C3F {
+    bits,  scom_data,         expr;
+    48:53, 0b000010,          (abus_enabled);
+}
+
+#-- ABUS.TX_WRAP.TX2.TXCTL.TX_CTL_REGS.TX_ID1_PG
+scom 0x800C944008010C3F {
+    bits,  scom_data,         expr;
+    48:53, 0b000011,          (abus_enabled);
+}
+
+#-- ABUS.RX2.RXCTL.RX_CTL_REGS.RX_ID1_PG
+scom 0x8008504008010C3F {
+    bits,  scom_data,         expr;
+    48:53, 0b000011,          (abus_enabled);
+}
+
+#-- ABUS RX_MODE_PL (broadcast to all groups/lanes), set RX_LANE_PDWN
+scom 0x800001FF08010C3F {
+    bits, scom_data,          expr;
+    0:63, 0x0000000000008000, (abus_enabled);
+}
+
+#-- ABUS TX_MODE_PL (broadcast to all groups/lanes), set TX_LANE_PDWN
+scom 0x800405FF08010C3F {
+    bits, scom_data,          expr;
+    0:63, 0x0000000000008000, (abus_enabled);
+}
+
+#-- ABUS RX_LANE_DISABLED_VEC_0_15_PG (broadcast to all groups), disable all
+scom 0x800929E008010C3F {
+    bits, scom_data,          expr;
+    0:63, 0x000000000000FFFF, (abus_enabled);
+}
+
+#-- ABUS RX_LANE_DISABLED_VEC_16_31_PG (broadcast to all groups), disable all
+scom 0x800931E008010C3F {
+    bits, scom_data,          expr;
+    0:63, 0x000000000000FFFF, (abus_enabled);
+}
+
+#-- ABUS RX_CLK_MODE_PG (broadcast to all groups), set RX_CLK_PDWN
+scom 0x800801E008010C3F {
+    bits, scom_data,          expr;
+    0:63, 0x0000000000008000, (abus_enabled);
+}
+
+#-- ABUS TX_LANE_DISABLED_VEC_0_15_PG (broadcast to all groups), disable all
+scom 0x800D1DE008010C3F {
+    bits, scom_data,          expr;
+    0:63, 0x000000000000FFFF, (abus_enabled);
+}
+
+#-- ABUS TX_LANE_DISABLED_VEC_16_31_PG (broadcast to all groups), disable all
+scom 0x800D25E008010C3F {
+    bits, scom_data,          expr;
+    0:63, 0x000000000000FFFF, (abus_enabled);
+}
+
+#-- ABUS TX_CLK_MODE_PG (broadcast to all groups), set TX_CLK_PDWN
+scom 0x800C05E008010C3F {
+    bits, scom_data,          expr;
+    0:63, 0x0000000000008000, (abus_enabled);
+}
+
+#-- ABUS RX_FENCE_PG (broadcast to all groups), set RX_FENCE
+scom 0x8009A9E008010C3F {
+    bits, scom_data,          expr;
+    0:63, 0x0000000000008000, (abus_enabled);
+}
+
 #-- ABUS PB (PBES)
 #-- set base configuration for FIR, leaving link specific FIR bits *masked*
 #-- (will be unmasked by iovalid procedure)
diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_abus_scominit.C b/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_abus_scominit.C
index 40d33f57f..85eebafab 100644
--- a/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_abus_scominit.C
+++ b/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_abus_scominit.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* IBM CONFIDENTIAL                                                       */
 /*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2013                   */
+/* COPYRIGHT International Business Machines Corp. 2013,2014              */
 /*                                                                        */
 /* p1                                                                     */
 /*                                                                        */
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_abus_scominit.C,v 1.5 2013/11/09 18:37:40 jmcgill Exp $
+// $Id: proc_abus_scominit.C,v 1.6 2014/03/12 18:56:56 jmcgill Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_abus_scominit.C,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2012
@@ -39,6 +39,7 @@
 //------------------------------------------------------------------------------
 //  Version     Date        Owner       Description
 //------------------------------------------------------------------------------
+//    1.6       03/10/14    jmcgill     Add endpoint power up
 //    1.5       11/08/13    jmcgill     Updates for RAS review
 //    1.4       02/18/13    thomsen     Changed targeting to use Abus_chiplet,
 //                                      chip, connected_Abus_chiplet &
@@ -56,6 +57,16 @@
 //------------------------------------------------------------------------------
 #include <fapiHwpExecInitFile.H>
 #include <proc_abus_scominit.H>
+#include <p8_scom_addresses.H>
+
+//------------------------------------------------------------------------------
+//  Constant definitions
+//------------------------------------------------------------------------------
+
+// map ABUS chiplet ID -> associated bus IORESET bit in ABUS SCOM_MODE_PB
+// register
+const uint8_t ABUS_SCOM_MODE_PB_IORESET_BIT[3] = { 2,3,4 };
+
 
 extern "C" {
 
@@ -68,10 +79,15 @@ fapi::ReturnCode proc_abus_scominit(const fapi::Target & i_abus_target,
                                     const fapi::Target & i_connected_abus_target)
 {
     fapi::ReturnCode rc;
+    uint32_t rc_ecmd = 0x0;
+
     std::vector<fapi::Target> targets;
     fapi::Target this_pu_target;
     fapi::Target connected_pu_target;
     uint8_t abus_enable_attr;
+    uint8_t abus_pos;
+
+    ecmdDataBufferBase data(64);
 
     // mark HWP entry
     FAPI_INF("proc_abus_scominit: Start");
@@ -125,6 +141,43 @@ fapi::ReturnCode proc_abus_scominit(const fapi::Target & i_abus_target,
                 break;
             }
 
+            // assert IO reset to power-up bus endpoint logic
+            rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_abus_target, abus_pos);
+            if (!rc.ok())
+            {
+                FAPI_ERR("proc_abus_scominit: Error from FAPI_ATTR_GET (ATTR_CHIP_UNIT_POS) on %s",
+                         i_abus_target.toEcmdString());
+                break;
+            }
+
+            // read-modify-write, set single reset bit (HW auto-clears)
+            // on writeback
+            rc = fapiGetScom(i_abus_target, A_ABUS_SCOM_MODE_PB_0x08010C20, data);
+            if (!rc.ok())
+            {
+                FAPI_ERR("proc_abus_scominit: Error from fapiGetScom (A_ABUS_SCOM_MODE_PB_0x08010C20) on %s",
+                         i_abus_target.toEcmdString());
+                break;
+            }
+
+            rc_ecmd |= data.setBit(ABUS_SCOM_MODE_PB_IORESET_BIT[abus_pos]);
+            if (rc_ecmd)
+            {
+                FAPI_ERR("proc_abus_scominit: Error 0x%x forming ABUS SCOM Mode PB register data buffer on %s",
+                         rc_ecmd, i_abus_target.toEcmdString());
+                rc.setEcmdError(rc_ecmd);
+                break;
+            }
+
+            rc = fapiPutScom(i_abus_target, A_ABUS_SCOM_MODE_PB_0x08010C20, data);
+            if (!rc.ok())
+            {
+                FAPI_ERR("proc_abus_scominit: Error from fapiPutScom (A_ABUS_SCOM_MODE_PB_0x08010C20) on %s",
+                         i_abus_target.toEcmdString());
+                break;
+            }
+
+
             // Call BASE ABUS SCOMINIT
             FAPI_INF("proc_abus_scominit: fapiHwpExecInitfile executing %s on %s, %s, %s, %s",
                 ABUS_BASE_IF,
diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_xbus_scominit.C b/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_xbus_scominit.C
index 11ba8fada..4ea17fd9b 100644
--- a/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_xbus_scominit.C
+++ b/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_xbus_scominit.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* IBM CONFIDENTIAL                                                       */
 /*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2013                   */
+/* COPYRIGHT International Business Machines Corp. 2013,2014              */
 /*                                                                        */
 /* p1                                                                     */
 /*                                                                        */
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_xbus_scominit.C,v 1.5 2013/11/09 18:37:40 jmcgill Exp $
+// $Id: proc_xbus_scominit.C,v 1.6 2014/03/12 18:56:56 jmcgill Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_xbus_scominit.C,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2012
@@ -39,6 +39,7 @@
 //------------------------------------------------------------------------------
 //  Version     Date        Owner       Description
 //------------------------------------------------------------------------------
+//    1.6       03/10/14    jmcgill     Add endpoint power up
 //    1.5       11/08/13    jmcgill     Updates for RAS review
 //    1.4       02/06/13    thomsen     Changed order of targets expected by
 //                                      initfile
@@ -62,6 +63,7 @@
 //------------------------------------------------------------------------------
 #include <fapiHwpExecInitFile.H>
 #include <proc_xbus_scominit.H>
+#include <p8_scom_addresses.H>
 
 extern "C" {
 
@@ -74,11 +76,15 @@ fapi::ReturnCode proc_xbus_scominit(const fapi::Target & i_xbus_target,
                                     const fapi::Target & i_connected_xbus_target)
 {
     fapi::ReturnCode rc;
+    uint32_t rc_ecmd = 0x0;
+
     std::vector<fapi::Target> targets;
     fapi::Target this_pu_target;
     fapi::Target connected_pu_target;
     uint8_t xbus_enable_attr;
 
+    ecmdDataBufferBase data(64);
+
     // mark HWP entry
     FAPI_INF("proc_xbus_scominit: Start");
 
@@ -131,6 +137,35 @@ fapi::ReturnCode proc_xbus_scominit(const fapi::Target & i_xbus_target,
                 break;
             }
 
+            // assert IO reset to power-up bus endpoint logic
+            // read-modify-write, set single reset bit (HW auto-clears)
+            // on writeback
+            rc = fapiGetScom(i_xbus_target, X_XBUS_SCOM_MODE_PB_0x04011020, data);
+            if (!rc.ok())
+            {
+                FAPI_ERR("proc_xbus_scominit: Error from fapiGetScom (X_XBUS_SCOM_MODE_PB_0x04011020) on %s",
+                         i_xbus_target.toEcmdString());
+                break;
+            }
+
+            rc_ecmd |= data.setBit(2,5);
+            if (rc_ecmd)
+            {
+                FAPI_ERR("proc_xbus_scominit: Error 0x%x forming XBUS SCOM Mode PB register data buffer on %s",
+                         rc_ecmd, i_xbus_target.toEcmdString());
+                rc.setEcmdError(rc_ecmd);
+                break;
+            }
+
+            rc = fapiPutScom(i_xbus_target, X_XBUS_SCOM_MODE_PB_0x04011020, data);
+            if (!rc.ok())
+            {
+                FAPI_ERR("proc_xbus_scominit: Error from fapiPutScom (X_XBUS_SCOM_MODE_PB_0x04011020) on %s",
+                         i_xbus_target.toEcmdString());
+                break;
+            }
+
+
             // Call BASE XBUS SCOMINIT
             FAPI_INF("proc_xbus_scominit: fapiHwpExecInitfile executing %s on %s, %s, %s, %s",
                 XBUS_BASE_IF,