SW262033: INITPROC: remove redundant write to ATTR_MSS_INIT_STATE in proc_cen_fr

CQ:SW262033
Change-Id: I1b215d0d1fd37f6cdd7123d79f5d95db5d341c13
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/11204
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Tested-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/11205
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

4 files changed, 85 insertions, 25 deletions

diff --git a/src/usr/hwpf/hwp/bus_training/io_cleanup.C b/src/usr/hwpf/hwp/bus_training/io_cleanup.C
index 38719d7fc..34713ad90 100644
--- a/src/usr/hwpf/hwp/bus_training/io_cleanup.C
+++ b/src/usr/hwpf/hwp/bus_training/io_cleanup.C
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: io_cleanup.C,v 1.8 2014/04/09 16:23:51 varkeykv Exp $
+// $Id: io_cleanup.C,v 1.13 2014/05/16 18:23:37 dcrowell Exp $
 // *!***************************************************************************
 // *! (C) Copyright International Business Machines Corp. 1997, 1998
 // *!           All Rights Reserved -- Property of IBM
@@ -216,6 +216,61 @@ ReturnCode do_cleanup(const Target &master_target,io_interface_t master_interfac
                    scom_mode_pb_reg_addr[FIR_CEN_DMI]);
           return rc;
      }
+     ///////////////////////////////SW256413//////////////////////////////
+     ecmdDataBufferBase rx_set_bits(16);
+     ecmdDataBufferBase tx_set_bits(16);
+     ecmdDataBufferBase mask_bits(  16);
+
+     rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &master_target, chip_unit);
+     if (!rc.ok()){
+        FAPI_ERR("Error retreiving MCS chiplet number, while setting bus id.");
+        return rc;
+     }
+     mask_bits.flushTo0();
+     uint32_t rxbits = 0;
+     uint32_t txbits = 0;
+     // Tuleta has MCS4-7 corresponding to port DMI1
+     // Brazos has MCS0-7 corresponding to port DMI0 and DMI1
+     if(chip_unit == 0){
+        rxbits = 0x0000;    //bus_id: 0 group_id: 0
+        txbits = 0x0100;    //bus_id: 0 group_id: 32
+     }else if(chip_unit == 1){
+        rxbits = 0x0400;    //bus_id: 1 group_id: 0
+        txbits = 0x0500;    //bus_id: 1 group_id: 32
+     }else if(chip_unit == 2){
+        rxbits = 0x0800;    //bus_id: 2 group_id: 0
+        txbits = 0x0900;    //bus_id: 2 group_id: 32
+     }else if(chip_unit == 3){
+        rxbits = 0x0C00;    //bus_id: 3 group_id: 0
+        txbits = 0x0D00;    //bus_id: 3 group_id: 32
+     }else if(chip_unit == 4){
+        rxbits = 0x0000;    //bus_id: 0 group_id: 0
+        txbits = 0x0100;    //bus_id: 0 group_id: 32
+     }else if(chip_unit == 5){
+        rxbits = 0x0400;    //bus_id: 1 group_id: 0
+        txbits = 0x0500;    //bus_id: 1 group_id: 32
+     }else if(chip_unit == 6){
+        rxbits = 0x0800;    //bus_id: 2 group_id: 0
+        txbits = 0x0900;    //bus_id: 2 group_id: 32
+     }else if(chip_unit == 7){
+        rxbits = 0x0C00;    //bus_id: 3 group_id: 0
+        txbits = 0x0D00;    //bus_id: 3 group_id: 32
+     }else{      //If chip_unit is unkown, set return error
+        FAPI_ERR("Invalid io_cleanup HWP invocation . MCS chiplet number is unknown while setting the bus id.");
+        const fapi::Target & MASTER_TARGET = master_target;
+        FAPI_SET_HWP_ERROR(rc, IO_CLEANUP_INVALID_MCS_RC);
+        return rc;
+     }
+     rc_ecmd |= rx_set_bits.insertFromRight(rxbits, 0, 16);
+     rc_ecmd |= tx_set_bits.insertFromRight(txbits, 0, 16);
+     if(rc_ecmd)
+     {
+        rc.setEcmdError(rc_ecmd);
+        return(rc);
+     }
+     rc = GCR_write(master_target, master_interface, rx_id1_pg, master_group, 0, rx_set_bits, mask_bits,1,1);if (rc) {return(rc);}
+     rc = GCR_write(master_target, master_interface, tx_id1_pg, master_group, 0, tx_set_bits, mask_bits,1,1);if (rc) {return(rc);}
+     ///////////////////////////////SW256413//////////////////////////////
 
 
     // NOW We clear FIRS.. need to see if we need to do this or some other procedure will do this . Bellows/Irving to respond
diff --git a/src/usr/hwpf/hwp/bus_training/io_cleanup_errors.xml b/src/usr/hwpf/hwp/bus_training/io_cleanup_errors.xml
index 9899996d1..0cbc4100c 100755
--- a/src/usr/hwpf/hwp/bus_training/io_cleanup_errors.xml
+++ b/src/usr/hwpf/hwp/bus_training/io_cleanup_errors.xml
@@ -20,11 +20,11 @@
 <!-- Origin: 30                                                             -->
 <!--                                                                        -->
 <!-- IBM_PROLOG_END_TAG                                                     -->
-<!-- $Id: io_cleanup_errors.xml,v 1.3 2014/03/19 18:05:51 smcprek Exp $ -->
+<!-- $Id: io_cleanup_errors.xml,v 1.5 2014/05/16 18:33:48 dcrowell Exp $ -->
 <hwpErrors>
   <hwpError>
     <rc>IO_CLEANUP_INVALID_INVOCATION_RC</rc>
-    <description>io run training invoked with wrong pair of targets</description>
+    <description>io_cleanup invoked with wrong pair of targets</description>
     <ffdc>MASTER_TARGET</ffdc>
     <ffdc>SLAVE_TARGET</ffdc>
     <callout>
@@ -32,4 +32,15 @@
       <priority>HIGH</priority>
     </callout>
   </hwpError>
+
+  <hwpError>
+    <rc>IO_CLEANUP_INVALID_MCS_RC</rc>
+    <description>io_cleanup invoked with invalid mcs target</description>
+    <ffdc>MASTER_TARGET</ffdc>
+    <ffdc>chip_unit</ffdc>
+    <callout>
+      <procedure>CODE</procedure>
+      <priority>HIGH</priority>
+    </callout>
+  </hwpError>
 </hwpErrors>
diff --git a/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/proc_cen_framelock.C b/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/proc_cen_framelock.C
index 546ce4641..17a46b39d 100644
--- a/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/proc_cen_framelock.C
+++ b/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/proc_cen_framelock.C
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-/// $Id: proc_cen_framelock.C,v 1.25 2014/04/11 18:15:42 baysah Exp $
+/// $Id: proc_cen_framelock.C,v 1.26 2014/05/16 01:14:16 jmcgill Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_cen_framelock.C,v $
 //------------------------------------------------------------------------------
 // *|
@@ -2200,12 +2200,6 @@ fapi::ReturnCode proc_cen_framelock_cloned(const fapi::Target& i_pu_target,
         return l_rc;
     }
 
-      // set the init state attribute to DMI_ACTIVE
-    uint8_t l_attr_mss_init_state;
-    l_attr_mss_init_state=ENUM_ATTR_MSS_INIT_STATE_DMI_ACTIVE;
-    l_rc = FAPI_ATTR_SET(ATTR_MSS_INIT_STATE, &i_mem_target, l_attr_mss_init_state);
-    if(l_rc) return l_rc;
-
     // mark HWP exit
     FAPI_IMP("proc_cen_framelock: Exiting ...");
     return l_rc;
diff --git a/src/usr/hwpf/hwp/initfiles/p8.nx.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.nx.scom.initfile
index 76cb7451b..0cb1f91f9 100644
--- a/src/usr/hwpf/hwp/initfiles/p8.nx.scom.initfile
+++ b/src/usr/hwpf/hwp/initfiles/p8.nx.scom.initfile
@@ -1,4 +1,4 @@
-#-- $Id: p8.nx.scom.initfile,v 1.11 2014/04/02 14:42:26 johnre Exp $
+#-- $Id: p8.nx.scom.initfile,v 1.13 2014/05/16 02:56:33 jmcgill Exp $
 #-------------------------------------------------------------------------------
 #--
 #-- (C) Copyright International Business Machines Corp. 2011
@@ -170,7 +170,7 @@ scom 0x02013086 {
      9    ,   0b0           ;   #-- 0b00      PowerBus write address error
     10    ,   0b0           ;   #-- 0b01      PowerBus miscellaneous error
     11    ,   0b0           ;   #-- 0b01      MMIO BAR parity error
-    12    ,   0b0           ;   #-- 0b00*     CRB kill ISN received while holding ISN with UE error
+    12    ,   0b1           ;   #-- 0b11      CRB kill ISN received while holding ISN with UE error
     13    ,   0b0           ;   #-- 0b01      ACK_DEAD cresp received by read command
     14    ,   0b0           ;   #-- 0b01      ACK_DEAD cresp received by write command
     15    ,   0b0           ;   #-- 0b01      Link check aborted while waiting on data
@@ -193,7 +193,7 @@ scom 0x02013087 {
      9    ,   0b0           ;   #-- 0b00      PowerBus write address error
     10    ,   0b1           ;   #-- 0b01      PowerBus miscellaneous error
     11    ,   0b1           ;   #-- 0b01      MMIO BAR parity error
-    12    ,   0b0           ;   #-- 0b00*     CRB kill ISN received while holding ISN with UE error
+    12    ,   0b1           ;   #-- 0b11      CRB kill ISN received while holding ISN with UE error
     13    ,   0b1           ;   #-- 0b01      ACK_DEAD cresp received by read command
     14    ,   0b1           ;   #-- 0b01      ACK_DEAD cresp received by write command
     15    ,   0b1           ;   #-- 0b01      Link check aborted while waiting on data
@@ -238,7 +238,7 @@ scom 0x02013083 {
 scom 0x02013106 {
     bits  ,  scom_data      ;   #--Action
      0    ,  0b0            ;   #-- 0b00 mask Reserved
-     1    ,  0b0            ;   #-- 0b00*     ICS invalid state error FIR bit
+     1    ,  0b1            ;   #-- 0b11      ICS invalid state error FIR bit
      2:3  ,  0b00           ;   #-- 0b00 mask Reserved
      4    ,  0b0            ;   #-- 0b01      Channel 0 842 array corrected ECC error FIR bit" ;
      5    ,  0b0            ;   #-- 0b01      Channel 0 842 array uncorrectable ECC error FIR bit" ;
@@ -249,15 +249,15 @@ scom 0x02013106 {
     10    ,  0b0            ;   #-- 0b01      DMA outbound write/inbound read correctable ECC error FIR bit" ;
     11:13 ,  0b000          ;   #-- 0b01      Channel 5,6,7 AMF array corrected ECC error FIR bit" ;
     14    ,  0b0            ;   #-- 0b00 mask Error from other SCOM satellites FIR bit" ;
-    15    ,  0b0            ;   #-- 0b00*     DMA invalid state error FIR bit.  Unrecoverable despite name" ;
-    16    ,  0b0            ;   #-- 0b00*     DMA invalid state error FIR bit" ;
+    15    ,  0b1            ;   #-- 0b11      DMA invalid state error FIR bit.  Unrecoverable despite name" ;
+    16    ,  0b1            ;   #-- 0b11      DMA invalid state error FIR bit" ;
     17    ,  0b0            ;   #-- 0b01      DMA array uncorrectable ECC error FIR bit" ;
     18    ,  0b0            ;   #-- 0b01      DMA outbound write/inbound read uncorrectable ECC error FIR bit" ;
     19    ,  0b0            ;   #-- 0b01      DMA inbound read error FIR bit" ;
-    20:27 ,  0b00000000     ;   #-- 0b00*     Channel 0-7 invalid state error FIR bit" ;
+    20:27 ,  0b11111111     ;   #-- 0b11      Channel 0-7 invalid state error FIR bit" ;
     28:30 ,  0b000          ;   #-- 0b01      Channel 5,6,7 AMF array uncorrectable ECC error FIR bit" ;
-    31    ,  0b0            ;   #-- 0b00*     UE error on CRB(CSB address, CCB) FIR bit" ;
-    32    ,  0b0            ;   #-- 0b00*     SUE error on CRB(CSB address, CCB) FIR bit" ;
+    31    ,  0b1            ;   #-- 0b11      UE error on CRB(CSB address, CCB) FIR bit" ;
+    32    ,  0b1            ;   #-- 0b11      SUE error on CRB(CSB address, CCB) FIR bit" ;
     33    ,  0b0            ;   #-- 0b00 mask SUE error on something other than CRB(CSB address, CCB) FIR bit" ;
     34    ,  0b0            ;   #-- 0b00 mask Reserved
     35    ,  0b0            ;   #-- 0b00 mask Reserved
@@ -270,7 +270,7 @@ scom 0x02013106 {
 scom 0x02013107 {
     bits  ,  scom_data      ;   #--Action
      0    ,  0b0            ;   #-- 0b00 mask Reserved
-     1    ,  0b0            ;   #-- 0b00*     ICS invalid state error FIR bit
+     1    ,  0b1            ;   #-- 0b11      ICS invalid state error FIR bit
      2:3  ,  0b00           ;   #-- 0b00 mask Reserved
      4    ,  0b1            ;   #-- 0b01      Channel 0 842 array corrected ECC error FIR bit" ;
      5    ,  0b1            ;   #-- 0b01      Channel 0 842 array uncorrectable ECC error FIR bit" ;
@@ -281,15 +281,15 @@ scom 0x02013107 {
     10    ,  0b1            ;   #-- 0b01      DMA outbound write/inbound read correctable ECC error FIR bit" ;
     11:13 ,  0b111          ;   #-- 0b01      Channel 5,6,7 AMF array corrected ECC error FIR bit" ;
     14    ,  0b0            ;   #-- 0b00 mask Error from other SCOM satellites FIR bit" ;
-    15    ,  0b0            ;   #-- 0b00*     DMA invalid state error FIR bit.  Unrecoverable despite name" ;
-    16    ,  0b0            ;   #-- 0b00*     DMA invalid state error FIR bit" ;
+    15    ,  0b1            ;   #-- 0b11      DMA invalid state error FIR bit.  Unrecoverable despite name" ;
+    16    ,  0b1            ;   #-- 0b11      DMA invalid state error FIR bit" ;
     17    ,  0b1            ;   #-- 0b01      DMA array uncorrectable ECC error FIR bit" ;
     18    ,  0b1            ;   #-- 0b01      DMA outbound write/inbound read uncorrectable ECC error FIR bit" ;
     19    ,  0b1            ;   #-- 0b01      DMA inbound read error FIR bit" ;
-    20:27 ,  0b00000000     ;   #-- 0b00*     Channel 0-7 invalid state error FIR bit" ;
+    20:27 ,  0b11111111     ;   #-- 0b11      Channel 0-7 invalid state error FIR bit" ;
     28:30 ,  0b111          ;   #-- 0b01      Channel 5,6,7 AMF array uncorrectable ECC error FIR bit" ;
-    31    ,  0b0            ;   #-- 0b00*     UE error on CRB(CSB address, CCB) FIR bit" ;
-    32    ,  0b0            ;   #-- 0b00*     SUE error on CRB(CSB address, CCB) FIR bit" ;
+    31    ,  0b1            ;   #-- 0b11      UE error on CRB(CSB address, CCB) FIR bit" ;
+    32    ,  0b1            ;   #-- 0b11      SUE error on CRB(CSB address, CCB) FIR bit" ;
     33    ,  0b0            ;   #-- 0b00 mask SUE error on something other than CRB(CSB address, CCB) FIR bit" ;
     34    ,  0b0            ;   #-- 0b00 mask Reserved
     35    ,  0b0            ;   #-- 0b00 mask Reserved