Oscillator Init Code updates

Add supports for ATTR_OSCSWITCH_CTL0,1,2 and ATTR_REDUNDANT_CLOCKS

Change-Id: I06872a90b77f1de242bce71381db99d0650f57d2
CQ: SW241624
RTC: 107923
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/11214
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

6 files changed, 602 insertions, 316 deletions

diff --git a/src/usr/hwpf/hwp/chip_accessors/chip.mk b/src/usr/hwpf/hwp/chip_accessors/chip.mk
index c0d03819b..8bca9427c 100644
--- a/src/usr/hwpf/hwp/chip_accessors/chip.mk
+++ b/src/usr/hwpf/hwp/chip_accessors/chip.mk
@@ -26,4 +26,5 @@ EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/hwp/chip_accessors
 VPATH += ${HWPPATH}/chip_accessors
 
 OBJS += getPciOscswitchConfig.o
+OBJS += getOscswitchCtlAttr.o
 
diff --git a/src/usr/hwpf/hwp/chip_accessors/chip_errors.xml b/src/usr/hwpf/hwp/chip_accessors/chip_errors.xml
index 5a99fd16b..8781e536b 100644
--- a/src/usr/hwpf/hwp/chip_accessors/chip_errors.xml
+++ b/src/usr/hwpf/hwp/chip_accessors/chip_errors.xml
@@ -21,7 +21,7 @@
 <!--                                                                        -->
 <!-- IBM_PROLOG_END_TAG                                                     -->
 <!-- XML file specifying errors generated by chip HWPs. -->
-<!-- $Id: chip_errors.xml,v 1.2 2014/01/15 20:05:04 whs Exp $ -->
+<!-- $Id: chip_errors.xml,v 1.3 2014/05/23 01:07:27 whs Exp $ -->
 <hwpErrors>
   <!-- ******************************************************************** -->
   <hwpError>
@@ -60,4 +60,42 @@
     <ffdc>FFDC_CHIP_EC</ffdc>
   </hwpError>
   <!-- ******************************************************************** -->
+  <hwpError>
+    <rc>RC_OSC_SWITCH_CTL_UNEXPECTED_CHIP_TYPE</rc>
+    <description>
+        No entry in oscswitch ctl date for this chip type
+    </description>
+    <callout>
+        <procedure>CODE</procedure>
+        <priority>HIGH</priority>
+    </callout>
+    <ffdc>FFDC_CHIP_TYPE</ffdc>
+  </hwpError>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <rc>RC_OSC_SWITCH_CTL_UNEXPECTED_ATTR</rc>
+    <description>
+        Attribute request out of expected range.
+    </description>
+    <callout>
+        <procedure>CODE</procedure>
+        <priority>HIGH</priority>
+    </callout>
+    <ffdc>FFDC_UNEXPECTED_ATTR</ffdc>
+  </hwpError>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <rc>RC_OSC_SWITCH_CTL_INVALID_ATTR_SIZE</rc>
+    <description>
+        Oscswitch ctl attribute size passed does not match type of data to return
+    </description>
+    <callout>
+        <procedure>CODE</procedure>
+        <priority>HIGH</priority>
+    </callout>
+    <ffdc>FFDC_ATTR</ffdc>
+    <ffdc>FFDC_EXPECTED_SIZE</ffdc>
+    <ffdc>FFDC_PASSED_SIZE</ffdc>
+  </hwpError>
+  <!-- ******************************************************************** -->
 </hwpErrors>
diff --git a/src/usr/hwpf/hwp/chip_accessors/getOscswitchCtlAttr.C b/src/usr/hwpf/hwp/chip_accessors/getOscswitchCtlAttr.C
new file mode 100644
index 000000000..8ba0d9f93
--- /dev/null
+++ b/src/usr/hwpf/hwp/chip_accessors/getOscswitchCtlAttr.C
@@ -0,0 +1,190 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/usr/hwpf/hwp/chip_accessors/getOscswitchCtlAttr.C $       */
+/*                                                                        */
+/* OpenPOWER HostBoot Project                                             */
+/*                                                                        */
+/* COPYRIGHT International Business Machines Corp. 2012,2014              */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id: getOscswitchCtlAttr.C,v 1.1 2014/05/23 01:19:13 whs Exp $
+/**
+ *  @file getOscswitchCtlAttr.C
+ *
+ *  @brief Accessor for providing the ATTR_OSCSWITCH_CTLx attributes
+ *
+ */
+
+#include    <stdint.h>
+
+//  fapi support
+#include    <fapi.H>
+#include    <fapiUtil.H>
+#include    <getOscswitchCtlAttr.H>
+
+extern "C"
+{
+using   namespace   fapi;
+
+fapi::ReturnCode getOscswitchSizeCheck(
+                                  const fapi::getOscswitchCtl::Attr i_attr,
+                                  const size_t i_fieldSize,
+                                  const size_t i_len);
+
+// ----------------------------------------------------------------------------
+// HWP accessor for providing ATTR_OSCSWITCH_CTLx attributes
+// ----------------------------------------------------------------------------
+fapi::ReturnCode getOscswitchCtlAttr( const fapi::Target & i_pProcTarget,
+                                  const fapi::getOscswitchCtl::Attr i_attr,
+                                  void * o_pVal,
+                                  const size_t i_len)
+{
+    fapi::ReturnCode l_fapirc;
+
+    FAPI_DBG("getOscswitchCtlAttr: entry ");
+
+    do {
+        // see if platform has redundant clocks
+        uint8_t  l_redundantClocks = 0;
+        l_fapirc = FAPI_ATTR_GET(ATTR_REDUNDANT_CLOCKS,
+                                          NULL,
+                                          l_redundantClocks);
+        if (l_fapirc)
+        {
+             FAPI_ERR("getOscswitchCtlAttr:FAPI_ATTR_GET(ATTR_REDUNDANT_CLOCKS)"
+                     " failed w/rc=0x%08x",
+                     static_cast<uint32_t>(l_fapirc) );
+            break; // break out with error
+        }
+
+        // find the chip type if there are redundant clocks, otherwise use
+        // the ENUM_ATTR_NAME_NONE entry for systems without redundant clocks
+        fapi::ATTR_NAME_Type    l_chipType = ENUM_ATTR_NAME_NONE ;
+        if (l_redundantClocks)
+        {
+            // Get chip type
+            l_fapirc = FAPI_ATTR_GET_PRIVILEGED(ATTR_NAME,
+                                          &i_pProcTarget,
+                                          l_chipType);
+            if (l_fapirc)
+            {
+                 FAPI_ERR("getOscswitchCtlAttr:"
+                         " FAPI_ATTR_GET_PRIVILEGED(ATTR_NAME) "
+                         "failed w/rc=0x%08x",
+                         static_cast<uint32_t>(l_fapirc) );
+                break; // break out with error
+            }
+        }
+        FAPI_DBG("getOscswitchCtlAttr: Chip type=0x%02x",l_chipType);
+
+        // find entry in Oscswitch Ctl data table
+        const    getOscswitchCtl::OSCSWITCH_CTL_DATA * l_pOscswitchCtlData =
+                 reinterpret_cast<const getOscswitchCtl::OSCSWITCH_CTL_DATA *>
+                 (&getOscswitchCtl::OSCSWITCH_CTL_DATA_array);
+        uint8_t l_data = 0;
+        uint8_t l_tableSize = sizeof(getOscswitchCtl::OSCSWITCH_CTL_DATA_array)/
+                               sizeof(getOscswitchCtl::OSCSWITCH_CTL_DATA);
+        for (l_data = 0; l_data<l_tableSize; l_data++)
+        {
+            if (l_pOscswitchCtlData[l_data].l_CHIP_TYPE == l_chipType)
+            {
+                break; //found match. Could add EC check here if ever needed
+            }
+        }
+        if (l_data >= l_tableSize) // did not find an entry
+        {
+            const uint32_t FFDC_CHIP_TYPE = l_chipType;
+            FAPI_SET_HWP_ERROR(l_fapirc,RC_OSC_SWITCH_CTL_UNEXPECTED_CHIP_TYPE);
+            break ; // break with error
+        }
+
+        // return requested attribute value
+        switch (i_attr)
+        {
+            case fapi::getOscswitchCtl::CTL0:
+            {
+                uint32_t * l_pCtl0 = (uint32_t *) o_pVal;
+                l_fapirc = getOscswitchSizeCheck(i_attr,
+                           sizeof (l_pOscswitchCtlData[l_data].l_CTL0),
+                           i_len);
+                if (l_fapirc)
+                {
+                    break; // break with error
+                }
+                *l_pCtl0 = l_pOscswitchCtlData[l_data].l_CTL0;
+                break;
+            }
+            case fapi::getOscswitchCtl::CTL1:
+            {
+                uint8_t * l_pCtl1 = (uint8_t *) o_pVal;
+                l_fapirc = getOscswitchSizeCheck(i_attr,
+                           sizeof (l_pOscswitchCtlData[l_data].l_CTL1),
+                           i_len);
+                if (l_fapirc)
+                {
+                    break; // break with error
+                }
+                *l_pCtl1 = l_pOscswitchCtlData[l_data].l_CTL1;
+                break;
+            }
+            case fapi::getOscswitchCtl::CTL2:
+            {
+                uint32_t * l_pCtl2 = (uint32_t *) o_pVal;
+                l_fapirc = getOscswitchSizeCheck(i_attr,
+                           sizeof (l_pOscswitchCtlData[l_data].l_CTL2),
+                           i_len);
+                if (l_fapirc)
+                {
+                    break; // break with error
+                }
+                *l_pCtl2 = l_pOscswitchCtlData[l_data].l_CTL2;
+                break;
+            }
+            default:
+            {
+                const uint8_t FFDC_UNEXPECTED_ATTR = i_attr;
+                FAPI_SET_HWP_ERROR(l_fapirc,RC_OSC_SWITCH_CTL_UNEXPECTED_ATTR);
+                break ; // break with error
+            }
+        }
+
+    } while (0);
+
+    FAPI_DBG("getOscswitchCtlAttr: exit rc=0x%08x)",
+               static_cast<uint32_t>(l_fapirc));
+
+    return  l_fapirc;
+}
+
+// check output field length
+fapi::ReturnCode getOscswitchSizeCheck(
+                                  const fapi::getOscswitchCtl::Attr i_attr,
+                                  const size_t i_fieldSize,
+                                  const size_t i_len)
+{
+    fapi::ReturnCode l_fapirc;
+    if (i_len != i_fieldSize)
+    {
+        const fapi::getOscswitchCtl::Attr FFDC_ATTR = i_attr;
+        const size_t  FFDC_EXPECTED_SIZE = i_fieldSize;
+        const size_t  FFDC_PASSED_SIZE = i_len;
+        FAPI_SET_HWP_ERROR(l_fapirc,RC_OSC_SWITCH_CTL_INVALID_ATTR_SIZE);
+    }
+    return  l_fapirc;
+}
+
+
+}   // extern "C"
diff --git a/src/usr/hwpf/hwp/chip_attributes.xml b/src/usr/hwpf/hwp/chip_attributes.xml
index 12b7e9ba5..dcf90b0c7 100644
--- a/src/usr/hwpf/hwp/chip_attributes.xml
+++ b/src/usr/hwpf/hwp/chip_attributes.xml
@@ -20,7 +20,7 @@
 <!-- permissions and limitations under the License.                         -->
 <!--                                                                        -->
 <!-- IBM_PROLOG_END_TAG                                                     -->
-<!-- $Id: chip_attributes.xml,v 1.12 2013/10/31 14:10:49 jmcgill Exp $ -->
+<!-- $Id: chip_attributes.xml,v 1.14 2014/05/02 14:43:31 szhong Exp $ -->
 <!--
     XML file specifying HWPF attributes.
     These are platInit attributes associated with chips.
@@ -47,7 +47,7 @@
         Provided by the Machine Readable Workbook
     </description>
     <valueType>uint8</valueType>
-    <enum>NONE = 0, VENICE = 1, MURANO = 2, CENTAUR = 3</enum>
+    <enum>NONE = 0, VENICE = 1, MURANO = 2, CENTAUR = 3, NAPLES = 4</enum>
     <platInit/>
     <!-- To make HWPs data driven, this is a privileged attribute that cannot
          be accessed by normal HWPs. -->
@@ -187,4 +187,34 @@
     <platInit/>
   </attribute>
   <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_OSCSWITCH_CTL0</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+        Defines oscswitch ctl0 value (FSI GP3 bits 0:15)
+    </description>
+    <valueType>uint32</valueType>
+    <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_OSCSWITCH_CTL1</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+        Defines oscswitch ctl1 value (FSI GP6 bits 20:27)
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_OSCSWITCH_CTL2</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+        Defines oscswitch ctl2 value (FSI GP7 bits 8:31)
+    </description>
+    <valueType>uint32</valueType>
+    <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
 </attributes>
diff --git a/src/usr/hwpf/hwp/system_attributes.xml b/src/usr/hwpf/hwp/system_attributes.xml
index 0a2d12285..55ef39567 100644
--- a/src/usr/hwpf/hwp/system_attributes.xml
+++ b/src/usr/hwpf/hwp/system_attributes.xml
@@ -20,327 +20,339 @@
 <!-- permissions and limitations under the License.                         -->
 <!--                                                                        -->
 <!-- IBM_PROLOG_END_TAG                                                     -->
+<!-- $Id: system_attributes.xml,v 1.22 2014/05/23 01:13:54 whs Exp $ -->
 
-<!-- $Id: system_attributes.xml,v 1.20 2014/03/10 11:42:10 whs Exp $ -->
 <!--
     XML file specifying HWPF attributes.
     These are platInit attributes associated with the system.
     These attributes are not associated with particular targets.
     Each execution platform must initialize.
-    -->
+-->
 
 <attributes>
-    <!-- ********************************************************************* -->
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_EXECUTION_PLATFORM</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>
+        Which execution platform the HW Procedure is running on
+        Some HWPs (e.g. special wakeup) use different registers for different
+          platforms to avoid arbitration problems when multiple platforms do
+          the same thing concurrently
+    </description>
+    <valueType>uint8</valueType>
+    <enum>HOST = 0x01, FSP = 0x02, OCC = 0x03</enum>
+    <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_IS_SIMULATION</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>env: 1 = Awan/HWSimulator. 0 = Simics/RealHW.</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_MNFG_FLAGS</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>
+        The manufacturing flags.
+        This is a bitfield. Each bit is a flag and multiple flags can be set
+    </description>
+    <valueType>uint64</valueType>
+    <enum>
+        MNFG_NO_FLAG                        = 0x0000000000000000,
+        MNFG_THRESHOLDS                     = 0x0000000000000001,
+        MNFG_AVP_ENABLE                     = 0x0000000000000002,
+        MNFG_HDAT_AVP_ENABLE                = 0x0000000000000004,
+        MNFG_SRC_TERM                       = 0x0000000000000008,
+        MNFG_IPL_MEMORY_CE_CHECKING         = 0x0000000000000010,
+        MNFG_FAST_BACKGROUND_SCRUB          = 0x0000000000000020,
+        MNFG_TEST_DRAM_REPAIRS              = 0x0000000000000040,
+        MNFG_DISABLE_DRAM_REPAIRS           = 0x0000000000000080,
+        MNFG_ENABLE_EXHAUSTIVE_PATTERN_TEST = 0x0000000000000100,
+        MNFG_ENABLE_STANDARD_PATTERN_TEST   = 0x0000000000000200,
+        MNFG_ENABLE_MINIMUM_PATTERN_TEST    = 0x0000000000000400,
+        MNFG_DISABLE_FABRIC_eREPAIR         = 0x0000000000000800,
+        MNFG_DISABLE_MEMORY_eREPAIR         = 0x0000000000001000,
+        MNFG_FABRIC_DEPLOY_LANE_SPARES      = 0x0000000000002000,
+        MNFG_DMI_DEPLOY_LANE_SPARES         = 0x0000000000004000,
+        MNFG_PSI_DIAGNOSTIC                 = 0x0000000000008000,
+        MNFG_BRAZOS_WRAP_CONFIG             = 0x0000000000010000
+    </enum>
+    <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_IS_MPIPL</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>1 = in Memory Preserving IPL mode. 0 = in normal IPL mode.</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <writeable/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PROC_EPS_TABLE_TYPE</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>
+      Processor epsilon table type. Used to calculate the processor nest
+      epsilon register values.
+      Provided by the Machine Readable Workbook.
+    </description>
+    <valueType>uint8</valueType>
+    <enum>EPS_TYPE_LE = 0x01, EPS_TYPE_HE = 0x02, EPS_TYPE_1S = 0x03</enum>
+    <platInit/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PROC_FABRIC_PUMP_MODE</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>
+      Processor SMP Fabric broadcast scope configuration.
+      MODE1 = default = chip/group/system/remote group/foreign.
+      MODE2 = group/system/remote group/foreign.
+      Provided by the Machine Readable Workbook.
+    </description>
+    <valueType>uint8</valueType>
+    <enum>MODE1 = 0x01, MODE2 = 0x02</enum>
+    <platInit/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PROC_X_BUS_WIDTH</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>
+      Processor SMP X bus width.
+      Provided by the Machine Readable Workbook.
+    </description>
+    <valueType>uint8</valueType>
+    <enum>W4BYTE = 0x01, W8BYTE = 0x02</enum>
+    <platInit/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_ALL_MCS_IN_INTERLEAVING_GROUP</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>
+      If all MCS chiplets are in an interleaving group (1=true, 0=false).
+      If true the SMP fabric is setup in normal mode.
+      If false the SMP fabric is setup in checkerboard mode.
+      Provided by the Machine Readable Workbook.
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_NEST_FREQ_MHZ</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>
+     Nest Freq for system in MHz
+    </description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <writeable/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_BOOT_FREQ_MHZ</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>Boot frequency in MHZ.</description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <writeable/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_EX_GARD_BITS</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>
+      Vector to communicate the guarded EX chiplets to SBE
+      One Guard bit per EX chiplet, bit location aligned to chiplet ID
+      (bit 16: EX00, bit 17: EX01, bit 18: EX02 ... bit 31: EX15)
+      Guarded EX chiplets are marked by a '1'.
+    </description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <writeable/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_DISABLE_I2C_ACCESS</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>
+      Set to skip physical access to i2c interface in SBE execution.
+      Consumed by SBE hooks to permit skipping of selected code when
+      running on a test platform (i.e., wafer) which does not have a physical
+      SEEPROM connected.
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PIB_I2C_REFCLOCK</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>
+      i2c reference clock for the system
+    </description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <writeable/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PIB_I2C_NEST_PLL</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>
+      i2c pll for the system
+    </description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <writeable/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_SBE_IMAGE_OFFSET</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>
+      HostBoot image for SBE, offset to account for ECC
+    </description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <writeable/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_BOOT_VOLTAGE</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>
+     Boot Voltage for system
+    </description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <writeable/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_RISK_LEVEL</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>
+        Defines risk level to consider for initialization values applied during IPL.
+        Risk level 0 should contain solutions for all known errata, and may sacrifice performance to avoid data integrity issue/error checking cases.
+        Risk level 100 may introduce data integrity/error scenarios to provide full performance or visibility to state space/coverage behind known issues.
+    </description>
+    <valueType>uint32</valueType>
+    <enum>
+        RL0 = 0x000,
+        RL100 = 0x100
+    </enum>
+    <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PROC_REFCLOCK_RCVR_TERM</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>
+        Defines system specific value of processor refclock receiver termination (FSI GP4 bits 8:9)
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PCI_REFCLOCK_RCVR_TERM</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>
+        Defines system specific value of PCI refclock receiver termination (FSI GP4 bits 10:11)
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_MEM_FILTER_PLL_SOURCE</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>
+        Defines source of MEM filter PLL input (FSI GP4 bit 23)
+    </description>
+    <valueType>uint8</valueType>
+    <enum>
+        PROC_REFCLK = 0x0,
+        PCI_REFCLK = 0x1
+    </enum>
+    <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_MULTI_SCOM_BUFFER_MAX_SIZE</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>
+      Defines maximum size of data buffer to allocate for optimal
+      performance with platform implementation of fapiMultiScom API.
+    </description>
+    <valueType>uint64</valueType>
+    <enum>
+        MULTI_SCOM_BUFFER_SIZE_1KB   = 0x0000000000000400,
+        MULTI_SCOM_BUFFER_SIZE_2KB   = 0x0000000000000800,
+        MULTI_SCOM_BUFFER_SIZE_4KB   = 0x0000000000001000,
+        MULTI_SCOM_BUFFER_SIZE_8KB   = 0x0000000000002000,
+        MULTI_SCOM_BUFFER_SIZE_16KB  = 0x0000000000004000,
+        MULTI_SCOM_BUFFER_SIZE_32KB  = 0x0000000000008000,
+        MULTI_SCOM_BUFFER_SIZE_64KB  = 0x0000000000010000,
+        MULTI_SCOM_BUFFER_SIZE_128KB = 0x0000000000020000,
+        MULTI_SCOM_BUFFER_SIZE_256KB = 0x0000000000040000,
+        MULTI_SCOM_BUFFER_SIZE_512KB = 0x0000000000080000,
+        MULTI_SCOM_BUFFER_SIZE_1MB   = 0x0000000000100000
+    </enum>
+    <platInit/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_RECONFIGURE_LOOP</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>
+        Used to inidicate if a reconfigure loop is needed
+    </description>
+    <valueType>uint8</valueType>
+    <enum>
+        DECONFIGURE      = 0x1,
+        BAD_DQ_BIT_SET   = 0x2
+    </enum>
+    <writeable/>
+  </attribute>
+  <!-- ********************************************************************* -->
     <attribute>
-        <id>ATTR_EXECUTION_PLATFORM</id>
-        <targetType>TARGET_TYPE_SYSTEM</targetType>
-        <description>
-            Which execution platform the HW Procedure is running on
-            Some HWPs (e.g. special wakeup) use different registers for different
-            platforms to avoid arbitration problems when multiple platforms do
-            the same thing concurrently
-        </description>
-        <valueType>uint8</valueType>
-        <enum>HOST = 0x01, FSP = 0x02, OCC = 0x03</enum>
-        <platInit/>
+      <id>ATTR_PM_HWP_ATTR_VERSION</id>
+      <targetType>TARGET_TYPE_SYSTEM</targetType>
+      <description>
+          Defines HWP version to be checked inside HWPs to determine if new
+          code should be loaded/skipped/modified/etc. Service pack versions
+          of the procedures may diverge from the working branch. Specific
+          values to be defined as needed in the service pack release stream.
+      </description>
+      <valueType>uint32</valueType>
+      <platInit/>
+      <writeable/>
     </attribute>
-    <!-- ********************************************************************* -->
-    <attribute>
-        <id>ATTR_IS_SIMULATION</id>
-        <targetType>TARGET_TYPE_SYSTEM</targetType>
-        <description>env: 1 = Awan/HWSimulator. 0 = Simics/RealHW.</description>
-        <valueType>uint8</valueType>
-        <platInit/>
-    </attribute>
-    <!-- ********************************************************************* -->
-    <attribute>
-        <id>ATTR_MNFG_FLAGS</id>
-        <targetType>TARGET_TYPE_SYSTEM</targetType>
-        <description>
-            The manufacturing flags.
-            This is a bitfield. Each bit is a flag and multiple flags can be set
-        </description>
-        <valueType>uint64</valueType>
-        <enum>
-            MNFG_NO_FLAG                        = 0x0000000000000000,
-            MNFG_THRESHOLDS                     = 0x0000000000000001,
-            MNFG_AVP_ENABLE                     = 0x0000000000000002,
-            MNFG_HDAT_AVP_ENABLE                = 0x0000000000000004,
-            MNFG_SRC_TERM                       = 0x0000000000000008,
-            MNFG_IPL_MEMORY_CE_CHECKING         = 0x0000000000000010,
-            MNFG_FAST_BACKGROUND_SCRUB          = 0x0000000000000020,
-            MNFG_TEST_DRAM_REPAIRS              = 0x0000000000000040,
-            MNFG_DISABLE_DRAM_REPAIRS           = 0x0000000000000080,
-            MNFG_ENABLE_EXHAUSTIVE_PATTERN_TEST = 0x0000000000000100,
-            MNFG_ENABLE_STANDARD_PATTERN_TEST   = 0x0000000000000200,
-            MNFG_ENABLE_MINIMUM_PATTERN_TEST    = 0x0000000000000400,
-            MNFG_DISABLE_FABRIC_eREPAIR         = 0x0000000000000800,
-            MNFG_DISABLE_MEMORY_eREPAIR         = 0x0000000000001000,
-            MNFG_FABRIC_DEPLOY_LANE_SPARES      = 0x0000000000002000,
-            MNFG_DMI_DEPLOY_LANE_SPARES         = 0x0000000000004000,
-            MNFG_PSI_DIAGNOSTIC                 = 0x0000000000008000,
-            MNFG_BRAZOS_WRAP_CONFIG             = 0x0000000000010000
-        </enum>
-        <platInit/>
-    </attribute>
-    <!-- ********************************************************************* -->
-    <attribute>
-        <id>ATTR_IS_MPIPL</id>
-        <targetType>TARGET_TYPE_SYSTEM</targetType>
-        <description>1 = in Memory Preserving IPL mode. 0 = in normal IPL mode.</description>
-        <valueType>uint8</valueType>
-        <platInit/>
-        <writeable/>
-    </attribute>
-    <!-- ********************************************************************* -->
-    <attribute>
-        <id>ATTR_PROC_EPS_TABLE_TYPE</id>
-        <targetType>TARGET_TYPE_SYSTEM</targetType>
-        <description>
-            Processor epsilon table type. Used to calculate the processor nest
-            epsilon register values.
-            Provided by the Machine Readable Workbook.
-        </description>
-        <valueType>uint8</valueType>
-        <enum>EPS_TYPE_LE = 0x01, EPS_TYPE_HE = 0x02, EPS_TYPE_1S = 0x03</enum>
-        <platInit/>
-        <persistRuntime/>
-    </attribute>
-    <!-- ********************************************************************* -->
-    <attribute>
-        <id>ATTR_PROC_FABRIC_PUMP_MODE</id>
-        <targetType>TARGET_TYPE_SYSTEM</targetType>
-        <description>
-            Processor SMP Fabric broadcast scope configuration.
-            MODE1 = default = chip/group/system/remote group/foreign.
-            MODE2 = group/system/remote group/foreign.
-            Provided by the Machine Readable Workbook.
-        </description>
-        <valueType>uint8</valueType>
-        <enum>MODE1 = 0x01, MODE2 = 0x02</enum>
-        <platInit/>
-        <persistRuntime/>
-    </attribute>
-    <!-- ********************************************************************* -->
-    <attribute>
-        <id>ATTR_PROC_X_BUS_WIDTH</id>
-        <targetType>TARGET_TYPE_SYSTEM</targetType>
-        <description>
-            Processor SMP X bus width.
-            Provided by the Machine Readable Workbook.
-        </description>
-        <valueType>uint8</valueType>
-        <enum>W4BYTE = 0x01, W8BYTE = 0x02</enum>
-        <platInit/>
-        <persistRuntime/>
-    </attribute>
-    <!-- ********************************************************************* -->
-    <attribute>
-        <id>ATTR_ALL_MCS_IN_INTERLEAVING_GROUP</id>
-        <targetType>TARGET_TYPE_SYSTEM</targetType>
-        <description>
-            If all MCS chiplets are in an interleaving group (1=true, 0=false).
-            If true the SMP fabric is setup in normal mode.
-            If false the SMP fabric is setup in checkerboard mode.
-            Provided by the Machine Readable Workbook.
-        </description>
-        <valueType>uint8</valueType>
-        <platInit/>
-        <persistRuntime/>
-    </attribute>
-    <!-- ********************************************************************* -->
-    <attribute>
-        <id>ATTR_NEST_FREQ_MHZ</id>
-        <targetType>TARGET_TYPE_SYSTEM</targetType>
-        <description>
-            Nest Freq for system in MHz
-        </description>
-        <valueType>uint32</valueType>
-        <platInit/>
-        <writeable/>
-    </attribute>
-    <!-- ********************************************************************* -->
-    <attribute>
-        <id>ATTR_BOOT_FREQ_MHZ</id>
-        <targetType>TARGET_TYPE_SYSTEM</targetType>
-        <description>Boot frequency in MHZ.</description>
-        <valueType>uint32</valueType>
-        <platInit/>
-        <writeable/>
-    </attribute>
-    <!-- ********************************************************************* -->
-    <attribute>
-        <id>ATTR_EX_GARD_BITS</id>
-        <targetType>TARGET_TYPE_SYSTEM</targetType>
-        <description>
-            Vector to communicate the guarded EX chiplets to SBE
-            One Guard bit per EX chiplet, bit location aligned to chiplet ID
-            (bit 16: EX00, bit 17: EX01, bit 18: EX02 ... bit 31: EX15)
-            Guarded EX chiplets are marked by a '1'.
-        </description>
-        <valueType>uint32</valueType>
-        <platInit/>
-        <writeable/>
-    </attribute>
-    <!-- ********************************************************************* -->
-    <attribute>
-        <id>ATTR_DISABLE_I2C_ACCESS</id>
-        <targetType>TARGET_TYPE_SYSTEM</targetType>
-        <description>
-            Set to skip physical access to i2c interface in SBE execution.
-            Consumed by SBE hooks to permit skipping of selected code when
-            running on a test platform (i.e., wafer) which does not have a physical
-            SEEPROM connected.
-        </description>
-        <valueType>uint8</valueType>
-        <platInit/>
-    </attribute>
-    <!-- ********************************************************************* -->
-    <attribute>
-        <id>ATTR_PIB_I2C_REFCLOCK</id>
-        <targetType>TARGET_TYPE_SYSTEM</targetType>
-        <description>
-            i2c reference clock for the system
-        </description>
-        <valueType>uint32</valueType>
-        <platInit/>
-        <writeable/>
-    </attribute>
-    <!-- ********************************************************************* -->
-    <attribute>
-        <id>ATTR_PIB_I2C_NEST_PLL</id>
-        <targetType>TARGET_TYPE_SYSTEM</targetType>
-        <description>
-            i2c pll for the system
-        </description>
-        <valueType>uint32</valueType>
-        <platInit/>
-        <writeable/>
-    </attribute>
-    <!-- ********************************************************************* -->
-    <attribute>
-        <id>ATTR_SBE_IMAGE_OFFSET</id>
-        <targetType>TARGET_TYPE_SYSTEM</targetType>
-        <description>
-            HostBoot image for SBE, offset to account for ECC
-        </description>
-        <valueType>uint32</valueType>
-        <platInit/>
-        <writeable/>
-    </attribute>
-    <!-- ********************************************************************* -->
-    <attribute>
-        <id>ATTR_BOOT_VOLTAGE</id>
-        <targetType>TARGET_TYPE_SYSTEM</targetType>
-        <description>
-            Boot Voltage for system
-        </description>
-        <valueType>uint32</valueType>
-        <platInit/>
-        <writeable/>
-    </attribute>
-    <!-- ********************************************************************* -->
-    <attribute>
-        <id>ATTR_RISK_LEVEL</id>
-        <targetType>TARGET_TYPE_SYSTEM</targetType>
-        <description>
-            Defines risk level to consider for initialization values applied during IPL.
-            Risk level 0 should contain solutions for all known errata, and may sacrifice performance to avoid data integrity issue/error checking cases.
-            Risk level 100 may introduce data integrity/error scenarios to provide full performance or visibility to state space/coverage behind known issues.
-        </description>
-        <valueType>uint32</valueType>
-        <enum>
-            RL0 = 0x000,
-            RL100 = 0x100
-        </enum>
-        <platInit/>
-    </attribute>
-    <!-- ********************************************************************* -->
-    <attribute>
-        <id>ATTR_PROC_REFCLOCK_RCVR_TERM</id>
-        <targetType>TARGET_TYPE_SYSTEM</targetType>
-        <description>
-            Defines system specific value of processor refclock receiver termination (FSI GP4 bits 8:9)
-        </description>
-        <valueType>uint8</valueType>
-        <platInit/>
-    </attribute>
-    <!-- ********************************************************************* -->
-    <attribute>
-        <id>ATTR_PCI_REFCLOCK_RCVR_TERM</id>
-        <targetType>TARGET_TYPE_SYSTEM</targetType>
-        <description>
-            Defines system specific value of PCI refclock receiver termination (FSI GP4 bits 10:11)
-        </description>
-        <valueType>uint8</valueType>
-        <platInit/>
-    </attribute>
-    <!-- ********************************************************************* -->
-    <attribute>
-        <id>ATTR_MEM_FILTER_PLL_SOURCE</id>
-        <targetType>TARGET_TYPE_SYSTEM</targetType>
-        <description>
-            Defines source of MEM filter PLL input (FSI GP4 bit 23)
-        </description>
-        <valueType>uint8</valueType>
-        <enum>
-            PROC_REFCLK = 0x0,
-            PCI_REFCLK = 0x1
-        </enum>
-        <platInit/>
-    </attribute>
-    <!-- ********************************************************************* -->
-    <attribute>
-        <id>ATTR_MULTI_SCOM_BUFFER_MAX_SIZE</id>
-        <targetType>TARGET_TYPE_SYSTEM</targetType>
-        <description>
-            Defines maximum size of data buffer to allocate for optimal
-            performance with platform implementation of fapiMultiScom API.
-        </description>
-        <valueType>uint64</valueType>
-        <enum>
-            MULTI_SCOM_BUFFER_SIZE_1KB   = 0x0000000000000400,
-            MULTI_SCOM_BUFFER_SIZE_2KB   = 0x0000000000000800,
-            MULTI_SCOM_BUFFER_SIZE_4KB   = 0x0000000000001000,
-            MULTI_SCOM_BUFFER_SIZE_8KB   = 0x0000000000002000,
-            MULTI_SCOM_BUFFER_SIZE_16KB  = 0x0000000000004000,
-            MULTI_SCOM_BUFFER_SIZE_32KB  = 0x0000000000008000,
-            MULTI_SCOM_BUFFER_SIZE_64KB  = 0x0000000000010000,
-            MULTI_SCOM_BUFFER_SIZE_128KB = 0x0000000000020000,
-            MULTI_SCOM_BUFFER_SIZE_256KB = 0x0000000000040000,
-            MULTI_SCOM_BUFFER_SIZE_512KB = 0x0000000000080000,
-            MULTI_SCOM_BUFFER_SIZE_1MB   = 0x0000000000100000
-        </enum>
-        <platInit/>
-        <persistRuntime/>
-    </attribute>
-    <!-- ********************************************************************* -->
-    <attribute>
-        <id>ATTR_RECONFIGURE_LOOP</id>
-        <targetType>TARGET_TYPE_SYSTEM</targetType>
-        <description>
-            Used to inidicate if a reconfigure loop is needed
-        </description>
-        <valueType>uint8</valueType>
-        <enum>
-            DECONFIGURE      = 0x1,
-            BAD_DQ_BIT_SET   = 0x2
-        </enum>
-        <writeable/>
-    </attribute>
-    <!-- ********************************************************************* -->
-    <attribute>
-        <id>ATTR_PM_HWP_ATTR_VERSION</id>
-        <targetType>TARGET_TYPE_SYSTEM</targetType>
-        <description>
-            Defines HWP version to be checked inside HWPs to determine if new
-            code should be loaded/skipped/modified/etc. Service pack versions
-            of the procedures may diverge from the working branch. Specific
-            values to be defined as needed in the service pack release stream.
-        </description>
-        <valueType>uint32</valueType>
-        <platInit/>
-        <writeable/>
-    </attribute>
-    <!-- ********************************************************************* -->
+  <!-- ********************************************************************* -->
+    <attribute>
+      <id>ATTR_REDUNDANT_CLOCKS</id>
+      <targetType>TARGET_TYPE_SYSTEM</targetType>
+      <description>
+          1 = System has redundant clock oscillators
+          0 = System does not have redundant clock oscillators
+          From the Machine Readable Workbook
+      </description>
+      <valueType>uint8</valueType>
+      <platInit/>
+    </attribute>
+  <!-- ********************************************************************* -->
 </attributes>
diff --git a/src/usr/hwpf/plat/fapiPlatAttributeService.C b/src/usr/hwpf/plat/fapiPlatAttributeService.C
index ac58d87b4..6616883a9 100644
--- a/src/usr/hwpf/plat/fapiPlatAttributeService.C
+++ b/src/usr/hwpf/plat/fapiPlatAttributeService.C
@@ -52,6 +52,7 @@
 #include <hwpf/hwp/mvpd_accessors/getMBvpdSensorMap.H>
 #include <hwpf/hwp/mvpd_accessors/accessMBvpdL4BankDelete.H>
 #include <hwpf/hwp/chip_accessors/getPciOscswitchConfig.H>
+#include <hwpf/hwp/chip_accessors/getOscswitchCtlAttr.H>
 #include <fapiPllRingAttr.H>
 #include <hwpf/hwp/pll_accessors/getPllRingAttr.H>
 #include <hwpf/hwp/pll_accessors/getPllRingInfoAttr.H>
@@ -1553,6 +1554,20 @@ fapi::ReturnCode fapiPlatGetSpdModspecComRefRawCard
     return l_rc;
 }
 
+//-----------------------------------------------------------------------------
+fapi::ReturnCode fapiPlatGetOscswitchCtl
+                              (const fapi::Target * i_pProcTarget,
+                               const fapi::getOscswitchCtl::Attr i_attr,
+                               void * o_pVal,
+                               const size_t i_len)
+{
+    fapi::ReturnCode l_rc;
+
+    FAPI_EXEC_HWP(l_rc,getOscswitchCtlAttr,*i_pProcTarget,i_attr,o_pVal,i_len);
+
+    return l_rc;
+}
+
 
 } // End platAttrSvc namespace