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| author | Dan Crowell <dcrowell@us.ibm.com> | 2019-04-30 13:06:07 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2019-05-08 16:45:47 -0500 |
| commit | e929912354d61206c2dbfe43a3d1db46072056fe (patch) | |
| tree | a10ed4e1fa376c19aab5de483e7b057886a27e0c /src/usr/hwas/common | |
| parent | d035a51f51ae137f24301cca137cf8bdd9d6d561 (diff) | |
| download | blackbird-hostboot-e929912354d61206c2dbfe43a3d1db46072056fe.tar.gz blackbird-hostboot-e929912354d61206c2dbfe43a3d1db46072056fe.zip | |
Add Axone to RISK_LEVEL logic
Axone reuses the RISK_LEVEL settings for Nimbus DD2.3 so changes
are made to reflect that. This is primarily a documentation
exercise but there is logic now to normalize the RISK_LEVEl up
to 4,5 versus 0,1 just to stay sane and reduce the test matrix.
Change-Id: I5410d1bf7b12fc7f771e2c9826fcd086b2520091
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/76757
Reviewed-by: Matt Derksen <mderkse1@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Matthew Raybuck <matthew.raybuck@ibm.com>
Reviewed-by: Jayashankar Padath <jayashankar.padath@in.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/usr/hwas/common')
| -rw-r--r-- | src/usr/hwas/common/hwas.C | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/src/usr/hwas/common/hwas.C b/src/usr/hwas/common/hwas.C index 432d2d4f0..f0ce3ed04 100644 --- a/src/usr/hwas/common/hwas.C +++ b/src/usr/hwas/common/hwas.C @@ -4068,6 +4068,33 @@ errlHndl_t updateProcCompatibilityRiskLevel() return l_err; } +/** + * @brief Normalize the RISK_LEVEL for Axone to use the upper range + */ +void normalizeRiskLevelForAxone( void ) +{ + // Axone follows Nimbus DD2.3 settings except it can use + // the low or high numbers. Let's normalize it to the + // high range to make things less confusing. + Target* pSys; + targetService().getTopLevelTarget(pSys); + auto l_risk = pSys->getAttr<TARGETING::ATTR_RISK_LEVEL>(); + if( TARGETING::UTIL::P9A_RUGBY_FAVOR_SECURITY_LOWER == l_risk ) + { + l_risk = TARGETING::UTIL::P9A_RUGBY_FAVOR_SECURITY; + } + else if( TARGETING::UTIL::P9A_RUGBY_FAVOR_PERFORMANCE_LOWER == l_risk ) + { + l_risk = TARGETING::UTIL::P9A_RUGBY_FAVOR_PERFORMANCE; + } + else + { + // Nothing to change, just leave + return; + } + pSys->setAttr<TARGETING::ATTR_RISK_LEVEL>(l_risk); +} + errlHndl_t validateProcessorEcLevels() { HWAS_INF("validateProcessorEcLevels entry"); @@ -4113,6 +4140,12 @@ errlHndl_t validateProcessorEcLevels() break; } } + else if(TARGETING::MODEL_AXONE == l_model) + { + // Axone follows Nimbus DD2.3 settings except it can use + // the low or high numbers, going to force one way. + normalizeRiskLevelForAxone(); + } //Loop through all functional procs and create error logs //for any processors whose EC does not match the master |

