PRD: Skip Core RE analysis for special case mentioned below

     Skip Core RE analysis if its corresponding bit
     is not set in COREWOF and both Core CS/RE are
     on at the same time

Change-Id: If14234300b0244312dfed9b25632aebe1cbb2c14
CQ: SW273583
Backport: release-fips811
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/12796
Reviewed-by: Zane Shelley <zshelle@us.ibm.com>
Tested-by: Zane Shelley <zshelle@us.ibm.com>
Squashed: I3d9d7060be488f0a6f472d0ff53801bc3bb3bfd1
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/12805
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

3 files changed, 59 insertions, 4 deletions

diff --git a/src/usr/diag/prdf/common/plat/pegasus/Ex.rule b/src/usr/diag/prdf/common/plat/pegasus/Ex.rule
index 10f173d71..dfa64be50 100755
--- a/src/usr/diag/prdf/common/plat/pegasus/Ex.rule
+++ b/src/usr/diag/prdf/common/plat/pegasus/Ex.rule
@@ -1354,9 +1354,9 @@ group gCoreFir filter singlebit
     (CoreFir, bit(59)) ? defaultMaskedError;
 
     /** COREFIR[60]
-     *  DBG_FIR_CHECKSTOP_ON_TRIGGER: debug Trigger Error inject
+     *  Debug trigger error inject
      */
-    (CoreFir, bit(60)) ? SelfHighThr1;
+    (CoreFir, bit(60)) ? SelfMedThr32PerDay;
 
     /** COREFIR[61]
      *  SP_INJ_REC_ERR: SCOM or Firmware recoverable Error Inject
@@ -1929,6 +1929,9 @@ group gNcuFir filter singlebit
 actionclass analyzeCore
 {
     funccall("CheckCoreCheckstop");
+    # if core recoverable is not set in COREWOF and
+    # Core CS is on, analyze core checkstop
+    try(funccall("CoreRePresent"), funccall("SetCoreCheckstopCause"));
     analyze(gCoreFir);
     funccall("MaskIfCoreCheckstop");
     funccall("RestartTraceArray");
diff --git a/src/usr/diag/prdf/plat/pegasus/prdfPlatP8Ex.C b/src/usr/diag/prdf/plat/pegasus/prdfPlatP8Ex.C
index 5f6fba498..498c52b9b 100644
--- a/src/usr/diag/prdf/plat/pegasus/prdfPlatP8Ex.C
+++ b/src/usr/diag/prdf/plat/pegasus/prdfPlatP8Ex.C
@@ -5,7 +5,9 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012,2014              */
+/* Contributors Listed Below - COPYRIGHT 2013,2014                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
 /*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
@@ -152,5 +154,19 @@ int32_t InHostboot( ExtensibleChip * i_chip,
     return SUCCESS;
 } PRDF_PLUGIN_DEFINE(Ex, InHostboot);
 
+/**
+ * @brief check if both core CS and RE are on at the same time
+ *        and core recoverable is set in COREFIRWOF
+ * @param i_chip Ex chip.
+ * @param i_stepcode Step Code data struct
+ * @return SUCCESS in Hostboot since we don't want to analyze core CS
+ */
+int32_t CoreRePresent( ExtensibleChip * i_chip,
+                       STEP_CODE_DATA_STRUCT & i_stepcode )
+{
+    return SUCCESS;
+
+} PRDF_PLUGIN_DEFINE(Ex, CoreRePresent);
+
 } // end namespace Ex
 } // end namespace PRDF
diff --git a/src/usr/diag/prdf/test/prdfTest_Ex.H b/src/usr/diag/prdf/test/prdfTest_Ex.H
index c2a14a481..2dcdd2dae 100644
--- a/src/usr/diag/prdf/test/prdfTest_Ex.H
+++ b/src/usr/diag/prdf/test/prdfTest_Ex.H
@@ -5,7 +5,9 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012,2014              */
+/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
 /*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
@@ -84,5 +86,39 @@ class ExLFIR:public CxxTest::TestSuite
                 TS_FAIL("L3CE Test failed");
             }
         }
+
+        void TestCoreRecoverable(void)
+        {
+            PRDS_BEGIN("COREFIR recoverable attention");
+            PRDS_ERROR_ENTRY("NODE{0}:PROC{0}", PRDF::RECOVERABLE);
+            PRDS_EXPECTED_SIGNATURE("NODE{0}:PROC{0}:EX{5}", 0xc8e9003c);
+            // GLOBAL_RE_FIR
+            PRDS_SCR_WRITE("NODE{0}:PROC{0}", 0x570F001B, 0x0000040000000000);
+            // GLOBALUNITXSTPFIR
+            PRDS_SCR_WRITE("NODE{0}:PROC{0}", 0x51040001, 0x0000000000000000);
+            // EX_CHIPLET_RE_FIR
+            PRDS_SCR_WRITE("NODE{0}:PROC{0}:EX{5}", 0x10040001, 0x2000000000000000);
+            // EX_CHIPLET_RE_FIR_MASK
+            PRDS_SCR_WRITE("NODE{0}:PROC{0}:EX{5}", 0x10040002, 0x20ffffc000000000);
+            // COREFIR bit 60 on
+            PRDS_SCR_WRITE("NODE{0}:PROC{0}:EX{5}", 0x10013100, 0x0000000000000008);
+            // COREFIR WOF bit 60 on
+            PRDS_SCR_WRITE("NODE{0}:PROC{0}:EX{5}", 0x10013108, 0x0000000000000008);
+            // COREFIR_ACT0
+            PRDS_SCR_WRITE("NODE{0}:PROC{0}:EX{5}", 0x10013106, 0x15a20c688a448b01);
+            // COREFIR_ACT1
+            PRDS_SCR_WRITE("NODE{0}:PROC{0}:EX{5}", 0x10013107, 0xfefc17f7ff9c8a09);
+            // COREHMEER
+            PRDS_SCR_WRITE("NODE{0}:PROC{0}:EX{5}", 0x1001329B, 0xac10080000000000);
+            // SPATTN_0
+            PRDS_SCR_WRITE("NODE{0}:PROC{0}:EX{5}", 0x10013007, 0x0000000000000000);
+
+            PRDS_START_SIM();
+            if(!(PRDS_END()))
+            {
+                TS_FAIL("COREFIR recoverable attention test failed");
+            }
+        }
+
 };
 #endif