P9 PSIHB Base Interrupt Support

This change includes the following:
   - Kernel Updates to handle hypervisor interrupt vector
   - Interrupt Resource Provider changes to setup and handle
     LSI Based interrupts
   - Kernel updates to handle modified interrupt flow for
     LSI Based interrupts
   - Attribute updates for Scom BAR Registers

Change-Id: If63f246a0090ab8c81c3fa8ac3ab6871a0af2e31
RTC:137561
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/20692
Tested-by: Jenkins Server
Tested-by: FSP CI Jenkins
Reviewed-by: Andrew J. Geissler <andrewg@us.ibm.com>
Reviewed-by: Prachi Gupta <pragupta@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

4 files changed, 62 insertions, 18 deletions

diff --git a/src/include/kernel/cpumgr.H b/src/include/kernel/cpumgr.H
index 30009da73..25bb794bf 100644
--- a/src/include/kernel/cpumgr.H
+++ b/src/include/kernel/cpumgr.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2010,2015                        */
+/* Contributors Listed Below - COPYRIGHT 2010,2016                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -170,8 +170,9 @@ class CpuManager
          *  bit 51 - Wake-up from machine check.
          *  bit 60 - LPES(0) = 1 (see ISA).
          *  bit 61 - LPES(1) = 0 (P8 RFC02204 forces to 0)
+         *  bit 62 - HVICE - Hypervisor Virt Interrupt Conditionally Enable
          */
-        static const uint64_t WAKEUP_LPCR_VALUE =   0x0000000000007008;
+        static const uint64_t WAKEUP_LPCR_VALUE =   0x000000000000700A;
 
         /** Desired value for RPR after wakeup.
          *
diff --git a/src/include/kernel/intmsghandler.H b/src/include/kernel/intmsghandler.H
index 98d8d5288..8fd4e34b6 100644
--- a/src/include/kernel/intmsghandler.H
+++ b/src/include/kernel/intmsghandler.H
@@ -46,6 +46,7 @@ class InterruptMsgHdlr : public MessageHandler
     public:
 
         /**
+         * TODO RTC 150260
          * Field values for P8
          * @note This is used to calculate the mmio address offset
          * from the PIR for the interrupt presenter memory mapped registers.
@@ -56,19 +57,20 @@ class InterruptMsgHdlr : public MessageHandler
          */
         enum
         {
-            P8_PIR_THREADID_MSK = PIR_t::THREAD_MASK,
-            P8_PIR_COREID_MSK   = PIR_t::CORE_MASK,
-            P8_PIR_CHIPID_MSK   = PIR_t::CHIP_MASK,
-            P8_PIR_NODEID_MSK   = PIR_t::GROUP_MASK,
+            P9_PIR_THREADID_MSK = PIR_t::THREAD_MASK,
+            P9_PIR_COREID_MSK   = PIR_t::CORE_MASK,
+            P9_PIR_CHIPID_MSK   = PIR_t::CHIP_MASK,
+            P9_PIR_NODEID_MSK   = PIR_t::GROUP_MASK,
 
             // Logical Shift Left fields for mmio Base address from PIR.
             // (IP addr bit pos - PIR bit pos)
-            P8_IP_THREADID_LSL = (12-PIR_t::BITS_AFTER_CORE),
-            P8_IP_COREID_LSL   = (15-PIR_t::BITS_AFTER_CORE),
-            P8_IP_CHIPID_LSL   = (20-PIR_t::BITS_AFTER_CHIP),
-            P8_IP_NODEID_LSL   = (22-PIR_t::BITS_AFTER_GROUP),
+            P9_IP_THREADID_LSL = (12-PIR_t::BITS_AFTER_CORE),
+            P9_IP_COREID_LSL   = (15-PIR_t::BITS_AFTER_CORE),
+            P9_IP_CHIPID_LSL   = (20-PIR_t::BITS_AFTER_CHIP),
+            P9_IP_NODEID_LSL   = (22-PIR_t::BITS_AFTER_GROUP),
             XIRR_ADDR_OFFSET   = 4,
             MFRR_ADDR_OFFSET   = 12,
+            ACK_HYPERVISOR_INT_REG_OFFSET = 0x830,
 
             INTP_BAR_VALUE     = 0xFFFFE000,    // upper 32 bits of IPCBAR
 
@@ -109,16 +111,16 @@ class InterruptMsgHdlr : public MessageHandler
             // The PIR chip id field has 1 extra bit (8 chips), so we need
             // to shift the node and chip separately
             offset  |=
-                (i_pir & P8_PIR_NODEID_MSK) << P8_IP_NODEID_LSL;
+                (i_pir & P9_PIR_NODEID_MSK) << P9_IP_NODEID_LSL;
 
             offset  |=
-                (i_pir & P8_PIR_CHIPID_MSK) << P8_IP_CHIPID_LSL;
+                (i_pir & P9_PIR_CHIPID_MSK) << P9_IP_CHIPID_LSL;
 
             // The core and thread id field are adjacent in both the PIR and
             // the mmio offset, so they can be done in one shift operation.
             offset  |=
-                (i_pir & (P8_PIR_COREID_MSK | P8_PIR_THREADID_MSK))
-                << P8_IP_THREADID_LSL;
+                (i_pir & (P9_PIR_COREID_MSK | P9_PIR_THREADID_MSK))
+                << P9_IP_THREADID_LSL;
 
             return offset;
         }
diff --git a/src/include/usr/intr/interrupt.H b/src/include/usr/intr/interrupt.H
index 1b24c2eed..1666abd15 100644
--- a/src/include/usr/intr/interrupt.H
+++ b/src/include/usr/intr/interrupt.H
@@ -51,7 +51,8 @@ namespace INTR
     enum XISRvalue_t
     {
         NO_INTERRUPT = 0,       //!< no interrupt present
-        INTERPROC_XISR = 2,     //!< XISR value for IPIs
+        //TODO RTC 137564
+        INTERPROC_XISR = 0xFF,  //!< XISR value for IPIs
         MAX_XISR  = 0x00FFFFFF, //!< Max value of the XISR
         SHUT_DOWN = 0x01000000, //!< INTR presenter sends this when shutting down
     };
@@ -71,6 +72,33 @@ namespace INTR
                                 //Converts to INTERPROC_XISR when registered
     };
 
+    //These values are HW defined values from the LSI Interrupts status register
+    // on the PSIHB. These should only be changed if the spec changes.
+    enum LSIvalue_t
+    {
+        LSI_PSI         = 0,
+        LSI_OCC         = 1,
+        LSI_FSIMBOX     = 2,
+        LSI_LPC         = 3,
+        LSI_LCL_FIR     = 4,
+        LSI_GLOBAL      = 5,
+        LSI_TPM         = 6,
+        LSI_LPC_SERIAL0 = 7,
+        LSI_LPC_SERIAL1 = 8,
+        LSI_LPC_SERIAL2 = 9,
+        LSI_LPC_SERIAL3 = 10,
+        LSI_SBE_OR_I2C  = 11,
+        LSI_DIO         = 12,
+        LSI_PSU         = 13,
+        LSI_LAST_SOURCE,
+
+//TODO RTC 137564
+//        ISN_INTERPROC   = 0xF0, //"special" as it isn't part of PSIHB
+//                                //Converts to INTERPROC_XISR when registered
+//                                //
+    };
+
+
     /**
      * The XISR value is the logical OR of the Interrup Requestor Source
      * Number (IRSN) and the Interrrupt Source Number (ISN).
@@ -107,12 +135,12 @@ namespace INTR
         MSG_INTR_ENABLE,            //!< Enable external Interrupts
         MSG_INTR_DISABLE,           //!< Disable external interrupts
         MSG_INTR_SHUTDOWN,          //!< Call to shutdown interrupt presenter
-        MSG_INTR_ENABLE_PSI_INTR,   //!< Enable PSI interrupts
         MSG_INTR_MPIPL_CLEANUP,     //!< Clean up interrupts on MPIPL
         MSG_INTR_ADD_CPU_TIMEOUT,   //!< Check for a timeout waiting for a core.
         MSG_INTR_ADD_HBNODE,        //!< Add node info for MPIPL
         MSG_INTR_EOI,               //!< Issue EOI when received
         MSG_INTR_DRAIN_QUEUE,       //!< Allow intrp to drain Q of EOI
+        MSG_INTR_COALESCE,          //!< Pending interrupt to be handled
     };
 
     /**
@@ -181,12 +209,13 @@ namespace INTR
      */
     errlHndl_t disableExternalInterrupts();
 
+    //TODO RTC 150260
     /**
      * Initialize the IRSCReg to enable PSI to present interrupts
      * @param[in] i_target  The target processor
      * @return error log handle on error
      */
-    errlHndl_t enablePsiIntr(TARGETING::Target * i_target);
+    //errlHndl_t enablePsiIntr(TARGETING::Target * i_target);
 
     /**
      * Return the interrupt presenter for requested target/thread
diff --git a/src/include/usr/intr/intr_reasoncodes.H b/src/include/usr/intr/intr_reasoncodes.H
index 31869ac69..8ab758519 100644
--- a/src/include/usr/intr/intr_reasoncodes.H
+++ b/src/include/usr/intr/intr_reasoncodes.H
@@ -5,7 +5,9 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2011,2014              */
+/* Contributors Listed Below - COPYRIGHT 2011,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
 /*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
@@ -42,6 +44,11 @@ namespace INTR
         MOD_INTR_SYNC_ADDNODE        = 0x0A, /**< intrrp.C : IntrRp::addHbNodeToMpiplSyncArea */
         MOD_INTR_ADDHBNODE           = 0x0B, /**< intrrp.C : INTR::addHbNode */
         MOD_INTR_EXTRACTNODEINFO     = 0x0C, /**< intrrp.C : INTR::extractHbNodeInfo */
+        MOD_INTRRP_SENDEOI           = 0x0D, /**< intrrp.C : INTR::sendEOI */
+        MOD_INTRRP_MASKINTERRUPT     = 0x0E, /**< intrrp.C : INTR::maskInterruptSource */
+        MOD_INTRRP_UNMASKINTERRUPT   = 0x0F, /**< intrrp.C : INTR::unmaskInterruptSource */
+        MOD_INTRRP_HNDLPSUINTERRUPT  = 0x10, /**< intrrp.C : INTR::handlePsuInterrupt */
+        MOD_INTRRP_RESETINTUNIT      = 0x11, /**< intrrp.C : IntrRp::resetIntUnit */
     };
 
     enum IntrReasonCode
@@ -54,6 +61,11 @@ namespace INTR
         //termination_rc
         RC_PERSISTENT_INTERRUPTS      = INTR_COMP_ID | 0x06,
         RC_CANNOT_MAP_MEMORY          = INTR_COMP_ID | 0x07,
+        RC_PSIHB_ESB_EOI_FAIL         = INTR_COMP_ID | 0x08,
+        RC_XIVE_ESB_WRONG_STATE       = INTR_COMP_ID | 0x09,
+        RC_PSU_DOORBELL_TIMEOUT       = INTR_COMP_ID | 0x0A,
+        RC_XIVE_PBUS_QUIESCE_TIMEOUT  = INTR_COMP_ID | 0x0B,
+        RC_MESSAGE_SEND_ERROR         = INTR_COMP_ID | 0x0C,
     };
 };