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| author | dgilbert <dgilbert@us.ibm.com> | 2012-11-27 11:41:04 -0600 |
|---|---|---|
| committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2012-12-19 16:02:43 -0600 |
| commit | f5ae894024733fe3fb5ae26aaaa67cc8df0d0a3c (patch) | |
| tree | 7bcc9aa241f64758736e88d4f1bc9c4bf72db252 /src/include/usr/intr/intr_reasoncodes.H | |
| parent | 9458535739acca481800bbda1b59d4f1b213d2c2 (diff) | |
| download | blackbird-hostboot-f5ae894024733fe3fb5ae26aaaa67cc8df0d0a3c.tar.gz blackbird-hostboot-f5ae894024733fe3fb5ae26aaaa67cc8df0d0a3c.zip | |
Initialize the PIB hardware layer for interrupts
RTC: 47105
Change-Id: Iba893e65ee468b56e9e929a26d2888a67a4788af
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/2433
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src/include/usr/intr/intr_reasoncodes.H')
| -rw-r--r-- | src/include/usr/intr/intr_reasoncodes.H | 47 |
1 files changed, 25 insertions, 22 deletions
diff --git a/src/include/usr/intr/intr_reasoncodes.H b/src/include/usr/intr/intr_reasoncodes.H index 489eda68a..b336f8b14 100644 --- a/src/include/usr/intr/intr_reasoncodes.H +++ b/src/include/usr/intr/intr_reasoncodes.H @@ -1,25 +1,25 @@ -// IBM_PROLOG_BEGIN_TAG -// This is an automatically generated prolog. -// -// $Source: src/include/usr/intr/intr_reasoncodes.H $ -// -// IBM CONFIDENTIAL -// -// COPYRIGHT International Business Machines Corp. 2011 -// -// p1 -// -// Object Code Only (OCO) source materials -// Licensed Internal Code Source Materials -// IBM HostBoot Licensed Internal Code -// -// The source code for this program is not published or other- -// wise divested of its trade secrets, irrespective of what has -// been deposited with the U.S. Copyright Office. -// -// Origin: 30 -// -// IBM_PROLOG_END +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/include/usr/intr/intr_reasoncodes.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2011,2012 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ #ifndef INTR_REASONCODES_H #define INTR_REASONCODES_H @@ -35,6 +35,8 @@ namespace INTR MOD_INTR_REGISTER = 0x03, /**< intrrp.C : INTR::registerMsgQ */ MOD_INTRRP_CHECKADDRESS = 0x04, /**< intrrp.C : IntrRp::checkAddress */ MOD_INTRRP_REGISTERINTERRUPT = 0x05, /**< intrrp.C : IntrRp::registerInterrupt */ + MOD_INTR_ENABLE_PSI_INTR = 0x06, /**< intrrp.C : INTR::enablePsiIntr */ + MOD_INTR_INIT_XIVR = 0x07, /**< intrrp.C : INTR::initXIVR */ }; enum IntrReasonCode @@ -43,6 +45,7 @@ namespace INTR RC_REGISTRY_NOT_READY = INTR_COMP_ID | 0x02, RC_RP_NOT_INITIALIZED = INTR_COMP_ID | 0x03, RC_BAD_VIRTUAL_IO_ADDRESS = INTR_COMP_ID | 0x04, + RC_BAD_ISN = INTR_COMP_ID | 0x05, }; }; |
